mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-07 01:54:10 +00:00
13 lines
126 B
Plaintext
13 lines
126 B
Plaintext
ram distributed \RAM_LUT {
|
|
abits 4;
|
|
width 4;
|
|
init any;
|
|
cost 4;
|
|
port ar "R" {
|
|
}
|
|
port arsw "RW" {
|
|
clock anyedge;
|
|
}
|
|
}
|
|
|