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Add celltype unit tests.
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nella
parent
cbe847e8f5
commit
97e1a3b7c7
3 changed files with 1256 additions and 42 deletions
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@ -146,7 +146,7 @@ struct CellTypes
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bool builtin_is_known(size_t idx) const
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{
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return enabled_cats && idx < (size_t)StaticCellTypes::GEN_MAX_CELLS &&
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StaticCellTypes::GeneratedData::is_known[idx];
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StaticCellTypes::GeneratedData::is_known[idx];
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}
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bool cell_known(const RTLIL::IdString &type) const
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@ -157,7 +157,6 @@ struct CellTypes
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} else if (builtin_match(type.index_)) {
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return true;
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}
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return cell_types.count(type) != 0;
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}
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@ -171,10 +170,8 @@ struct CellTypes
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for (uint16_t i = 0; i < count; i++)
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if (StaticCellTypes::GeneratedData::port_outputs_ports[idx][i] == target)
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return true;
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return false;
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}
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auto it = cell_types.find(type);
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return it != cell_types.end() && it->second.outputs.count(port) != 0;
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}
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@ -189,10 +186,8 @@ struct CellTypes
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for (uint16_t i = 0; i < count; i++)
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if (StaticCellTypes::GeneratedData::port_inputs_ports[idx][i] == target)
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return true;
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return false;
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}
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auto it = cell_types.find(type);
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return it != cell_types.end() && it->second.inputs.count(port) != 0;
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}
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@ -206,24 +201,17 @@ struct CellTypes
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uint32_t target = (uint32_t)port.index_;
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uint16_t ic = StaticCellTypes::GeneratedData::port_inputs_counts[idx];
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for (uint16_t i = 0; i < ic; i++)
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if (StaticCellTypes::GeneratedData::port_inputs_ports[idx][i] == target) {
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is_in = true;
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break;
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}
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if (StaticCellTypes::GeneratedData::port_inputs_ports[idx][i] == target)
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{ is_in = true; break; }
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uint16_t oc = StaticCellTypes::GeneratedData::port_outputs_counts[idx];
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for (uint16_t i = 0; i < oc; i++)
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if (StaticCellTypes::GeneratedData::port_outputs_ports[idx][i] == target) {
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is_out = true;
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break;
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}
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if (StaticCellTypes::GeneratedData::port_outputs_ports[idx][i] == target)
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{ is_out = true; break; }
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return RTLIL::PortDir(is_in + is_out * 2);
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}
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auto it = cell_types.find(type);
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if (it == cell_types.end())
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return RTLIL::PD_UNKNOWN;
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bool is_in = it->second.inputs.count(port);
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bool is_out = it->second.outputs.count(port);
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return RTLIL::PortDir(is_in + is_out * 2);
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@ -234,8 +222,8 @@ struct CellTypes
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size_t idx = type.index_;
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bool is_builtin = (enabled_cats == BITS_ALL) ? builtin_is_known(idx) : builtin_match(idx);
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if (is_builtin)
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return idx < (size_t)StaticCellTypes::GEN_MAX_CELLS && StaticCellTypes::GeneratedData::is_evaluable[idx];
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return idx < (size_t)StaticCellTypes::GEN_MAX_CELLS &&
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StaticCellTypes::GeneratedData::is_cell_evaluable[idx];
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auto it = cell_types.find(type);
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return it != cell_types.end() && it->second.is_evaluable;
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}
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@ -245,7 +233,6 @@ struct CellTypes
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for (auto bit : v)
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if (bit == State::S0) bit = State::S1;
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else if (bit == State::S1) bit = State::S0;
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return v;
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}
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@ -361,7 +348,6 @@ struct CellTypes
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std::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).to_bits();
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while (GetSize(t) < (1 << width))
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t.push_back(State::S0);
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t.resize(1 << width);
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return const_bmux(t, arg1);
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@ -373,7 +359,7 @@ struct CellTypes
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int depth = cell->parameters.at(ID::DEPTH).as_int();
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std::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).to_bits();
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while (GetSize(t) < width * depth * 2)
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while (GetSize(t) < width*depth*2)
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t.push_back(State::S0);
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RTLIL::State default_ret = State::S0;
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@ -385,11 +371,11 @@ struct CellTypes
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for (int j = 0; j < width; j++) {
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RTLIL::State a = arg1.at(j);
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if (t.at(2 * width * i + 2 * j + 0) == State::S1) {
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if (t.at(2*width*i + 2*j + 0) == State::S1) {
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if (a == State::S1) match_x = false;
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if (a != State::S0) match = false;
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}
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if (t.at(2 * width * i + 2 * j + 1) == State::S1) {
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if (t.at(2*width*i + 2*j + 1) == State::S1) {
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if (a == State::S0) match_x = false;
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if (a != State::S1) match = false;
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}
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@ -39,6 +39,7 @@ def resolve_id(index_map, name):
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@dataclass
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class Features:
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is_evaluable: bool = False
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is_cell_evaluable: bool = False
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is_combinatorial: bool = False
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is_synthesizable: bool = False
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is_stdcell: bool = False
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@ -51,7 +52,7 @@ class Features:
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@dataclass
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class CellInfo:
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type_name: str
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inputs: MAX_CELLS
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inputs: list
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outputs: list
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features: Features
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@ -64,7 +65,7 @@ def build_cell_table():
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Features(**vars(features))))
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# setup_internals_other
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f = Features(is_tristate=True)
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f = Features(is_tristate=True, is_cell_evaluable=True)
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setup_type("$tribuf", ["A", "EN"], ["Y"], f)
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f = Features()
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@ -79,9 +80,13 @@ def build_cell_table():
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setup_type("$allconst", [], ["Y"], f)
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setup_type("$allseq", [], ["Y"], f)
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setup_type("$equiv", ["A", "B"], ["Y"], f)
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f = Features(is_cell_evaluable=True)
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setup_type("$specify2", ["EN", "SRC", "DST"], [], f)
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setup_type("$specify3", ["EN", "SRC", "DST", "DAT"], [], f)
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setup_type("$specrule", ["EN_SRC", "EN_DST", "SRC", "DST"], [], f)
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f = Features()
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setup_type("$print", ["EN", "ARGS", "TRG"], [], f)
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setup_type("$check", ["A", "EN", "ARGS", "TRG"], [], f)
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setup_type("$set_tag", ["A", "SET", "CLR"], ["Y"], f)
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@ -94,7 +99,7 @@ def build_cell_table():
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setup_type("$connect", ["A", "B"], [], f)
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# setup_internals_eval
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f = Features(is_evaluable=True)
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f = Features(is_evaluable=True, is_cell_evaluable=True)
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unary_ops = [
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"$not", "$pos", "$buf", "$neg",
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@ -150,7 +155,7 @@ def build_cell_table():
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f = Features(is_anyinit=True)
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setup_type("$anyinit", ["D"], ["Q"], f)
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# setup_internals_mem_noff
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# setup_internals_mem_noff (mem cells that are NOT FFs)
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f = Features(is_mem_noff=True)
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setup_type("$memrd", ["CLK", "EN", "ADDR"], ["DATA"], f)
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setup_type("$memrd_v2", ["CLK", "EN", "ARST", "SRST", "ADDR"],
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@ -170,11 +175,11 @@ def build_cell_table():
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setup_type("$fsm", ["CLK", "ARST", "CTRL_IN"], ["CTRL_OUT"], f)
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# setup_stdcells_tristate
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f = Features(is_stdcell=True, is_tristate=True)
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f = Features(is_stdcell=True, is_tristate=True, is_cell_evaluable=True)
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setup_type("$_TBUF_", ["A", "E"], ["Y"], f)
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# setup_stdcells_eval
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f = Features(is_stdcell=True, is_evaluable=True)
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f = Features(is_stdcell=True, is_evaluable=True, is_cell_evaluable=True)
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setup_type("$_BUF_", ["A"], ["Y"], f)
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setup_type("$_NOT_", ["A"], ["Y"], f)
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setup_type("$_AND_", ["A", "B"], ["Y"], f)
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@ -298,6 +303,7 @@ def build_arrays(cells, index_map):
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cats = {
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"is_known": [0] * MAX_CELLS,
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"is_evaluable": [0] * MAX_CELLS,
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"is_cell_evaluable": [0] * MAX_CELLS,
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"is_combinatorial": [0] * MAX_CELLS,
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"is_synthesizable": [0] * MAX_CELLS,
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"is_stdcell": [0] * MAX_CELLS,
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@ -320,9 +326,9 @@ def build_arrays(cells, index_map):
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continue
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cats["is_known"][idx] = 1
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for feat in ["is_evaluable", "is_combinatorial", "is_synthesizable",
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"is_stdcell", "is_ff", "is_mem_noff", "is_anyinit",
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"is_tristate"]:
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for feat in ["is_evaluable", "is_cell_evaluable", "is_combinatorial",
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"is_synthesizable", "is_stdcell", "is_ff", "is_mem_noff",
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"is_anyinit", "is_tristate"]:
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if getattr(cell.features, feat):
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cats[feat][idx] = 1
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@ -449,7 +455,13 @@ constexpr int GEN_MAX_PORTS = {MAX_PORTS};
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namespace GeneratedData {{
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extern const uint8_t is_known[GEN_MAX_CELLS];
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// Category flag: true for cells in setup_internals_eval / setup_stdcells_eval.
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// Used by builtin_match() for subset filtering.
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extern const uint8_t is_evaluable[GEN_MAX_CELLS];
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// Property flag: true for any cell whose original setup_type() had is_evaluable=true.
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// Superset of is_evaluable (includes $tribuf, $specify*, $_TBUF_).
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// Used by cell_evaluable() to answer "can this cell be const-evaluated?"
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extern const uint8_t is_cell_evaluable[GEN_MAX_CELLS];
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extern const uint8_t is_combinatorial[GEN_MAX_CELLS];
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extern const uint8_t is_synthesizable[GEN_MAX_CELLS];
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extern const uint8_t is_stdcell[GEN_MAX_CELLS];
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@ -498,15 +510,16 @@ struct GenPortLookup {{
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}}
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}};
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inline GenCategory gen_is_known() {{ return {{GeneratedData::is_known}}; }}
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inline GenCategory gen_is_evaluable() {{ return {{GeneratedData::is_evaluable}}; }}
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inline GenCategory gen_is_combinatorial() {{ return {{GeneratedData::is_combinatorial}}; }}
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inline GenCategory gen_is_synthesizable() {{ return {{GeneratedData::is_synthesizable}}; }}
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inline GenCategory gen_is_stdcell() {{ return {{GeneratedData::is_stdcell}}; }}
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inline GenCategory gen_is_ff() {{ return {{GeneratedData::is_ff}}; }}
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inline GenCategory gen_is_mem_noff() {{ return {{GeneratedData::is_mem_noff}}; }}
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inline GenCategory gen_is_anyinit() {{ return {{GeneratedData::is_anyinit}}; }}
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inline GenCategory gen_is_tristate() {{ return {{GeneratedData::is_tristate}}; }}
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inline GenCategory gen_is_known() {{ return {{GeneratedData::is_known}}; }}
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inline GenCategory gen_is_evaluable() {{ return {{GeneratedData::is_evaluable}}; }}
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inline GenCategory gen_is_cell_evaluable() {{ return {{GeneratedData::is_cell_evaluable}}; }}
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inline GenCategory gen_is_combinatorial() {{ return {{GeneratedData::is_combinatorial}}; }}
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inline GenCategory gen_is_synthesizable() {{ return {{GeneratedData::is_synthesizable}}; }}
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inline GenCategory gen_is_stdcell() {{ return {{GeneratedData::is_stdcell}}; }}
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inline GenCategory gen_is_ff() {{ return {{GeneratedData::is_ff}}; }}
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inline GenCategory gen_is_mem_noff() {{ return {{GeneratedData::is_mem_noff}}; }}
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inline GenCategory gen_is_anyinit() {{ return {{GeneratedData::is_anyinit}}; }}
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inline GenCategory gen_is_tristate() {{ return {{GeneratedData::is_tristate}}; }}
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inline GenCategory gen_compat_internals_all() {{ return {{GeneratedData::compat_internals_all}}; }}
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inline GenCategory gen_compat_mem_ff() {{ return {{GeneratedData::compat_mem_ff}}; }}
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1215
tests/unit/kernel/celltypesTest.cc
Normal file
1215
tests/unit/kernel/celltypesTest.cc
Normal file
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