From 9776084eda50060594c6609295c7aa540bb400e1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 7 Aug 2019 16:40:24 -0700
Subject: [PATCH] Allow whitebox modules to be overwritten
---
frontends/ast/ast.cc | 2 +-
techlibs/ice40/tests/test_arith.ys | 2 --
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 943466ee3..c8ca6d164 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -1172,7 +1172,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
if (design->has((*it)->str)) {
RTLIL::Module *existing_mod = design->module((*it)->str);
- if (!nooverwrite && !overwrite && !existing_mod->get_bool_attribute("\\blackbox")) {
+ if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) {
log_file_error((*it)->filename, (*it)->linenum, "Re-definition of module `%s'!\n", (*it)->str.c_str());
} else if (nooverwrite) {
log("Ignoring re-definition of module `%s' at %s:%d.\n",
diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys
index 7e928ec78..ddb80b700 100644
--- a/techlibs/ice40/tests/test_arith.ys
+++ b/techlibs/ice40/tests/test_arith.ys
@@ -8,8 +8,6 @@ rename test gold
miter -equiv -flatten -make_outputs gold gate miter
sat -verify -prove trigger 0 -show-ports miter
-delete A:whitebox # Necessary since whiteboxes cannot
- # be overwritten...
synth_ice40 -top gate
read_verilog test_arith.v