mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-28 03:15:50 +00:00
Allow whitebox modules to be overwritten
This commit is contained in:
parent
9962e6fc1a
commit
9776084eda
2 changed files with 1 additions and 3 deletions
|
@ -1172,7 +1172,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
|
|||
|
||||
if (design->has((*it)->str)) {
|
||||
RTLIL::Module *existing_mod = design->module((*it)->str);
|
||||
if (!nooverwrite && !overwrite && !existing_mod->get_bool_attribute("\\blackbox")) {
|
||||
if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) {
|
||||
log_file_error((*it)->filename, (*it)->linenum, "Re-definition of module `%s'!\n", (*it)->str.c_str());
|
||||
} else if (nooverwrite) {
|
||||
log("Ignoring re-definition of module `%s' at %s:%d.\n",
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue