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intel: register bram celltypes

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This commit is contained in:
Emil J. Tywoniak 2026-04-02 17:01:32 +02:00
parent d7b6f1c095
commit 9717a558cc
2 changed files with 3 additions and 3 deletions
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2
techlibs/intel/synth_intel.cc
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@ -241,7 +241,7 @@ struct SynthIntelPass : public ScriptPass {
family_opt == "cycloneive" || family_opt == "cycloneive" ||
family_opt == "max10" || family_opt == "max10" ||
help_mode) { help_mode) {
run("memory_bram -rules +/intel/common/brams_m9k.txt", "(if applicable for family)"); run("memory_bram -rules +/intel/common/brams_m9k.txt -register", "(if applicable for family)");
run("techmap -map +/intel/common/brams_map_m9k.v", "(if applicable for family)"); run("techmap -map +/intel/common/brams_map_m9k.v", "(if applicable for family)");
} else { } else {
log_warning("BRAM mapping is not currently supported for %s.\n", family_opt); log_warning("BRAM mapping is not currently supported for %s.\n", family_opt);

4
techlibs/intel_alm/synth_intel_alm.cc
View file

@ -227,12 +227,12 @@ struct SynthIntelALMPass : public ScriptPass {
} }
if (!nobram && check_label("map_bram", "(skip if -nobram)")) { if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
run(stringf("memory_bram -rules +/intel_alm/common/bram_%s.txt", bram_type)); run(stringf("memory_bram -rules +/intel_alm/common/bram_%s.txt -register", bram_type));
run(stringf("techmap -map +/intel_alm/common/bram_%s_map.v", bram_type)); run(stringf("techmap -map +/intel_alm/common/bram_%s_map.v", bram_type));
} }
if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) { if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) {
run("memory_bram -rules +/intel_alm/common/lutram_mlab.txt", "(for Cyclone V)"); run("memory_bram -rules +/intel_alm/common/lutram_mlab.txt -register", "(for Cyclone V)");
} }
if (check_label("map_ffram")) { if (check_label("map_ffram")) {