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https://github.com/YosysHQ/yosys
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WIP migration to twine
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parent
25f27026f0
commit
96b0ba9581
51 changed files with 289 additions and 275 deletions
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@ -674,8 +674,8 @@ struct FlowmapWorker
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labels[node] = -1;
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for (auto input : inputs)
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{
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if (input.wire->attributes.count(TW($flowmap_level)))
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labels[input] = input.wire->attributes[TW($flowmap_level)].as_int();
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if (input.wire->attributes.count(ID($flowmap_level)))
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labels[input] = input.wire->attributes[ID($flowmap_level)].as_int();
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else
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labels[input] = 0;
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}
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@ -1356,10 +1356,10 @@ struct FlowmapWorker
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auto origin = node_origins[node];
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if (origin.cell->getPort(origin.port).size() == 1)
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log("Packing %s.%s.%s (%s).\n",
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module, origin.cell, origin.port.c_str(), log_signal(node));
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module, origin.cell, module->design->twines.str(origin.port).c_str(), log_signal(node));
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else
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log("Packing %s.%s.%s [%d] (%s).\n",
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module, origin.cell, origin.port.c_str(), origin.offset, log_signal(node));
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module, origin.cell, module->design->twines.str(origin.port).c_str(), origin.offset, log_signal(node));
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}
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else
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{
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@ -1376,10 +1376,10 @@ struct FlowmapWorker
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auto gate_origin = node_origins[gate_node];
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if (gate_origin.cell->getPort(gate_origin.port).size() == 1)
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log(" Packing %s.%s.%s (%s).\n",
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module, gate_origin.cell, gate_origin.port.c_str(), log_signal(gate_node));
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module, gate_origin.cell, gate_module->design->twines.str(origin.port).c_str(), log_signal(gate_node));
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else
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log(" Packing %s.%s.%s [%d] (%s).\n",
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module, gate_origin.cell, gate_origin.port.c_str(), gate_origin.offset, log_signal(gate_node));
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module, gate_origin.cell, gate_module->design->twines.str(origin.port).c_str(), gate_origin.offset, log_signal(gate_node));
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}
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vector<RTLIL::SigBit> input_nodes(lut_edges_bw[node].begin(), lut_edges_bw[node].end());
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@ -1590,7 +1590,7 @@ struct FlowmapPass : public Pass {
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}
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else
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{
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cell_types = {TW($_NOT_), TW($_AND_), TW($_OR_), TW($_XOR_), TW($_MUX_)};
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cell_types = {ID($_NOT_), ID($_AND_), ID($_OR_), ID($_XOR_), ID($_MUX_)};
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}
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const char *algo_r = relax ? "-r" : "";
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