From 96b0ba9581c7847835b2c5775d8313d39e511b32 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 17 Jun 2026 11:04:03 +0200 Subject: [PATCH] WIP migration to twine --- backends/aiger2/aiger.cc | 36 ++++++++++----------- backends/blif/blif.cc | 15 +++++---- backends/btor/btor.cc | 28 ++++++++-------- backends/cxxrtl/cxxrtl_backend.cc | 54 +++++++++++++++---------------- backends/simplec/simplec.cc | 4 +-- backends/smt2/smt2.cc | 2 +- backends/spice/spice.cc | 2 +- frontends/aiger/aigerparse.cc | 38 +++++++++++----------- frontends/aiger2/xaiger.cc | 6 ++-- frontends/json/jsonparse.cc | 4 +-- frontends/liberty/liberty.cc | 10 +++--- frontends/rpc/rpc_frontend.cc | 2 +- passes/cmds/abstract.cc | 2 +- passes/cmds/add.cc | 6 ++-- passes/cmds/check.cc | 6 ++-- passes/cmds/connect.cc | 6 ++-- passes/cmds/delete.cc | 2 +- passes/cmds/rename.cc | 12 +++---- passes/cmds/timeest.cc | 4 +-- passes/cmds/viz.cc | 4 +-- passes/equiv/equiv_add.cc | 4 +-- passes/equiv/equiv_make.cc | 16 ++++----- passes/equiv/equiv_miter.cc | 4 +-- passes/equiv/equiv_purge.cc | 4 +-- passes/hierarchy/flatten.cc | 6 ++-- passes/memory/memory_map.cc | 2 +- passes/sat/clk2fflogic.cc | 16 ++++----- passes/sat/cutpoint.cc | 9 +++--- passes/sat/eval.cc | 34 +++++++++---------- passes/sat/formalff.cc | 20 ++++++------ passes/sat/freduce.cc | 4 +-- passes/sat/miter.cc | 32 ++++++++++-------- passes/sat/supercover.cc | 2 +- passes/sat/synthprop.cc | 22 +++++++------ passes/techmap/aigmap.cc | 20 ++++++------ passes/techmap/attrmap.cc | 4 +-- passes/techmap/attrmvcp.cc | 2 +- passes/techmap/clockgate.cc | 31 +++++++++--------- passes/techmap/constmap.cc | 13 +++++--- passes/techmap/dffinit.cc | 12 +++---- passes/techmap/dfflegalize.cc | 8 ++--- passes/techmap/dfflibmap.cc | 2 +- passes/techmap/extract_fa.cc | 2 +- passes/techmap/extract_reduce.cc | 2 +- passes/techmap/flowmap.cc | 14 ++++---- passes/techmap/hilomap.cc | 8 ++--- passes/techmap/insbuf.cc | 10 +++--- passes/techmap/lut2mux.cc | 2 +- passes/techmap/muxcover.cc | 2 +- passes/techmap/nlutmap.cc | 4 +-- passes/techmap/tribuf.cc | 10 +++--- 51 files changed, 289 insertions(+), 275 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index ca5aee7a8..a8b1fb9c2 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -109,7 +109,7 @@ struct Index { int pos = index_wires(info, m); for (auto cell : m->cells()) { - if (known_ops(cell->type) || cell->type.in(TW($scopeinfo), TW($specify2), TW($specify3), TW($input_port), TW($output_port), TW($public))) + if (known_ops(cell->type.ref()) || cell->type.in(TW($scopeinfo), TW($specify2), TW($specify3), TW($input_port), TW($output_port), TW($public))) continue; Module *submodule = m->design->module(cell->type_impl); @@ -628,7 +628,7 @@ struct Index { // an output of a cell Cell *driver = bit.wire->driverCell(); - if (known_ops(driver->type)) { + if (known_ops(driver->type.ref())) { ret = impl_op(cursor, driver, bit.wire->driverPort(), bit.offset); } else { Module *def = cursor.enter(*this, driver); @@ -660,7 +660,7 @@ struct Index { auto &port = instance->getPort(portname); if (bit.offset >= port.size()) log_error("Bit %d of input port %s on instance %s of %s unconnected\n", - bit.offset, design->twines.str(portname).c_str(), instance, design->twines.unescaped_str(instance->type)); + bit.offset, design->twines.str(portname).c_str(), instance, instance->type.unescaped()); ret = visit(cursor, port[bit.offset]); } cursor.enter(*this, instance); @@ -845,7 +845,7 @@ struct AigerWriter : Index { char buf[32]; snprintf(buf, sizeof(buf), "o%d ", i); f->write(buf, strlen(buf)); - std::string name = design->twines.unescaped_str(bit.wire->name); + std::string name = bit.wire->name.unescaped(); f->write(name.data(), name.size()); f->put('\n'); } @@ -858,7 +858,7 @@ struct AigerWriter : Index { char buf[32]; snprintf(buf, sizeof(buf), "i%d ", i); f->write(buf, strlen(buf)); - std::string name = design->twines.unescaped_str(bit.wire->name); + std::string name = bit.wire->name.unescaped(); f->write(name.data(), name.size()); f->put('\n'); } @@ -899,7 +899,7 @@ struct XAigerAnalysis : Index { return false; Cell *driver = bit.wire->driverCell(); - Module *mod = design->module(driver->type); + Module *mod = design->module(driver->type.ref()); if (!mod || !mod->has_attribute(ID::abc9_box_id)) return false; @@ -935,7 +935,7 @@ struct XAigerAnalysis : Index { HierCursor cursor; for (auto box : top_minfo->found_blackboxes) { - Module *def = design->module(box->type); + Module *def = design->module(box->type.ref()); if (!(def && def->has_attribute(ID::abc9_box_id))) for (auto &conn : box->connections_) if (box->port_dir(conn.first) != RTLIL::PD_INPUT) @@ -951,7 +951,7 @@ struct XAigerAnalysis : Index { } for (auto box : top_minfo->found_blackboxes) { - Module *def = design->module(box->type); + Module *def = design->module(box->type.ref()); if (!(def && def->has_attribute(ID::abc9_box_id))) for (auto &conn : box->connections_) if (box->port_dir(conn.first) == RTLIL::PD_INPUT) @@ -1090,9 +1090,9 @@ struct XAigerWriter : AigerWriter { for (auto box : minfo.found_blackboxes) { log_debug(" - %s.%s (type %s): ", cursor.path(), box, - design->twines.unescaped_str(box->type)); + box->type.unescaped()); - Module *box_module = design->module(box->type), *box_derived; + Module *box_module = design->module(box->type.ref()), *box_derived; if (box_module && !box->parameters.empty()) { // TODO: This is potentially costly even if a cached derivation exists @@ -1129,13 +1129,13 @@ struct XAigerWriter : AigerWriter { nonopaque_boxes.clear(); for (auto box : boxes_order) { HierCursor cursor; - Module *def = design->module(box->type); + Module *def = design->module(box->type.ref()); nonopaque_boxes.push_back(std::make_tuple(cursor, box, def)); } for (auto [cursor, box, def] : nonopaque_boxes) { // use `def->meta_->name` not `box->type` as we want the derived type - Cell *holes_wb = holes_module->addCell(NEW_TWINE, IdString(design->twines.str(def->meta_->name))); + Cell *holes_wb = holes_module->addCell(NEW_TWINE, def->meta_->name); int holes_pi_idx = 0; if (map_file.is_open()) { @@ -1159,7 +1159,7 @@ struct XAigerWriter : AigerWriter { } else { // FIXME: hierarchical path log_warning("connection on port %s[%d] of instance %s (type %s) missing, using 1'bx\n", - design->twines.str(port_id).c_str(), i, box, design->twines.unescaped_str(box->type)); + design->twines.str(port_id).c_str(), i, box, box->type.unescaped()); bit = RTLIL::Sx; } @@ -1194,7 +1194,7 @@ struct XAigerWriter : AigerWriter { } else { // FIXME: hierarchical path log_warning("connection on port %s[%d] of instance %s (type %s) missing\n", - design->twines.str(port_id).c_str(), i, box, design->twines.unescaped_str(box->type)); + design->twines.str(port_id).c_str(), i, box, box->type.unescaped()); pad_pi(); continue; } @@ -1211,7 +1211,7 @@ struct XAigerWriter : AigerWriter { holes_wb->setPort(port_id, w); } else { log_error("Ambiguous port direction on %s/%s\n", - design->twines.unescaped_str(box->type), design->twines.str(port_id).c_str()); + box->type.unescaped(), design->twines.str(port_id).c_str()); } } } @@ -1279,7 +1279,7 @@ struct XAigerWriter : AigerWriter { // do emit a proper PO. if (map_file.is_open() && !driven_by_opaque_box.count(SigBit(w, i))) { map_file << "po " << proper_pos_counter << " " << i - << " " << w->name.c_str() << "\n"; + << " " << w->name.str().c_str() << "\n"; } proper_pos_counter++; pos.push_back(std::make_pair(SigBit(w, i), HierCursor{})); @@ -1406,7 +1406,7 @@ struct Aiger2Backend : Backend { continue; if (known_ops(cell.type)) continue; - std::string name = design->twines.unescaped_str(cell.type); + std::string name = TW::str(cell.type); if (col + name.size() + 2 > 72) { log("\n "); col = 0; @@ -1428,7 +1428,7 @@ struct Aiger2Backend : Backend { continue; if (known_ops(cell.type)) continue; - std::string name = design->twines.unescaped_str(cell.type); + std::string name = TW::str(cell.type); if (col + name.size() + 2 > 72) { log("\n "); col = 0; diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index eaccc7fcc..be4e0b957 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -91,7 +91,7 @@ struct BlifDumper const std::string str(RTLIL::IdString id) { - std::string str = design->twines.unescaped_str(id); + std::string str = RTLIL::unescape_id(id); for (size_t i = 0; i < str.size(); i++) if (str[i] == '#' || str[i] == '=' || str[i] == '<' || str[i] == '>') str[i] = '?'; @@ -108,7 +108,7 @@ struct BlifDumper return config->undef_type == "-" || config->undef_type == "+" ? config->undef_out.c_str() : "$undef"; } - std::string str = design->twines.unescaped_str(sig.wire->name); + std::string str = sig.wire->name.unescaped(); for (size_t i = 0; i < str.size(); i++) if (str[i] == '#' || str[i] == '=' || str[i] == '<' || str[i] == '>') str[i] = '?'; @@ -140,9 +140,10 @@ struct BlifDumper { if (!config->gates_mode) return "subckt"; - if (design->module(RTLIL::escape_id(cell_type)) == nullptr) + TwineRef cell_type_ref = TwineSearch(&design->twines).find(RTLIL::escape_id(cell_type)); + if (design->module(cell_type_ref) == nullptr) return "gate"; - if (design->module(RTLIL::escape_id(cell_type))->get_blackbox_attribute()) + if (design->module(cell_type_ref)->get_blackbox_attribute()) return "gate"; return "subckt"; } @@ -150,7 +151,7 @@ struct BlifDumper void dump_params(const char *command, dict ¶ms) { for (auto ¶m : params) { - f << stringf("%s %s ", command, design->twines.unescaped_str(param.first)); + f << stringf("%s %s ", command, RTLIL::unescape_id(param.first).c_str()); if (param.second.flags & RTLIL::CONST_FLAG_STRING) { std::string str = param.second.decode_string(); f << stringf("\""); @@ -237,8 +238,8 @@ struct BlifDumper if (config->unbuf_types.count(cell->type)) { auto portnames = config->unbuf_types.at(cell->type); - TwineRef port_in = design->twines.lookup(portnames.first.str()); - TwineRef port_out = design->twines.lookup(portnames.second.str()); + TwineRef port_in = TwineSearch(&design->twines).find(portnames.first.str()); + TwineRef port_out = TwineSearch(&design->twines).find(portnames.second.str()); f << stringf(".names %s %s\n1 1\n", str(cell->getPort(port_in)).c_str(), str(cell->getPort(port_out)).c_str()); continue; diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index e9d219596..5191da5b8 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -119,17 +119,17 @@ struct BtorWorker template string getinfo(T *obj, bool srcsym = false) { - string infostr = design->twines.unescaped_str(obj->name); + string infostr = obj->name.unescaped(); if (!srcsym && !print_internal_names && infostr[0] == '$') return ""; if (obj->has_attribute(ID::src)) { string src = module && module->design ? module->design->get_src_attribute(obj) : std::string(); if (srcsym && infostr[0] == '$') { std::replace(src.begin(), src.end(), ' ', '_'); - TwineRef src_ref = module->design->twines.lookup(src); + TwineRef src_ref = TwineSearch(&module->design->twines).find(src); if (srcsymbols.count(src) || src_ref != Twine::Null) { for (int i = 1;; i++) { string s = stringf("%s-%d", src, i); - TwineRef s_ref = module->design->twines.lookup(s); + TwineRef s_ref = TwineSearch(&module->design->twines).find(s); if (!srcsymbols.count(s) && s_ref == Twine::Null) { src = s; break; @@ -147,17 +147,17 @@ struct BtorWorker string getinfo(Mem *mem, bool srcsym = false) { - string infostr = design->twines.unescaped_str(mem->memid); + string infostr = RTLIL::unescape_id(mem->memid); if (!srcsym && !print_internal_names && infostr[0] == '$') return ""; if (mem->has_attribute(ID::src)) { string src = module && module->design ? module->design->get_src_attribute(mem) : std::string(); if (srcsym && infostr[0] == '$') { std::replace(src.begin(), src.end(), ' ', '_'); - TwineRef src_ref = module->design->twines.lookup(src); + TwineRef src_ref = TwineSearch(&module->design->twines).find(src); if (srcsymbols.count(src) || src_ref != Twine::Null) { for (int i = 1;; i++) { string s = stringf("%s-%d", src, i); - TwineRef s_ref = module->design->twines.lookup(s); + TwineRef s_ref = TwineSearch(&module->design->twines).find(s); if (!srcsymbols.count(s) && s_ref == Twine::Null) { src = s; break; @@ -727,13 +727,13 @@ struct BtorWorker ywmap_clock_bits[sig_c] |= negedge ? 2 : 1; } - IdString symbol; + std::string symbol; if (sig_q.is_wire()) { Wire *w = sig_q.as_wire(); if (w->port_id == 0) { statewires.insert(w); - symbol = w->name; + symbol = w->name.unescaped(); } } @@ -756,7 +756,7 @@ struct BtorWorker if (symbol.empty() || (!print_internal_names && symbol[0] == '$')) btorf("%d state %d\n", nid, sid); else - btorf("%d state %d %s\n", nid, sid, design->twines.unescaped_str(symbol)); + btorf("%d state %d %s\n", nid, sid, symbol); if (cell->get_bool_attribute(ID(clk2fflogic))) ywmap_state(cell->getPort(TW::D)); // For a clk2fflogic FF the named signal is the D input not the Q output @@ -834,12 +834,12 @@ struct BtorWorker if (asyncwr && syncwr) log_error("Memory %s.%s has mixed async/sync write ports.\n", - module, design->twines.unescaped_str(mem->memid)); + module, RTLIL::unescape_id(mem->memid)); for (auto &port : mem->rd_ports) { if (port.clk_enable) log_error("Memory %s.%s has sync read ports. Please use memory_nordff to convert them first.\n", - module, design->twines.unescaped_str(mem->memid)); + module, RTLIL::unescape_id(mem->memid)); } int data_sid = get_bv_sid(mem->width); @@ -901,7 +901,7 @@ struct BtorWorker if (mem->memid[0] == '$') btorf("%d state %d\n", nid, sid); else - btorf("%d state %d %s\n", nid, sid, design->twines.unescaped_str(mem->memid)); + btorf("%d state %d %s\n", nid, sid, RTLIL::unescape_id(mem->memid)); ywmap_state(cell); @@ -1417,7 +1417,7 @@ struct BtorWorker int nid = it.first; Mem *mem = it.second; - btorf_push(stringf("next %s", design->twines.unescaped_str(mem->memid))); + btorf_push(stringf("next %s", RTLIL::unescape_id(mem->memid))); int abits = ceil_log2(mem->size); @@ -1465,7 +1465,7 @@ struct BtorWorker int nid2 = next_nid++; btorf("%d next %d %d %d%s\n", nid2, sid, nid, nid_head, getinfo(mem)); - btorf_pop(stringf("next %s", design->twines.unescaped_str(mem->memid))); + btorf_pop(stringf("next %s", RTLIL::unescape_id(mem->memid))); } } diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index c4abb2851..3f53d60f4 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -214,7 +214,7 @@ bool is_ff_cell(TwineRef type) bool is_internal_cell(TwineRef type) { - return !type.isPublic() && !type.begins_with("$paramod"); + return !type.is_public() && type.untag().value < STATIC_TWINE_END; } bool is_effectful_cell(TwineRef type) @@ -435,11 +435,11 @@ struct FlowGraph { { for (auto conn : cell->connections()) { if (cell->output(conn.first)) { - if (is_inlinable_cell(cell->type)) + if (is_inlinable_cell(cell->type.ref())) add_defs(node, conn.second, /*is_ff=*/false, /*inlinable=*/true); - else if (is_ff_cell(cell->type)) + else if (is_ff_cell(cell->type.ref())) add_defs(node, conn.second, /*is_ff=*/true, /*inlinable=*/false); - else if (is_internal_cell(cell->type)) + else if (is_internal_cell(cell->type.ref())) add_defs(node, conn.second, /*is_ff=*/false, /*inlinable=*/false); else if (!is_cxxrtl_sync_port(cell, conn.first)) { // Although at first it looks like outputs of user-defined cells may always be inlined, the reality is @@ -687,7 +687,7 @@ struct WireType { } WireType(Type type, const RTLIL::Cell *cell) : type(type), cell_subst(cell) { - log_assert(type == INLINE && is_inlinable_cell(cell->type)); + log_assert(type == INLINE && is_inlinable_cell(cell->type.ref())); } WireType(Type type, RTLIL::SigSpec sig) : type(type), sig_subst(sig) { @@ -1150,17 +1150,17 @@ struct CxxrtlWorker { void dump_cell_expr(const RTLIL::Cell *cell, bool for_debug = false) { // Unary cells - if (is_unary_cell(cell->type)) { + if (is_unary_cell(cell->type.ref())) { f << cell->type.substr(1); - if (is_extending_cell(cell->type)) + if (is_extending_cell(cell->type.ref())) f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u'); f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">("; dump_sigspec_rhs(cell->getPort(TW::A), for_debug); f << ")"; // Binary cells - } else if (is_binary_cell(cell->type)) { + } else if (is_binary_cell(cell->type.ref())) { f << cell->type.substr(1); - if (is_extending_cell(cell->type)) + if (is_extending_cell(cell->type.ref())) f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') << (cell->getParam(ID::B_SIGNED).as_bool() ? 's' : 'u'); f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">("; @@ -1380,14 +1380,14 @@ struct CxxrtlWorker { dump_inlined_cells(inlined_cells); // Elidable cells - if (is_inlinable_cell(cell->type)) { + if (is_inlinable_cell(cell->type.ref())) { f << indent; dump_sigspec_lhs(cell->getPort(TW::Y), for_debug); f << " = "; dump_cell_expr(cell, for_debug); f << ";\n"; // Effectful cells - } else if (is_effectful_cell(cell->type)) { + } else if (is_effectful_cell(cell->type.ref())) { log_assert(!for_debug); // Sync effectful cells are grouped into EFFECT_SYNC nodes in the FlowGraph. @@ -1419,7 +1419,7 @@ struct CxxrtlWorker { f << indent << "}\n"; } // Flip-flops - } else if (is_ff_cell(cell->type)) { + } else if (is_ff_cell(cell->type.ref())) { log_assert(!for_debug); // Clocks might be slices of larger signals but should only ever be single bit if (cell->hasPort(TW::CLK) && is_valid_clock(cell->getPort(TW::CLK))) { @@ -1535,7 +1535,7 @@ struct CxxrtlWorker { } // Internal cells } else if (cell->type.in(TW($input_port), TW($output_port), TW($public))) { - } else if (is_internal_cell(cell->type)) { + } else if (is_internal_cell(cell->type.ref())) { log_cmd_error("Unsupported internal cell `%s'.\n", cell->type); // User cells } else if (for_debug) { @@ -1776,7 +1776,7 @@ struct CxxrtlWorker { for (auto &action : sync->actions) dump_assign(action, for_debug); for (auto &memwr : sync->mem_write_actions) { - TwineRef memid_ref = proc->module->design->twines.lookup(memwr.memid.str()); + TwineRef memid_ref = TwineSearch(&proc->module->design->twines).find(memwr.memid.str()); log_assert(memid_ref != Twine::Null); RTLIL::Memory *memory = proc->module->memories[memid_ref]; std::string valid_index_temp = fresh_temporary(); @@ -2164,10 +2164,10 @@ struct CxxrtlWorker { } for (auto cell : module->cells()) { // Async and initial effectful cells have additional state, which must be reset as well. - if (is_effectful_cell(cell->type)) + if (is_effectful_cell(cell->type.ref())) if (!cell->getParam(ID::TRG_ENABLE).as_bool() || cell->getParam(ID::TRG_WIDTH).as_int() == 0) f << indent << mangle(cell) << " = {};\n"; - if (is_internal_cell(cell->type)) + if (is_internal_cell(cell->type.ref())) continue; f << indent << mangle(cell); RTLIL::Module *cell_module = module->design->module(cell->type_impl); @@ -2289,7 +2289,7 @@ struct CxxrtlWorker { f << indent << "if (" << mangle(&mem) << ".commit(observer)) changed = true;\n"; } for (auto cell : module->cells()) { - if (is_internal_cell(cell->type)) + if (is_internal_cell(cell->type.ref())) continue; const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : "."; f << indent << "if (" << mangle(cell) << access << "commit(observer)) changed = true;\n"; @@ -2584,7 +2584,7 @@ struct CxxrtlWorker { f << indent << "}\n"; if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) { for (auto cell : module->cells()) { - if (is_internal_cell(cell->type)) + if (is_internal_cell(cell->type.ref())) continue; const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : "."; f << indent << mangle(cell) << access; @@ -2694,7 +2694,7 @@ struct CxxrtlWorker { bool has_cells = false; for (auto cell : module->cells()) { // Async and initial effectful cells have additional state, which requires storage. - if (is_effectful_cell(cell->type)) { + if (is_effectful_cell(cell->type.ref())) { if (cell->getParam(ID::TRG_ENABLE).as_bool() && cell->getParam(ID::TRG_WIDTH).as_int() == 0) f << indent << "value<1> " << mangle(cell) << ";\n"; // async initial cell if (!cell->getParam(ID::TRG_ENABLE).as_bool() && cell->type == TW($print)) @@ -2702,7 +2702,7 @@ struct CxxrtlWorker { if (!cell->getParam(ID::TRG_ENABLE).as_bool() && cell->type == TW($check)) f << indent << "value<2> " << mangle(cell) << ";\n"; // {EN, A} } - if (is_internal_cell(cell->type)) + if (is_internal_cell(cell->type.ref())) continue; dump_attrs(cell); RTLIL::Module *cell_module = module->design->module(cell->type_impl); @@ -2820,7 +2820,7 @@ struct CxxrtlWorker { topo_design.node(module); for (auto cell : module->cells()) { - if (is_internal_cell(cell->type) || is_cxxrtl_blackbox_cell(cell)) + if (is_internal_cell(cell->type.ref()) || is_cxxrtl_blackbox_cell(cell)) continue; RTLIL::Module *cell_module = design->module(cell->type_impl); log_assert(cell_module != nullptr); @@ -3034,7 +3034,7 @@ struct CxxrtlWorker { } // Effectful cells may be triggered on posedge/negedge events. - if (is_effectful_cell(cell->type) && cell->getParam(ID::TRG_ENABLE).as_bool()) { + if (is_effectful_cell(cell->type.ref()) && cell->getParam(ID::TRG_ENABLE).as_bool()) { for (size_t i = 0; i < (size_t)cell->getParam(ID::TRG_WIDTH).as_int(); i++) { RTLIL::SigBit trg = cell->getPort(TW::TRG).extract(i, 1); if (is_valid_clock(trg)) @@ -3175,9 +3175,9 @@ struct CxxrtlWorker { // Discover nodes reachable from primary outputs (i.e. members) and collect reachable wire users. pool worklist; for (auto node : flow.nodes) { - if (node->type == FlowGraph::Node::Type::CELL_EVAL && !is_internal_cell(node->cell->type)) + if (node->type == FlowGraph::Node::Type::CELL_EVAL && !is_internal_cell(node->cell->type.ref())) worklist.insert(node); // node evaluates a submodule - else if (node->type == FlowGraph::Node::Type::CELL_EVAL && is_effectful_cell(node->cell->type)) + else if (node->type == FlowGraph::Node::Type::CELL_EVAL && is_effectful_cell(node->cell->type.ref())) worklist.insert(node); // node has async effects else if (node->type == FlowGraph::Node::Type::EFFECT_SYNC) worklist.insert(node); // node has sync effects @@ -3224,7 +3224,7 @@ struct CxxrtlWorker { FlowGraph::Node *node = *flow.wire_comb_defs[wire].begin(); switch (node->type) { case FlowGraph::Node::Type::CELL_EVAL: - if (!is_inlinable_cell(node->cell->type)) continue; + if (!is_inlinable_cell(node->cell->type.ref())) continue; wire_type = {WireType::INLINE, node->cell}; // wire replaced with cell break; case FlowGraph::Node::Type::CONNECT: @@ -3242,7 +3242,7 @@ struct CxxrtlWorker { for (auto node : node_order) if (live_nodes[node]) { if (node->type == FlowGraph::Node::Type::CELL_EVAL && - is_effectful_cell(node->cell->type) && + is_effectful_cell(node->cell->type.ref()) && node->cell->getParam(ID::TRG_ENABLE).as_bool() && node->cell->getParam(ID::TRG_WIDTH).as_int() != 0) effect_sync_cells[make_pair(node->cell->getPort(TW::TRG), node->cell->getParam(ID::TRG_POLARITY))].push_back(node->cell); @@ -3362,7 +3362,7 @@ struct CxxrtlWorker { FlowGraph::Node *node = *flow.wire_comb_defs[wire].begin(); switch (node->type) { case FlowGraph::Node::Type::CELL_EVAL: - if (!is_inlinable_cell(node->cell->type)) continue; + if (!is_inlinable_cell(node->cell->type.ref())) continue; debug_wire_type = {WireType::INLINE, node->cell}; // wire replaced with cell break; case FlowGraph::Node::Type::CONNECT: diff --git a/backends/simplec/simplec.cc b/backends/simplec/simplec.cc index 39744581a..ced0de639 100644 --- a/backends/simplec/simplec.cc +++ b/backends/simplec/simplec.cc @@ -337,7 +337,7 @@ struct SimplecWorker topo.sort(); for (int i = 0; i < GetSize(topo.sorted); i++) - topoidx[mod->cell(design->twines.lookup(topo.sorted[i].str()))] = i; + topoidx[mod->cell(TwineSearch(&design->twines).find(topo.sorted[i].str()))] = i; string ifdef_name = stringf("yosys_simplec_%s_state_t", cid(RTLIL::IdString(design->twines.str(mod->meta_->name)))); @@ -527,7 +527,7 @@ struct SimplecWorker for (auto outbit : bit2output[work->module][bit]) { Module *parent_mod = work->parent->module; - Cell *parent_cell = parent_mod->cell(parent_mod->design->twines.lookup(work->hiername.str())); + Cell *parent_cell = parent_mod->cell(TwineSearch(&parent_mod->design->twines).find(work->hiername.str())); TwineRef port_name = outbit.wire->meta_->name; int port_offset = outbit.offset; diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index b0dd77364..7c923007f 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -1867,7 +1867,7 @@ struct Smt2Backend : public Backend { for (auto mod : design->modules()) { module_deps[mod] = std::set(); for (auto cell : mod->cells()) { - TwineRef cell_type_ref = design->twines.lookup(cell->type.str()); + TwineRef cell_type_ref = TwineSearch(&design->twines).find(cell->type.str()); if (cell_type_ref != Twine::Null && design->has(cell_type_ref)) module_deps[mod].insert(design->module(cell_type_ref)); } diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 832a5986a..b9052fba7 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -104,7 +104,7 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De for (RTLIL::Wire *wire : ports) { log_assert(wire != NULL); RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width); - TwineRef wire_name_ref = design->twines.lookup(wire->name.str()); + TwineRef wire_name_ref = TwineSearch(&design->twines).find(wire->name.str()); if (cell->hasPort(wire_name_ref)) { sig = sigmap(cell->getPort(wire_name_ref)); sig.extend_u0(wire->width, false); diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 0d2b99bb7..e9c27b4a8 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -269,7 +269,7 @@ end_of_header: else log_abort(); - RTLIL::Wire* n0 = module->wire(design->twines.lookup(stringf("$aiger%d$0", aiger_autoidx))); + RTLIL::Wire* n0 = module->wire(TwineSearch(&design->twines).find(stringf("$aiger%d$0", aiger_autoidx))); if (n0) module->connect(n0, State::S0); @@ -294,7 +294,7 @@ end_of_header: log_assert(l1 < latches.size()); wire = latches[l1]; } else if (c == 'o') { - wire = module->wire(design->twines.lookup(escaped_s.str())); + wire = module->wire(TwineSearch(&design->twines).find(escaped_s.str())); log_assert(l1 < outputs.size()); if (wire) { // Could have been renamed by a latch @@ -347,16 +347,16 @@ RTLIL::Wire* AigerReader::createWireIfNotExists(RTLIL::Module *module, unsigned const unsigned variable = literal >> 1; const bool invert = literal & 1; RTLIL::IdString wire_name(stringf("$aiger%d$%d%s", aiger_autoidx, variable, invert ? "b" : "")); - RTLIL::Wire *wire = module->wire(design->twines.lookup(wire_name.str())); + RTLIL::Wire *wire = module->wire(TwineSearch(&design->twines).find(wire_name.str())); if (wire) return wire; log_debug2("Creating %s\n", wire_name.c_str()); wire = module->addWire(Twine{wire_name.str()}); wire->port_input = wire->port_output = false; if (!invert) return wire; RTLIL::IdString wire_inv_name(stringf("$aiger%d$%d", aiger_autoidx, variable)); - RTLIL::Wire *wire_inv = module->wire(design->twines.lookup(wire_inv_name.str())); + RTLIL::Wire *wire_inv = module->wire(TwineSearch(&design->twines).find(wire_inv_name.str())); if (wire_inv) { - if (module->cell(design->twines.lookup(wire_inv_name.str()))) return wire; + if (module->cell(TwineSearch(&design->twines).find(wire_inv_name.str()))) return wire; } else { log_debug2("Creating %s\n", wire_inv_name.c_str()); @@ -402,7 +402,7 @@ void AigerReader::parse_xaiger() else log_abort(); - RTLIL::Wire* n0 = module->wire(design->twines.lookup(stringf("$aiger%d$0", aiger_autoidx))); + RTLIL::Wire* n0 = module->wire(TwineSearch(&design->twines).find(stringf("$aiger%d$0", aiger_autoidx))); if (n0) module->connect(n0, State::S0); @@ -426,7 +426,7 @@ void AigerReader::parse_xaiger() uint32_t rootNodeID = parse_xaiger_literal(f); uint32_t cutLeavesM = parse_xaiger_literal(f); log_debug2("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM); - RTLIL::Wire *output_sig = module->wire(design->twines.lookup(stringf("$aiger%d$%d", aiger_autoidx, rootNodeID))); + RTLIL::Wire *output_sig = module->wire(TwineSearch(&design->twines).find(stringf("$aiger%d$%d", aiger_autoidx, rootNodeID))); log_assert(output_sig); uint32_t nodeID; RTLIL::SigSpec input_sig; @@ -437,7 +437,7 @@ void AigerReader::parse_xaiger() log_debug("\tLUT '$lut$aiger%d$%d' input %d is constant!\n", aiger_autoidx, rootNodeID, cutLeavesM); continue; } - RTLIL::Wire *wire = module->wire(design->twines.lookup(stringf("$aiger%d$%d", aiger_autoidx, nodeID))); + RTLIL::Wire *wire = module->wire(TwineSearch(&design->twines).find(stringf("$aiger%d$%d", aiger_autoidx, nodeID))); log_assert(wire); input_sig.append(wire); } @@ -456,7 +456,7 @@ void AigerReader::parse_xaiger() log_assert(o.wire == nullptr); lut_mask.set(gray, o.data); } - RTLIL::Cell *output_cell = module->cell(design->twines.lookup(stringf("$and$aiger%d$%d", aiger_autoidx, rootNodeID))); + RTLIL::Cell *output_cell = module->cell(TwineSearch(&design->twines).find(stringf("$and$aiger%d$%d", aiger_autoidx, rootNodeID))); log_assert(output_cell); module->remove(output_cell); module->addLut(Twine{stringf("$lut$aiger%d$%d", aiger_autoidx, rootNodeID)}, input_sig, output_sig, std::move(lut_mask)); @@ -548,7 +548,7 @@ void AigerReader::parse_aiger_ascii() // Parse latches RTLIL::Wire *clk_wire = nullptr; if (L > 0 && !clk_name.empty()) { - clk_wire = module->wire(design->twines.lookup(clk_name.str())); + clk_wire = module->wire(TwineSearch(&design->twines).find(clk_name.str())); log_assert(!clk_wire); log_debug2("Creating %s\n", clk_name.c_str()); clk_wire = module->addWire(Twine{clk_name.str()}); @@ -675,7 +675,7 @@ void AigerReader::parse_aiger_binary() // Parse latches RTLIL::Wire *clk_wire = nullptr; if (L > 0 && !clk_name.empty()) { - clk_wire = module->wire(design->twines.lookup(clk_name.str())); + clk_wire = module->wire(TwineSearch(&design->twines).find(clk_name.str())); log_assert(!clk_wire); log_debug2("Creating %s\n", clk_name.c_str()); clk_wire = module->addWire(Twine{clk_name.str()}); @@ -830,7 +830,7 @@ void AigerReader::post_process() // Cope with the fact that a CI might be identical // to a PI (necessary due to ABC); in those cases // simply connect the latter to the former - existing = module->wire(design->twines.lookup(escaped_s.str())); + existing = module->wire(TwineSearch(&design->twines).find(escaped_s.str())); if (!existing) module->rename(wire, design->twines.add(Twine{escaped_s.str()})); else { @@ -841,7 +841,7 @@ void AigerReader::post_process() } else { RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index); - existing = module->wire(design->twines.lookup(indexed_name.str())); + existing = module->wire(TwineSearch(&design->twines).find(indexed_name.str())); if (!existing) module->rename(wire, design->twines.add(Twine{indexed_name.str()})); else { @@ -875,7 +875,7 @@ void AigerReader::post_process() // Cope with the fact that a CO might be identical // to a PO (necessary due to ABC); in those cases // simply connect the latter to the former - existing = module->wire(design->twines.lookup(escaped_s.str())); + existing = module->wire(TwineSearch(&design->twines).find(escaped_s.str())); if (!existing) module->rename(wire, design->twines.add(Twine{escaped_s.str()})); else { @@ -888,7 +888,7 @@ void AigerReader::post_process() } else { RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index); - existing = module->wire(design->twines.lookup(indexed_name.str())); + existing = module->wire(TwineSearch(&design->twines).find(indexed_name.str())); if (!existing) module->rename(wire, design->twines.add(Twine{indexed_name.str()})); else { @@ -912,7 +912,7 @@ void AigerReader::post_process() } } else if (type == "box") { - RTLIL::Cell* cell = module->cell(design->twines.lookup(stringf("$box%d", variable))); + RTLIL::Cell* cell = module->cell(TwineSearch(&design->twines).find(stringf("$box%d", variable))); if (!cell) log_debug("Box %d (%s) no longer exists.\n", variable, log_id(escaped_s)); else @@ -930,7 +930,7 @@ void AigerReader::post_process() if (min == 0 && max == 0) continue; - RTLIL::Wire *wire = module->wire(design->twines.lookup(name.str())); + RTLIL::Wire *wire = module->wire(TwineSearch(&design->twines).find(name.str())); if (wire) module->rename(wire, design->twines.add(Twine{RTLIL::escape_id(stringf("%s[%d]", name.str(), 0))})); @@ -939,7 +939,7 @@ void AigerReader::post_process() bool port_input = false, port_output = false; for (int i = min; i <= max; i++) { RTLIL::IdString other_name = name.str() + stringf("[%d]", i); - RTLIL::Wire *other_wire = module->wire(design->twines.lookup(other_name.str())); + RTLIL::Wire *other_wire = module->wire(TwineSearch(&design->twines).find(other_name.str())); if (other_wire) { port_input = port_input || other_wire->port_input; port_output = port_output || other_wire->port_output; @@ -953,7 +953,7 @@ void AigerReader::post_process() for (int i = min; i <= max; i++) { RTLIL::IdString other_name = stringf("%s[%d]", name, i); - RTLIL::Wire *other_wire = module->wire(design->twines.lookup(other_name.str())); + RTLIL::Wire *other_wire = module->wire(TwineSearch(&design->twines).find(other_name.str())); if (other_wire) { other_wire->port_input = false; other_wire->port_output = false; diff --git a/frontends/aiger2/xaiger.cc b/frontends/aiger2/xaiger.cc index 7decbe916..d279eb7b6 100644 --- a/frontends/aiger2/xaiger.cc +++ b/frontends/aiger2/xaiger.cc @@ -414,7 +414,7 @@ struct Xaiger2Frontend : public Frontend { log_error("Bad map file: primary output literal out of range\n"); if (bits[lit] == RTLIL::Sm) log_error("Bad map file: primary output literal is a marker\n"); - Wire *w = module->wire(design->twines.lookup(name)); + Wire *w = module->wire(TwineSearch(&design->twines).find(name)); if (!w || woffset < 0 || woffset >= w->width) log_error("Map file references non-existent signal bit %s[%d]\n", name.c_str(), woffset); @@ -434,8 +434,8 @@ struct Xaiger2Frontend : public Frontend { log_error("Bad map file: pseudo primary output literal out of range\n"); if (bits[lit] == RTLIL::Sm) log_error("Bad map file: pseudo primary output literal is a marker\n"); - Cell *cell = module->cell(design->twines.lookup(box_name)); - auto box_port_ref = design->twines.lookup(box_port); + Cell *cell = module->cell(TwineSearch(&design->twines).find(box_name)); + auto box_port_ref = TwineSearch(&design->twines).find(box_port); if (!cell || !cell->hasPort(box_port_ref)) log_error("Map file references non-existent box port %s/%s\n", box_name.c_str(), box_port.c_str()); diff --git a/frontends/json/jsonparse.cc b/frontends/json/jsonparse.cc index 04feeb74d..dd7a96021 100644 --- a/frontends/json/jsonparse.cc +++ b/frontends/json/jsonparse.cc @@ -357,7 +357,7 @@ void json_import(Design *design, string &modname, JsonNode *node) if (port_bits_node->type != 'A') log_error("JSON port node '%s' has non-array bits attribute.\n", port_name.unescape()); - Wire *port_wire = module->wire(design->twines.lookup(port_name.str())); + Wire *port_wire = module->wire(TwineSearch(&design->twines).find(port_name.str())); if (port_wire == nullptr) port_wire = module->addWire(Twine{port_name.str()}, GetSize(port_bits_node->data_array)); @@ -455,7 +455,7 @@ void json_import(Design *design, string &modname, JsonNode *node) if (bits_node->type != 'A') log_error("JSON netname node '%s' has non-array bits attribute.\n", net_name.unescape()); - Wire *wire = module->wire(design->twines.lookup(net_name.str())); + Wire *wire = module->wire(TwineSearch(&design->twines).find(net_name.str())); if (wire == nullptr) wire = module->addWire(Twine{net_name.str()}, GetSize(bits_node->data_array)); diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index 7da45363f..1517adf62 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -47,7 +47,7 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *& return *(expr++) == '0' ? RTLIL::State::S0 : RTLIL::State::S1; std::string id = RTLIL::escape_id(std::string(expr, id_len)); - TwineRef wire_ref = module->design->twines.lookup(id); + TwineRef wire_ref = TwineSearch(&module->design->twines).find(id); RTLIL::Wire *w = module->wire(wire_ref); if (!w) log_error("Can't resolve wire name %s in %s.\n", RTLIL::unescape_id(id), module); @@ -202,8 +202,8 @@ static void create_latch_ff_wires(RTLIL::Module *module, const LibertyAst *node) static std::pair find_latch_ff_wires(RTLIL::Module *module, const LibertyAst *node) { - TwineRef iq_ref = module->design->twines.lookup(RTLIL::escape_id(node->args.at(0))); - TwineRef iqn_ref = module->design->twines.lookup(RTLIL::escape_id(node->args.at(1))); + TwineRef iq_ref = TwineSearch(&module->design->twines).find(RTLIL::escape_id(node->args.at(0))); + TwineRef iqn_ref = TwineSearch(&module->design->twines).find(RTLIL::escape_id(node->args.at(1))); auto* iq_wire = module->wire(iq_ref); auto* iqn_wire = module->wire(iqn_ref); log_assert(iq_wire && iqn_wire); @@ -613,7 +613,7 @@ struct LibertyFrontend : public Frontend { RTLIL::Module *module = new RTLIL::Module; module->design = design; std::string cell_name = RTLIL::escape_id(cell->args.at(0)); - TwineRef cell_name_ref = design->twines.lookup(cell_name); + TwineRef cell_name_ref = TwineSearch(&design->twines).find(cell_name); module->meta_->name = design->twines.add(Twine{cell_name}); if (flag_lib) @@ -734,7 +734,7 @@ struct LibertyFrontend : public Frontend { if (flag_lib && dir->value == "internal") continue; - TwineRef wire_ref = module->design->twines.lookup(RTLIL::escape_id(node->args.at(0))); + TwineRef wire_ref = TwineSearch(&module->design->twines).find(RTLIL::escape_id(node->args.at(0))); RTLIL::Wire *wire = module->wire(wire_ref); log_assert(wire); diff --git a/frontends/rpc/rpc_frontend.cc b/frontends/rpc/rpc_frontend.cc index 8f41c79f7..da419e57b 100644 --- a/frontends/rpc/rpc_frontend.cc +++ b/frontends/rpc/rpc_frontend.cc @@ -179,7 +179,7 @@ struct RpcModule : RTLIL::Module { else derived_name = "$paramod" + stripped_name + parameter_info; - if (design->has(design->twines.lookup(derived_name))) { + if (design->has(TwineSearch(&design->twines).find(derived_name))) { log("Found cached RTLIL representation for module `%s'.\n", derived_name); } else { std::string command, input; diff --git a/passes/cmds/abstract.cc b/passes/cmds/abstract.cc index f0d73681f..4f93a71f1 100644 --- a/passes/cmds/abstract.cc +++ b/passes/cmds/abstract.cc @@ -496,7 +496,7 @@ struct AbstractPass : public Pass { } break; case Enable::ActiveLow: case Enable::ActiveHigh: { - Wire *enable_wire = mod->wire(mod->design->twines.lookup("\\" + enable_name)); + Wire *enable_wire = mod->wire(TwineSearch(&mod->design->twines).find("\\" + enable_name)); if (!enable_wire) log_cmd_error("Enable wire %s not found in module %s\n", enable_name, log_id(mod)); if (GetSize(enable_wire) != 1) diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 7eb7caa0d..aa42a0d44 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -35,7 +35,7 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const std::string escaped_name = RTLIL::escape_id(name); std::string escaped_enable_name = (enable_name != "") ? RTLIL::escape_id(enable_name) : ""; RTLIL::Design *design = module->design; - RTLIL::Wire *wire = module->wire(design->twines.lookup(escaped_name)); + RTLIL::Wire *wire = module->wire(TwineSearch(&design->twines).find(escaped_name)); log_assert(is_formal_celltype(celltype)); if (wire == nullptr) { @@ -50,7 +50,7 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const log("Added $%s cell for wire \"%s.%s\"\n", celltype, log_id(module), name); } else { - RTLIL::Wire *enable_wire = module->wire(design->twines.lookup(escaped_enable_name)); + RTLIL::Wire *enable_wire = module->wire(TwineSearch(&design->twines).find(escaped_enable_name)); if(enable_wire == nullptr) log_error("Could not find enable wire with name \"%s\".\n", enable_name); @@ -64,7 +64,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n { RTLIL::Wire *wire = nullptr; name = RTLIL::escape_id(name); - TwineRef name_ref = design->twines.lookup(name); + TwineRef name_ref = TwineSearch(&design->twines).find(name); if (name_ref != Twine::Null) { diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index 44fa5c668..4cd2d650b 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -485,7 +485,7 @@ struct CheckPass : public Pass { SigBit prev; for (auto it = loop.rbegin(); it != loop.rend(); it++) if (it->second != -1) { // skip the fallback helper nodes - prev = SigBit(module->wire(module->design->twines.lookup(it->first.str())), it->second); + prev = SigBit(module->wire(TwineSearch(&module->design->twines).find(it->first.str())), it->second); break; } log_assert(prev != SigBit()); @@ -517,9 +517,9 @@ struct CheckPass : public Pass { } }; - Wire *wire = module->wire(module->design->twines.lookup(pair.first.str())); + Wire *wire = module->wire(TwineSearch(&module->design->twines).find(pair.first.str())); log_assert(wire); - SigBit bit(module->wire(module->design->twines.lookup(pair.first.str())), pair.second); + SigBit bit(module->wire(TwineSearch(&module->design->twines).find(pair.first.str())), pair.second); log_assert(driver_cells.count(bit)); Cell *driver = driver_cells.at(bit); diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index 44f1d5c5c..e48aaa8bd 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -198,7 +198,7 @@ struct ConnectPass : public Pass { if (flag_nounset) log_cmd_error("Can't use -port together with -nounset.\n"); - if (module->cell(module->design->twines.lookup(RTLIL::escape_id(port_cell))) == nullptr) + if (module->cell(TwineSearch(&module->design->twines).find(RTLIL::escape_id(port_cell))) == nullptr) log_cmd_error("Can't find cell %s.\n", port_cell); RTLIL::SigSpec sig; @@ -206,9 +206,9 @@ struct ConnectPass : public Pass { log_cmd_error("Failed to parse port expression `%s'.\n", port_expr); if (!flag_assert) { - module->cell(module->design->twines.lookup(RTLIL::escape_id(port_cell)))->setPort(module->design->twines.lookup(RTLIL::escape_id(port_port)), sigmap(sig)); + module->cell(TwineSearch(&module->design->twines).find(RTLIL::escape_id(port_cell)))->setPort(TwineSearch(&module->design->twines).find(RTLIL::escape_id(port_port)), sigmap(sig)); } else { - SigSpec cur = module->cell(module->design->twines.lookup(RTLIL::escape_id(port_cell)))->getPort(module->design->twines.lookup(RTLIL::escape_id(port_port))); + SigSpec cur = module->cell(TwineSearch(&module->design->twines).find(RTLIL::escape_id(port_cell)))->getPort(TwineSearch(&module->design->twines).find(RTLIL::escape_id(port_port))); if (sigmap(sig) != sigmap(cur)) { log_cmd_error("Expected connection not present: expected %s, found %s.\n", log_signal(sig), log_signal(cur)); } diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index 2f594ec75..55187b9ec 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -104,7 +104,7 @@ struct DeletePass : public Pass { if (design->selected(module, cell)) delete_cells.insert(cell); if (cell->has_memid() && - delete_mems.count(design->twines.lookup(cell->parameters.at(ID::MEMID).decode_string())) != 0) + delete_mems.count(TwineSearch(&design->twines).find(cell->parameters.at(ID::MEMID).decode_string())) != 0) delete_cells.insert(cell); } diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index d755bddf5..61cbb3b85 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -31,11 +31,11 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std:: from_name = RTLIL::escape_id(from_name); to_name = RTLIL::escape_id(to_name); - TwineRef to_ref = module->design->twines.lookup(to_name); + TwineRef to_ref = TwineSearch(&module->design->twines).find(to_name); if (module->count_id(to_ref)) log_cmd_error("There is already an object `%s' in module `%s'.\n", RTLIL::unescape_id(to_name), log_id(module)); - TwineRef from_ref = module->design->twines.lookup(from_name); + TwineRef from_ref = TwineSearch(&module->design->twines).find(from_name); RTLIL::Wire *wire_to_rename = module->wire(from_ref); RTLIL::Cell *cell_to_rename = module->cell(from_ref); @@ -109,7 +109,7 @@ static IdString derive_name_from_cell_output_wire(const RTLIL::Cell *cell, strin RTLIL::Wire *wire; if (move_to_cell) { - TwineRef name_ref = cell->module->design->twines.lookup(name); + TwineRef name_ref = TwineSearch(&cell->module->design->twines).find(name); if (name_ref == Twine::Null || (!(wire = cell->module->wire(name_ref)) || !(wire->port_input || wire->port_output))) return name; } @@ -425,7 +425,7 @@ struct RenamePass : public Pass { new_cell_names[cell] = derive_name_from_cell_output_wire(cell, cell_suffix, flag_move_to_cell); for (auto &[cell, new_name] : new_cell_names) { if (flag_move_to_cell) { - TwineRef new_name_ref = module->design->twines.lookup(new_name.str()); + TwineRef new_name_ref = TwineSearch(&module->design->twines).find(new_name.str()); RTLIL::Wire *found_wire = new_name_ref != Twine::Null ? module->wire(new_name_ref) : nullptr; if (found_wire) { std::string wire_suffix = cell_suffix; @@ -462,7 +462,7 @@ struct RenamePass : public Pass { TwineRef buf_ref; do { buf = stringf("\\%s%d%s", pattern_prefix, counter++, pattern_suffix); - buf_ref = module->design->twines.lookup(buf.str()); + buf_ref = TwineSearch(&module->design->twines).find(buf.str()); } while (buf_ref != Twine::Null && module->wire(buf_ref) != nullptr); new_wire_names[wire] = buf; } @@ -473,7 +473,7 @@ struct RenamePass : public Pass { TwineRef buf_ref; do { buf = stringf("\\%s%d%s", pattern_prefix, counter++, pattern_suffix); - buf_ref = module->design->twines.lookup(buf.str()); + buf_ref = TwineSearch(&module->design->twines).find(buf.str()); } while (buf_ref != Twine::Null && module->cell(buf_ref) != nullptr); new_cell_names[cell] = buf; } diff --git a/passes/cmds/timeest.cc b/passes/cmds/timeest.cc index fa984c489..5d31cfd4b 100644 --- a/passes/cmds/timeest.cc +++ b/passes/cmds/timeest.cc @@ -424,12 +424,12 @@ struct TimeestPass : Pass { std::optional clk; if (clk_domain_specified) { - if (!m->wire(m->design->twines.lookup(RTLIL::escape_id(clk_name)))) { + if (!m->wire(TwineSearch(&m->design->twines).find(RTLIL::escape_id(clk_name)))) { log_warning("No domain '%s' in module %s\n", clk_name.c_str(), m); continue; } - clk = SigBit(m->wire(m->design->twines.lookup(RTLIL::escape_id(clk_name))), 0); + clk = SigBit(m->wire(TwineSearch(&m->design->twines).find(RTLIL::escape_id(clk_name))), 0); } EstimateSta sta(m, clk, /*top_port_endpoints=*/ !clk_domain_specified); diff --git a/passes/cmds/viz.cc b/passes/cmds/viz.cc index 4f2b887c0..c72b49095 100644 --- a/passes/cmds/viz.cc +++ b/passes/cmds/viz.cc @@ -708,8 +708,8 @@ struct VizWorker c->attributes.erase(vg_id); for (auto g : graph.nodes) { for (auto name : g->names()) { - auto w = module->wire(module->design->twines.lookup(name.str())); - auto c = module->cell(module->design->twines.lookup(name.str())); + auto w = module->wire(TwineSearch(&module->design->twines).find(name.str())); + auto c = module->cell(TwineSearch(&module->design->twines).find(name.str())); if (w) w->attributes[vg_id] = g->index; if (c) c->attributes[vg_id] = g->index; } diff --git a/passes/equiv/equiv_add.cc b/passes/equiv/equiv_add.cc index 492608e81..d5f79491a 100644 --- a/passes/equiv/equiv_add.cc +++ b/passes/equiv/equiv_add.cc @@ -56,8 +56,8 @@ struct EquivAddPass : public Pass { if (GetSize(args) == 4 && args[1] == "-cell") { - Cell *gold_cell = module->cell(design->twines.lookup(RTLIL::escape_id(args[2]))); - Cell *gate_cell = module->cell(design->twines.lookup(RTLIL::escape_id(args[3]))); + Cell *gold_cell = module->cell(TwineSearch(&design->twines).find(RTLIL::escape_id(args[2]))); + Cell *gate_cell = module->cell(TwineSearch(&design->twines).find(RTLIL::escape_id(args[3]))); if (gold_cell == nullptr) { if (try_mode) { diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index dcc79601c..c79205472 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -156,8 +156,8 @@ struct EquivMakeWorker for (auto id : wire_names) { - TwineRef gold_id = equiv_mod->design->twines.lookup(id.str() + "_gold"); - TwineRef gate_id = equiv_mod->design->twines.lookup(id.str() + "_gate"); + TwineRef gold_id = TwineSearch(&equiv_mod->design->twines).find(id.str() + "_gold"); + TwineRef gate_id = TwineSearch(&equiv_mod->design->twines).find(id.str() + "_gate"); Wire *gold_wire = equiv_mod->wire(gold_id); Wire *gate_wire = equiv_mod->wire(gate_id); @@ -333,8 +333,8 @@ struct EquivMakeWorker for (auto id : cell_names) { - TwineRef gold_id = equiv_mod->design->twines.lookup(id.str() + "_gold"); - TwineRef gate_id = equiv_mod->design->twines.lookup(id.str() + "_gate"); + TwineRef gold_id = TwineSearch(&equiv_mod->design->twines).find(id.str() + "_gold"); + TwineRef gate_id = TwineSearch(&equiv_mod->design->twines).find(id.str() + "_gate"); Cell *gold_cell = equiv_mod->cell(gold_id); Cell *gate_cell = equiv_mod->cell(gate_id); @@ -380,7 +380,7 @@ struct EquivMakeWorker } equiv_mod->remove(gate_cell); - equiv_mod->rename(gold_cell, equiv_mod->design->twines.lookup(id.str())); + equiv_mod->rename(gold_cell, TwineSearch(&equiv_mod->design->twines).find(id.str())); } } @@ -492,9 +492,9 @@ struct EquivMakePass : public Pass { if (argidx+3 != args.size()) log_cmd_error("Invalid number of arguments.\n"); - worker.gold_mod = design->module(design->twines.lookup(RTLIL::escape_id(args[argidx]))); - worker.gate_mod = design->module(design->twines.lookup(RTLIL::escape_id(args[argidx+1]))); - worker.equiv_mod = design->module(design->twines.lookup(RTLIL::escape_id(args[argidx+2]))); + worker.gold_mod = design->module(TwineSearch(&design->twines).find(RTLIL::escape_id(args[argidx]))); + worker.gate_mod = design->module(TwineSearch(&design->twines).find(RTLIL::escape_id(args[argidx+1]))); + worker.equiv_mod = design->module(TwineSearch(&design->twines).find(RTLIL::escape_id(args[argidx+2]))); if (worker.gold_mod == nullptr) log_cmd_error("Can't find gold module %s.\n", args[argidx]); diff --git a/passes/equiv/equiv_miter.cc b/passes/equiv/equiv_miter.cc index 8f9c063a5..65cc64c07 100644 --- a/passes/equiv/equiv_miter.cc +++ b/passes/equiv/equiv_miter.cc @@ -160,7 +160,7 @@ struct EquivMiterWorker vector chunks = sig.chunks(); for (auto &c : chunks) if (c.wire != NULL) - c.wire = mod->wire(mod->design->twines.lookup(c.wire->name.str())); + c.wire = mod->wire(TwineSearch(&mod->design->twines).find(c.wire->name.str())); sig = chunks; } }; @@ -323,7 +323,7 @@ struct EquivMiterPass : public Pass { // TODO disable signorm due to rewrite_sigspecs assert design->sigNormalize(false); - if (design->module(design->twines.lookup(worker.miter_name.str()))) + if (design->module(TwineSearch(&design->twines).find(worker.miter_name.str()))) log_cmd_error("Miter module %s already exists.\n", log_id(worker.miter_name)); worker.source_module = nullptr; diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc index af7415ca4..30d143f30 100644 --- a/passes/equiv/equiv_purge.cc +++ b/passes/equiv/equiv_purge.cc @@ -47,7 +47,7 @@ struct EquivPurgeWorker while (1) { std::string name = stringf("\\equiv_%d", name_cnt++); - if (module->count_id(module->design->twines.lookup(name))) + if (module->count_id(TwineSearch(&module->design->twines).find(name))) continue; Wire *wire = module->addWire(Twine{name}, GetSize(sig)); @@ -74,7 +74,7 @@ struct EquivPurgeWorker while (1) { std::string name = stringf("\\equiv_%d", name_cnt++); - if (module->count_id(module->design->twines.lookup(name))) + if (module->count_id(TwineSearch(&module->design->twines).find(name))) continue; Wire *wire = module->addWire(Twine{name}, GetSize(sig)); diff --git a/passes/hierarchy/flatten.cc b/passes/hierarchy/flatten.cc index 40f693c4a..a458723e5 100644 --- a/passes/hierarchy/flatten.cc +++ b/passes/hierarchy/flatten.cc @@ -173,7 +173,7 @@ struct FlattenWorker RTLIL::Wire *new_wire = nullptr; if (tpl_wire->name[0] == '\\') { std::string wire_name = concat_name(cell, tpl_wire->name, separator).str(); - RTLIL::Wire *hier_wire = module->wire(design->twines.lookup(wire_name)); + RTLIL::Wire *hier_wire = module->wire(TwineSearch(&design->twines).find(wire_name)); if (hier_wire != nullptr && hier_wire->get_bool_attribute(ID::hierconn)) { hier_wire->attributes.erase(ID::hierconn); if (GetSize(hier_wire) < GetSize(tpl_wire)) { @@ -200,7 +200,7 @@ struct FlattenWorker map_attributes(cell, new_proc, design->twines.str(tpl_proc_it.second->meta_->name)); for (auto new_proc_sync : new_proc->syncs) for (auto &memwr_action : new_proc_sync->mem_write_actions) { - TwineRef old_memid_ref = design->twines.lookup(memwr_action.memid.str()); + TwineRef old_memid_ref = TwineSearch(&design->twines).find(memwr_action.memid.str()); memwr_action.memid = design->twines.str(memory_map.at(old_memid_ref)); } auto rewriter = [&](RTLIL::SigSpec &sig) { map_sigspec(wire_map, sig); }; @@ -215,7 +215,7 @@ struct FlattenWorker map_attributes(cell, new_cell, tpl_cell->name); if (new_cell->has_memid()) { IdString memid = new_cell->getParam(ID::MEMID).decode_string(); - TwineRef memid_ref = design->twines.lookup(memid.str()); + TwineRef memid_ref = TwineSearch(&design->twines).find(memid.str()); new_cell->setParam(ID::MEMID, Const(design->twines.str(memory_map.at(memid_ref)))); } else if (new_cell->is_mem_cell()) { IdString memid = new_cell->getParam(ID::MEMID).decode_string(); diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 076099a04..faeec222d 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -260,7 +260,7 @@ struct MemoryMapWorker c->setPort(TW::D, w_in); std::string w_out_name = stringf("%s[%d]", mem.memid.str(), addr); - if (module->wire(design->twines.lookup(w_out_name)) != nullptr) + if (module->wire(TwineSearch(&design->twines).find(w_out_name)) != nullptr) w_out_name = genid(mem.memid, "", addr, "$q"); RTLIL::Wire *w_out = module->addWire(design->twines.add(Twine{w_out_name}), mem.width); diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index 81fd12840..e8789f3fa 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -124,11 +124,11 @@ struct Clk2fflogicPass : public Pass { } SigSpec bitwise_sr(Module *module, SigSpec a, SigSpec s, SigSpec r, bool is_fine) { if (is_fine) { - return module->MuxGate(NEW_ID, module->AndGate(NEW_ID, module->OrGate(NEW_ID, a, s), module->NotGate(NEW_ID, r)), RTLIL::State::Sx, module->AndGate(NEW_TWINE, s, r)); + return module->MuxGate(NEW_TWINE, module->AndGate(NEW_TWINE, module->OrGate(NEW_TWINE, a, s), module->NotGate(NEW_TWINE, r)), RTLIL::State::Sx, module->AndGate(NEW_TWINE, s, r)); } else { std::vector y; for (int i = 0; i < a.size(); i++) - y.push_back(module->MuxGate(NEW_ID, module->AndGate(NEW_ID, module->OrGate(NEW_ID, a[i], s[i]), module->NotGate(NEW_ID, r[i])), RTLIL::State::Sx, module->AndGate(NEW_TWINE, s[i], r[i]))); + y.push_back(module->MuxGate(NEW_TWINE, module->AndGate(NEW_TWINE, module->OrGate(NEW_TWINE, a[i], s[i]), module->NotGate(NEW_TWINE, r[i])), RTLIL::State::Sx, module->AndGate(NEW_TWINE, s[i], r[i]))); return y; } } @@ -173,7 +173,7 @@ struct Clk2fflogicPass : public Pass { auto &port = mem.rd_ports[i]; if (port.clk_enable) log_error("Read port %d of memory %s.%s is clocked. This is not supported by \"clk2fflogic\"! " - "Call \"memory\" with -nordff to avoid this error.\n", i, design->twines.unescaped_str(mem.memid), module); + "Call \"memory\" with -nordff to avoid this error.\n", i, RTLIL::unescape_id(mem.memid), module); } for (int i = 0; i < GetSize(mem.wr_ports); i++) @@ -184,10 +184,10 @@ struct Clk2fflogicPass : public Pass { continue; log("Modifying write port %d on memory %s.%s: CLK=%s, A=%s, D=%s\n", - i, module, design->twines.unescaped_str(mem.memid), log_signal(port.clk), + i, module, RTLIL::unescape_id(mem.memid), log_signal(port.clk), log_signal(port.addr), log_signal(port.data)); - Wire *past_clk = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#past_clk#%s", design->twines.unescaped_str(mem.memid), i, log_signal(port.clk)))); + Wire *past_clk = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#past_clk#%s", RTLIL::unescape_id(mem.memid), i, log_signal(port.clk)))); past_clk->attributes[ID::init] = port.clk_polarity ? State::S1 : State::S0; module->addFf(NEW_TWINE, port.clk, past_clk); @@ -203,13 +203,13 @@ struct Clk2fflogicPass : public Pass { SigSpec clock_edge = module->Eqx(NEW_TWINE, {port.clk, SigSpec(past_clk)}, clock_edge_pattern); - SigSpec en_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#en_q", design->twines.unescaped_str(mem.memid), i)), GetSize(port.en)); + SigSpec en_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#en_q", RTLIL::unescape_id(mem.memid), i)), GetSize(port.en)); module->addFf(NEW_TWINE, port.en, en_q); - SigSpec addr_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#addr_q", design->twines.unescaped_str(mem.memid), i)), GetSize(port.addr)); + SigSpec addr_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#addr_q", RTLIL::unescape_id(mem.memid), i)), GetSize(port.addr)); module->addFf(NEW_TWINE, port.addr, addr_q); - SigSpec data_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#data_q", design->twines.unescaped_str(mem.memid), i)), GetSize(port.data)); + SigSpec data_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#data_q", RTLIL::unescape_id(mem.memid), i)), GetSize(port.data)); module->addFf(NEW_TWINE, port.data, data_q); port.clk = State::S0; diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc index d800c685e..1d3133184 100644 --- a/passes/sat/cutpoint.cc +++ b/passes/sat/cutpoint.cc @@ -152,8 +152,9 @@ struct CutpointPass : public Pass { } RTLIL::Cell *scopeinfo = nullptr; - RTLIL::IdString cell_name(cell->name); - if (flag_scopeinfo && cell_name.isPublic()) { + TwineRef cell_name_ref = cell->name.ref(); + bool cell_name_is_public = cell->name.isPublic(); + if (flag_scopeinfo && cell_name_is_public) { auto scopeinfo = module->addCell(NEW_TWINE, TW($scopeinfo)); scopeinfo->setParam(ID::TYPE, RTLIL::Const("blackbox")); @@ -162,14 +163,14 @@ struct CutpointPass : public Pass { if (attr.first == ID::hdlname) scopeinfo->attributes.insert(attr); else - scopeinfo->attributes.emplace(stringf("\\cell_%s", design->twines.unescaped_str(attr.first)), attr.second); + scopeinfo->attributes.emplace(stringf("\\cell_%s", RTLIL::unescape_id(attr.first)), attr.second); } } module->remove(cell); if (scopeinfo != nullptr) - module->rename(scopeinfo, cell_name); + module->rename(scopeinfo, cell_name_ref); } for (auto wire : module->selected_wires()) { diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 2432bdedc..db8932ec1 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -93,10 +93,10 @@ struct BruteForceEquivChecker if (w->port_id == 0) continue; - if (mod2->wire(w->name) == nullptr) + if (mod2->wire(w->name.ref()) == nullptr) log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", w->name); - RTLIL::Wire *w2 = mod2->wire(w->name); + RTLIL::Wire *w2 = mod2->wire(w->name.ref()); if (w->width != w2->width || w->port_input != w2->port_input || w->port_output != w2->port_output) log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", w->name); @@ -149,15 +149,15 @@ struct VlogHammerReporter for (auto c : module->cells()) if (!satgen.importCell(c)) - log_error("Failed to import cell %s (type %s) to SAT database.\n", design->twines.unescaped_str(c->name), design->twines.unescaped_str(c->type)); + log_error("Failed to import cell %s (type %s) to SAT database.\n", log_id(c), log_id(c->type)); ez->assume(satgen.signals_eq(recorded_set_vars, recorded_set_vals)); - std::vector y_vec = satgen.importDefSigSpec(module->wire(ID(y))); + std::vector y_vec = satgen.importDefSigSpec(module->wire(TW::y)); std::vector y_values; if (model_undef) { - std::vector y_undef_vec = satgen.importUndefSigSpec(module->wire(ID(y))); + std::vector y_undef_vec = satgen.importUndefSigSpec(module->wire(TW::y)); y_vec.insert(y_vec.end(), y_undef_vec.begin(), y_undef_vec.end()); } @@ -252,7 +252,7 @@ struct VlogHammerReporter std::vector bits(patterns[idx].begin(), patterns[idx].begin() + total_input_width); for (int i = 0; i < int(inputs.size()); i++) { - RTLIL::Wire *wire = module->wire(inputs[i]); + RTLIL::Wire *wire = module->wire(TwineSearch(&design->twines).find(inputs[i].str())); for (int j = input_widths[i]-1; j >= 0; j--) { ce.set(RTLIL::SigSpec(wire, j), bits.back()); recorded_set_vars.append(RTLIL::SigSpec(wire, j)); @@ -262,16 +262,16 @@ struct VlogHammerReporter if (module == modules.front()) { RTLIL::SigSpec sig(wire); if (!ce.eval(sig)) - log_error("Can't read back value for port %s!\n", design->twines.unescaped_str(inputs[i])); + log_error("Can't read back value for port %s!\n", RTLIL::unescape_id(inputs[i]).c_str()); input_pattern_list += stringf(" %s", sig.as_const().as_string()); - log("++PAT++ %d %s %s #\n", idx, design->twines.unescaped_str(inputs[i]), sig.as_const().as_string()); + log("++PAT++ %d %s %s #\n", idx, RTLIL::unescape_id(inputs[i]).c_str(), sig.as_const().as_string()); } } - if (module->wire(ID(y)) == nullptr) + if (module->wire(TW::y) == nullptr) log_error("No output wire (y) found in module %s!\n", design->twines.unescaped_str(module->name)); - RTLIL::SigSpec sig(module->wire(ID(y))); + RTLIL::SigSpec sig(module->wire(TW::y)); RTLIL::SigSpec undef; while (!ce.eval(sig, undef)) { @@ -306,10 +306,10 @@ struct VlogHammerReporter { for (auto name : split(module_list, ",")) { RTLIL::IdString esc_name = RTLIL::escape_id(module_prefix + name); - if (design->module(esc_name) == nullptr) + if (design->module(TwineSearch(&design->twines).find(esc_name.str())) == nullptr) log_error("Can't find module %s in current design!\n", name); log("Using module %s (%s).\n", esc_name, name); - modules.push_back(design->module(esc_name)); + modules.push_back(design->module(TwineSearch(&design->twines).find(esc_name.str()))); module_names.push_back(name); } @@ -318,9 +318,9 @@ struct VlogHammerReporter int width = -1; RTLIL::IdString esc_name = RTLIL::escape_id(name); for (auto mod : modules) { - if (mod->wire(esc_name) == nullptr) + if (mod->wire(TwineSearch(&design->twines).find(esc_name.str())) == nullptr) log_error("Can't find input %s in module %s!\n", name, design->twines.unescaped_str(mod->name)); - RTLIL::Wire *port = mod->wire(esc_name); + RTLIL::Wire *port = mod->wire(TwineSearch(&design->twines).find(esc_name.str())); if (!port->port_input || port->port_output) log_error("Wire %s in module %s is not an input!\n", name, design->twines.unescaped_str(mod->name)); if (width >= 0 && width != port->width) @@ -414,11 +414,11 @@ struct EvalPass : public Pass { /* this should only be used for regression testing of ConstEval -- see vloghammer */ std::string mod1_name = RTLIL::escape_id(args[++argidx]); std::string mod2_name = RTLIL::escape_id(args[++argidx]); - if (design->module(mod1_name) == nullptr) + if (design->module(TwineSearch(&design->twines).find(mod1_name)) == nullptr) log_error("Can't find module `%s'!\n", mod1_name); - if (design->module(mod2_name) == nullptr) + if (design->module(TwineSearch(&design->twines).find(mod2_name)) == nullptr) log_error("Can't find module `%s'!\n", mod2_name); - BruteForceEquivChecker checker(design->module(mod1_name), design->module(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x"); + BruteForceEquivChecker checker(design->module(TwineSearch(&design->twines).find(mod1_name)), design->module(TwineSearch(&design->twines).find(mod2_name)), args[argidx-2] == "-brute_force_equiv_checker_x"); if (checker.errors > 0) log_cmd_error("Modules are not equivalent!\n"); log("Verified %s = %s (using brute-force check on %d cases).\n", diff --git a/passes/sat/formalff.cc b/passes/sat/formalff.cc index d0655b20b..88b2a13e3 100644 --- a/passes/sat/formalff.cc +++ b/passes/sat/formalff.cc @@ -133,8 +133,8 @@ struct InitValWorker if (cell->type.in(TW($and), TW($or))) { - State init_a = initconst(bit_in_port(cell, ID::A, ID::A_SIGNED, portbit.offset)); - State init_b = initconst(bit_in_port(cell, ID::B, ID::B_SIGNED, portbit.offset)); + State init_a = initconst(bit_in_port(cell, TW::A, ID::A_SIGNED, portbit.offset)); + State init_b = initconst(bit_in_port(cell, TW::B, ID::B_SIGNED, portbit.offset)); State init_y; if (init_a == init_b) init_y = init_a; @@ -162,12 +162,12 @@ struct InitValWorker State init_y = State::S1; for (int i = 0; init_y != State::S0 && i < GetSize(sig_a); i++) { - State init_ai = initconst(bit_in_port(cell, ID::A, ID::A_SIGNED, i)); + State init_ai = initconst(bit_in_port(cell, TW::A, ID::A_SIGNED, i)); if (init_ai == State::Sx) { init_y = State::Sx; continue; } - State init_bi = initconst(bit_in_port(cell, ID::B, ID::B_SIGNED, i)); + State init_bi = initconst(bit_in_port(cell, TW::B, ID::B_SIGNED, i)); if (init_bi == State::Sx) init_y = State::Sx; else if (init_ai != init_bi) @@ -320,7 +320,7 @@ struct InitValWorker }; struct ReplacedPort { - IdString name; + TwineRef name; int offset; bool clk_pol; }; @@ -402,7 +402,7 @@ struct PropagateWorker sigmap.apply(bit); if (replaced_clk_bits.count(bit)) log_error("derived signal %s driven by %s (%s) from module %s is used as clock, derived clocks are only supported with clk2fflogic.\n", - log_signal(bit), cell->module->design->twines.str(cell->meta_->name), cell->type.unescaped(), module); + log_signal(bit), log_id(cell), log_id(cell->type), log_id(module)); } } } @@ -462,7 +462,7 @@ const std::vector &HierarchyWorker::find_replaced_clk_inputs(IdStr if (!cell_type.isPublic()) return empty; - Module *module = design->module(cell_type); + Module *module = design->module(TwineSearch(&design->twines).find(cell_type.str())); if (module == nullptr) return empty; @@ -712,7 +712,7 @@ struct FormalFfPass : public Pass { if (!is_gate) { log_debug("unsupported gating logic %s.%s (%s) for clock %s %s.%s\n", module, - driver.cell, design->twines.unescaped_str(driver.cell->type), pol_clk ? "posedge" : "negedge", + driver.cell, log_id(driver.cell->type), pol_clk ? "posedge" : "negedge", module, log_signal(SigSpec(clk))); continue; @@ -754,7 +754,7 @@ struct FormalFfPass : public Pass { log_debug( "FF driver for gate enable %s.%s of gated clk bit %s.%s has incompatible type: %s\n", module, log_signal(SigSpec(gate_enable)), module, log_signal(SigSpec(clk)), - design->twines.unescaped_str(gate_driver.cell->type)); + log_id(gate_driver.cell->type)); continue; } @@ -782,7 +782,7 @@ struct FormalFfPass : public Pass { for (auto clocked_cell : clocked_cells) { log_debug("rewriting cell %s.%s (%s)\n", module, clocked_cell, - design->twines.unescaped_str(clocked_cell->type)); + log_id(clocked_cell->type)); if (clocked_cell->is_builtin_ff()) { diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 25063d844..1bcece0ce 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -139,7 +139,7 @@ struct FindReducedInputs if (ez_cells.count(drv.first) == 0) { satgen.setContext(&sigmap, "A"); if (!satgen.importCell(drv.first)) - log_error("Can't create SAT model for cell %s (%s)!\n", drv.first, design->twines.unescaped_str(drv.first->type)); + log_error("Can't create SAT model for cell %s (%s)!\n", log_id(drv.first), log_id(drv.first->type)); satgen.setContext(&sigmap, "B"); if (!satgen.importCell(drv.first)) log_abort(); @@ -256,7 +256,7 @@ struct PerformReduction std::pair> &drv = drivers.at(out); if (celldone.count(drv.first) == 0) { if (!satgen.importCell(drv.first)) - log_error("Can't create SAT model for cell %s (%s)!\n", drv.first, design->twines.unescaped_str(drv.first->type)); + log_error("Can't create SAT model for cell %s (%s)!\n", log_id(drv.first), log_id(drv.first->type)); celldone.insert(drv.first); } int max_child_depth = 0; diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 941c2e14d..f8788e75f 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -75,15 +75,17 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: RTLIL::IdString gate_name = RTLIL::escape_id(args[argidx++]); RTLIL::IdString miter_name = RTLIL::escape_id(args[argidx++]); - if (design->module(gold_name) == nullptr) + TwineSearch search(&design->twines); + + if (design->module(search.find(gold_name.str())) == nullptr) log_cmd_error("Can't find gold module %s!\n", gold_name); - if (design->module(gate_name) == nullptr) + if (design->module(search.find(gate_name.str())) == nullptr) log_cmd_error("Can't find gate module %s!\n", gate_name); - if (design->module(miter_name) != nullptr) + if (design->module(search.find(miter_name.str())) != nullptr) log_cmd_error("There is already a module %s!\n", miter_name); - RTLIL::Module *gold_module = design->module(gold_name); - RTLIL::Module *gate_module = design->module(gate_name); + RTLIL::Module *gold_module = design->module(search.find(gold_name.str())); + RTLIL::Module *gate_module = design->module(search.find(gate_name.str())); pool gold_cross_ports; for (auto gold_wire : gold_module->wires()) { @@ -128,15 +130,15 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: log_cmd_error("No matching port in gold module was found for %s!\n", design->twines.str(gate_wire->meta_->name).c_str()); } - log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", design->twines.unescaped_str(miter_name), design->twines.unescaped_str(gold_name), design->twines.unescaped_str(gate_name)); + log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", RTLIL::unescape_id(miter_name).c_str(), RTLIL::unescape_id(gold_name).c_str(), RTLIL::unescape_id(gate_name).c_str()); RTLIL::Module *miter_module = new RTLIL::Module; miter_module->design = design; - miter_module->meta_->name = design->twines.add(Twine{miter_name.str()}); + miter_module->meta_->name = design->twines.add(std::string{miter_name.str()}); design->add(miter_module); - RTLIL::Cell *gold_cell = miter_module->addCell(TW::gold, gold_name); - RTLIL::Cell *gate_cell = miter_module->addCell(TW::gate, gate_name); + RTLIL::Cell *gold_cell = miter_module->addCell(TW::gold, gold_module->meta_->name); + RTLIL::Cell *gate_cell = miter_module->addCell(TW::gate, gate_module->meta_->name); RTLIL::SigSpec all_conditions; @@ -322,16 +324,18 @@ void create_miter_assert(struct Pass *that, std::vector args, RTLIL IdString module_name = RTLIL::escape_id(args[argidx++]); IdString miter_name = argidx < args.size() ? RTLIL::escape_id(args[argidx++]) : ""; - if (design->module(module_name) == nullptr) + TwineSearch search(&design->twines); + + if (design->module(search.find(module_name.str())) == nullptr) log_cmd_error("Can't find module %s!\n", module_name); - if (!miter_name.empty() && design->module(miter_name) != nullptr) + if (!miter_name.empty() && design->module(search.find(miter_name.str())) != nullptr) log_cmd_error("There is already a module %s!\n", miter_name); - Module *module = design->module(module_name); + Module *module = design->module(search.find(module_name.str())); if (!miter_name.empty()) { module = module->clone(); - module->meta_->name = design->twines.add(Twine{miter_name.str()}); + module->meta_->name = design->twines.add(std::string{miter_name.str()}); design->add(module); } @@ -339,7 +343,7 @@ void create_miter_assert(struct Pass *that, std::vector args, RTLIL for (auto wire : module->wires()) wire->port_output = false; - Wire *trigger = module->addWire(ID(trigger)); + Wire *trigger = module->addWire(TW::trigger); trigger->port_output = true; module->fixup_ports(); diff --git a/passes/sat/supercover.cc b/passes/sat/supercover.cc index b6a0e815b..92259c09d 100644 --- a/passes/sat/supercover.cc +++ b/passes/sat/supercover.cc @@ -68,7 +68,7 @@ struct SupercoverPass : public Pass { for (auto wire : module->selected_wires()) { bool counted_wire = false; - Twine src{wire->get_src_attribute()}; + TwineRef src = wire->src_ref(); for (auto bit : sigmap(SigSpec(wire))) { diff --git a/passes/sat/synthprop.cc b/passes/sat/synthprop.cc index 9417fc9b8..634ef1ebf 100644 --- a/passes/sat/synthprop.cc +++ b/passes/sat/synthprop.cc @@ -95,9 +95,11 @@ void SynthPropWorker::run() TrackingData tracing_data; tracing(module, 0, tracing_data, design->twines.unescaped_str(module->name)); + TwineRef port_ref = design->twines.add(std::string{port_name.str()}); + for (auto &data : tracing_data) { if (data.second.names.size() == 0) continue; - RTLIL::Wire *wire = data.first->addWire(port_name, data.second.names.size()); + RTLIL::Wire *wire = data.first->addWire(port_ref, data.second.names.size()); wire->port_output = true; data.first->fixup_ports(); } @@ -105,7 +107,7 @@ void SynthPropWorker::run() RTLIL::Wire *output = nullptr; for (auto &data : tracing_data) { int num = 0; - RTLIL::Wire *port_wire = data.first->wire(port_name); + RTLIL::Wire *port_wire = data.first->wire(port_ref); if (!reset_name.empty() && data.first == module) { port_wire = data.first->addWire(NEW_TWINE, data.second.names.size()); output = port_wire; @@ -115,8 +117,8 @@ void SynthPropWorker::run() if (cell->type == TW($assert)) { RTLIL::Wire *neg_wire = data.first->addWire(NEW_TWINE); RTLIL::Wire *result_wire = data.first->addWire(NEW_TWINE); - data.first->addNot(NEW_ID, cell->getPort(TW::A), neg_wire); - data.first->addAnd(NEW_ID, cell->getPort(TW::EN), neg_wire, result_wire); + data.first->addNot(NEW_TWINE, cell->getPort(TW::A), neg_wire); + data.first->addAnd(NEW_TWINE, cell->getPort(TW::EN), neg_wire, result_wire); if (!or_outputs) { data.first->connect(SigBit(port_wire,num), result_wire); } else { @@ -130,10 +132,10 @@ void SynthPropWorker::run() if (RTLIL::Module *submod = design->module(cell->type_impl)) { if (tracing_data[submod].names.size() > 0) { if (!or_outputs) { - cell->setPort(port_name, SigChunk(port_wire, num, tracing_data[submod].names.size())); + cell->setPort(port_ref, SigChunk(port_wire, num, tracing_data[submod].names.size())); } else { RTLIL::Wire *result_wire = data.first->addWire(NEW_TWINE); - cell->setPort(port_name, result_wire); + cell->setPort(port_ref, result_wire); connected.emplace(result_wire); } num += tracing_data[submod].names.size(); @@ -147,7 +149,7 @@ void SynthPropWorker::run() prev_wire = wire; } else { RTLIL::Wire *result = data.first->addWire(NEW_TWINE); - data.first->addOr(NEW_ID, prev_wire, wire, result); + data.first->addOr(NEW_TWINE, prev_wire, wire, result); prev_wire = result; } } @@ -160,10 +162,10 @@ void SynthPropWorker::run() if (!reset_name.empty()) { int width = tracing_data[module].names.size(); - SigSpec reset = module->wire(reset_name); + SigSpec reset = module->wire(TwineSearch(&design->twines).find(reset_name.str())); reset.extend_u0(width, true); - module->addDlatchsr(NEW_TWINE, State::S1, Const(State::S0,width), reset, output, module->wire(port_name), true, true, reset_pol); + module->addDlatchsr(NEW_TWINE, State::S1, Const(State::S0,width), reset, output, module->wire(port_ref), true, true, reset_pol); } if (!map_file.empty()) { @@ -255,7 +257,7 @@ struct SyntProperties : public Pass { if (top == nullptr) log_cmd_error("Can't find top module in current design!\n"); - auto *reset = top->wire(worker.reset_name); + auto *reset = top->wire(TwineSearch(&design->twines).find(worker.reset_name.str())); if (!worker.reset_name.empty() && reset == nullptr) log_cmd_error("Can't find reset line in current design!\n"); diff --git a/passes/techmap/aigmap.cc b/passes/techmap/aigmap.cc index bff1aa0b1..96ea15380 100644 --- a/passes/techmap/aigmap.cc +++ b/passes/techmap/aigmap.cc @@ -68,11 +68,11 @@ struct AigmapPass : public Pass { { vector replaced_cells; int not_replaced_count = 0; - dict stat_replaced; - dict stat_not_replaced; + dict stat_replaced; + dict stat_not_replaced; int orig_num_cells = GetSize(module->cells()); - pool new_sel; + pool new_sel; for (auto cell : module->selected_cells()) { Aig aig(cell); @@ -85,9 +85,9 @@ struct AigmapPass : public Pass { if (aig.name.empty()) { not_replaced_count++; - stat_not_replaced[cell->type]++; + stat_not_replaced[cell->type_impl]++; if (select_mode) - new_sel.insert(cell->name); + new_sel.insert(cell->name.ref()); continue; } @@ -111,7 +111,7 @@ struct AigmapPass : public Pass { bit = module->addWire(NEW_TWINE); auto gate = module->addNandGate(NEW_TWINE, A, B, bit); if (select_mode) - new_sel.insert(gate->name); + new_sel.insert(gate->name.ref()); goto skip_inverter; } else { @@ -122,7 +122,7 @@ struct AigmapPass : public Pass { bit = module->addWire(NEW_TWINE); auto gate = module->addAndGate(NEW_TWINE, A, B, bit); if (select_mode) - new_sel.insert(gate->name); + new_sel.insert(gate->name.ref()); } } } @@ -132,7 +132,7 @@ struct AigmapPass : public Pass { auto gate = module->addNotGate(NEW_TWINE, bit, new_bit); bit = new_bit; if (select_mode) - new_sel.insert(gate->name); + new_sel.insert(gate->name.ref()); } @@ -144,7 +144,7 @@ struct AigmapPass : public Pass { } replaced_cells.push_back(cell); - stat_replaced[cell->type]++; + stat_replaced[cell->type_impl]++; } if (not_replaced_count == 0 && replaced_cells.empty()) @@ -172,7 +172,7 @@ struct AigmapPass : public Pass { if (select_mode) { RTLIL::Selection& sel = design->selection(); - sel.selected_members[module->name] = std::move(new_sel); + sel.selected_members[module->meta_->name] = std::move(new_sel); } } diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc index 7a33a3770..4c97f6ab1 100644 --- a/passes/techmap/attrmap.cc +++ b/passes/techmap/attrmap.cc @@ -131,13 +131,13 @@ void attrmap_apply(string objname, vector> &actio if (new_attr != attr) log("Changed attribute on %s: %s=%s -> %s=%s\n", objname, - attr.first.unescape(), log_const(attr.second), design->twines.unescaped_str(new_attr.first), log_const(new_attr.second)); + attr.first.unescape(), log_const(attr.second), new_attr.first.unescape(), log_const(new_attr.second)); new_attributes[new_attr.first] = new_attr.second; if (0) delete_this_attr: - log("Removed attribute on %s: %s=%s\n", objname, design->twines.unescaped_str(attr.first), log_const(attr.second)); + log("Removed attribute on %s: %s=%s\n", objname, attr.first.unescape(), log_const(attr.second)); } attributes.swap(new_attributes); diff --git a/passes/techmap/attrmvcp.cc b/passes/techmap/attrmvcp.cc index 0f9cc1a6b..cff7d8697 100644 --- a/passes/techmap/attrmvcp.cc +++ b/passes/techmap/attrmvcp.cc @@ -121,7 +121,7 @@ struct AttrmvcpPass : public Pass { for (auto bit : sigmap(wire)) if (net2cells.count(bit)) for (auto cell : net2cells.at(bit)) { - log("Moving attribute %s=%s from %s.%s to %s.%s.\n", design->twines.unescaped_str(attr.first), log_const(attr.second), + log("Moving attribute %s=%s from %s.%s to %s.%s.\n", attr.first.unescape(), log_const(attr.second), module, wire, module, cell); cell->attributes[attr.first] = attr.second; did_something = true; diff --git a/passes/techmap/clockgate.cc b/passes/techmap/clockgate.cc index 9c81f658e..c02552368 100644 --- a/passes/techmap/clockgate.cc +++ b/passes/techmap/clockgate.cc @@ -8,11 +8,11 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct ClockGateCell { - IdString name; - IdString ce_pin; - IdString clk_in_pin; - IdString clk_out_pin; - std::vector tie_lo_pins; + std::string name; + std::string ce_pin; + std::string clk_in_pin; + std::string clk_out_pin; + std::vector tie_lo_pins; }; ClockGateCell icg_from_arg(std::string& name, std::string& str) { @@ -162,9 +162,9 @@ static std::pair, std::optional> winning = cost < goal; if (winning) - log_debug("%s beats %s\n", icg_interface.name, icg_to_beat->name); + log_debug("%s beats %s\n", icg_interface.name.c_str(), icg_to_beat->name.c_str()); } else { - log_debug("%s is the first of its polarity\n", icg_interface.name); + log_debug("%s is the first of its polarity\n", icg_interface.name.c_str()); winning = true; } if (winning) { @@ -176,11 +176,11 @@ static std::pair, std::optional> std::optional pos; std::optional neg; if (best_pos) { - log("Selected rising edge ICG %s from Liberty file\n", best_pos->name); + log("Selected rising edge ICG %s from Liberty file\n", best_pos->name.c_str()); pos.emplace(*best_pos); } if (best_neg) { - log("Selected falling edge ICG %s from Liberty file\n", best_neg->name); + log("Selected falling edge ICG %s from Liberty file\n", best_neg->name.c_str()); neg.emplace(*best_neg); } return std::make_pair(pos, neg); @@ -371,18 +371,19 @@ struct ClockgatePass : public Pass { if (!matching_icg_desc) continue; - Cell* icg = module->addCell(NEW_TWINE, matching_icg_desc->name); - icg->setPort(matching_icg_desc->ce_pin, clk.ce_bit); - icg->setPort(matching_icg_desc->clk_in_pin, clk.clk_bit); + auto& twines = module->design->twines; + Cell* icg = module->addCell(NEW_TWINE, twines.add(std::string{matching_icg_desc->name})); + icg->setPort(twines.add(std::string{matching_icg_desc->ce_pin}), clk.ce_bit); + icg->setPort(twines.add(std::string{matching_icg_desc->clk_in_pin}), clk.clk_bit); gclk.new_net = module->addWire(NEW_TWINE); - icg->setPort(matching_icg_desc->clk_out_pin, gclk.new_net); + icg->setPort(twines.add(std::string{matching_icg_desc->clk_out_pin}), gclk.new_net); // Tie low DFT ports like scan chain enable for (auto port : matching_icg_desc->tie_lo_pins) - icg->setPort(port, Const(0, 1)); + icg->setPort(twines.add(std::string{port}), Const(0, 1)); // Fix CE polarity if needed if (!clk.pol_ce) { SigBit ce_fixed_pol = module->NotGate(NEW_TWINE, clk.ce_bit); - icg->setPort(matching_icg_desc->ce_pin, ce_fixed_pol); + icg->setPort(twines.add(std::string{matching_icg_desc->ce_pin}), ce_fixed_pol); } } diff --git a/passes/techmap/constmap.cc b/passes/techmap/constmap.cc index f04340fe2..5a5a44080 100644 --- a/passes/techmap/constmap.cc +++ b/passes/techmap/constmap.cc @@ -25,6 +25,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN static std::string celltype, cell_portname, cell_paramname; +static TwineRef celltype_ref, cell_portname_ref; static RTLIL::Module *module; static RTLIL::SigChunk value; @@ -33,9 +34,9 @@ void constmap_worker(RTLIL::SigSpec &sig) { if (sig.is_fully_const()){ value = module->addWire(NEW_TWINE, sig.size()); - RTLIL::Cell *cell = module->addCell(NEW_TWINE, celltype); + RTLIL::Cell *cell = module->addCell(NEW_TWINE, celltype_ref); cell->setParam(cell_paramname, sig.as_const()); - cell->setPort(cell_portname, value); + cell->setPort(cell_portname_ref, value); sig = value; } } @@ -77,8 +78,12 @@ struct ConstmapPass : public Pass { // TODO disable signorm due to rewrite_sigspecs assert design->sigNormalize(false); - if (design->has(celltype)) { - Module *existing = design->module(celltype); + celltype_ref = design->twines.add(std::string{celltype}); + cell_portname_ref = design->twines.add(std::string{cell_portname}); + + TwineSearch design_search(&design->twines); + if (design->has(design_search.find(celltype))) { + Module *existing = design->module(design_search.find(celltype)); bool has_port = false; for (auto &p : existing->ports){ if (p == cell_portname){ diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc index a79c45ceb..45eb05637 100644 --- a/passes/techmap/dffinit.cc +++ b/passes/techmap/dffinit.cc @@ -59,7 +59,7 @@ struct DffinitPass : public Pass { { log_header(design, "Executing DFFINIT pass (set INIT param on FF cells).\n"); - dict> ff_types; + dict> ff_types; bool highlow_mode = false, noreinit = false; std::string high_string, low_string; @@ -79,7 +79,7 @@ struct DffinitPass : public Pass { } if (args[argidx] == "-ff" && argidx+3 < args.size()) { IdString cell_name = RTLIL::escape_id(args[++argidx]); - IdString output_port = RTLIL::escape_id(args[++argidx]); + TwineRef output_port = design->twines.add(std::string{RTLIL::escape_id(args[++argidx])}); IdString init_param = RTLIL::escape_id(args[++argidx]); ff_types[cell_name][output_port] = init_param; continue; @@ -123,14 +123,14 @@ struct DffinitPass : public Pass { if (noreinit && value[i] != State::Sx && value[i] != initval[i]) log_error("Trying to assign a different init value for %s.%s.%s which technically " "have a conflicted init value.\n", - module, cell, design->twines.unescaped_str(it.second)); + module, cell, it.second.unescape()); value.set(i, initval[i]); } if (highlow_mode && GetSize(value) != 0) { if (GetSize(value) != 1) log_error("Multi-bit init value for %s.%s.%s is incompatible with -highlow mode.\n", - module, cell, design->twines.unescaped_str(it.second)); + module, cell, it.second.unescape()); if (value[0] == State::S1) value = Const(high_string); else @@ -138,8 +138,8 @@ struct DffinitPass : public Pass { } if (value.size() != 0) { - log("Setting %s.%s.%s (port=%s, net=%s) to %s.\n", module, cell, design->twines.unescaped_str(it.second), - it.first.unescape(), log_signal(sig), log_signal(value)); + log("Setting %s.%s.%s (port=%s, net=%s) to %s.\n", module, cell, it.second.unescape(), + design->twines.unescaped_str(it.first), log_signal(sig), log_signal(value)); cell->setParam(it.second, value); } } diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc index d1d5845d7..992b949b9 100644 --- a/passes/techmap/dfflegalize.cc +++ b/passes/techmap/dfflegalize.cc @@ -263,7 +263,7 @@ struct DffLegalizePass : public Pass { } void fail_ff(const FfData &ff, const char *reason) { - log_error("FF %s.%s (type %s) cannot be legalized: %s\n", design->twines.unescaped_str(ff.module->name), ff.cell->module->design->twines.str(cell->meta_->name), design->twines.unescaped_str(ff.cell->type), reason); + log_error("FF %s.%s (type %s) cannot be legalized: %s\n", ff.module->name.unescaped(), ff.cell->name.str(), ff.cell->type.unescaped(), reason); } bool try_flip(FfData &ff, int supported_mask) { @@ -381,7 +381,7 @@ struct DffLegalizePass : public Pass { if (ff.has_ce && !supported_cells[FF_ADFFE]) ff.unmap_ce(); - log_warning("Emulating async set + reset with several FFs and a mux for %s.%s\n", design->twines.unescaped_str(ff.module->name), ff.cell->module->design->twines.str(cell->meta_->name)); + log_warning("Emulating async set + reset with several FFs and a mux for %s.%s\n", ff.module->name.unescaped(), ff.cell->name.str()); log_assert(ff.width == 1); ff.remove(); @@ -600,7 +600,7 @@ struct DffLegalizePass : public Pass { ff.unmap_ce(); if (ff.cell) - log_warning("Emulating mismatched async reset and init with several FFs and a mux for %s.%s\n", design->twines.unescaped_str(ff.module->name), ff.cell->module->design->twines.str(cell->meta_->name)); + log_warning("Emulating mismatched async reset and init with several FFs and a mux for %s.%s\n", ff.module->name.unescaped(), ff.cell->name.str()); emulate_split_init_arst(ff); return; } @@ -752,7 +752,7 @@ struct DffLegalizePass : public Pass { // The only hope left is breaking down to adlatch + dlatch + dlatch + mux. if (ff.cell) - log_warning("Emulating mismatched async reset and init with several latches and a mux for %s.%s\n", design->twines.unescaped_str(ff.module->name), ff.cell->module->design->twines.str(cell->meta_->name)); + log_warning("Emulating mismatched async reset and init with several latches and a mux for %s.%s\n", ff.module->name.unescaped(), ff.cell->name.str()); ff.remove(); emulate_split_init_arst(ff); diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 62e0199b1..8a5af2e2b 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -524,7 +524,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) cell_mapping &cm = cell_mappings[cell_type]; RTLIL::Cell *new_cell = module->addCell(Twine{cell_name.str()}, twines.add(Twine{cm.cell_name.str()})); - new_cell->set_src_attribute(src); + new_cell->set_src_attribute(twines.add(Twine{src})); bool has_q = false, has_qn = false; for (auto &port : cm.ports) { diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc index 2ad76fe67..156b623f9 100644 --- a/passes/techmap/extract_fa.cc +++ b/passes/techmap/extract_fa.cc @@ -262,7 +262,7 @@ struct ExtractFaWorker pool new_leaves = leaves; new_leaves.erase(bit); - for (auto port : {ID::A, ID::B, ID::C, ID::D}) { + for (auto port : {TW::A, TW::B, TW::C, TW::D}) { if (!cell->hasPort(port)) continue; auto bit = sigmap(SigBit(cell->getPort(port))); diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc index 7f48c4fc7..f4c12c9a7 100644 --- a/passes/techmap/extract_reduce.cc +++ b/passes/techmap/extract_reduce.cc @@ -234,7 +234,7 @@ struct ExtractReducePass : public Pass Cell* x = bfs_queue.front(); bfs_queue.pop_front(); - for (auto port: {ID::A, ID::B}) { + for (auto port: {TW::A, TW::B}) { auto bit = sigmap(x->getPort(port)[0]); bool sink_single = sig_to_sink[bit].size() == 1 && !port_sigs.count(bit); diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc index 03bd4cb69..af18cb16b 100644 --- a/passes/techmap/flowmap.cc +++ b/passes/techmap/flowmap.cc @@ -674,8 +674,8 @@ struct FlowmapWorker labels[node] = -1; for (auto input : inputs) { - if (input.wire->attributes.count(TW($flowmap_level))) - labels[input] = input.wire->attributes[TW($flowmap_level)].as_int(); + if (input.wire->attributes.count(ID($flowmap_level))) + labels[input] = input.wire->attributes[ID($flowmap_level)].as_int(); else labels[input] = 0; } @@ -1356,10 +1356,10 @@ struct FlowmapWorker auto origin = node_origins[node]; if (origin.cell->getPort(origin.port).size() == 1) log("Packing %s.%s.%s (%s).\n", - module, origin.cell, origin.port.c_str(), log_signal(node)); + module, origin.cell, module->design->twines.str(origin.port).c_str(), log_signal(node)); else log("Packing %s.%s.%s [%d] (%s).\n", - module, origin.cell, origin.port.c_str(), origin.offset, log_signal(node)); + module, origin.cell, module->design->twines.str(origin.port).c_str(), origin.offset, log_signal(node)); } else { @@ -1376,10 +1376,10 @@ struct FlowmapWorker auto gate_origin = node_origins[gate_node]; if (gate_origin.cell->getPort(gate_origin.port).size() == 1) log(" Packing %s.%s.%s (%s).\n", - module, gate_origin.cell, gate_origin.port.c_str(), log_signal(gate_node)); + module, gate_origin.cell, gate_module->design->twines.str(origin.port).c_str(), log_signal(gate_node)); else log(" Packing %s.%s.%s [%d] (%s).\n", - module, gate_origin.cell, gate_origin.port.c_str(), gate_origin.offset, log_signal(gate_node)); + module, gate_origin.cell, gate_module->design->twines.str(origin.port).c_str(), gate_origin.offset, log_signal(gate_node)); } vector input_nodes(lut_edges_bw[node].begin(), lut_edges_bw[node].end()); @@ -1590,7 +1590,7 @@ struct FlowmapPass : public Pass { } else { - cell_types = {TW($_NOT_), TW($_AND_), TW($_OR_), TW($_XOR_), TW($_MUX_)}; + cell_types = {ID($_NOT_), ID($_AND_), ID($_OR_), ID($_XOR_), ID($_MUX_)}; } const char *algo_r = relax ? "-r" : ""; diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index 8fa4c5c0c..d8f71f32e 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -37,16 +37,16 @@ void hilomap_worker(RTLIL::SigSpec &sig) if (bit == RTLIL::State::S1 && !hicell_celltype.empty()) { if (!singleton_mode || last_hi == RTLIL::State::Sm) { last_hi = module->addWire(NEW_TWINE); - RTLIL::Cell *cell = module->addCell(NEW_TWINE, RTLIL::escape_id(hicell_celltype)); - cell->setPort(RTLIL::escape_id(hicell_portname), last_hi); + RTLIL::Cell *cell = module->addCell(NEW_TWINE, Twine{RTLIL::escape_id(hicell_celltype)}); + cell->setPort(module->design->twines.add(std::string{RTLIL::escape_id(hicell_portname)}), last_hi); } bit = last_hi; } if (bit == RTLIL::State::S0 && !locell_celltype.empty()) { if (!singleton_mode || last_lo == RTLIL::State::Sm) { last_lo = module->addWire(NEW_TWINE); - RTLIL::Cell *cell = module->addCell(NEW_TWINE, RTLIL::escape_id(locell_celltype)); - cell->setPort(RTLIL::escape_id(locell_portname), last_lo); + RTLIL::Cell *cell = module->addCell(NEW_TWINE, Twine{RTLIL::escape_id(locell_celltype)}); + cell->setPort(module->design->twines.add(std::string{RTLIL::escape_id(locell_portname)}), last_lo); } bit = last_lo; } diff --git a/passes/techmap/insbuf.cc b/passes/techmap/insbuf.cc index 0ae30955d..f2475ea70 100644 --- a/passes/techmap/insbuf.cc +++ b/passes/techmap/insbuf.cc @@ -44,7 +44,7 @@ struct InsbufPass : public Pass { { log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n"); - IdString celltype = TW($_BUF_), in_portname = ID::A, out_portname = ID::Y; + TwineRef celltype = TW($_BUF_), in_portname = TW::A, out_portname = TW::Y; bool chain_mode = false; size_t argidx; @@ -52,9 +52,9 @@ struct InsbufPass : public Pass { { std::string arg = args[argidx]; if (arg == "-buf" && argidx+3 < args.size()) { - celltype = RTLIL::escape_id(args[++argidx]); - in_portname = RTLIL::escape_id(args[++argidx]); - out_portname = RTLIL::escape_id(args[++argidx]); + celltype = design->twines.add(std::string{RTLIL::escape_id(args[++argidx])}); + in_portname = design->twines.add(std::string{RTLIL::escape_id(args[++argidx])}); + out_portname = design->twines.add(std::string{RTLIL::escape_id(args[++argidx])}); continue; } if (arg == "-chain") { @@ -116,7 +116,7 @@ struct InsbufPass : public Pass { if (s == port.second) continue; log("Rewrite %s/%s/%s: %s -> %s\n", module, cell, - port.first.unescape(), log_signal(port.second), log_signal(s)); + module->design->twines.unescaped_str(port.first).c_str(), log_signal(port.second), log_signal(s)); cell->setPort(port.first, s); } } diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc index c72aabf10..67cbf3d7c 100644 --- a/passes/techmap/lut2mux.cc +++ b/passes/techmap/lut2mux.cc @@ -97,7 +97,7 @@ struct Lut2muxPass : public Pass { if (cell->type == TW($lut)) { IdString cell_name = cell->name; int count = lut2mux(cell, word_mode); - log("Converted %s.%s to %d MUX cells.\n", module, design->twines.unescaped_str(cell_name), count); + log("Converted %s.%s to %d MUX cells.\n", module, RTLIL::unescape_id(cell_name).c_str(), count); } } } diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc index 03ae51217..20b661abe 100644 --- a/passes/techmap/muxcover.cc +++ b/passes/techmap/muxcover.cc @@ -170,7 +170,7 @@ struct MuxcoverWorker return true; } char port_name[3] = {'\\', *path, 0}; - return follow_muxtree(ret_bit, tree, sigmap(tree.muxes.at(bit)->getPort(port_name)), path+1, false); + return follow_muxtree(ret_bit, tree, sigmap(tree.muxes.at(bit)->getPort(tree.muxes.at(bit)->module->design->twines.add(Twine{std::string(port_name)}))), path+1, false); } else { ret_bit = bit; return true; diff --git a/passes/techmap/nlutmap.cc b/passes/techmap/nlutmap.cc index 7ca43886d..ba888f436 100644 --- a/passes/techmap/nlutmap.cc +++ b/passes/techmap/nlutmap.cc @@ -100,10 +100,10 @@ struct NlutmapWorker cand.second -= bit_lut_count[bit]; } - vector> rated_candidates; + vector> rated_candidates; for (auto &cand : candidate_ratings) - rated_candidates.push_back(pair(cand.second, cand.first->name)); + rated_candidates.push_back({cand.second, cand.first->meta_->name}); std::sort(rated_candidates.begin(), rated_candidates.end()); diff --git a/passes/techmap/tribuf.cc b/passes/techmap/tribuf.cc index a75eddd8b..11cf8fb1f 100644 --- a/passes/techmap/tribuf.cc +++ b/passes/techmap/tribuf.cc @@ -73,8 +73,8 @@ struct TribufWorker { if (cell->type.in(TW($mux), TW($_MUX_))) { - IdString en_port = cell->type == TW($mux) ? ID::EN : ID::E; - IdString tri_type = cell->type == TW($mux) ? TW($tribuf) : TW($_TBUF_); + TwineRef en_port = cell->type == TW($mux) ? TW::EN : TW::E; + TwineRef tri_type = cell->type == TW($mux) ? TW($tribuf) : TW($_TBUF_); if (is_all_z(cell->getPort(TW::A)) && is_all_z(cell->getPort(TW::B))) { module->remove(cell); @@ -86,7 +86,7 @@ struct TribufWorker { cell->setPort(en_port, cell->getPort(TW::S)); cell->unsetPort(TW::B); cell->unsetPort(TW::S); - cell->type_impl = cell->module->design->twines.add(Twine{tri_type.str()}); + cell->type_impl = tri_type; tribuf_cells[sigmap(cell->getPort(TW::Y))].push_back(cell); module->design->scratchpad_set_bool("tribuf.added_something", true); continue; @@ -96,7 +96,7 @@ struct TribufWorker { cell->setPort(en_port, module->Not(NEW_TWINE, cell->getPort(TW::S))); cell->unsetPort(TW::B); cell->unsetPort(TW::S); - cell->type_impl = cell->module->design->twines.add(Twine{tri_type.str()}); + cell->type_impl = tri_type; tribuf_cells[sigmap(cell->getPort(TW::Y))].push_back(cell); module->design->scratchpad_set_bool("tribuf.added_something", true); continue; @@ -143,7 +143,7 @@ struct TribufWorker { auto conflict = module->And(NEW_TWINE, cell_s, other_s); std::string name = stringf("$tribuf_conflict$%s", cell->module->design->twines.str(cell->meta_->name)); - auto assert_cell = module->addAssert(name, module->Not(NEW_TWINE, conflict), SigSpec(true)); + auto assert_cell = module->addAssert(Twine{name}, module->Not(NEW_TWINE, conflict), SigSpec(true)); assert_cell->adopt_src_from(cell); assert_cell->set_bool_attribute(ID::keep);