mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-23 07:32:32 +00:00
Code Activity

WIP migration to twine

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-06-17 11:04:03 +02:00
parent 25f27026f0
commit 96b0ba9581
51 changed files with 289 additions and 275 deletions
Download patch file Download diff file Expand all files Collapse all files

13
passes/techmap/constmap.cc
View file

@ -25,6 +25,7 @@ USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
static std::string celltype, cell_portname, cell_paramname;
static TwineRef celltype_ref, cell_portname_ref;
static RTLIL::Module *module;
static RTLIL::SigChunk value;
@ -33,9 +34,9 @@ void constmap_worker(RTLIL::SigSpec &sig)
{
if (sig.is_fully_const()){
value = module->addWire(NEW_TWINE, sig.size());
RTLIL::Cell *cell = module->addCell(NEW_TWINE, celltype);
RTLIL::Cell *cell = module->addCell(NEW_TWINE, celltype_ref);
cell->setParam(cell_paramname, sig.as_const());
cell->setPort(cell_portname, value);
cell->setPort(cell_portname_ref, value);
sig = value;
}
}
@ -77,8 +78,12 @@ struct ConstmapPass : public Pass {
// TODO disable signorm due to rewrite_sigspecs assert
design->sigNormalize(false);
if (design->has(celltype)) {
Module *existing = design->module(celltype);
celltype_ref = design->twines.add(std::string{celltype});
cell_portname_ref = design->twines.add(std::string{cell_portname});
TwineSearch design_search(&design->twines);
if (design->has(design_search.find(celltype))) {
Module *existing = design->module(design_search.find(celltype));
bool has_port = false;
for (auto &p : existing->ports){
if (p == cell_portname){