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WIP migration to twine

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This commit is contained in:
Emil J. Tywoniak 2026-06-17 11:04:03 +02:00
parent 25f27026f0
commit 96b0ba9581
51 changed files with 289 additions and 275 deletions
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20
passes/techmap/aigmap.cc
View file

@ -68,11 +68,11 @@ struct AigmapPass : public Pass {
{
vector<Cell*> replaced_cells;
int not_replaced_count = 0;
dict<IdString, int> stat_replaced;
dict<IdString, int> stat_not_replaced;
dict<TwineRef, int> stat_replaced;
dict<TwineRef, int> stat_not_replaced;
int orig_num_cells = GetSize(module->cells());
pool<IdString> new_sel;
pool<TwineRef> new_sel;
for (auto cell : module->selected_cells())
{
Aig aig(cell);
@ -85,9 +85,9 @@ struct AigmapPass : public Pass {
if (aig.name.empty()) {
not_replaced_count++;
stat_not_replaced[cell->type]++;
stat_not_replaced[cell->type_impl]++;
if (select_mode)
new_sel.insert(cell->name);
new_sel.insert(cell->name.ref());
continue;
}
@ -111,7 +111,7 @@ struct AigmapPass : public Pass {
bit = module->addWire(NEW_TWINE);
auto gate = module->addNandGate(NEW_TWINE, A, B, bit);
if (select_mode)
new_sel.insert(gate->name);
new_sel.insert(gate->name.ref());
goto skip_inverter;
} else {
@ -122,7 +122,7 @@ struct AigmapPass : public Pass {
bit = module->addWire(NEW_TWINE);
auto gate = module->addAndGate(NEW_TWINE, A, B, bit);
if (select_mode)
new_sel.insert(gate->name);
new_sel.insert(gate->name.ref());
}
}
}
@ -132,7 +132,7 @@ struct AigmapPass : public Pass {
auto gate = module->addNotGate(NEW_TWINE, bit, new_bit);
bit = new_bit;
if (select_mode)
new_sel.insert(gate->name);
new_sel.insert(gate->name.ref());
}
@ -144,7 +144,7 @@ struct AigmapPass : public Pass {
}
replaced_cells.push_back(cell);
stat_replaced[cell->type]++;
stat_replaced[cell->type_impl]++;
}
if (not_replaced_count == 0 && replaced_cells.empty())
@ -172,7 +172,7 @@ struct AigmapPass : public Pass {
if (select_mode) {
RTLIL::Selection& sel = design->selection();
sel.selected_members[module->name] = std::move(new_sel);
sel.selected_members[module->meta_->name] = std::move(new_sel);
}
}

4
passes/techmap/attrmap.cc
View file

@ -131,13 +131,13 @@ void attrmap_apply(string objname, vector<std::unique_ptr<AttrmapAction>> &actio
if (new_attr != attr)
log("Changed attribute on %s: %s=%s -> %s=%s\n", objname,
attr.first.unescape(), log_const(attr.second), design->twines.unescaped_str(new_attr.first), log_const(new_attr.second));
attr.first.unescape(), log_const(attr.second), new_attr.first.unescape(), log_const(new_attr.second));
new_attributes[new_attr.first] = new_attr.second;
if (0)
delete_this_attr:
log("Removed attribute on %s: %s=%s\n", objname, design->twines.unescaped_str(attr.first), log_const(attr.second));
log("Removed attribute on %s: %s=%s\n", objname, attr.first.unescape(), log_const(attr.second));
}
attributes.swap(new_attributes);

2
passes/techmap/attrmvcp.cc
View file

@ -121,7 +121,7 @@ struct AttrmvcpPass : public Pass {
for (auto bit : sigmap(wire))
if (net2cells.count(bit))
for (auto cell : net2cells.at(bit)) {
log("Moving attribute %s=%s from %s.%s to %s.%s.\n", design->twines.unescaped_str(attr.first), log_const(attr.second),
log("Moving attribute %s=%s from %s.%s to %s.%s.\n", attr.first.unescape(), log_const(attr.second),
module, wire, module, cell);
cell->attributes[attr.first] = attr.second;
did_something = true;

31
passes/techmap/clockgate.cc
View file

@ -8,11 +8,11 @@ USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct ClockGateCell {
IdString name;
IdString ce_pin;
IdString clk_in_pin;
IdString clk_out_pin;
std::vector<IdString> tie_lo_pins;
std::string name;
std::string ce_pin;
std::string clk_in_pin;
std::string clk_out_pin;
std::vector<std::string> tie_lo_pins;
};
ClockGateCell icg_from_arg(std::string& name, std::string& str) {
@ -162,9 +162,9 @@ static std::pair<std::optional<ClockGateCell>, std::optional<ClockGateCell>>
winning = cost < goal;
if (winning)
log_debug("%s beats %s\n", icg_interface.name, icg_to_beat->name);
log_debug("%s beats %s\n", icg_interface.name.c_str(), icg_to_beat->name.c_str());
} else {
log_debug("%s is the first of its polarity\n", icg_interface.name);
log_debug("%s is the first of its polarity\n", icg_interface.name.c_str());
winning = true;
}
if (winning) {
@ -176,11 +176,11 @@ static std::pair<std::optional<ClockGateCell>, std::optional<ClockGateCell>>
std::optional<ClockGateCell> pos;
std::optional<ClockGateCell> neg;
if (best_pos) {
log("Selected rising edge ICG %s from Liberty file\n", best_pos->name);
log("Selected rising edge ICG %s from Liberty file\n", best_pos->name.c_str());
pos.emplace(*best_pos);
}
if (best_neg) {
log("Selected falling edge ICG %s from Liberty file\n", best_neg->name);
log("Selected falling edge ICG %s from Liberty file\n", best_neg->name.c_str());
neg.emplace(*best_neg);
}
return std::make_pair(pos, neg);
@ -371,18 +371,19 @@ struct ClockgatePass : public Pass {
if (!matching_icg_desc)
continue;
Cell* icg = module->addCell(NEW_TWINE, matching_icg_desc->name);
icg->setPort(matching_icg_desc->ce_pin, clk.ce_bit);
icg->setPort(matching_icg_desc->clk_in_pin, clk.clk_bit);
auto& twines = module->design->twines;
Cell* icg = module->addCell(NEW_TWINE, twines.add(std::string{matching_icg_desc->name}));
icg->setPort(twines.add(std::string{matching_icg_desc->ce_pin}), clk.ce_bit);
icg->setPort(twines.add(std::string{matching_icg_desc->clk_in_pin}), clk.clk_bit);
gclk.new_net = module->addWire(NEW_TWINE);
icg->setPort(matching_icg_desc->clk_out_pin, gclk.new_net);
icg->setPort(twines.add(std::string{matching_icg_desc->clk_out_pin}), gclk.new_net);
// Tie low DFT ports like scan chain enable
for (auto port : matching_icg_desc->tie_lo_pins)
icg->setPort(port, Const(0, 1));
icg->setPort(twines.add(std::string{port}), Const(0, 1));
// Fix CE polarity if needed
if (!clk.pol_ce) {
SigBit ce_fixed_pol = module->NotGate(NEW_TWINE, clk.ce_bit);
icg->setPort(matching_icg_desc->ce_pin, ce_fixed_pol);
icg->setPort(twines.add(std::string{matching_icg_desc->ce_pin}), ce_fixed_pol);
}
}

13
passes/techmap/constmap.cc
View file

@ -25,6 +25,7 @@ USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
static std::string celltype, cell_portname, cell_paramname;
static TwineRef celltype_ref, cell_portname_ref;
static RTLIL::Module *module;
static RTLIL::SigChunk value;
@ -33,9 +34,9 @@ void constmap_worker(RTLIL::SigSpec &sig)
{
if (sig.is_fully_const()){
value = module->addWire(NEW_TWINE, sig.size());
RTLIL::Cell *cell = module->addCell(NEW_TWINE, celltype);
RTLIL::Cell *cell = module->addCell(NEW_TWINE, celltype_ref);
cell->setParam(cell_paramname, sig.as_const());
cell->setPort(cell_portname, value);
cell->setPort(cell_portname_ref, value);
sig = value;
}
}
@ -77,8 +78,12 @@ struct ConstmapPass : public Pass {
// TODO disable signorm due to rewrite_sigspecs assert
design->sigNormalize(false);
if (design->has(celltype)) {
Module *existing = design->module(celltype);
celltype_ref = design->twines.add(std::string{celltype});
cell_portname_ref = design->twines.add(std::string{cell_portname});
TwineSearch design_search(&design->twines);
if (design->has(design_search.find(celltype))) {
Module *existing = design->module(design_search.find(celltype));
bool has_port = false;
for (auto &p : existing->ports){
if (p == cell_portname){

12
passes/techmap/dffinit.cc
View file

@ -59,7 +59,7 @@ struct DffinitPass : public Pass {
{
log_header(design, "Executing DFFINIT pass (set INIT param on FF cells).\n");
dict<IdString, dict<IdString, IdString>> ff_types;
dict<IdString, dict<TwineRef, IdString>> ff_types;
bool highlow_mode = false, noreinit = false;
std::string high_string, low_string;
@ -79,7 +79,7 @@ struct DffinitPass : public Pass {
}
if (args[argidx] == "-ff" && argidx+3 < args.size()) {
IdString cell_name = RTLIL::escape_id(args[++argidx]);
IdString output_port = RTLIL::escape_id(args[++argidx]);
TwineRef output_port = design->twines.add(std::string{RTLIL::escape_id(args[++argidx])});
IdString init_param = RTLIL::escape_id(args[++argidx]);
ff_types[cell_name][output_port] = init_param;
continue;
@ -123,14 +123,14 @@ struct DffinitPass : public Pass {
if (noreinit && value[i] != State::Sx && value[i] != initval[i])
log_error("Trying to assign a different init value for %s.%s.%s which technically "
"have a conflicted init value.\n",
module, cell, design->twines.unescaped_str(it.second));
module, cell, it.second.unescape());
value.set(i, initval[i]);
}
if (highlow_mode && GetSize(value) != 0) {
if (GetSize(value) != 1)
log_error("Multi-bit init value for %s.%s.%s is incompatible with -highlow mode.\n",
module, cell, design->twines.unescaped_str(it.second));
module, cell, it.second.unescape());
if (value[0] == State::S1)
value = Const(high_string);
else
@ -138,8 +138,8 @@ struct DffinitPass : public Pass {
}
if (value.size() != 0) {
log("Setting %s.%s.%s (port=%s, net=%s) to %s.\n", module, cell, design->twines.unescaped_str(it.second),
it.first.unescape(), log_signal(sig), log_signal(value));
log("Setting %s.%s.%s (port=%s, net=%s) to %s.\n", module, cell, it.second.unescape(),
design->twines.unescaped_str(it.first), log_signal(sig), log_signal(value));
cell->setParam(it.second, value);
}
}

8
passes/techmap/dfflegalize.cc
View file

@ -263,7 +263,7 @@ struct DffLegalizePass : public Pass {
}
void fail_ff(const FfData &ff, const char *reason) {
log_error("FF %s.%s (type %s) cannot be legalized: %s\n", design->twines.unescaped_str(ff.module->name), ff.cell->module->design->twines.str(cell->meta_->name), design->twines.unescaped_str(ff.cell->type), reason);
log_error("FF %s.%s (type %s) cannot be legalized: %s\n", ff.module->name.unescaped(), ff.cell->name.str(), ff.cell->type.unescaped(), reason);
}
bool try_flip(FfData &ff, int supported_mask) {
@ -381,7 +381,7 @@ struct DffLegalizePass : public Pass {
if (ff.has_ce && !supported_cells[FF_ADFFE])
ff.unmap_ce();
log_warning("Emulating async set + reset with several FFs and a mux for %s.%s\n", design->twines.unescaped_str(ff.module->name), ff.cell->module->design->twines.str(cell->meta_->name));
log_warning("Emulating async set + reset with several FFs and a mux for %s.%s\n", ff.module->name.unescaped(), ff.cell->name.str());
log_assert(ff.width == 1);
ff.remove();
@ -600,7 +600,7 @@ struct DffLegalizePass : public Pass {
ff.unmap_ce();
if (ff.cell)
log_warning("Emulating mismatched async reset and init with several FFs and a mux for %s.%s\n", design->twines.unescaped_str(ff.module->name), ff.cell->module->design->twines.str(cell->meta_->name));
log_warning("Emulating mismatched async reset and init with several FFs and a mux for %s.%s\n", ff.module->name.unescaped(), ff.cell->name.str());
emulate_split_init_arst(ff);
return;
}
@ -752,7 +752,7 @@ struct DffLegalizePass : public Pass {
// The only hope left is breaking down to adlatch + dlatch + dlatch + mux.
if (ff.cell)
log_warning("Emulating mismatched async reset and init with several latches and a mux for %s.%s\n", design->twines.unescaped_str(ff.module->name), ff.cell->module->design->twines.str(cell->meta_->name));
log_warning("Emulating mismatched async reset and init with several latches and a mux for %s.%s\n", ff.module->name.unescaped(), ff.cell->name.str());
ff.remove();
emulate_split_init_arst(ff);

2
passes/techmap/dfflibmap.cc
View file

@ -524,7 +524,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
cell_mapping &cm = cell_mappings[cell_type];
RTLIL::Cell *new_cell = module->addCell(Twine{cell_name.str()}, twines.add(Twine{cm.cell_name.str()}));
new_cell->set_src_attribute(src);
new_cell->set_src_attribute(twines.add(Twine{src}));
bool has_q = false, has_qn = false;
for (auto &port : cm.ports) {

2
passes/techmap/extract_fa.cc
View file

@ -262,7 +262,7 @@ struct ExtractFaWorker
pool<SigBit> new_leaves = leaves;
new_leaves.erase(bit);
for (auto port : {ID::A, ID::B, ID::C, ID::D}) {
for (auto port : {TW::A, TW::B, TW::C, TW::D}) {
if (!cell->hasPort(port))
continue;
auto bit = sigmap(SigBit(cell->getPort(port)));

2
passes/techmap/extract_reduce.cc
View file

@ -234,7 +234,7 @@ struct ExtractReducePass : public Pass
Cell* x = bfs_queue.front();
bfs_queue.pop_front();
for (auto port: {ID::A, ID::B}) {
for (auto port: {TW::A, TW::B}) {
auto bit = sigmap(x->getPort(port)[0]);
bool sink_single = sig_to_sink[bit].size() == 1 && !port_sigs.count(bit);

14
passes/techmap/flowmap.cc
View file

@ -674,8 +674,8 @@ struct FlowmapWorker
labels[node] = -1;
for (auto input : inputs)
{
if (input.wire->attributes.count(TW($flowmap_level)))
labels[input] = input.wire->attributes[TW($flowmap_level)].as_int();
if (input.wire->attributes.count(ID($flowmap_level)))
labels[input] = input.wire->attributes[ID($flowmap_level)].as_int();
else
labels[input] = 0;
}
@ -1356,10 +1356,10 @@ struct FlowmapWorker
auto origin = node_origins[node];
if (origin.cell->getPort(origin.port).size() == 1)
log("Packing %s.%s.%s (%s).\n",
module, origin.cell, origin.port.c_str(), log_signal(node));
module, origin.cell, module->design->twines.str(origin.port).c_str(), log_signal(node));
else
log("Packing %s.%s.%s [%d] (%s).\n",
module, origin.cell, origin.port.c_str(), origin.offset, log_signal(node));
module, origin.cell, module->design->twines.str(origin.port).c_str(), origin.offset, log_signal(node));
}
else
{
@ -1376,10 +1376,10 @@ struct FlowmapWorker
auto gate_origin = node_origins[gate_node];
if (gate_origin.cell->getPort(gate_origin.port).size() == 1)
log(" Packing %s.%s.%s (%s).\n",
module, gate_origin.cell, gate_origin.port.c_str(), log_signal(gate_node));
module, gate_origin.cell, gate_module->design->twines.str(origin.port).c_str(), log_signal(gate_node));
else
log(" Packing %s.%s.%s [%d] (%s).\n",
module, gate_origin.cell, gate_origin.port.c_str(), gate_origin.offset, log_signal(gate_node));
module, gate_origin.cell, gate_module->design->twines.str(origin.port).c_str(), gate_origin.offset, log_signal(gate_node));
}
vector<RTLIL::SigBit> input_nodes(lut_edges_bw[node].begin(), lut_edges_bw[node].end());
@ -1590,7 +1590,7 @@ struct FlowmapPass : public Pass {
}
else
{
cell_types = {TW($_NOT_), TW($_AND_), TW($_OR_), TW($_XOR_), TW($_MUX_)};
cell_types = {ID($_NOT_), ID($_AND_), ID($_OR_), ID($_XOR_), ID($_MUX_)};
}
const char *algo_r = relax ? "-r" : "";

8
passes/techmap/hilomap.cc
View file

@ -37,16 +37,16 @@ void hilomap_worker(RTLIL::SigSpec &sig)
if (bit == RTLIL::State::S1 && !hicell_celltype.empty()) {
if (!singleton_mode || last_hi == RTLIL::State::Sm) {
last_hi = module->addWire(NEW_TWINE);
RTLIL::Cell *cell = module->addCell(NEW_TWINE, RTLIL::escape_id(hicell_celltype));
cell->setPort(RTLIL::escape_id(hicell_portname), last_hi);
RTLIL::Cell *cell = module->addCell(NEW_TWINE, Twine{RTLIL::escape_id(hicell_celltype)});
cell->setPort(module->design->twines.add(std::string{RTLIL::escape_id(hicell_portname)}), last_hi);
}
bit = last_hi;
}
if (bit == RTLIL::State::S0 && !locell_celltype.empty()) {
if (!singleton_mode || last_lo == RTLIL::State::Sm) {
last_lo = module->addWire(NEW_TWINE);
RTLIL::Cell *cell = module->addCell(NEW_TWINE, RTLIL::escape_id(locell_celltype));
cell->setPort(RTLIL::escape_id(locell_portname), last_lo);
RTLIL::Cell *cell = module->addCell(NEW_TWINE, Twine{RTLIL::escape_id(locell_celltype)});
cell->setPort(module->design->twines.add(std::string{RTLIL::escape_id(locell_portname)}), last_lo);
}
bit = last_lo;
}

10
passes/techmap/insbuf.cc
View file

@ -44,7 +44,7 @@ struct InsbufPass : public Pass {
{
log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n");
IdString celltype = TW($_BUF_), in_portname = ID::A, out_portname = ID::Y;
TwineRef celltype = TW($_BUF_), in_portname = TW::A, out_portname = TW::Y;
bool chain_mode = false;
size_t argidx;
@ -52,9 +52,9 @@ struct InsbufPass : public Pass {
{
std::string arg = args[argidx];
if (arg == "-buf" && argidx+3 < args.size()) {
celltype = RTLIL::escape_id(args[++argidx]);
in_portname = RTLIL::escape_id(args[++argidx]);
out_portname = RTLIL::escape_id(args[++argidx]);
celltype = design->twines.add(std::string{RTLIL::escape_id(args[++argidx])});
in_portname = design->twines.add(std::string{RTLIL::escape_id(args[++argidx])});
out_portname = design->twines.add(std::string{RTLIL::escape_id(args[++argidx])});
continue;
}
if (arg == "-chain") {
@ -116,7 +116,7 @@ struct InsbufPass : public Pass {
if (s == port.second)
continue;
log("Rewrite %s/%s/%s: %s -> %s\n", module, cell,
port.first.unescape(), log_signal(port.second), log_signal(s));
module->design->twines.unescaped_str(port.first).c_str(), log_signal(port.second), log_signal(s));
cell->setPort(port.first, s);
}
}

2
passes/techmap/lut2mux.cc
View file

@ -97,7 +97,7 @@ struct Lut2muxPass : public Pass {
if (cell->type == TW($lut)) {
IdString cell_name = cell->name;
int count = lut2mux(cell, word_mode);
log("Converted %s.%s to %d MUX cells.\n", module, design->twines.unescaped_str(cell_name), count);
log("Converted %s.%s to %d MUX cells.\n", module, RTLIL::unescape_id(cell_name).c_str(), count);
}
}
}

2
passes/techmap/muxcover.cc
View file

@ -170,7 +170,7 @@ struct MuxcoverWorker
return true;
}
char port_name[3] = {'\\', *path, 0};
return follow_muxtree(ret_bit, tree, sigmap(tree.muxes.at(bit)->getPort(port_name)), path+1, false);
return follow_muxtree(ret_bit, tree, sigmap(tree.muxes.at(bit)->getPort(tree.muxes.at(bit)->module->design->twines.add(Twine{std::string(port_name)}))), path+1, false);
} else {
ret_bit = bit;
return true;

4
passes/techmap/nlutmap.cc
View file

@ -100,10 +100,10 @@ struct NlutmapWorker
cand.second -= bit_lut_count[bit];
}
vector<pair<int, IdString>> rated_candidates;
vector<pair<int, TwineRef>> rated_candidates;
for (auto &cand : candidate_ratings)
rated_candidates.push_back(pair<int, IdString>(cand.second, cand.first->name));
rated_candidates.push_back({cand.second, cand.first->meta_->name});
std::sort(rated_candidates.begin(), rated_candidates.end());

10
passes/techmap/tribuf.cc
View file

@ -73,8 +73,8 @@ struct TribufWorker {
if (cell->type.in(TW($mux), TW($_MUX_)))
{
IdString en_port = cell->type == TW($mux) ? ID::EN : ID::E;
IdString tri_type = cell->type == TW($mux) ? TW($tribuf) : TW($_TBUF_);
TwineRef en_port = cell->type == TW($mux) ? TW::EN : TW::E;
TwineRef tri_type = cell->type == TW($mux) ? TW($tribuf) : TW($_TBUF_);
if (is_all_z(cell->getPort(TW::A)) && is_all_z(cell->getPort(TW::B))) {
module->remove(cell);
@ -86,7 +86,7 @@ struct TribufWorker {
cell->setPort(en_port, cell->getPort(TW::S));
cell->unsetPort(TW::B);
cell->unsetPort(TW::S);
cell->type_impl = cell->module->design->twines.add(Twine{tri_type.str()});
cell->type_impl = tri_type;
tribuf_cells[sigmap(cell->getPort(TW::Y))].push_back(cell);
module->design->scratchpad_set_bool("tribuf.added_something", true);
continue;
@ -96,7 +96,7 @@ struct TribufWorker {
cell->setPort(en_port, module->Not(NEW_TWINE, cell->getPort(TW::S)));
cell->unsetPort(TW::B);
cell->unsetPort(TW::S);
cell->type_impl = cell->module->design->twines.add(Twine{tri_type.str()});
cell->type_impl = tri_type;
tribuf_cells[sigmap(cell->getPort(TW::Y))].push_back(cell);
module->design->scratchpad_set_bool("tribuf.added_something", true);
continue;
@ -143,7 +143,7 @@ struct TribufWorker {
auto conflict = module->And(NEW_TWINE, cell_s, other_s);
std::string name = stringf("$tribuf_conflict$%s", cell->module->design->twines.str(cell->meta_->name));
auto assert_cell = module->addAssert(name, module->Not(NEW_TWINE, conflict), SigSpec(true));
auto assert_cell = module->addAssert(Twine{name}, module->Not(NEW_TWINE, conflict), SigSpec(true));
assert_cell->adopt_src_from(cell);
assert_cell->set_bool_attribute(ID::keep);