mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-25 16:42:35 +00:00
WIP migration to twine
This commit is contained in:
Emil J. Tywoniak
parent
25f27026f0
commit
96b0ba9581
51 changed files with 289 additions and 275 deletions
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@ -269,7 +269,7 @@ end_of_header:
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else
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log_abort();
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RTLIL::Wire* n0 = module->wire(design->twines.lookup(stringf("$aiger%d$0", aiger_autoidx)));
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RTLIL::Wire* n0 = module->wire(TwineSearch(&design->twines).find(stringf("$aiger%d$0", aiger_autoidx)));
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if (n0)
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module->connect(n0, State::S0);
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@ -294,7 +294,7 @@ end_of_header:
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log_assert(l1 < latches.size());
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wire = latches[l1];
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} else if (c == 'o') {
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wire = module->wire(design->twines.lookup(escaped_s.str()));
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wire = module->wire(TwineSearch(&design->twines).find(escaped_s.str()));
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log_assert(l1 < outputs.size());
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if (wire) {
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// Could have been renamed by a latch
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@ -347,16 +347,16 @@ RTLIL::Wire* AigerReader::createWireIfNotExists(RTLIL::Module *module, unsigned
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const unsigned variable = literal >> 1;
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const bool invert = literal & 1;
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RTLIL::IdString wire_name(stringf("$aiger%d$%d%s", aiger_autoidx, variable, invert ? "b" : ""));
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RTLIL::Wire *wire = module->wire(design->twines.lookup(wire_name.str()));
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RTLIL::Wire *wire = module->wire(TwineSearch(&design->twines).find(wire_name.str()));
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if (wire) return wire;
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log_debug2("Creating %s\n", wire_name.c_str());
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wire = module->addWire(Twine{wire_name.str()});
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wire->port_input = wire->port_output = false;
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if (!invert) return wire;
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RTLIL::IdString wire_inv_name(stringf("$aiger%d$%d", aiger_autoidx, variable));
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RTLIL::Wire *wire_inv = module->wire(design->twines.lookup(wire_inv_name.str()));
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RTLIL::Wire *wire_inv = module->wire(TwineSearch(&design->twines).find(wire_inv_name.str()));
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if (wire_inv) {
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if (module->cell(design->twines.lookup(wire_inv_name.str()))) return wire;
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if (module->cell(TwineSearch(&design->twines).find(wire_inv_name.str()))) return wire;
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}
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else {
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log_debug2("Creating %s\n", wire_inv_name.c_str());
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@ -402,7 +402,7 @@ void AigerReader::parse_xaiger()
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else
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log_abort();
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RTLIL::Wire* n0 = module->wire(design->twines.lookup(stringf("$aiger%d$0", aiger_autoidx)));
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RTLIL::Wire* n0 = module->wire(TwineSearch(&design->twines).find(stringf("$aiger%d$0", aiger_autoidx)));
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if (n0)
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module->connect(n0, State::S0);
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@ -426,7 +426,7 @@ void AigerReader::parse_xaiger()
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uint32_t rootNodeID = parse_xaiger_literal(f);
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uint32_t cutLeavesM = parse_xaiger_literal(f);
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log_debug2("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM);
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RTLIL::Wire *output_sig = module->wire(design->twines.lookup(stringf("$aiger%d$%d", aiger_autoidx, rootNodeID)));
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RTLIL::Wire *output_sig = module->wire(TwineSearch(&design->twines).find(stringf("$aiger%d$%d", aiger_autoidx, rootNodeID)));
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log_assert(output_sig);
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uint32_t nodeID;
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RTLIL::SigSpec input_sig;
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@ -437,7 +437,7 @@ void AigerReader::parse_xaiger()
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log_debug("\tLUT '$lut$aiger%d$%d' input %d is constant!\n", aiger_autoidx, rootNodeID, cutLeavesM);
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continue;
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}
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RTLIL::Wire *wire = module->wire(design->twines.lookup(stringf("$aiger%d$%d", aiger_autoidx, nodeID)));
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RTLIL::Wire *wire = module->wire(TwineSearch(&design->twines).find(stringf("$aiger%d$%d", aiger_autoidx, nodeID)));
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log_assert(wire);
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input_sig.append(wire);
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}
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@ -456,7 +456,7 @@ void AigerReader::parse_xaiger()
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log_assert(o.wire == nullptr);
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lut_mask.set(gray, o.data);
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}
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RTLIL::Cell *output_cell = module->cell(design->twines.lookup(stringf("$and$aiger%d$%d", aiger_autoidx, rootNodeID)));
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RTLIL::Cell *output_cell = module->cell(TwineSearch(&design->twines).find(stringf("$and$aiger%d$%d", aiger_autoidx, rootNodeID)));
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log_assert(output_cell);
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module->remove(output_cell);
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module->addLut(Twine{stringf("$lut$aiger%d$%d", aiger_autoidx, rootNodeID)}, input_sig, output_sig, std::move(lut_mask));
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@ -548,7 +548,7 @@ void AigerReader::parse_aiger_ascii()
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// Parse latches
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RTLIL::Wire *clk_wire = nullptr;
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if (L > 0 && !clk_name.empty()) {
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clk_wire = module->wire(design->twines.lookup(clk_name.str()));
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clk_wire = module->wire(TwineSearch(&design->twines).find(clk_name.str()));
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log_assert(!clk_wire);
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log_debug2("Creating %s\n", clk_name.c_str());
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clk_wire = module->addWire(Twine{clk_name.str()});
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@ -675,7 +675,7 @@ void AigerReader::parse_aiger_binary()
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// Parse latches
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RTLIL::Wire *clk_wire = nullptr;
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if (L > 0 && !clk_name.empty()) {
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clk_wire = module->wire(design->twines.lookup(clk_name.str()));
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clk_wire = module->wire(TwineSearch(&design->twines).find(clk_name.str()));
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log_assert(!clk_wire);
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log_debug2("Creating %s\n", clk_name.c_str());
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clk_wire = module->addWire(Twine{clk_name.str()});
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@ -830,7 +830,7 @@ void AigerReader::post_process()
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// Cope with the fact that a CI might be identical
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// to a PI (necessary due to ABC); in those cases
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// simply connect the latter to the former
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existing = module->wire(design->twines.lookup(escaped_s.str()));
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existing = module->wire(TwineSearch(&design->twines).find(escaped_s.str()));
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if (!existing)
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module->rename(wire, design->twines.add(Twine{escaped_s.str()}));
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else {
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@ -841,7 +841,7 @@ void AigerReader::post_process()
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}
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else {
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RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index);
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existing = module->wire(design->twines.lookup(indexed_name.str()));
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existing = module->wire(TwineSearch(&design->twines).find(indexed_name.str()));
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if (!existing)
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module->rename(wire, design->twines.add(Twine{indexed_name.str()}));
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else {
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@ -875,7 +875,7 @@ void AigerReader::post_process()
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// Cope with the fact that a CO might be identical
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// to a PO (necessary due to ABC); in those cases
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// simply connect the latter to the former
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existing = module->wire(design->twines.lookup(escaped_s.str()));
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existing = module->wire(TwineSearch(&design->twines).find(escaped_s.str()));
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if (!existing)
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module->rename(wire, design->twines.add(Twine{escaped_s.str()}));
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else {
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@ -888,7 +888,7 @@ void AigerReader::post_process()
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}
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else {
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RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index);
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existing = module->wire(design->twines.lookup(indexed_name.str()));
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existing = module->wire(TwineSearch(&design->twines).find(indexed_name.str()));
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if (!existing)
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module->rename(wire, design->twines.add(Twine{indexed_name.str()}));
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else {
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@ -912,7 +912,7 @@ void AigerReader::post_process()
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}
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}
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else if (type == "box") {
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RTLIL::Cell* cell = module->cell(design->twines.lookup(stringf("$box%d", variable)));
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RTLIL::Cell* cell = module->cell(TwineSearch(&design->twines).find(stringf("$box%d", variable)));
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if (!cell)
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log_debug("Box %d (%s) no longer exists.\n", variable, log_id(escaped_s));
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else
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@ -930,7 +930,7 @@ void AigerReader::post_process()
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if (min == 0 && max == 0)
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continue;
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RTLIL::Wire *wire = module->wire(design->twines.lookup(name.str()));
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RTLIL::Wire *wire = module->wire(TwineSearch(&design->twines).find(name.str()));
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if (wire)
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module->rename(wire, design->twines.add(Twine{RTLIL::escape_id(stringf("%s[%d]", name.str(), 0))}));
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@ -939,7 +939,7 @@ void AigerReader::post_process()
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bool port_input = false, port_output = false;
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for (int i = min; i <= max; i++) {
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RTLIL::IdString other_name = name.str() + stringf("[%d]", i);
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RTLIL::Wire *other_wire = module->wire(design->twines.lookup(other_name.str()));
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RTLIL::Wire *other_wire = module->wire(TwineSearch(&design->twines).find(other_name.str()));
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if (other_wire) {
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port_input = port_input || other_wire->port_input;
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port_output = port_output || other_wire->port_output;
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@ -953,7 +953,7 @@ void AigerReader::post_process()
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for (int i = min; i <= max; i++) {
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RTLIL::IdString other_name = stringf("%s[%d]", name, i);
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RTLIL::Wire *other_wire = module->wire(design->twines.lookup(other_name.str()));
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RTLIL::Wire *other_wire = module->wire(TwineSearch(&design->twines).find(other_name.str()));
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if (other_wire) {
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other_wire->port_input = false;
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other_wire->port_output = false;
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