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WIP migration to twine

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This commit is contained in:
Emil J. Tywoniak 2026-06-17 11:04:03 +02:00
parent 25f27026f0
commit 96b0ba9581
51 changed files with 289 additions and 275 deletions
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36
backends/aiger2/aiger.cc
View file

@ -109,7 +109,7 @@ struct Index {
int pos = index_wires(info, m);
for (auto cell : m->cells()) {
if (known_ops(cell->type) || cell->type.in(TW($scopeinfo), TW($specify2), TW($specify3), TW($input_port), TW($output_port), TW($public)))
if (known_ops(cell->type.ref()) || cell->type.in(TW($scopeinfo), TW($specify2), TW($specify3), TW($input_port), TW($output_port), TW($public)))
continue;
Module *submodule = m->design->module(cell->type_impl);
@ -628,7 +628,7 @@ struct Index {
// an output of a cell
Cell *driver = bit.wire->driverCell();
if (known_ops(driver->type)) {
if (known_ops(driver->type.ref())) {
ret = impl_op(cursor, driver, bit.wire->driverPort(), bit.offset);
} else {
Module *def = cursor.enter(*this, driver);
@ -660,7 +660,7 @@ struct Index {
auto &port = instance->getPort(portname);
if (bit.offset >= port.size())
log_error("Bit %d of input port %s on instance %s of %s unconnected\n",
bit.offset, design->twines.str(portname).c_str(), instance, design->twines.unescaped_str(instance->type));
bit.offset, design->twines.str(portname).c_str(), instance, instance->type.unescaped());
ret = visit(cursor, port[bit.offset]);
}
cursor.enter(*this, instance);
@ -845,7 +845,7 @@ struct AigerWriter : Index<AigerWriter, unsigned int, 0, 1> {
char buf[32];
snprintf(buf, sizeof(buf), "o%d ", i);
f->write(buf, strlen(buf));
std::string name = design->twines.unescaped_str(bit.wire->name);
std::string name = bit.wire->name.unescaped();
f->write(name.data(), name.size());
f->put('\n');
}
@ -858,7 +858,7 @@ struct AigerWriter : Index<AigerWriter, unsigned int, 0, 1> {
char buf[32];
snprintf(buf, sizeof(buf), "i%d ", i);
f->write(buf, strlen(buf));
std::string name = design->twines.unescaped_str(bit.wire->name);
std::string name = bit.wire->name.unescaped();
f->write(name.data(), name.size());
f->put('\n');
}
@ -899,7 +899,7 @@ struct XAigerAnalysis : Index<XAigerAnalysis, int, 0, 0> {
return false;
Cell *driver = bit.wire->driverCell();
Module *mod = design->module(driver->type);
Module *mod = design->module(driver->type.ref());
if (!mod || !mod->has_attribute(ID::abc9_box_id))
return false;
@ -935,7 +935,7 @@ struct XAigerAnalysis : Index<XAigerAnalysis, int, 0, 0> {
HierCursor cursor;
for (auto box : top_minfo->found_blackboxes) {
Module *def = design->module(box->type);
Module *def = design->module(box->type.ref());
if (!(def && def->has_attribute(ID::abc9_box_id)))
for (auto &conn : box->connections_)
if (box->port_dir(conn.first) != RTLIL::PD_INPUT)
@ -951,7 +951,7 @@ struct XAigerAnalysis : Index<XAigerAnalysis, int, 0, 0> {
}
for (auto box : top_minfo->found_blackboxes) {
Module *def = design->module(box->type);
Module *def = design->module(box->type.ref());
if (!(def && def->has_attribute(ID::abc9_box_id)))
for (auto &conn : box->connections_)
if (box->port_dir(conn.first) == RTLIL::PD_INPUT)
@ -1090,9 +1090,9 @@ struct XAigerWriter : AigerWriter {
for (auto box : minfo.found_blackboxes) {
log_debug(" - %s.%s (type %s): ", cursor.path(),
box,
design->twines.unescaped_str(box->type));
box->type.unescaped());
Module *box_module = design->module(box->type), *box_derived;
Module *box_module = design->module(box->type.ref()), *box_derived;
if (box_module && !box->parameters.empty()) {
// TODO: This is potentially costly even if a cached derivation exists
@ -1129,13 +1129,13 @@ struct XAigerWriter : AigerWriter {
nonopaque_boxes.clear();
for (auto box : boxes_order) {
HierCursor cursor;
Module *def = design->module(box->type);
Module *def = design->module(box->type.ref());
nonopaque_boxes.push_back(std::make_tuple(cursor, box, def));
}
for (auto [cursor, box, def] : nonopaque_boxes) {
// use `def->meta_->name` not `box->type` as we want the derived type
Cell *holes_wb = holes_module->addCell(NEW_TWINE, IdString(design->twines.str(def->meta_->name)));
Cell *holes_wb = holes_module->addCell(NEW_TWINE, def->meta_->name);
int holes_pi_idx = 0;
if (map_file.is_open()) {
@ -1159,7 +1159,7 @@ struct XAigerWriter : AigerWriter {
} else {
// FIXME: hierarchical path
log_warning("connection on port %s[%d] of instance %s (type %s) missing, using 1'bx\n",
design->twines.str(port_id).c_str(), i, box, design->twines.unescaped_str(box->type));
design->twines.str(port_id).c_str(), i, box, box->type.unescaped());
bit = RTLIL::Sx;
}
@ -1194,7 +1194,7 @@ struct XAigerWriter : AigerWriter {
} else {
// FIXME: hierarchical path
log_warning("connection on port %s[%d] of instance %s (type %s) missing\n",
design->twines.str(port_id).c_str(), i, box, design->twines.unescaped_str(box->type));
design->twines.str(port_id).c_str(), i, box, box->type.unescaped());
pad_pi();
continue;
}
@ -1211,7 +1211,7 @@ struct XAigerWriter : AigerWriter {
holes_wb->setPort(port_id, w);
} else {
log_error("Ambiguous port direction on %s/%s\n",
design->twines.unescaped_str(box->type), design->twines.str(port_id).c_str());
box->type.unescaped(), design->twines.str(port_id).c_str());
}
}
}
@ -1279,7 +1279,7 @@ struct XAigerWriter : AigerWriter {
// do emit a proper PO.
if (map_file.is_open() && !driven_by_opaque_box.count(SigBit(w, i))) {
map_file << "po " << proper_pos_counter << " " << i
<< " " << w->name.c_str() << "\n";
<< " " << w->name.str().c_str() << "\n";
}
proper_pos_counter++;
pos.push_back(std::make_pair(SigBit(w, i), HierCursor{}));
@ -1406,7 +1406,7 @@ struct Aiger2Backend : Backend {
continue;
if (known_ops(cell.type))
continue;
std::string name = design->twines.unescaped_str(cell.type);
std::string name = TW::str(cell.type);
if (col + name.size() + 2 > 72) {
log("\n ");
col = 0;
@ -1428,7 +1428,7 @@ struct Aiger2Backend : Backend {
continue;
if (known_ops(cell.type))
continue;
std::string name = design->twines.unescaped_str(cell.type);
std::string name = TW::str(cell.type);
if (col + name.size() + 2 > 72) {
log("\n ");
col = 0;

15
backends/blif/blif.cc
View file

@ -91,7 +91,7 @@ struct BlifDumper
const std::string str(RTLIL::IdString id)
{
std::string str = design->twines.unescaped_str(id);
std::string str = RTLIL::unescape_id(id);
for (size_t i = 0; i < str.size(); i++)
if (str[i] == '#' || str[i] == '=' || str[i] == '<' || str[i] == '>')
str[i] = '?';
@ -108,7 +108,7 @@ struct BlifDumper
return config->undef_type == "-" || config->undef_type == "+" ? config->undef_out.c_str() : "$undef";
}
std::string str = design->twines.unescaped_str(sig.wire->name);
std::string str = sig.wire->name.unescaped();
for (size_t i = 0; i < str.size(); i++)
if (str[i] == '#' || str[i] == '=' || str[i] == '<' || str[i] == '>')
str[i] = '?';
@ -140,9 +140,10 @@ struct BlifDumper
{
if (!config->gates_mode)
return "subckt";
if (design->module(RTLIL::escape_id(cell_type)) == nullptr)
TwineRef cell_type_ref = TwineSearch(&design->twines).find(RTLIL::escape_id(cell_type));
if (design->module(cell_type_ref) == nullptr)
return "gate";
if (design->module(RTLIL::escape_id(cell_type))->get_blackbox_attribute())
if (design->module(cell_type_ref)->get_blackbox_attribute())
return "gate";
return "subckt";
}
@ -150,7 +151,7 @@ struct BlifDumper
void dump_params(const char *command, dict<IdString, Const> &params)
{
for (auto &param : params) {
f << stringf("%s %s ", command, design->twines.unescaped_str(param.first));
f << stringf("%s %s ", command, RTLIL::unescape_id(param.first).c_str());
if (param.second.flags & RTLIL::CONST_FLAG_STRING) {
std::string str = param.second.decode_string();
f << stringf("\"");
@ -237,8 +238,8 @@ struct BlifDumper
if (config->unbuf_types.count(cell->type)) {
auto portnames = config->unbuf_types.at(cell->type);
TwineRef port_in = design->twines.lookup(portnames.first.str());
TwineRef port_out = design->twines.lookup(portnames.second.str());
TwineRef port_in = TwineSearch(&design->twines).find(portnames.first.str());
TwineRef port_out = TwineSearch(&design->twines).find(portnames.second.str());
f << stringf(".names %s %s\n1 1\n",
str(cell->getPort(port_in)).c_str(), str(cell->getPort(port_out)).c_str());
continue;

28
backends/btor/btor.cc
View file

@ -119,17 +119,17 @@ struct BtorWorker
template<typename T>
string getinfo(T *obj, bool srcsym = false)
{
string infostr = design->twines.unescaped_str(obj->name);
string infostr = obj->name.unescaped();
if (!srcsym && !print_internal_names && infostr[0] == '$') return "";
if (obj->has_attribute(ID::src)) {
string src = module && module->design ? module->design->get_src_attribute(obj) : std::string();
if (srcsym && infostr[0] == '$') {
std::replace(src.begin(), src.end(), ' ', '_');
TwineRef src_ref = module->design->twines.lookup(src);
TwineRef src_ref = TwineSearch(&module->design->twines).find(src);
if (srcsymbols.count(src) || src_ref != Twine::Null) {
for (int i = 1;; i++) {
string s = stringf("%s-%d", src, i);
TwineRef s_ref = module->design->twines.lookup(s);
TwineRef s_ref = TwineSearch(&module->design->twines).find(s);
if (!srcsymbols.count(s) && s_ref == Twine::Null) {
src = s;
break;
@ -147,17 +147,17 @@ struct BtorWorker
string getinfo(Mem *mem, bool srcsym = false)
{
string infostr = design->twines.unescaped_str(mem->memid);
string infostr = RTLIL::unescape_id(mem->memid);
if (!srcsym && !print_internal_names && infostr[0] == '$') return "";
if (mem->has_attribute(ID::src)) {
string src = module && module->design ? module->design->get_src_attribute(mem) : std::string();
if (srcsym && infostr[0] == '$') {
std::replace(src.begin(), src.end(), ' ', '_');
TwineRef src_ref = module->design->twines.lookup(src);
TwineRef src_ref = TwineSearch(&module->design->twines).find(src);
if (srcsymbols.count(src) || src_ref != Twine::Null) {
for (int i = 1;; i++) {
string s = stringf("%s-%d", src, i);
TwineRef s_ref = module->design->twines.lookup(s);
TwineRef s_ref = TwineSearch(&module->design->twines).find(s);
if (!srcsymbols.count(s) && s_ref == Twine::Null) {
src = s;
break;
@ -727,13 +727,13 @@ struct BtorWorker
ywmap_clock_bits[sig_c] |= negedge ? 2 : 1;
}
IdString symbol;
std::string symbol;
if (sig_q.is_wire()) {
Wire *w = sig_q.as_wire();
if (w->port_id == 0) {
statewires.insert(w);
symbol = w->name;
symbol = w->name.unescaped();
}
}
@ -756,7 +756,7 @@ struct BtorWorker
if (symbol.empty() || (!print_internal_names && symbol[0] == '$'))
btorf("%d state %d\n", nid, sid);
else
btorf("%d state %d %s\n", nid, sid, design->twines.unescaped_str(symbol));
btorf("%d state %d %s\n", nid, sid, symbol);
if (cell->get_bool_attribute(ID(clk2fflogic)))
ywmap_state(cell->getPort(TW::D)); // For a clk2fflogic FF the named signal is the D input not the Q output
@ -834,12 +834,12 @@ struct BtorWorker
if (asyncwr && syncwr)
log_error("Memory %s.%s has mixed async/sync write ports.\n",
module, design->twines.unescaped_str(mem->memid));
module, RTLIL::unescape_id(mem->memid));
for (auto &port : mem->rd_ports) {
if (port.clk_enable)
log_error("Memory %s.%s has sync read ports. Please use memory_nordff to convert them first.\n",
module, design->twines.unescaped_str(mem->memid));
module, RTLIL::unescape_id(mem->memid));
}
int data_sid = get_bv_sid(mem->width);
@ -901,7 +901,7 @@ struct BtorWorker
if (mem->memid[0] == '$')
btorf("%d state %d\n", nid, sid);
else
btorf("%d state %d %s\n", nid, sid, design->twines.unescaped_str(mem->memid));
btorf("%d state %d %s\n", nid, sid, RTLIL::unescape_id(mem->memid));
ywmap_state(cell);
@ -1417,7 +1417,7 @@ struct BtorWorker
int nid = it.first;
Mem *mem = it.second;
btorf_push(stringf("next %s", design->twines.unescaped_str(mem->memid)));
btorf_push(stringf("next %s", RTLIL::unescape_id(mem->memid)));
int abits = ceil_log2(mem->size);
@ -1465,7 +1465,7 @@ struct BtorWorker
int nid2 = next_nid++;
btorf("%d next %d %d %d%s\n", nid2, sid, nid, nid_head, getinfo(mem));
btorf_pop(stringf("next %s", design->twines.unescaped_str(mem->memid)));
btorf_pop(stringf("next %s", RTLIL::unescape_id(mem->memid)));
}
}

54
backends/cxxrtl/cxxrtl_backend.cc
View file

@ -214,7 +214,7 @@ bool is_ff_cell(TwineRef type)
bool is_internal_cell(TwineRef type)
{
return !type.isPublic() && !type.begins_with("$paramod");
return !type.is_public() && type.untag().value < STATIC_TWINE_END;
}
bool is_effectful_cell(TwineRef type)
@ -435,11 +435,11 @@ struct FlowGraph {
{
for (auto conn : cell->connections()) {
if (cell->output(conn.first)) {
if (is_inlinable_cell(cell->type))
if (is_inlinable_cell(cell->type.ref()))
add_defs(node, conn.second, /*is_ff=*/false, /*inlinable=*/true);
else if (is_ff_cell(cell->type))
else if (is_ff_cell(cell->type.ref()))
add_defs(node, conn.second, /*is_ff=*/true, /*inlinable=*/false);
else if (is_internal_cell(cell->type))
else if (is_internal_cell(cell->type.ref()))
add_defs(node, conn.second, /*is_ff=*/false, /*inlinable=*/false);
else if (!is_cxxrtl_sync_port(cell, conn.first)) {
// Although at first it looks like outputs of user-defined cells may always be inlined, the reality is
@ -687,7 +687,7 @@ struct WireType {
}
WireType(Type type, const RTLIL::Cell *cell) : type(type), cell_subst(cell) {
log_assert(type == INLINE && is_inlinable_cell(cell->type));
log_assert(type == INLINE && is_inlinable_cell(cell->type.ref()));
}
WireType(Type type, RTLIL::SigSpec sig) : type(type), sig_subst(sig) {
@ -1150,17 +1150,17 @@ struct CxxrtlWorker {
void dump_cell_expr(const RTLIL::Cell *cell, bool for_debug = false)
{
// Unary cells
if (is_unary_cell(cell->type)) {
if (is_unary_cell(cell->type.ref())) {
f << cell->type.substr(1);
if (is_extending_cell(cell->type))
if (is_extending_cell(cell->type.ref()))
f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u');
f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
f << ")";
// Binary cells
} else if (is_binary_cell(cell->type)) {
} else if (is_binary_cell(cell->type.ref())) {
f << cell->type.substr(1);
if (is_extending_cell(cell->type))
if (is_extending_cell(cell->type.ref()))
f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') <<
(cell->getParam(ID::B_SIGNED).as_bool() ? 's' : 'u');
f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
@ -1380,14 +1380,14 @@ struct CxxrtlWorker {
dump_inlined_cells(inlined_cells);
// Elidable cells
if (is_inlinable_cell(cell->type)) {
if (is_inlinable_cell(cell->type.ref())) {
f << indent;
dump_sigspec_lhs(cell->getPort(TW::Y), for_debug);
f << " = ";
dump_cell_expr(cell, for_debug);
f << ";\n";
// Effectful cells
} else if (is_effectful_cell(cell->type)) {
} else if (is_effectful_cell(cell->type.ref())) {
log_assert(!for_debug);
// Sync effectful cells are grouped into EFFECT_SYNC nodes in the FlowGraph.
@ -1419,7 +1419,7 @@ struct CxxrtlWorker {
f << indent << "}\n";
}
// Flip-flops
} else if (is_ff_cell(cell->type)) {
} else if (is_ff_cell(cell->type.ref())) {
log_assert(!for_debug);
// Clocks might be slices of larger signals but should only ever be single bit
if (cell->hasPort(TW::CLK) && is_valid_clock(cell->getPort(TW::CLK))) {
@ -1535,7 +1535,7 @@ struct CxxrtlWorker {
}
// Internal cells
} else if (cell->type.in(TW($input_port), TW($output_port), TW($public))) {
} else if (is_internal_cell(cell->type)) {
} else if (is_internal_cell(cell->type.ref())) {
log_cmd_error("Unsupported internal cell `%s'.\n", cell->type);
// User cells
} else if (for_debug) {
@ -1776,7 +1776,7 @@ struct CxxrtlWorker {
for (auto &action : sync->actions)
dump_assign(action, for_debug);
for (auto &memwr : sync->mem_write_actions) {
TwineRef memid_ref = proc->module->design->twines.lookup(memwr.memid.str());
TwineRef memid_ref = TwineSearch(&proc->module->design->twines).find(memwr.memid.str());
log_assert(memid_ref != Twine::Null);
RTLIL::Memory *memory = proc->module->memories[memid_ref];
std::string valid_index_temp = fresh_temporary();
@ -2164,10 +2164,10 @@ struct CxxrtlWorker {
}
for (auto cell : module->cells()) {
// Async and initial effectful cells have additional state, which must be reset as well.
if (is_effectful_cell(cell->type))
if (is_effectful_cell(cell->type.ref()))
if (!cell->getParam(ID::TRG_ENABLE).as_bool() || cell->getParam(ID::TRG_WIDTH).as_int() == 0)
f << indent << mangle(cell) << " = {};\n";
if (is_internal_cell(cell->type))
if (is_internal_cell(cell->type.ref()))
continue;
f << indent << mangle(cell);
RTLIL::Module *cell_module = module->design->module(cell->type_impl);
@ -2289,7 +2289,7 @@ struct CxxrtlWorker {
f << indent << "if (" << mangle(&mem) << ".commit(observer)) changed = true;\n";
}
for (auto cell : module->cells()) {
if (is_internal_cell(cell->type))
if (is_internal_cell(cell->type.ref()))
continue;
const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
f << indent << "if (" << mangle(cell) << access << "commit(observer)) changed = true;\n";
@ -2584,7 +2584,7 @@ struct CxxrtlWorker {
f << indent << "}\n";
if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
for (auto cell : module->cells()) {
if (is_internal_cell(cell->type))
if (is_internal_cell(cell->type.ref()))
continue;
const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
f << indent << mangle(cell) << access;
@ -2694,7 +2694,7 @@ struct CxxrtlWorker {
bool has_cells = false;
for (auto cell : module->cells()) {
// Async and initial effectful cells have additional state, which requires storage.
if (is_effectful_cell(cell->type)) {
if (is_effectful_cell(cell->type.ref())) {
if (cell->getParam(ID::TRG_ENABLE).as_bool() && cell->getParam(ID::TRG_WIDTH).as_int() == 0)
f << indent << "value<1> " << mangle(cell) << ";\n"; // async initial cell
if (!cell->getParam(ID::TRG_ENABLE).as_bool() && cell->type == TW($print))
@ -2702,7 +2702,7 @@ struct CxxrtlWorker {
if (!cell->getParam(ID::TRG_ENABLE).as_bool() && cell->type == TW($check))
f << indent << "value<2> " << mangle(cell) << ";\n"; // {EN, A}
}
if (is_internal_cell(cell->type))
if (is_internal_cell(cell->type.ref()))
continue;
dump_attrs(cell);
RTLIL::Module *cell_module = module->design->module(cell->type_impl);
@ -2820,7 +2820,7 @@ struct CxxrtlWorker {
topo_design.node(module);
for (auto cell : module->cells()) {
if (is_internal_cell(cell->type) || is_cxxrtl_blackbox_cell(cell))
if (is_internal_cell(cell->type.ref()) || is_cxxrtl_blackbox_cell(cell))
continue;
RTLIL::Module *cell_module = design->module(cell->type_impl);
log_assert(cell_module != nullptr);
@ -3034,7 +3034,7 @@ struct CxxrtlWorker {
}
// Effectful cells may be triggered on posedge/negedge events.
if (is_effectful_cell(cell->type) && cell->getParam(ID::TRG_ENABLE).as_bool()) {
if (is_effectful_cell(cell->type.ref()) && cell->getParam(ID::TRG_ENABLE).as_bool()) {
for (size_t i = 0; i < (size_t)cell->getParam(ID::TRG_WIDTH).as_int(); i++) {
RTLIL::SigBit trg = cell->getPort(TW::TRG).extract(i, 1);
if (is_valid_clock(trg))
@ -3175,9 +3175,9 @@ struct CxxrtlWorker {
// Discover nodes reachable from primary outputs (i.e. members) and collect reachable wire users.
pool<FlowGraph::Node*> worklist;
for (auto node : flow.nodes) {
if (node->type == FlowGraph::Node::Type::CELL_EVAL && !is_internal_cell(node->cell->type))
if (node->type == FlowGraph::Node::Type::CELL_EVAL && !is_internal_cell(node->cell->type.ref()))
worklist.insert(node); // node evaluates a submodule
else if (node->type == FlowGraph::Node::Type::CELL_EVAL && is_effectful_cell(node->cell->type))
else if (node->type == FlowGraph::Node::Type::CELL_EVAL && is_effectful_cell(node->cell->type.ref()))
worklist.insert(node); // node has async effects
else if (node->type == FlowGraph::Node::Type::EFFECT_SYNC)
worklist.insert(node); // node has sync effects
@ -3224,7 +3224,7 @@ struct CxxrtlWorker {
FlowGraph::Node *node = *flow.wire_comb_defs[wire].begin();
switch (node->type) {
case FlowGraph::Node::Type::CELL_EVAL:
if (!is_inlinable_cell(node->cell->type)) continue;
if (!is_inlinable_cell(node->cell->type.ref())) continue;
wire_type = {WireType::INLINE, node->cell}; // wire replaced with cell
break;
case FlowGraph::Node::Type::CONNECT:
@ -3242,7 +3242,7 @@ struct CxxrtlWorker {
for (auto node : node_order)
if (live_nodes[node]) {
if (node->type == FlowGraph::Node::Type::CELL_EVAL &&
is_effectful_cell(node->cell->type) &&
is_effectful_cell(node->cell->type.ref()) &&
node->cell->getParam(ID::TRG_ENABLE).as_bool() &&
node->cell->getParam(ID::TRG_WIDTH).as_int() != 0)
effect_sync_cells[make_pair(node->cell->getPort(TW::TRG), node->cell->getParam(ID::TRG_POLARITY))].push_back(node->cell);
@ -3362,7 +3362,7 @@ struct CxxrtlWorker {
FlowGraph::Node *node = *flow.wire_comb_defs[wire].begin();
switch (node->type) {
case FlowGraph::Node::Type::CELL_EVAL:
if (!is_inlinable_cell(node->cell->type)) continue;
if (!is_inlinable_cell(node->cell->type.ref())) continue;
debug_wire_type = {WireType::INLINE, node->cell}; // wire replaced with cell
break;
case FlowGraph::Node::Type::CONNECT:

4
backends/simplec/simplec.cc
View file

@ -337,7 +337,7 @@ struct SimplecWorker
topo.sort();
for (int i = 0; i < GetSize(topo.sorted); i++)
topoidx[mod->cell(design->twines.lookup(topo.sorted[i].str()))] = i;
topoidx[mod->cell(TwineSearch(&design->twines).find(topo.sorted[i].str()))] = i;
string ifdef_name = stringf("yosys_simplec_%s_state_t", cid(RTLIL::IdString(design->twines.str(mod->meta_->name))));
@ -527,7 +527,7 @@ struct SimplecWorker
for (auto outbit : bit2output[work->module][bit])
{
Module *parent_mod = work->parent->module;
Cell *parent_cell = parent_mod->cell(parent_mod->design->twines.lookup(work->hiername.str()));
Cell *parent_cell = parent_mod->cell(TwineSearch(&parent_mod->design->twines).find(work->hiername.str()));
TwineRef port_name = outbit.wire->meta_->name;
int port_offset = outbit.offset;

2
backends/smt2/smt2.cc
View file

@ -1867,7 +1867,7 @@ struct Smt2Backend : public Backend {
for (auto mod : design->modules()) {
module_deps[mod] = std::set<RTLIL::Module*>();
for (auto cell : mod->cells()) {
TwineRef cell_type_ref = design->twines.lookup(cell->type.str());
TwineRef cell_type_ref = TwineSearch(&design->twines).find(cell->type.str());
if (cell_type_ref != Twine::Null && design->has(cell_type_ref))
module_deps[mod].insert(design->module(cell_type_ref));
}

2
backends/spice/spice.cc
View file

@ -104,7 +104,7 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
for (RTLIL::Wire *wire : ports) {
log_assert(wire != NULL);
RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width);
TwineRef wire_name_ref = design->twines.lookup(wire->name.str());
TwineRef wire_name_ref = TwineSearch(&design->twines).find(wire->name.str());
if (cell->hasPort(wire_name_ref)) {
sig = sigmap(cell->getPort(wire_name_ref));
sig.extend_u0(wire->width, false);