Replaced RTLIL::Const::str with generic decoder method

backends/edif/edif.cc

@@ -280,8 +280,8 @@ struct EdifBackend : public Backend {
 				fprintf(f, "            (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_NAME(cell->type),
 						lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
 				for (auto &p : cell->parameters)
-					if (!p.second.str.empty())
+					if ((p.second.flags & RTLIL::CONST_FLAG_STRING) != 0)
-						fprintf(f, "\n            (property %s (string \"%s\"))", EDIF_NAME(p.first), p.second.str.c_str());
+						fprintf(f, "\n            (property %s (string \"%s\"))", EDIF_NAME(p.first), p.second.decode_string().c_str());
 					else if (p.second.bits.size() <= 32 && RTLIL::SigSpec(p.second).is_fully_def())
 						fprintf(f, "\n            (property %s (integer %u))", EDIF_NAME(p.first), p.second.as_int());
 					else {

backends/ilang/ilang_backend.cc

@@ -36,7 +36,7 @@ void ILANG_BACKEND::dump_const(FILE *f, const RTLIL::Const &data, int width, int
 {
 	if (width < 0)
 		width = data.bits.size() - offset;
-	if (data.str.empty() || width != (int)data.bits.size()) {
+	if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) {
 		if (width == 32 && autoint) {
 			int32_t val = 0;
 			for (int i = 0; i < width; i++) {
@@ -66,17 +66,20 @@ void ILANG_BACKEND::dump_const(FILE *f, const RTLIL::Const &data, int width, int
 		}
 	} else {
 		fprintf(f, "\"");
-		for (size_t i = 0; i < data.str.size(); i++) {
+		std::string str = data.decode_string();
-			if (data.str[i] == '\n')
+		for (size_t i = 0; i < str.size(); i++) {
+			if (str[i] == '\n')
 				fprintf(f, "\\n");
-			else if (data.str[i] == '\t')
+			else if (str[i] == '\t')
 				fprintf(f, "\\t");
-			else if (data.str[i] < 32)
+			else if (str[i] < 32)
-				fprintf(f, "\\%03o", data.str[i]);
+				fprintf(f, "\\%03o", str[i]);
-			else if (data.str[i] == '"')
+			else if (str[i] == '"')
 				fprintf(f, "\\\"");
+			else if (str[i] == '\\')
+				fprintf(f, "\\\\");
 			else
-				fputc(data.str[i], f);
+				fputc(str[i], f);
 		}
 		fprintf(f, "\"");
 	}

backends/verilog/verilog_backend.cc

@@ -153,7 +153,7 @@ void dump_const(FILE *f, RTLIL::Const &data, int width = -1, int offset = 0, boo
 {
 	if (width < 0)
 		width = data.bits.size() - offset;
-	if (data.str.empty() || width != (int)data.bits.size()) {
+	if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) {
 		if (width == 32 && !no_decimal) {
 			int32_t val = 0;
 			for (int i = offset+width-1; i >= offset; i--) {
@@ -184,17 +184,20 @@ void dump_const(FILE *f, RTLIL::Const &data, int width = -1, int offset = 0, boo
 		}
 	} else {
 		fprintf(f, "\"");
-		for (size_t i = 0; i < data.str.size(); i++) {
+		std::string str = data.decode_string();
-			if (data.str[i] == '\n')
+		for (size_t i = 0; i < str.size(); i++) {
+			if (str[i] == '\n')
 				fprintf(f, "\\n");
-			else if (data.str[i] == '\t')
+			else if (str[i] == '\t')
 				fprintf(f, "\\t");
-			else if (data.str[i] < 32)
+			else if (str[i] < 32)
-				fprintf(f, "\\%03o", data.str[i]);
+				fprintf(f, "\\%03o", str[i]);
-			else if (data.str[i] == '"')
+			else if (str[i] == '"')
 				fprintf(f, "\\\"");
+			else if (str[i] == '\\')
+				fprintf(f, "\\\\");
 			else
-				fputc(data.str[i], f);
+				fputc(str[i], f);
 		}
 		fprintf(f, "\"");
 	}

frontends/ast/ast.cc

@@ -677,6 +677,29 @@ RTLIL::Const AstNode::bitsAsConst(int width)
 	return bitsAsConst(width, is_signed);
 }
 
+RTLIL::Const AstNode::asAttrConst()
+{
+	log_assert(type == AST_CONSTANT);
+
+	RTLIL::Const val;
+	val.bits = bits;
+
+	if (!str.empty()) {
+		val.flags |= RTLIL::CONST_FLAG_STRING;
+		log_assert(val.decode_string() == str);
+	}
+
+	return val;
+}
+
+RTLIL::Const AstNode::asParaConst()
+{
+	RTLIL::Const val = asAttrConst();
+	if (is_signed)
+		val.flags |= RTLIL::CONST_FLAG_SIGNED;
+	return val;
+}
+
 // create a new AstModule from an AST_MODULE AST node
 static AstModule* process_module(AstNode *ast)
 {
@@ -729,8 +752,7 @@ static AstModule* process_module(AstNode *ast)
 		if (attr.second->type != AST_CONSTANT)
 			log_error("Attribute `%s' with non-constant value at %s:%d!\n",
 					attr.first.c_str(), ast->filename.c_str(), ast->linenum);
-		current_module->attributes[attr.first].str = attr.second->str;
+		current_module->attributes[attr.first] = attr.second->asAttrConst();
-		current_module->attributes[attr.first].bits = attr.second->bits;
 	}
 	for (size_t i = 0; i < ast->children.size(); i++) {
 		AstNode *node = ast->children[i];

frontends/ast/ast.h

@@ -216,6 +216,8 @@ namespace AST
 		// helper function for creating sign-extended const objects
 		RTLIL::Const bitsAsConst(int width, bool is_signed);
 		RTLIL::Const bitsAsConst(int width = -1);
+		RTLIL::Const asAttrConst();
+		RTLIL::Const asParaConst();
 	};
 
 	// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code

frontends/ast/genrtlil.cc

@@ -70,8 +70,7 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi
 			if (attr.second->type != AST_CONSTANT)
 				log_error("Attribute `%s' with non-constant value at %s:%d!\n",
 						attr.first.c_str(), that->filename.c_str(), that->linenum);
-			cell->attributes[attr.first].str = attr.second->str;
+			cell->attributes[attr.first] = attr.second->asAttrConst();
-			cell->attributes[attr.first].bits = attr.second->bits;
 		}
 
 	cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
@@ -120,8 +119,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
 			if (attr.second->type != AST_CONSTANT)
 				log_error("Attribute `%s' with non-constant value at %s:%d!\n",
 						attr.first.c_str(), that->filename.c_str(), that->linenum);
-			cell->attributes[attr.first].str = attr.second->str;
+			cell->attributes[attr.first] = attr.second->asAttrConst();
-			cell->attributes[attr.first].bits = attr.second->bits;
 		}
 
 	cell->parameters["\\A_SIGNED"] = RTLIL::Const(is_signed);
@@ -164,8 +162,7 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_wi
 		if (attr.second->type != AST_CONSTANT)
 			log_error("Attribute `%s' with non-constant value at %s:%d!\n",
 					attr.first.c_str(), that->filename.c_str(), that->linenum);
-		cell->attributes[attr.first].str = attr.second->str;
+		cell->attributes[attr.first] = attr.second->asAttrConst();
-		cell->attributes[attr.first].bits = attr.second->bits;
 	}
 
 	cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
@@ -215,8 +212,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
 		if (attr.second->type != AST_CONSTANT)
 			log_error("Attribute `%s' with non-constant value at %s:%d!\n",
 					attr.first.c_str(), that->filename.c_str(), that->linenum);
-		cell->attributes[attr.first].str = attr.second->str;
+		cell->attributes[attr.first] = attr.second->asAttrConst();
-		cell->attributes[attr.first].bits = attr.second->bits;
 	}
 
 	cell->parameters["\\WIDTH"] = RTLIL::Const(left.width);
@@ -271,8 +267,7 @@ struct AST_INTERNAL::ProcessGenerator
 			if (attr.second->type != AST_CONSTANT)
 				log_error("Attribute `%s' with non-constant value at %s:%d!\n",
 						attr.first.c_str(), always->filename.c_str(), always->linenum);
-			proc->attributes[attr.first].str = attr.second->str;
+			proc->attributes[attr.first] = attr.second->asAttrConst();
-			proc->attributes[attr.first].bits = attr.second->bits;
 		}
 		current_module->processes[proc->name] = proc;
 		current_case = &proc->root_case;
@@ -491,8 +486,7 @@ struct AST_INTERNAL::ProcessGenerator
 					if (attr.second->type != AST_CONSTANT)
 						log_error("Attribute `%s' with non-constant value at %s:%d!\n",
 								attr.first.c_str(), ast->filename.c_str(), ast->linenum);
-					sw->attributes[attr.first].str = attr.second->str;
+					sw->attributes[attr.first] = attr.second->asAttrConst();
-					sw->attributes[attr.first].bits = attr.second->bits;
 				}
 
 				RTLIL::SigSpec this_case_eq_lvalue;
@@ -854,8 +848,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				if (attr.second->type != AST_CONSTANT)
 					log_error("Attribute `%s' with non-constant value at %s:%d!\n",
 							attr.first.c_str(), filename.c_str(), linenum);
-				wire->attributes[attr.first].str = attr.second->str;
+				wire->attributes[attr.first] = attr.second->asAttrConst();
-				wire->attributes[attr.first].bits = attr.second->bits;
 			}
 		}
 		break;
@@ -890,8 +883,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				if (attr.second->type != AST_CONSTANT)
 					log_error("Attribute `%s' with non-constant value at %s:%d!\n",
 							attr.first.c_str(), filename.c_str(), linenum);
-				memory->attributes[attr.first].str = attr.second->str;
+				memory->attributes[attr.first] = attr.second->asAttrConst();
-				memory->attributes[attr.first].bits = attr.second->bits;
 			}
 		}
 		break;
@@ -1314,13 +1306,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 						snprintf(buf, 100, "$%d", ++para_counter);
 						if (child->children[0]->is_signed)
 							cell->signed_parameters.insert(buf);
-						cell->parameters[buf].str = child->children[0]->str;
+						cell->parameters[buf] = child->children[0]->asParaConst();
-						cell->parameters[buf].bits = child->children[0]->bits;
 					} else {
 						if (child->children[0]->is_signed)
 							cell->signed_parameters.insert(child->str);
-						cell->parameters[child->str].str = child->children[0]->str;
+						cell->parameters[child->str] = child->children[0]->asParaConst();
-						cell->parameters[child->str].bits = child->children[0]->bits;
 					}
 					continue;
 				}
@@ -1343,8 +1333,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				if (attr.second->type != AST_CONSTANT)
 					log_error("Attribute `%s' with non-constant value at %s:%d!\n",
 							attr.first.c_str(), filename.c_str(), linenum);
-				cell->attributes[attr.first].str = attr.second->str;
+				cell->attributes[attr.first] = attr.second->asAttrConst();
-				cell->attributes[attr.first].bits = attr.second->bits;
 			}
 			if (current_module->cells.count(cell->name) != 0)
 				log_error("Re-definition of cell `%s' at %s:%d!\n",

kernel/rtlil.cc

@@ -28,9 +28,15 @@
 
 int RTLIL::autoidx = 1;
 
-RTLIL::Const::Const(std::string str) : str(str)
+RTLIL::Const::Const()
 {
-	for (size_t i = 0; i < str.size(); i++) {
+	flags = RTLIL::CONST_FLAG_NONE;
+}
+
+RTLIL::Const::Const(std::string str)
+{
+	flags = RTLIL::CONST_FLAG_STRING;
+	for (int i = str.size()-1; i >= 0; i--) {
 		unsigned char ch = str[i];
 		for (int j = 0; j < 8; j++) {
 			bits.push_back((ch & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
@@ -41,6 +47,7 @@ RTLIL::Const::Const(std::string str) : str(str)
 
 RTLIL::Const::Const(int val, int width)
 {
+	flags = RTLIL::CONST_FLAG_NONE;
 	for (int i = 0; i < width; i++) {
 		bits.push_back((val & 1) != 0 ? RTLIL::S1 : RTLIL::S0);
 		val = val >> 1;
@@ -49,6 +56,7 @@ RTLIL::Const::Const(int val, int width)
 
 RTLIL::Const::Const(RTLIL::State bit, int width)
 {
+	flags = RTLIL::CONST_FLAG_NONE;
 	for (int i = 0; i < width; i++)
 		bits.push_back(bit);
 }
@@ -105,6 +113,23 @@ std::string RTLIL::Const::as_string() const
 	return ret;
 }
 
+std::string RTLIL::Const::decode_string() const
+{
+	std::string string;
+	std::vector <char> string_chars;
+	for (int i = 0; i < int (bits.size()); i += 8) {
+		char ch = 0;
+		for (int j = 0; j < 8 && i + j < int (bits.size()); j++)
+			if (bits[i + j] == RTLIL::State::S1)
+				ch |= 1 << j;
+		if (ch != 0)
+			string_chars.push_back(ch);
+	}
+	for (int i = int (string_chars.size()) - 1; i >= 0; i--)
+		string += string_chars[i];
+	return string;
+}
+
 bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
 {
 	if (full_selection)
@@ -965,7 +990,6 @@ void RTLIL::SigSpec::expand()
 {
 	std::vector<RTLIL::SigChunk> new_chunks;
 	for (size_t i = 0; i < chunks.size(); i++) {
-		assert(chunks[i].data.str.empty());
 		for (int j = 0; j < chunks[i].width; j++)
 			new_chunks.push_back(chunks[i].extract(j, 1));
 	}
@@ -1323,13 +1347,11 @@ void RTLIL::SigSpec::check() const
 		if (chunk.wire == NULL) {
 			assert(chunk.offset == 0);
 			assert(chunk.data.bits.size() == (size_t)chunk.width);
-			assert(chunk.data.str.size() == 0 || chunk.data.str.size()*8 == chunk.data.bits.size());
 		} else {
 			assert(chunk.offset >= 0);
 			assert(chunk.width >= 0);
 			assert(chunk.offset + chunk.width <= chunk.wire->width);
 			assert(chunk.data.bits.size() == 0);
-			assert(chunk.data.str.size() == 0);
 		}
 		w += chunk.width;
 	}

kernel/rtlil.h

@@ -38,6 +38,7 @@ namespace RTLIL
 		Sa = 4, // don't care (used only in cases)
 		Sm = 5  // marker (used internally by some passes)
 	};
+
 	enum SyncType {
 		ST0 = 0, // level sensitive: 0
 		ST1 = 1, // level sensitive: 1
@@ -48,6 +49,13 @@ namespace RTLIL
 		STi = 6  // init
 	};
 
+	enum ConstFlags {
+		CONST_FLAG_NONE   = 0,
+		CONST_FLAG_STRING = 1,
+		CONST_FLAG_SIGNED = 2,  // unused -- to be used for parameters
+		CONST_FLAG_REAL   = 4   // unused -- to be used for parameters
+	};
+
 	extern int autoidx;
 
 	struct Const;
@@ -181,9 +189,10 @@ namespace RTLIL
 };
 
 struct RTLIL::Const {
-	std::string str;
+	int flags;
 	std::vector<RTLIL::State> bits;
-	Const(std::string str = std::string());
+	Const();
+	Const(std::string str);
 	Const(int val, int width = 32);
 	Const(RTLIL::State bit, int width = 1);
 	Const(std::vector<RTLIL::State> bits) : bits(bits) { };
@@ -193,6 +202,7 @@ struct RTLIL::Const {
 	bool as_bool() const;
 	int as_int() const;
 	std::string as_string() const;
+	std::string decode_string() const;
 };
 
 struct RTLIL::Selection {

passes/cmds/select.cc

@@ -48,7 +48,9 @@ static bool match_ids(RTLIL::IdString id, std::string pattern)
 
 static bool match_attr_val(const RTLIL::Const &value, std::string pattern)
 {
-	if (!fnmatch(pattern.c_str(), value.str.c_str(), FNM_NOESCAPE))
+	if ((value.flags & RTLIL::CONST_FLAG_STRING) == 0)
+		return false;
+	if (!fnmatch(pattern.c_str(), value.decode_string().c_str(), FNM_NOESCAPE))
 		return true;
 	return false;
 }

passes/cmds/show.cc

@@ -400,7 +400,7 @@ struct ShowWorker
 
 			std::string proc_src = RTLIL::unescape_id(proc->name);
 			if (proc->attributes.count("\\src") > 0)
-				proc_src = proc->attributes.at("\\src").str;
+				proc_src = proc->attributes.at("\\src").decode_string();
 			fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\"];\n", pidx, escape(proc->name, true), proc_src.c_str());
 		}
 

passes/fsm/fsm_export.cc

@@ -60,8 +60,8 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st
 	attr_it = cell->attributes.find("\\fsm_export");
 	if (!filename.empty()) {
 	  kiss_name.assign(filename);
-	} else if (attr_it != cell->attributes.end() && attr_it->second.str != "") {
+	} else if (attr_it != cell->attributes.end() && attr_it->second.decode_string() != "") {
-		kiss_name.assign(attr_it->second.str);
+		kiss_name.assign(attr_it->second.decode_string());
 	}
 	else {
 		kiss_name.assign(module->name);

passes/fsm/fsm_extract.cc

@@ -376,7 +376,7 @@ struct FsmExtractPass : public Pass {
 
 			std::vector<RTLIL::Wire*> wire_list;
 			for (auto &wire_it : module->wires)
-				if (wire_it.second->attributes.count("\\fsm_encoding") > 0 && wire_it.second->attributes["\\fsm_encoding"].str != "none")
+				if (wire_it.second->attributes.count("\\fsm_encoding") > 0 && wire_it.second->attributes["\\fsm_encoding"].decode_string() != "none")
 					if (design->selected(module, wire_it.second))
 						wire_list.push_back(wire_it.second);
 			for (auto wire : wire_list)

passes/fsm/fsm_map.cc

@@ -168,7 +168,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 	// create state register
 
 	RTLIL::Wire *state_wire = new RTLIL::Wire;
-	state_wire->name = fsm_cell->parameters["\\NAME"].str;
+	state_wire->name = fsm_cell->parameters["\\NAME"].decode_string();
 	while (module->count_id(state_wire->name) > 0)
 		state_wire->name += "_";
 	state_wire->width = fsm_data.state_bits;

passes/fsm/fsm_opt.cc

@@ -42,7 +42,7 @@ struct FsmOpt
 		if (!wire || wire->attributes.count("\\unused_bits") == 0)
 			return false;
 		
-		char *str = strdup(wire->attributes["\\unused_bits"].str.c_str());
+		char *str = strdup(wire->attributes["\\unused_bits"].decode_string().c_str());
 		for (char *tok = strtok(str, " "); tok != NULL; tok = strtok(NULL, " ")) {
 			if (tok[0] && bit == atoi(tok))
 				return true;

passes/fsm/fsm_recode.cc

@@ -28,12 +28,12 @@
 
 static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &fsm_data, const char *prefix, FILE *f)
 {
+	std::string name = cell->parameters["\\NAME"].decode_string();
+
 	fprintf(f, "set_fsm_state_vector {");
 	for (int i = fsm_data.state_bits-1; i >= 0; i--)
-		fprintf(f, " %s_reg[%d]", cell->parameters["\\NAME"].str[0] == '\\' ?
+		fprintf(f, " %s_reg[%d]", name[0] == '\\' ?  name.substr(1).c_str() : name.c_str(), i);
-				cell->parameters["\\NAME"].str.substr(1).c_str() : cell->parameters["\\NAME"].str.c_str(), i);
+	fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n", prefix, RTLIL::unescape_id(name).c_str(),
-	fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n",
-			prefix, RTLIL::unescape_id(cell->parameters["\\NAME"].str).c_str(),
 			prefix, RTLIL::unescape_id(module->name).c_str());
 
 	fprintf(f, "set_fsm_encoding {");
@@ -43,13 +43,13 @@ static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &
 			fprintf(f, "%c", fsm_data.state_table[i].bits[j] == RTLIL::State::S1 ? '1' : '0');
 	}
 	fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n",
-			prefix, RTLIL::unescape_id(cell->parameters["\\NAME"].str).c_str(),
+			prefix, RTLIL::unescape_id(name).c_str(),
 			prefix, RTLIL::unescape_id(module->name).c_str());
 }
 
 static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fsm_file, std::string default_encoding)
 {
-	std::string encoding = cell->attributes.count("\\fsm_encoding") ? cell->attributes.at("\\fsm_encoding").str : "auto";
+	std::string encoding = cell->attributes.count("\\fsm_encoding") ? cell->attributes.at("\\fsm_encoding").decode_string() : "auto";
 
 	log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name.c_str(), module->name.c_str(), encoding.c_str());
 	if (encoding != "none" && encoding != "one-hot" && encoding != "binary") {

passes/fsm/fsmdata.h

@@ -133,7 +133,7 @@ struct FsmData
 	{
 		log("-------------------------------------\n");
 		log("\n");
-		log("  Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters["\\NAME"].str.c_str());
+		log("  Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters["\\NAME"].decode_string().c_str());
 		log("\n");
 		log("  Number of input signals:  %3d\n", num_inputs);
 		log("  Number of output signals: %3d\n", num_outputs);

passes/memory/memory_collect.cc

@@ -53,7 +53,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 	{
 		RTLIL::Cell *cell = cell_it.second;
 
-		if (cell->type == "$memwr" && cell->parameters["\\MEMID"].str == memory->name)
+		if (cell->type == "$memwr" && cell->parameters["\\MEMID"].decode_string() == memory->name)
 		{
 			wr_ports++;
 			del_cell_ids.push_back(cell->name);
@@ -80,7 +80,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 			sig_wr_en.append(en);
 		}
 
-		if (cell->type == "$memrd" && cell->parameters["\\MEMID"].str == memory->name)
+		if (cell->type == "$memrd" && cell->parameters["\\MEMID"].decode_string() == memory->name)
 		{
 			rd_ports++;
 			del_cell_ids.push_back(cell->name);

passes/memory/memory_map.cc

@@ -138,7 +138,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
 			c->connections["\\D"] = data_reg_in.back();
 
 			RTLIL::Wire *w_out = new RTLIL::Wire;
-			w_out->name = stringf("%s[%d]", cell->parameters["\\MEMID"].str.c_str(), i);
+			w_out->name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i);
 			if (module->wires.count(w_out->name) > 0)
 				w_out->name = genid(cell->name, "", i, "$q");
 			w_out->width = mem_width;

passes/submod/submod.cc

@@ -218,12 +218,12 @@ struct SubmodWorker
 			for (auto &it : module->cells)
 			{
 				RTLIL::Cell *cell = it.second;
-				if (cell->attributes.count("\\submod") == 0 || cell->attributes["\\submod"].str.size() == 0) {
+				if (cell->attributes.count("\\submod") == 0 || cell->attributes["\\submod"].bits.size() == 0) {
 					cell->attributes.erase("\\submod");
 					continue;
 				}
 
-				std::string submod_str = cell->attributes["\\submod"].str;
+				std::string submod_str = cell->attributes["\\submod"].decode_string();
 				cell->attributes.erase("\\submod");
 
 				if (submodules.count(submod_str) == 0) {

passes/techmap/techmap.cc

@@ -313,19 +313,7 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::
 						data.wire->name = new_name;
 						tpl->add(data.wire);
 
-						std::string cmd_string;
+						std::string cmd_string = data.value.as_const().decode_string();
-						std::vector<char> cmd_string_chars;
-						std::vector<RTLIL::State> bits = data.value.as_const().bits;
-						for (int i = 0; i < int(bits.size()); i += 8) {
-							char ch = 0;
-							for (int j = 0; j < 8 && i+j < int(bits.size()); j++)
-								if (bits[i+j] == RTLIL::State::S1)
-									ch |= 1 << j;
-							if (ch != 0)
-								cmd_string_chars.push_back(ch);
-						}
-						for (int i = int(cmd_string_chars.size())-1; i >= 0; i--)
-							cmd_string += cmd_string_chars[i];
 
 						RTLIL::Selection tpl_mod_sel(false);
 						tpl_mod_sel.select(tpl);
@@ -507,8 +495,8 @@ struct TechmapPass : public Pass {
 
 		std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
 		for (auto &it : map->modules) {
-			if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").str.empty()) {
+			if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").bits.empty()) {
-				char *p = strdup(it.second->attributes.at("\\techmap_celltype").str.c_str());
+				char *p = strdup(it.second->attributes.at("\\techmap_celltype").decode_string().c_str());
 				for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
 					celltypeMap[RTLIL::escape_id(q)].insert(it.first);
 				free(p);

tests/simple/values.v

@@ -33,7 +33,7 @@ always @*
 		4'b1001: y = 16'h123abc;
 		4'b1010: y = 16'o1234567;
 		4'b1011: y = 16'd3456789;
-		4'b1100: y = "foobar";
+		4'b1100: y = { "foo", "bar" };
 		4'b1101: y = "foobarfoobarfoobar";
 		4'b1110: y = 16'h1;
 		4'b1111: y = a;