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Replaced RTLIL::Const::str with generic decoder method
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parent
a2d053694b
commit
93a70959f3
21 changed files with 125 additions and 84 deletions
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@ -313,19 +313,7 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::
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data.wire->name = new_name;
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tpl->add(data.wire);
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std::string cmd_string;
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std::vector<char> cmd_string_chars;
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std::vector<RTLIL::State> bits = data.value.as_const().bits;
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for (int i = 0; i < int(bits.size()); i += 8) {
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char ch = 0;
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for (int j = 0; j < 8 && i+j < int(bits.size()); j++)
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if (bits[i+j] == RTLIL::State::S1)
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ch |= 1 << j;
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if (ch != 0)
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cmd_string_chars.push_back(ch);
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}
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for (int i = int(cmd_string_chars.size())-1; i >= 0; i--)
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cmd_string += cmd_string_chars[i];
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std::string cmd_string = data.value.as_const().decode_string();
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RTLIL::Selection tpl_mod_sel(false);
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tpl_mod_sel.select(tpl);
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@ -507,8 +495,8 @@ struct TechmapPass : public Pass {
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std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
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for (auto &it : map->modules) {
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if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").str.empty()) {
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char *p = strdup(it.second->attributes.at("\\techmap_celltype").str.c_str());
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if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").bits.empty()) {
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char *p = strdup(it.second->attributes.at("\\techmap_celltype").decode_string().c_str());
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for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
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celltypeMap[RTLIL::escape_id(q)].insert(it.first);
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free(p);
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