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Replaced RTLIL::Const::str with generic decoder method
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parent
a2d053694b
commit
93a70959f3
21 changed files with 125 additions and 84 deletions
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@ -53,7 +53,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
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{
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RTLIL::Cell *cell = cell_it.second;
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if (cell->type == "$memwr" && cell->parameters["\\MEMID"].str == memory->name)
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if (cell->type == "$memwr" && cell->parameters["\\MEMID"].decode_string() == memory->name)
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{
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wr_ports++;
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del_cell_ids.push_back(cell->name);
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@ -80,7 +80,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
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sig_wr_en.append(en);
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}
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if (cell->type == "$memrd" && cell->parameters["\\MEMID"].str == memory->name)
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if (cell->type == "$memrd" && cell->parameters["\\MEMID"].decode_string() == memory->name)
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{
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rd_ports++;
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del_cell_ids.push_back(cell->name);
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@ -138,7 +138,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
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c->connections["\\D"] = data_reg_in.back();
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RTLIL::Wire *w_out = new RTLIL::Wire;
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w_out->name = stringf("%s[%d]", cell->parameters["\\MEMID"].str.c_str(), i);
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w_out->name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i);
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if (module->wires.count(w_out->name) > 0)
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w_out->name = genid(cell->name, "", i, "$q");
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w_out->width = mem_width;
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