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Replaced RTLIL::Const::str with generic decoder method

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This commit is contained in:
Clifford Wolf 2013-12-04 14:14:05 +01:00
parent a2d053694b
commit 93a70959f3
21 changed files with 125 additions and 84 deletions
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4
passes/cmds/select.cc
View file

@ -48,7 +48,9 @@ static bool match_ids(RTLIL::IdString id, std::string pattern)
static bool match_attr_val(const RTLIL::Const &value, std::string pattern)
{
if (!fnmatch(pattern.c_str(), value.str.c_str(), FNM_NOESCAPE))
if ((value.flags & RTLIL::CONST_FLAG_STRING) == 0)
return false;
if (!fnmatch(pattern.c_str(), value.decode_string().c_str(), FNM_NOESCAPE))
return true;
return false;
}

2
passes/cmds/show.cc
View file

@ -400,7 +400,7 @@ struct ShowWorker
std::string proc_src = RTLIL::unescape_id(proc->name);
if (proc->attributes.count("\\src") > 0)
proc_src = proc->attributes.at("\\src").str;
proc_src = proc->attributes.at("\\src").decode_string();
fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\"];\n", pidx, escape(proc->name, true), proc_src.c_str());
}

4
passes/fsm/fsm_export.cc
View file

@ -60,8 +60,8 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st
attr_it = cell->attributes.find("\\fsm_export");
if (!filename.empty()) {
kiss_name.assign(filename);
} else if (attr_it != cell->attributes.end() && attr_it->second.str != "") {
kiss_name.assign(attr_it->second.str);
} else if (attr_it != cell->attributes.end() && attr_it->second.decode_string() != "") {
kiss_name.assign(attr_it->second.decode_string());
}
else {
kiss_name.assign(module->name);

2
passes/fsm/fsm_extract.cc
View file

@ -376,7 +376,7 @@ struct FsmExtractPass : public Pass {
std::vector<RTLIL::Wire*> wire_list;
for (auto &wire_it : module->wires)
if (wire_it.second->attributes.count("\\fsm_encoding") > 0 && wire_it.second->attributes["\\fsm_encoding"].str != "none")
if (wire_it.second->attributes.count("\\fsm_encoding") > 0 && wire_it.second->attributes["\\fsm_encoding"].decode_string() != "none")
if (design->selected(module, wire_it.second))
wire_list.push_back(wire_it.second);
for (auto wire : wire_list)

2
passes/fsm/fsm_map.cc
View file

@ -168,7 +168,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
// create state register
RTLIL::Wire *state_wire = new RTLIL::Wire;
state_wire->name = fsm_cell->parameters["\\NAME"].str;
state_wire->name = fsm_cell->parameters["\\NAME"].decode_string();
while (module->count_id(state_wire->name) > 0)
state_wire->name += "_";
state_wire->width = fsm_data.state_bits;

2
passes/fsm/fsm_opt.cc
View file

@ -42,7 +42,7 @@ struct FsmOpt
if (!wire || wire->attributes.count("\\unused_bits") == 0)
return false;
char *str = strdup(wire->attributes["\\unused_bits"].str.c_str());
char *str = strdup(wire->attributes["\\unused_bits"].decode_string().c_str());
for (char *tok = strtok(str, " "); tok != NULL; tok = strtok(NULL, " ")) {
if (tok[0] && bit == atoi(tok))
return true;

12
passes/fsm/fsm_recode.cc
View file

@ -28,12 +28,12 @@
static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &fsm_data, const char *prefix, FILE *f)
{
std::string name = cell->parameters["\\NAME"].decode_string();
fprintf(f, "set_fsm_state_vector {");
for (int i = fsm_data.state_bits-1; i >= 0; i--)
fprintf(f, " %s_reg[%d]", cell->parameters["\\NAME"].str[0] == '\\' ?
cell->parameters["\\NAME"].str.substr(1).c_str() : cell->parameters["\\NAME"].str.c_str(), i);
fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n",
prefix, RTLIL::unescape_id(cell->parameters["\\NAME"].str).c_str(),
fprintf(f, " %s_reg[%d]", name[0] == '\\' ? name.substr(1).c_str() : name.c_str(), i);
fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n", prefix, RTLIL::unescape_id(name).c_str(),
prefix, RTLIL::unescape_id(module->name).c_str());
fprintf(f, "set_fsm_encoding {");
@ -43,13 +43,13 @@ static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &
fprintf(f, "%c", fsm_data.state_table[i].bits[j] == RTLIL::State::S1 ? '1' : '0');
}
fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n",
prefix, RTLIL::unescape_id(cell->parameters["\\NAME"].str).c_str(),
prefix, RTLIL::unescape_id(name).c_str(),
prefix, RTLIL::unescape_id(module->name).c_str());
}
static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fsm_file, std::string default_encoding)
{
std::string encoding = cell->attributes.count("\\fsm_encoding") ? cell->attributes.at("\\fsm_encoding").str : "auto";
std::string encoding = cell->attributes.count("\\fsm_encoding") ? cell->attributes.at("\\fsm_encoding").decode_string() : "auto";
log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name.c_str(), module->name.c_str(), encoding.c_str());
if (encoding != "none" && encoding != "one-hot" && encoding != "binary") {

2
passes/fsm/fsmdata.h
View file

@ -133,7 +133,7 @@ struct FsmData
{
log("-------------------------------------\n");
log("\n");
log(" Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters["\\NAME"].str.c_str());
log(" Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters["\\NAME"].decode_string().c_str());
log("\n");
log(" Number of input signals: %3d\n", num_inputs);
log(" Number of output signals: %3d\n", num_outputs);

4
passes/memory/memory_collect.cc
View file

@ -53,7 +53,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
{
RTLIL::Cell *cell = cell_it.second;
if (cell->type == "$memwr" && cell->parameters["\\MEMID"].str == memory->name)
if (cell->type == "$memwr" && cell->parameters["\\MEMID"].decode_string() == memory->name)
{
wr_ports++;
del_cell_ids.push_back(cell->name);
@ -80,7 +80,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
sig_wr_en.append(en);
}
if (cell->type == "$memrd" && cell->parameters["\\MEMID"].str == memory->name)
if (cell->type == "$memrd" && cell->parameters["\\MEMID"].decode_string() == memory->name)
{
rd_ports++;
del_cell_ids.push_back(cell->name);

2
passes/memory/memory_map.cc
View file

@ -138,7 +138,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
c->connections["\\D"] = data_reg_in.back();
RTLIL::Wire *w_out = new RTLIL::Wire;
w_out->name = stringf("%s[%d]", cell->parameters["\\MEMID"].str.c_str(), i);
w_out->name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i);
if (module->wires.count(w_out->name) > 0)
w_out->name = genid(cell->name, "", i, "$q");
w_out->width = mem_width;

4
passes/submod/submod.cc
View file

@ -218,12 +218,12 @@ struct SubmodWorker
for (auto &it : module->cells)
{
RTLIL::Cell *cell = it.second;
if (cell->attributes.count("\\submod") == 0 || cell->attributes["\\submod"].str.size() == 0) {
if (cell->attributes.count("\\submod") == 0 || cell->attributes["\\submod"].bits.size() == 0) {
cell->attributes.erase("\\submod");
continue;
}
std::string submod_str = cell->attributes["\\submod"].str;
std::string submod_str = cell->attributes["\\submod"].decode_string();
cell->attributes.erase("\\submod");
if (submodules.count(submod_str) == 0) {

18
passes/techmap/techmap.cc
View file

@ -313,19 +313,7 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::
data.wire->name = new_name;
tpl->add(data.wire);
std::string cmd_string;
std::vector<char> cmd_string_chars;
std::vector<RTLIL::State> bits = data.value.as_const().bits;
for (int i = 0; i < int(bits.size()); i += 8) {
char ch = 0;
for (int j = 0; j < 8 && i+j < int(bits.size()); j++)
if (bits[i+j] == RTLIL::State::S1)
ch |= 1 << j;
if (ch != 0)
cmd_string_chars.push_back(ch);
}
for (int i = int(cmd_string_chars.size())-1; i >= 0; i--)
cmd_string += cmd_string_chars[i];
std::string cmd_string = data.value.as_const().decode_string();
RTLIL::Selection tpl_mod_sel(false);
tpl_mod_sel.select(tpl);
@ -507,8 +495,8 @@ struct TechmapPass : public Pass {
std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
for (auto &it : map->modules) {
if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").str.empty()) {
char *p = strdup(it.second->attributes.at("\\techmap_celltype").str.c_str());
if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").bits.empty()) {
char *p = strdup(it.second->attributes.at("\\techmap_celltype").decode_string().c_str());
for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
celltypeMap[RTLIL::escape_id(q)].insert(it.first);
free(p);