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autoname: Fix selection arg

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Krystine Sherwin 2025-08-09 10:52:52 +12:00
parent 7073606299
commit 93874d274e
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2 changed files with 7 additions and 3 deletions
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1
passes/cmds/autoname.cc
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@ -127,6 +127,7 @@ struct AutonamePass : public Pass {
// }
break;
}
extra_args(args, argidx, design);
log_header(design, "Executing AUTONAME pass.\n");

9
tests/various/autoname.ys
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@ -171,11 +171,14 @@ module \top
end
end
EOT
# wires all named for being cell outputs
# wires are named for being cell outputs
logger -expect log "Rename wire .d in top to or_Y" 1
logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1
debug autoname t:$or
logger -check-expected
# $name gets shortest name (otherwise bcd_$__unknown_B)
logger -expect log "Rename cell .name in top to a_.__unknown_A" 1
logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1
# another output wire
logger -expect log "Rename wire .e in top to or_Y_.or_B_Y" 1
# $name3 named for lowest fanout wire (otherwise a_$__unknown_A_Y_$and_A)
@ -183,5 +186,5 @@ logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1
# $c gets shortest name, since the cell driving it doesn't have known port
# directions
logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1
debug autoname t:$and
debug autoname
logger -check-expected