From 93874d274e7ad04d284f65ff233fcca36c08ee38 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Sat, 9 Aug 2025 10:52:52 +1200
Subject: [PATCH] autoname: Fix selection arg

---
 passes/cmds/autoname.cc   | 1 +
 tests/various/autoname.ys | 9 ++++++---
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/passes/cmds/autoname.cc b/passes/cmds/autoname.cc
index 75e54f4b1..d2ff568c3 100644
--- a/passes/cmds/autoname.cc
+++ b/passes/cmds/autoname.cc
@@ -127,6 +127,7 @@ struct AutonamePass : public Pass {
 			// }
 			break;
 		}
+		extra_args(args, argidx, design);
 
 		log_header(design, "Executing AUTONAME pass.\n");
 
diff --git a/tests/various/autoname.ys b/tests/various/autoname.ys
index 88d0837d9..29ca81bbe 100644
--- a/tests/various/autoname.ys
+++ b/tests/various/autoname.ys
@@ -171,11 +171,14 @@ module \top
   end
 end
 EOT
-# wires all named for being cell outputs
+# wires are named for being cell outputs
 logger -expect log "Rename wire .d in top to or_Y" 1
+logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1
+debug autoname t:$or
+logger -check-expected
+
 # $name gets shortest name (otherwise bcd_$__unknown_B)
 logger -expect log "Rename cell .name in top to a_.__unknown_A" 1
-logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1
 # another output wire
 logger -expect log "Rename wire .e in top to or_Y_.or_B_Y" 1
 # $name3 named for lowest fanout wire (otherwise a_$__unknown_A_Y_$and_A)
@@ -183,5 +186,5 @@ logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1
 # $c gets shortest name, since the cell driving it doesn't have known port
 # directions
 logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1
-debug autoname t:$and
+debug autoname
 logger -check-expected