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Remove black boxes for now.

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nella 2026-05-25 10:38:51 +02:00
parent b17792c451
commit 932be8c611
3 changed files with 6 additions and 86 deletions
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15
tests/arith_tree/arith_tree_final_adder.ys
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@ -68,18 +68,3 @@ select -assert-min 1 t:$_AND_
select -assert-min 1 t:$_XOR_
design -reset
read_verilog <<EOT
module elarith_macro(
input [15:0] a, b, c, d,
output [15:0] y
);
assign y = a + b + c + d;
endmodule
EOT
hierarchy -auto-top
proc
arith_tree -elarith-macro
select -assert-count 0 t:$fa
select -assert-count 0 t:$add
select -assert-count 1 t:\AddMopCsv
design -reset