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70 lines
1.3 KiB
Text
70 lines
1.3 KiB
Text
read_verilog <<EOT
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module final_auto_wide(
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input [31:0] a, b, c, d,
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output [31:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree -final auto
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design -load postopt
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select -assert-none t:$add
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select -assert-count 2 t:$fa
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select -assert-min 1 t:$_AND_
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select -assert-min 1 t:$_XOR_
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design -reset
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read_verilog <<EOT
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module final_auto_narrow(
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input [7:0] a, b, c, d,
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output [7:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree -final auto
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design -load postopt
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select -assert-count 1 t:$add
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select -assert-count 2 t:$fa
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select -assert-count 0 t:$add a:adder_arch %i
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select -assert-none t:$_AND_ t:$_OR_ %u
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design -reset
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read_verilog <<EOT
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module final_ripple(
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input [31:0] a, b, c, d,
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output [31:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree -final ripple
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design -load postopt
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select -assert-count 1 t:$add
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select -assert-count 0 t:$add a:adder_arch %i
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select -assert-none t:$_AND_ t:$_OR_ %u
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design -reset
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read_verilog <<EOT
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module final_prefix_narrow(
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input [7:0] a, b, c, d,
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output [7:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree -final prefix
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design -load postopt
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select -assert-none t:$add
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select -assert-min 1 t:$_AND_
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select -assert-min 1 t:$_XOR_
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design -reset
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