mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-01 12:07:51 +00:00
Code Activity

Fix files with CRLF line endings

Browse source
This commit is contained in:
Claire Xenia Wolf 2021-06-09 12:16:33 +02:00
parent 72787f52fc
commit 92e705cb51
5 changed files with 422 additions and 422 deletions
Download patch file Download diff file Expand all files Collapse all files

22
tests/arch/common/counter.v
View file

@ -1,11 +1,11 @@
module top ( out, clk, reset );
output [7:0] out;
input clk, reset;
reg [7:0] out;
always @(posedge clk, posedge reset)
if (reset)
out <= 8'b0;
else
out <= out + 1;
endmodule
module top ( out, clk, reset );
output [7:0] out;
input clk, reset;
reg [7:0] out;
always @(posedge clk, posedge reset)
if (reset)
out <= 8'b0;
else
out <= out + 1;
endmodule