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12 lines
224 B
Verilog
12 lines
224 B
Verilog
module top ( out, clk, reset );
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output [7:0] out;
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input clk, reset;
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reg [7:0] out;
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always @(posedge clk, posedge reset)
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if (reset)
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out <= 8'b0;
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else
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out <= out + 1;
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endmodule
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