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Remove tech independent synthesis

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This commit is contained in:
Eddie Hung 2019-08-22 12:30:49 -07:00
parent 388eb3288c
commit 9224b3bc17
9 changed files with 20 additions and 16 deletions
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8
tests/ice40/mux.ys
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@ -1,6 +1,8 @@
read_verilog mux.v
synth_ice40
proc
flatten
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40
design -load postopt
select -assert-count 20 t:SB_LUT4
select -assert-count 1 t:SB_CARRY
cd top
select -assert-count 19 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D