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9 lines
189 B
Plaintext
9 lines
189 B
Plaintext
read_verilog mux.v
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proc
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flatten
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equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40
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design -load postopt
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cd top
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select -assert-count 19 t:SB_LUT4
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select -assert-none t:SB_LUT4 %% t:* %D
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