mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-06-01 06:37:51 +00:00
Code Activity

Fix compiling on GCC11

Browse source
This commit is contained in:
Miodrag Milanovic 2026-05-13 10:11:36 +02:00
parent 6ff6f8fb3c
commit 90e019e319
2 changed files with 6 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

6
passes/cmds/timeest.cc
View file

@ -100,7 +100,7 @@ struct EstimateSta {
log_id(cell), log_id(cell->type)); log_id(cell), log_id(cell->type));
continue; continue;
} }
if (ff.sig_clk != clk) if (!clk || ff.sig_clk.as_bit() != *clk)
continue; continue;
launch.append(ff.sig_q); launch.append(ff.sig_q);
sample.append(ff.sig_d); sample.append(ff.sig_d);
@ -144,12 +144,12 @@ struct EstimateSta {
log_error("Unsupported async memory port '%s'\n", log_id(rd.cell)); log_error("Unsupported async memory port '%s'\n", log_id(rd.cell));
continue; continue;
} }
if (sigmap(rd.clk) != clk) if (!clk || sigmap(rd.clk).as_bit() != *clk)
continue; continue;
add_seq(rd.cell, rd.data, {rd.addr, rd.srst, rd.en}); add_seq(rd.cell, rd.data, {rd.addr, rd.srst, rd.en});
} }
for (auto &wr : mem.wr_ports) { for (auto &wr : mem.wr_ports) {
if (sigmap(wr.clk) != clk) if (!clk || sigmap(wr.clk).as_bit() != *clk)
continue; continue;
add_seq(wr.cell, {}, {wr.en, wr.addr, wr.data}); add_seq(wr.cell, {}, {wr.en, wr.addr, wr.data});
} }

6
passes/sat/formalff.cc
View file

@ -767,7 +767,7 @@ struct FormalFfPass : public Pass {
ff.sig_d = ff.sig_ad; ff.sig_d = ff.sig_ad;
} }
if (!ff.has_clk || sigmap(ff.sig_clk) != gate_clock || ff.pol_clk != pol_clk) { if (!ff.has_clk || sigmap(ff.sig_clk).as_bit() != gate_clock || ff.pol_clk != pol_clk) {
log_debug("FF driver for gate enable %s.%s of gated clk bit %s.%s has incompatible clocking: " log_debug("FF driver for gate enable %s.%s of gated clk bit %s.%s has incompatible clocking: "
"%s %s.%s\n", "%s %s.%s\n",
log_id(module), log_signal(SigSpec(gate_enable)), log_id(module), log_id(module), log_signal(SigSpec(gate_enable)), log_id(module),
@ -798,7 +798,7 @@ struct FormalFfPass : public Pass {
auto &mem = memories.at(clocked_cell->name); auto &mem = memories.at(clocked_cell->name);
bool changed = false; bool changed = false;
for (auto &rd_port : mem.rd_ports) { for (auto &rd_port : mem.rd_ports) {
if (rd_port.clk_enable && rd_port.clk == clk && rd_port.clk_polarity == pol_clk) { if (rd_port.clk_enable && rd_port.clk.as_bit() == clk && rd_port.clk_polarity == pol_clk) {
log_debug("patching rd port\n"); log_debug("patching rd port\n");
changed = true; changed = true;
rd_port.clk = gate_clock; rd_port.clk = gate_clock;
@ -808,7 +808,7 @@ struct FormalFfPass : public Pass {
} }
} }
for (auto &wr_port : mem.wr_ports) { for (auto &wr_port : mem.wr_ports) {
if (wr_port.clk_enable && wr_port.clk == clk && wr_port.clk_polarity == pol_clk) { if (wr_port.clk_enable && wr_port.clk.as_bit() == clk && wr_port.clk_polarity == pol_clk) {
log_debug("patching wr port\n"); log_debug("patching wr port\n");
changed = true; changed = true;
wr_port.clk = gate_clock; wr_port.clk = gate_clock;