From 90e019e319a0b0b81c4b95199937900b20045cce Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 13 May 2026 10:11:36 +0200
Subject: [PATCH] Fix compiling on GCC11

---
 passes/cmds/timeest.cc | 6 +++---
 passes/sat/formalff.cc | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/passes/cmds/timeest.cc b/passes/cmds/timeest.cc
index 1caa1ddaf..4f6105356 100644
--- a/passes/cmds/timeest.cc
+++ b/passes/cmds/timeest.cc
@@ -100,7 +100,7 @@ struct EstimateSta {
 								log_id(cell), log_id(cell->type));
 					continue;
 				}
-				if (ff.sig_clk != clk)
+				if (!clk || ff.sig_clk.as_bit() != *clk)
 					continue;
 				launch.append(ff.sig_q);
 				sample.append(ff.sig_d);
@@ -144,12 +144,12 @@ struct EstimateSta {
 					log_error("Unsupported async memory port '%s'\n", log_id(rd.cell));
 					continue;
 				}
-				if (sigmap(rd.clk) != clk)
+				if (!clk || sigmap(rd.clk).as_bit() != *clk)
 					continue;
 				add_seq(rd.cell, rd.data, {rd.addr, rd.srst, rd.en});
 			}
 			for (auto &wr : mem.wr_ports) {
-				if (sigmap(wr.clk) != clk)
+				if (!clk || sigmap(wr.clk).as_bit() != *clk)
 					continue;
 				add_seq(wr.cell, {}, {wr.en, wr.addr, wr.data});
 			}
diff --git a/passes/sat/formalff.cc b/passes/sat/formalff.cc
index 452e0e59b..5ac93eca7 100644
--- a/passes/sat/formalff.cc
+++ b/passes/sat/formalff.cc
@@ -767,7 +767,7 @@ struct FormalFfPass : public Pass {
 							ff.sig_d = ff.sig_ad;
 						}
 
-						if (!ff.has_clk || sigmap(ff.sig_clk) != gate_clock || ff.pol_clk != pol_clk) {
+						if (!ff.has_clk || sigmap(ff.sig_clk).as_bit() != gate_clock || ff.pol_clk != pol_clk) {
 							log_debug("FF driver for gate enable %s.%s of gated clk bit %s.%s has incompatible clocking: "
 								  "%s %s.%s\n",
 								  log_id(module), log_signal(SigSpec(gate_enable)), log_id(module),
@@ -798,7 +798,7 @@ struct FormalFfPass : public Pass {
 								auto &mem = memories.at(clocked_cell->name);
 								bool changed = false;
 								for (auto &rd_port : mem.rd_ports) {
-									if (rd_port.clk_enable && rd_port.clk == clk && rd_port.clk_polarity == pol_clk) {
+									if (rd_port.clk_enable && rd_port.clk.as_bit() == clk && rd_port.clk_polarity == pol_clk) {
 										log_debug("patching rd port\n");
 										changed = true;
 										rd_port.clk = gate_clock;
@@ -808,7 +808,7 @@ struct FormalFfPass : public Pass {
 									}
 								}
 								for (auto &wr_port : mem.wr_ports) {
-									if (wr_port.clk_enable && wr_port.clk == clk && wr_port.clk_polarity == pol_clk) {
+									if (wr_port.clk_enable && wr_port.clk.as_bit() == clk && wr_port.clk_polarity == pol_clk) {
 										log_debug("patching wr port\n");
 										changed = true;
 										wr_port.clk = gate_clock;