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https://github.com/YosysHQ/yosys
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Fix compiling on GCC11
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parent
6ff6f8fb3c
commit
90e019e319
2 changed files with 6 additions and 6 deletions
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@ -100,7 +100,7 @@ struct EstimateSta {
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log_id(cell), log_id(cell->type));
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continue;
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}
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if (ff.sig_clk != clk)
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if (!clk || ff.sig_clk.as_bit() != *clk)
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continue;
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launch.append(ff.sig_q);
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sample.append(ff.sig_d);
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@ -144,12 +144,12 @@ struct EstimateSta {
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log_error("Unsupported async memory port '%s'\n", log_id(rd.cell));
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continue;
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}
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if (sigmap(rd.clk) != clk)
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if (!clk || sigmap(rd.clk).as_bit() != *clk)
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continue;
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add_seq(rd.cell, rd.data, {rd.addr, rd.srst, rd.en});
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}
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for (auto &wr : mem.wr_ports) {
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if (sigmap(wr.clk) != clk)
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if (!clk || sigmap(wr.clk).as_bit() != *clk)
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continue;
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add_seq(wr.cell, {}, {wr.en, wr.addr, wr.data});
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}
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