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libparse: fix quoting and negedge in filterlib -verilogsim

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This commit is contained in:
Emil J. Tywoniak 2025-11-05 14:13:58 +01:00
parent 504b668ea6
commit 90553267b0
4 changed files with 39 additions and 31 deletions
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6
tests/liberty/dff.lib.verilogsim.ok
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@ -1,12 +1,12 @@
module dff (D, CLK, Q);
reg "IQ", "IQN";
reg IQ, IQN;
input D;
input CLK;
output Q;
assign Q = IQ; // IQ
always @(posedge CLK) begin
// "(D)"
"IQ" <= D;
"IQN" <= ~(D);
IQ <= D;
IQN <= ~(D);
end
endmodule

24
tests/liberty/normal.lib.verilogsim.ok
View file

@ -40,7 +40,7 @@ module imux2 (A, B, S, Y);
assign Y = (~((A&S)|(B&(~S)))); // "( (A * S) + (B * S') )'"
endmodule
module dff (D, CLK, RESET, PRESET, Q, QN);
reg "IQ", "IQN";
reg IQ, IQN;
input D;
input CLK;
input RESET;
@ -51,26 +51,26 @@ module dff (D, CLK, RESET, PRESET, Q, QN);
assign QN = IQN; // "IQN"
always @(posedge CLK, posedge RESET, posedge PRESET) begin
if ((RESET) && (PRESET)) begin
"IQ" <= 0;
"IQN" <= 0;
IQ <= 0;
IQN <= 0;
end
else if (RESET) begin
"IQ" <= 0;
"IQN" <= 1;
IQ <= 0;
IQN <= 1;
end
else if (PRESET) begin
"IQ" <= 1;
"IQN" <= 0;
IQ <= 1;
IQN <= 0;
end
else begin
// "D"
"IQ" <= D;
"IQN" <= ~(D);
IQ <= D;
IQN <= ~(D);
end
end
endmodule
module latch (D, G, Q, QN);
reg "IQ", "IQN";
reg IQ, IQN;
input D;
input G;
output Q;
@ -79,8 +79,8 @@ module latch (D, G, Q, QN);
assign QN = IQN; // "IQN"
always @* begin
if (G) begin
"IQ" <= D;
"IQN" <= ~(D);
IQ <= D;
IQN <= ~(D);
end
end
endmodule

14
tests/liberty/unquoted.lib.verilogsim.ok
View file

@ -1,13 +1,13 @@
module dff1 (D, CLK, Q);
reg "IQ", "IQN";
reg IQ, IQN;
input D;
input CLK;
output Q;
assign Q = IQ; // IQ
always @(posedge CLK) begin
// !D
"IQ" <= (~D);
"IQN" <= ~((~D));
IQ <= (~D);
IQN <= ~((~D));
end
endmodule
module dff2 (D, CLK, Q);
@ -23,7 +23,7 @@ module dff2 (D, CLK, Q);
end
endmodule
module dffe (D, EN, CLK, Q, QN);
reg "IQ", "IQN";
reg IQ, IQN;
input D;
input EN;
input CLK;
@ -31,9 +31,9 @@ module dffe (D, EN, CLK, Q, QN);
assign Q = IQ; // "IQ"
output QN;
assign QN = IQN; // "IQN"
always @(posedge (~CLK)) begin
always @(negedge CLK) begin
// ( D & EN ) | ( IQ & ! EN )
"IQ" <= ((D&EN)|(IQ&(~EN)));
"IQN" <= ~(((D&EN)|(IQ&(~EN))));
IQ <= ((D&EN)|(IQ&(~EN)));
IQN <= ~(((D&EN)|(IQ&(~EN))));
end
endmodule