From 90553267b0a3a98bad21b6892f0e170422fdddad Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 5 Nov 2025 14:13:58 +0100 Subject: [PATCH] libparse: fix quoting and negedge in filterlib -verilogsim --- passes/techmap/libparse.cc | 26 ++++++++++++++++-------- tests/liberty/dff.lib.verilogsim.ok | 6 +++--- tests/liberty/normal.lib.verilogsim.ok | 24 +++++++++++----------- tests/liberty/unquoted.lib.verilogsim.ok | 14 ++++++------- 4 files changed, 39 insertions(+), 31 deletions(-) diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc index da88dfc66..2d3f1792a 100644 --- a/passes/techmap/libparse.cc +++ b/passes/techmap/libparse.cc @@ -25,6 +25,7 @@ #include #include #include +#include #ifdef FILTERLIB #undef log_assert @@ -825,6 +826,12 @@ std::string func2vl(std::string str) return LibertyExpression::parse(helper).vlog_str(); } +std::string vlog_identifier(std::string str) +{ + str.erase(std::remove(str.begin(), str.end(), '\"'), str.end()); + return str; +} + void event2vl(const LibertyAst *ast, std::string &edge, std::string &expr) { edge.clear(); @@ -867,13 +874,13 @@ void gen_verilogsim_cell(const LibertyAst *ast) return; CHECK_NV(ast->args.size(), == 1); - printf("module %s (", ast->args[0].c_str()); + printf("module %s (", vlog_identifier(ast->args[0]).c_str()); bool first = true; for (auto child : ast->children) { if (child->id != "pin") continue; CHECK_NV(child->args.size(), == 1); - printf("%s%s", first ? "" : ", ", child->args[0].c_str()); + printf("%s%s", first ? "" : ", ", vlog_identifier(child->args[0]).c_str()); first = false; } printf(");\n"); @@ -884,7 +891,7 @@ void gen_verilogsim_cell(const LibertyAst *ast) printf(" reg "); first = true; for (auto arg : child->args) { - printf("%s%s", first ? "" : ", ", arg.c_str()); + printf("%s%s", first ? "" : ", ", vlog_identifier(arg).c_str()); first = false; } printf(";\n"); @@ -896,9 +903,10 @@ void gen_verilogsim_cell(const LibertyAst *ast) CHECK_NV(child->args.size(), == 1); const LibertyAst *dir = find_non_null(child, "direction"); const LibertyAst *func = child->find("function"); - printf(" %s %s;\n", dir->value.c_str(), child->args[0].c_str()); + std::string var = vlog_identifier(child->args[0]); + printf(" %s %s;\n", dir->value.c_str(), var.c_str()); if (func != NULL) - printf(" assign %s = %s; // %s\n", child->args[0].c_str(), func2vl(func->value).c_str(), func->value.c_str()); + printf(" assign %s = %s; // %s\n", var.c_str(), func2vl(func->value).c_str(), func->value.c_str()); } for (auto child : ast->children) @@ -906,8 +914,8 @@ void gen_verilogsim_cell(const LibertyAst *ast) if (child->id != "ff" || child->args.size() != 2) continue; - std::string iq_var = child->args[0]; - std::string iqn_var = child->args[1]; + std::string iq_var = vlog_identifier(child->args[0]); + std::string iqn_var = vlog_identifier(child->args[1]); std::string clock_edge, clock_expr; event2vl(child->find("clocked_on"), clock_edge, clock_expr); @@ -970,8 +978,8 @@ void gen_verilogsim_cell(const LibertyAst *ast) if (child->id != "latch" || child->args.size() != 2) continue; - std::string iq_var = child->args[0]; - std::string iqn_var = child->args[1]; + std::string iq_var = vlog_identifier(child->args[0]); + std::string iqn_var = vlog_identifier(child->args[1]); std::string enable_edge, enable_expr; event2vl(child->find("enable"), enable_edge, enable_expr); diff --git a/tests/liberty/dff.lib.verilogsim.ok b/tests/liberty/dff.lib.verilogsim.ok index 4f2a5750c..e560df539 100644 --- a/tests/liberty/dff.lib.verilogsim.ok +++ b/tests/liberty/dff.lib.verilogsim.ok @@ -1,12 +1,12 @@ module dff (D, CLK, Q); - reg "IQ", "IQN"; + reg IQ, IQN; input D; input CLK; output Q; assign Q = IQ; // IQ always @(posedge CLK) begin // "(D)" - "IQ" <= D; - "IQN" <= ~(D); + IQ <= D; + IQN <= ~(D); end endmodule diff --git a/tests/liberty/normal.lib.verilogsim.ok b/tests/liberty/normal.lib.verilogsim.ok index 190ecd285..92efbf8aa 100644 --- a/tests/liberty/normal.lib.verilogsim.ok +++ b/tests/liberty/normal.lib.verilogsim.ok @@ -40,7 +40,7 @@ module imux2 (A, B, S, Y); assign Y = (~((A&S)|(B&(~S)))); // "( (A * S) + (B * S') )'" endmodule module dff (D, CLK, RESET, PRESET, Q, QN); - reg "IQ", "IQN"; + reg IQ, IQN; input D; input CLK; input RESET; @@ -51,26 +51,26 @@ module dff (D, CLK, RESET, PRESET, Q, QN); assign QN = IQN; // "IQN" always @(posedge CLK, posedge RESET, posedge PRESET) begin if ((RESET) && (PRESET)) begin - "IQ" <= 0; - "IQN" <= 0; + IQ <= 0; + IQN <= 0; end else if (RESET) begin - "IQ" <= 0; - "IQN" <= 1; + IQ <= 0; + IQN <= 1; end else if (PRESET) begin - "IQ" <= 1; - "IQN" <= 0; + IQ <= 1; + IQN <= 0; end else begin // "D" - "IQ" <= D; - "IQN" <= ~(D); + IQ <= D; + IQN <= ~(D); end end endmodule module latch (D, G, Q, QN); - reg "IQ", "IQN"; + reg IQ, IQN; input D; input G; output Q; @@ -79,8 +79,8 @@ module latch (D, G, Q, QN); assign QN = IQN; // "IQN" always @* begin if (G) begin - "IQ" <= D; - "IQN" <= ~(D); + IQ <= D; + IQN <= ~(D); end end endmodule diff --git a/tests/liberty/unquoted.lib.verilogsim.ok b/tests/liberty/unquoted.lib.verilogsim.ok index 8706d1773..2a2f1d173 100644 --- a/tests/liberty/unquoted.lib.verilogsim.ok +++ b/tests/liberty/unquoted.lib.verilogsim.ok @@ -1,13 +1,13 @@ module dff1 (D, CLK, Q); - reg "IQ", "IQN"; + reg IQ, IQN; input D; input CLK; output Q; assign Q = IQ; // IQ always @(posedge CLK) begin // !D - "IQ" <= (~D); - "IQN" <= ~((~D)); + IQ <= (~D); + IQN <= ~((~D)); end endmodule module dff2 (D, CLK, Q); @@ -23,7 +23,7 @@ module dff2 (D, CLK, Q); end endmodule module dffe (D, EN, CLK, Q, QN); - reg "IQ", "IQN"; + reg IQ, IQN; input D; input EN; input CLK; @@ -31,9 +31,9 @@ module dffe (D, EN, CLK, Q, QN); assign Q = IQ; // "IQ" output QN; assign QN = IQN; // "IQN" - always @(posedge (~CLK)) begin + always @(negedge CLK) begin // ( D & EN ) | ( IQ & ! EN ) - "IQ" <= ((D&EN)|(IQ&(~EN))); - "IQN" <= ~(((D&EN)|(IQ&(~EN)))); + IQ <= ((D&EN)|(IQ&(~EN))); + IQN <= ~(((D&EN)|(IQ&(~EN)))); end endmodule