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Merge pull request #2314 from YosysHQ/verifix_errorfix

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Verific - prevent exit yosys due to stored error
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Miodrag Milanović 2020-07-29 15:41:26 +02:00 committed by GitHub
parent dc18bf1969 cc02d58194
commit 2f50c5af48
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1 changed files with 3 additions and 1 deletions
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frontends/verific/verific.cc
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@ -2354,8 +2354,10 @@ struct VerificPass : public Pass {
while (argidx < GetSize(args))
file_names.Insert(args[argidx++].c_str());
if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, work.c_str(), veri_file::MFCU))
if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, work.c_str(), veri_file::MFCU)) {
verific_error_msg.clear();
log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
}
verific_import_pending = true;
goto check_error;