mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-24 05:08:56 +00:00
Merge remote-tracking branch 'origin/master' into xaig_dff
This commit is contained in:
Eddie Hung
commit
8f5710c464
174 changed files with 26477 additions and 2398 deletions
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@ -25,7 +25,10 @@ techlibs/xilinx/brams_init_8.vh: techlibs/xilinx/brams_init.mk
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_xtra.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_cells_xtra.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6v_cells_xtra.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_cells_xtra.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_cells_xtra.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_bb.v))
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@ -35,7 +38,8 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_ff_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_ff_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
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@ -128,7 +128,7 @@ module RAM32X1D (
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parameter INIT = 32'h0;
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parameter IS_WCLK_INVERTED = 1'b0;
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wire \$DPO , \$SPO ;
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\$__ABC_RAM32X1D #(
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RAM32X1D #(
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.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
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) _TECHMAP_REPLACE_ (
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.DPO(\$DPO ), .SPO(\$SPO ),
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@ -136,8 +136,8 @@ module RAM32X1D (
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.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
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.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
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);
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\$__ABC_LUTMUX6 dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO));
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\$__ABC_LUTMUX6 spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO));
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\$__ABC_LUT6 dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO));
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\$__ABC_LUT6 spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO));
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endmodule
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module RAM64X1D (
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@ -151,7 +151,7 @@ module RAM64X1D (
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parameter INIT = 64'h0;
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parameter IS_WCLK_INVERTED = 1'b0;
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wire \$DPO , \$SPO ;
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\$__ABC_RAM64X1D #(
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RAM64X1D #(
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.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
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) _TECHMAP_REPLACE_ (
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.DPO(\$DPO ), .SPO(\$SPO ),
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@ -159,8 +159,8 @@ module RAM64X1D (
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.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
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.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
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);
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\$__ABC_LUTMUX6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO));
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\$__ABC_LUTMUX6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO));
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\$__ABC_LUT6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO));
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\$__ABC_LUT6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO));
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endmodule
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module RAM128X1D (
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@ -173,7 +173,7 @@ module RAM128X1D (
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parameter INIT = 128'h0;
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parameter IS_WCLK_INVERTED = 1'b0;
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wire \$DPO , \$SPO ;
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\$__ABC_RAM128X1D #(
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RAM128X1D #(
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.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
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) _TECHMAP_REPLACE_ (
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.DPO(\$DPO ), .SPO(\$SPO ),
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@ -181,8 +181,8 @@ module RAM128X1D (
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.A(A),
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.DPRA(DPRA)
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);
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\$__ABC_LUTMUX7 dpo (.A(\$DPO ), .S(A), .Y(DPO));
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\$__ABC_LUTMUX7 spo (.A(\$SPO ), .S(A), .Y(SPO));
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\$__ABC_LUT7 dpo (.A(\$DPO ), .S(A), .Y(DPO));
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\$__ABC_LUT7 spo (.A(\$SPO ), .S(A), .Y(SPO));
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endmodule
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module SRL16E (
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@ -192,14 +192,13 @@ module SRL16E (
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parameter [15:0] INIT = 16'h0000;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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wire \$Q ;
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\$__ABC_SRL16E #(
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SRL16E #(
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.INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
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) _TECHMAP_REPLACE_ (
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.Q(\$Q ),
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.A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
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);
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// TODO: Check if SRL uses fast inputs or slow inputs
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\$__ABC_LUTMUX6 q (.A(\$Q ), .S({A0, A1, A2, A3, 1'b0, 1'b0}), .Y(Q));
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\$__ABC_LUT6 q (.A(\$Q ), .S({1'b1, A0, A1, A2, A3, 1'b1}), .Y(Q));
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endmodule
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module SRLC32E (
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@ -211,12 +210,11 @@ module SRLC32E (
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parameter [31:0] INIT = 32'h00000000;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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wire \$Q ;
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\$__ABC_SRLC32E #(
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SRLC32E #(
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.INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
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) _TECHMAP_REPLACE_ (
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.Q(\$Q ), .Q31(Q31),
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.A(A), .CE(CE), .CLK(CLK), .D(D)
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);
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// TODO: Check if SRL uses fast inputs or slow inputs
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\$__ABC_LUTMUX6 q (.A(\$Q ), .S({A, 1'b0}), .Y(Q));
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\$__ABC_LUT6 q (.A(\$Q ), .S({1'b1, A}), .Y(Q));
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endmodule
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@ -115,65 +115,8 @@ module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
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endmodule
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(* abc_box_id=2000 *)
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module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
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module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
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endmodule
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(* abc_box_id=2001 *)
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module \$__ABC_LUTMUX7 (input A, input [6:0] S, output Y);
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endmodule
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module \$__ABC_RAM32X1D (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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(* abc_arrival=1153 *) output DPO, SPO,
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input D,
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input WCLK,
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input WE,
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input A0, A1, A2, A3, A4,
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input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
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);
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endmodule
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module \$__ABC_RAM64X1D (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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(* abc_arrival=1153 *) output DPO, SPO,
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input D,
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input WCLK,
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input WE,
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input A0, A1, A2, A3, A4, A5,
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input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
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);
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parameter INIT = 64'h0;
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parameter IS_WCLK_INVERTED = 1'b0;
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endmodule
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module \$__ABC_RAM128X1D (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
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(* abc_arrival=1153 *) output DPO, SPO,
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input D,
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input WCLK,
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input WE,
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input [6:0] A, DPRA
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);
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parameter INIT = 128'h0;
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parameter IS_WCLK_INVERTED = 1'b0;
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endmodule
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module SRL16E (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
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(* abc_arrival=1472 *) output Q,
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input A0, A1, A2, A3, CE, CLK, D
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);
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parameter [15:0] INIT = 16'h0000;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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endmodule
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module SRLC32E (
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// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
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(* abc_arrival=1472 *) output Q,
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(* abc_arrival=1114 *) output Q31,
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input [4:0] A,
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input CE, CLK, D
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);
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parameter [31:0] INIT = 32'h00000000;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
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endmodule
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|
|
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@ -139,101 +139,9 @@ module \$__ABC_FDPE_1 (output Q,
|
|||
);
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endmodule
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module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
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module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
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assign Y = A;
|
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endmodule
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module \$__ABC_LUTMUX7 (input A, input [6:0] S, output Y);
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module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
|
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assign Y = A;
|
||||
endmodule
|
||||
|
||||
module \$__ABC_RAM32X1D (
|
||||
output DPO, SPO,
|
||||
input D,
|
||||
input WCLK,
|
||||
input WE,
|
||||
input A0, A1, A2, A3, A4,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
|
||||
);
|
||||
parameter INIT = 32'h0;
|
||||
parameter IS_WCLK_INVERTED = 1'b0;
|
||||
RAM32X1D #(
|
||||
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DPO(DPO), .SPO(SPO),
|
||||
.D(D), .WCLK(WCLK), .WE(WE),
|
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.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
|
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.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
|
||||
);
|
||||
endmodule
|
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|
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module \$__ABC_RAM64X1D (
|
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output DPO, SPO,
|
||||
input D,
|
||||
input WCLK,
|
||||
input WE,
|
||||
input A0, A1, A2, A3, A4, A5,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
|
||||
);
|
||||
parameter INIT = 64'h0;
|
||||
parameter IS_WCLK_INVERTED = 1'b0;
|
||||
RAM64X1D #(
|
||||
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DPO(DPO), .SPO(SPO),
|
||||
.D(D), .WCLK(WCLK), .WE(WE),
|
||||
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
|
||||
.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module \$__ABC_RAM128X1D (
|
||||
output DPO, SPO,
|
||||
input D,
|
||||
input WCLK,
|
||||
input WE,
|
||||
input A,
|
||||
input DPRA,
|
||||
);
|
||||
parameter INIT = 128'h0;
|
||||
parameter IS_WCLK_INVERTED = 1'b0;
|
||||
RAM128X1D #(
|
||||
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DPO(DPO), .SPO(SPO),
|
||||
.D(D), .WCLK(WCLK), .WE(WE),
|
||||
.A(A),
|
||||
.DPRA(DPRA)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module \$__ABC_SRL16E (
|
||||
output Q,
|
||||
input A0, A1, A2, A3, CE, CLK, D
|
||||
);
|
||||
parameter [15:0] INIT = 16'h0000;
|
||||
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
||||
|
||||
SRL16E #(
|
||||
.INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.Q(Q),
|
||||
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module \$__ABC_SRLC32E (
|
||||
output Q,
|
||||
output Q31,
|
||||
input [4:0] A,
|
||||
input CE, CLK, D
|
||||
);
|
||||
parameter [31:0] INIT = 32'h00000000;
|
||||
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
||||
|
||||
SRLC32E #(
|
||||
.INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.Q(Q), .Q31(Q31),
|
||||
.A(A), .CE(CE), .CLK(CLK), .D(D)
|
||||
);
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -15,7 +15,10 @@ F7MUX 1 1 3 1
|
|||
MUXF8 2 1 3 1
|
||||
104 94 273
|
||||
|
||||
# Box containing MUXF7.[AB] + MUXF8
|
||||
# Box containing MUXF7.[AB] + MUXF8,
|
||||
# Necessary to make these an atomic unit so that
|
||||
# ABC cannot optimise just one of the MUXF7 away
|
||||
# and expect to save on its delay
|
||||
# Inputs: I0 I1 I2 I3 S0 S1
|
||||
# Outputs: O
|
||||
$__MUXF78 3 1 6 1
|
||||
|
|
@ -81,14 +84,19 @@ FDPE_1 1006 1 5 1
|
|||
|
||||
# SLICEM/A6LUT
|
||||
# Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
|
||||
# Necessary since RAMD* and SRL* have both combinatorial (i.e.
|
||||
# same-cycle read operation) and sequential (write operation
|
||||
# is only committed on the next clock edge).
|
||||
# To model the combinatorial path, such cells have to be split
|
||||
# into comb and seq parts, with this box modelling only the former.
|
||||
# Inputs: A S0 S1 S2 S3 S4 S5
|
||||
# Outputs: Y
|
||||
$__ABC_LUTRAM6 2000 0 7 1
|
||||
$__ABC_LUT6 2000 0 7 1
|
||||
0 642 631 472 407 238 127
|
||||
|
||||
# SLICEM/A6LUT + F7BMUX
|
||||
# Box to emulate comb/seq behaviour of RAMD128
|
||||
# Inputs: A S0 S1 S2 S3 S4 S5 S6
|
||||
# Outputs: DPO SPO
|
||||
$__ABC_LUTRAM7 2001 0 8 1
|
||||
$__ABC_LUT7 2001 0 8 1
|
||||
0 1047 1036 877 812 643 532 478
|
||||
|
|
|
|||
|
|
@ -29,29 +29,49 @@ module GND(output G);
|
|||
assign G = 0;
|
||||
endmodule
|
||||
|
||||
module IBUF(output O, input I);
|
||||
module IBUF(
|
||||
output O,
|
||||
(* iopad_external_pin *)
|
||||
input I);
|
||||
parameter IOSTANDARD = "default";
|
||||
parameter IBUF_LOW_PWR = 0;
|
||||
assign O = I;
|
||||
endmodule
|
||||
|
||||
module OBUF(output O, input I);
|
||||
module OBUF(
|
||||
(* iopad_external_pin *)
|
||||
output O,
|
||||
input I);
|
||||
parameter IOSTANDARD = "default";
|
||||
parameter DRIVE = 12;
|
||||
parameter SLEW = "SLOW";
|
||||
assign O = I;
|
||||
endmodule
|
||||
|
||||
module BUFG(output O, input I);
|
||||
module BUFG(
|
||||
(* clkbuf_driver *)
|
||||
output O,
|
||||
input I);
|
||||
|
||||
assign O = I;
|
||||
endmodule
|
||||
|
||||
module BUFGCTRL(
|
||||
(* clkbuf_driver *)
|
||||
output O,
|
||||
input I0, input I1,
|
||||
input S0, input S1,
|
||||
input CE0, input CE1,
|
||||
input IGNORE0, input IGNORE1);
|
||||
(* invertible_pin = "IS_S0_INVERTED" *)
|
||||
input S0,
|
||||
(* invertible_pin = "IS_S1_INVERTED" *)
|
||||
input S1,
|
||||
(* invertible_pin = "IS_CE0_INVERTED" *)
|
||||
input CE0,
|
||||
(* invertible_pin = "IS_CE1_INVERTED" *)
|
||||
input CE1,
|
||||
(* invertible_pin = "IS_IGNORE0_INVERTED" *)
|
||||
input IGNORE0,
|
||||
(* invertible_pin = "IS_IGNORE1_INVERTED" *)
|
||||
input IGNORE1);
|
||||
|
||||
parameter [0:0] INIT_OUT = 1'b0;
|
||||
parameter PRESELECT_I0 = "FALSE";
|
||||
|
|
@ -72,7 +92,12 @@ assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
|
|||
|
||||
endmodule
|
||||
|
||||
module BUFHCE(output O, input I, input CE);
|
||||
module BUFHCE(
|
||||
(* clkbuf_driver *)
|
||||
output O,
|
||||
input I,
|
||||
(* invertible_pin = "IS_CE_INVERTED" *)
|
||||
input CE);
|
||||
|
||||
parameter [0:0] INIT_OUT = 1'b0;
|
||||
parameter CE_TYPE = "SYNC";
|
||||
|
|
@ -175,9 +200,11 @@ endmodule
|
|||
|
||||
(* abc_box_id = 4, lib_whitebox *)
|
||||
module CARRY4(
|
||||
(* abc_carry *) output [3:0] CO,
|
||||
(* abc_carry *)
|
||||
output [3:0] CO,
|
||||
output [3:0] O,
|
||||
(* abc_carry *) input CI,
|
||||
(* abc_carry *)
|
||||
input CI,
|
||||
input CYINIT,
|
||||
input [3:0] DI, S
|
||||
);
|
||||
|
|
@ -211,7 +238,20 @@ endmodule
|
|||
|
||||
`endif
|
||||
|
||||
module FDRE (output reg Q, input C, CE, D, R);
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
|
||||
|
||||
module FDRE (
|
||||
(* abc_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
input C,
|
||||
input CE,
|
||||
(* invertible_pin = "IS_D_INVERTED" *)
|
||||
input D,
|
||||
(* invertible_pin = "IS_R_INVERTED" *)
|
||||
input R
|
||||
);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
parameter [0:0] IS_C_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_D_INVERTED = 1'b0;
|
||||
|
|
@ -223,7 +263,18 @@ module FDRE (output reg Q, input C, CE, D, R);
|
|||
endcase endgenerate
|
||||
endmodule
|
||||
|
||||
module FDSE (output reg Q, input C, CE, D, S);
|
||||
module FDSE (
|
||||
(* abc_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
input C,
|
||||
input CE,
|
||||
(* invertible_pin = "IS_D_INVERTED" *)
|
||||
input D,
|
||||
(* invertible_pin = "IS_S_INVERTED" *)
|
||||
input S
|
||||
);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
parameter [0:0] IS_C_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_D_INVERTED = 1'b0;
|
||||
|
|
@ -235,7 +286,18 @@ module FDSE (output reg Q, input C, CE, D, S);
|
|||
endcase endgenerate
|
||||
endmodule
|
||||
|
||||
module FDCE (output reg Q, input C, CE, D, CLR);
|
||||
module FDCE (
|
||||
(* abc_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
input C,
|
||||
input CE,
|
||||
(* invertible_pin = "IS_D_INVERTED" *)
|
||||
input D,
|
||||
(* invertible_pin = "IS_CLR_INVERTED" *)
|
||||
input CLR
|
||||
);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
parameter [0:0] IS_C_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_D_INVERTED = 1'b0;
|
||||
|
|
@ -249,7 +311,18 @@ module FDCE (output reg Q, input C, CE, D, CLR);
|
|||
endcase endgenerate
|
||||
endmodule
|
||||
|
||||
module FDPE (output reg Q, input C, CE, D, PRE);
|
||||
module FDPE (
|
||||
(* abc_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_C_INVERTED" *)
|
||||
input C,
|
||||
input CE,
|
||||
(* invertible_pin = "IS_D_INVERTED" *)
|
||||
input D,
|
||||
(* invertible_pin = "IS_PRE_INVERTED" *)
|
||||
input PRE
|
||||
);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
parameter [0:0] IS_C_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_D_INVERTED = 1'b0;
|
||||
|
|
@ -263,33 +336,61 @@ module FDPE (output reg Q, input C, CE, D, PRE);
|
|||
endcase endgenerate
|
||||
endmodule
|
||||
|
||||
module FDRE_1 (output reg Q, input C, CE, D, R);
|
||||
module FDRE_1 (
|
||||
(* abc_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
input C,
|
||||
input CE, D, R
|
||||
);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
initial Q <= INIT;
|
||||
always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
|
||||
endmodule
|
||||
|
||||
module FDSE_1 (output reg Q, input C, CE, D, S);
|
||||
module FDSE_1 (
|
||||
(* abc_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
input C,
|
||||
input CE, D, S
|
||||
);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
initial Q <= INIT;
|
||||
always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
|
||||
endmodule
|
||||
|
||||
module FDCE_1 (output reg Q, input C, CE, D, CLR);
|
||||
module FDCE_1 (
|
||||
(* abc_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
input C,
|
||||
input CE, D, CLR
|
||||
);
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
initial Q <= INIT;
|
||||
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
|
||||
endmodule
|
||||
|
||||
module FDPE_1 (output reg Q, input C, CE, D, PRE);
|
||||
module FDPE_1 (
|
||||
(* abc_arrival=303 *)
|
||||
output reg Q,
|
||||
(* clkbuf_sink *)
|
||||
input C,
|
||||
input CE, D, PRE
|
||||
);
|
||||
parameter [0:0] INIT = 1'b1;
|
||||
initial Q <= INIT;
|
||||
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
|
||||
endmodule
|
||||
|
||||
module RAM32X1D (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
|
||||
(* abc_arrival=1153 *)
|
||||
output DPO, SPO,
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
input WE,
|
||||
input A0, A1, A2, A3, A4,
|
||||
|
|
@ -307,8 +408,12 @@ module RAM32X1D (
|
|||
endmodule
|
||||
|
||||
module RAM64X1D (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
|
||||
(* abc_arrival=1153 *)
|
||||
output DPO, SPO,
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
input WE,
|
||||
input A0, A1, A2, A3, A4, A5,
|
||||
|
|
@ -326,8 +431,12 @@ module RAM64X1D (
|
|||
endmodule
|
||||
|
||||
module RAM128X1D (
|
||||
output DPO, SPO,
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
|
||||
(* abc_arrival=1153 *)
|
||||
output DPO, SPO,
|
||||
input D,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_WCLK_INVERTED" *)
|
||||
input WCLK,
|
||||
input WE,
|
||||
input [6:0] A, DPRA
|
||||
|
|
@ -342,8 +451,14 @@ module RAM128X1D (
|
|||
endmodule
|
||||
|
||||
module SRL16E (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
|
||||
(* abc_arrival=1472 *)
|
||||
output Q,
|
||||
input A0, A1, A2, A3, CE, CLK, D
|
||||
input A0, A1, A2, A3, CE,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_CLK_INVERTED" *)
|
||||
input CLK,
|
||||
input D
|
||||
);
|
||||
parameter [15:0] INIT = 16'h0000;
|
||||
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
||||
|
|
@ -355,15 +470,46 @@ module SRL16E (
|
|||
always @(negedge CLK) if (CE) r <= { r[14:0], D };
|
||||
end
|
||||
else
|
||||
always @(posedge CLK) if (CE) r <= { r[14:0], D };
|
||||
always @(posedge CLK) if (CE) r <= { r[14:0], D };
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
module SRLC16E (
|
||||
output Q,
|
||||
output Q15,
|
||||
input A0, A1, A2, A3, CE,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_CLK_INVERTED" *)
|
||||
input CLK,
|
||||
input D
|
||||
);
|
||||
parameter [15:0] INIT = 16'h0000;
|
||||
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
||||
|
||||
reg [15:0] r = INIT;
|
||||
assign Q15 = r[15];
|
||||
assign Q = r[{A3,A2,A1,A0}];
|
||||
generate
|
||||
if (IS_CLK_INVERTED) begin
|
||||
always @(negedge CLK) if (CE) r <= { r[14:0], D };
|
||||
end
|
||||
else
|
||||
always @(posedge CLK) if (CE) r <= { r[14:0], D };
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
module SRLC32E (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
|
||||
(* abc_arrival=1472 *)
|
||||
output Q,
|
||||
(* abc_arrival=1114 *)
|
||||
output Q31,
|
||||
input [4:0] A,
|
||||
input CE, CLK, D
|
||||
input CE,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_CLK_INVERTED" *)
|
||||
input CLK,
|
||||
input D
|
||||
);
|
||||
parameter [31:0] INIT = 32'h00000000;
|
||||
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
||||
|
|
|
|||
708
techlibs/xilinx/cells_xtra.py
Normal file
708
techlibs/xilinx/cells_xtra.py
Normal file
|
|
@ -0,0 +1,708 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
from argparse import ArgumentParser
|
||||
from io import StringIO
|
||||
from enum import Enum, auto
|
||||
import os.path
|
||||
import sys
|
||||
import re
|
||||
|
||||
|
||||
class Cell:
|
||||
def __init__(self, name, keep=False, port_attrs={}):
|
||||
self.name = name
|
||||
self.keep = keep
|
||||
self.port_attrs = port_attrs
|
||||
|
||||
|
||||
XC6S_CELLS = [
|
||||
# Design elements types listed in Xilinx UG615.
|
||||
|
||||
# Advanced.
|
||||
Cell('MCB'),
|
||||
Cell('PCIE_A1'),
|
||||
|
||||
# Arithmetic functions.
|
||||
Cell('DSP48A1', port_attrs={'CLK': ['clkbuf_sink']}),
|
||||
|
||||
# Clock components.
|
||||
# Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFH', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFIO2', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}),
|
||||
Cell('BUFIO2_2CLK', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}),
|
||||
Cell('BUFIO2FB', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFPLL_MCB', port_attrs={'IOCLK0': ['clkbuf_driver'], 'IOCLK1': ['clkbuf_driver']}),
|
||||
Cell('DCM_CLKGEN'),
|
||||
Cell('DCM_SP'),
|
||||
Cell('PLL_BASE'),
|
||||
|
||||
# Config/BSCAN components.
|
||||
Cell('BSCAN_SPARTAN6', keep=True),
|
||||
Cell('DNA_PORT'),
|
||||
Cell('ICAP_SPARTAN6', keep=True),
|
||||
Cell('POST_CRC_INTERNAL'),
|
||||
Cell('STARTUP_SPARTAN6', keep=True),
|
||||
Cell('SUSPEND_SYNC', keep=True),
|
||||
|
||||
# I/O components.
|
||||
Cell('GTPA1_DUAL'),
|
||||
# Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}),
|
||||
Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}),
|
||||
Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
|
||||
Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}),
|
||||
Cell('IODELAY2', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}),
|
||||
Cell('IODRP2', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}),
|
||||
Cell('IODRP2_MCB', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}),
|
||||
Cell('ISERDES2', port_attrs={
|
||||
'CLK0': ['clkbuf_sink'],
|
||||
'CLK1': ['clkbuf_sink'],
|
||||
'CLKDIV': ['clkbuf_sink'],
|
||||
}),
|
||||
Cell('KEEPER'),
|
||||
# Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}),
|
||||
Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
||||
Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
|
||||
Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
||||
Cell('OSERDES2', port_attrs={
|
||||
'CLK0': ['clkbuf_sink'],
|
||||
'CLK1': ['clkbuf_sink'],
|
||||
'CLKDIV': ['clkbuf_sink'],
|
||||
}),
|
||||
Cell('PULLDOWN'),
|
||||
Cell('PULLUP'),
|
||||
|
||||
# RAM/ROM.
|
||||
#Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
# NOTE: not in the official library guide!
|
||||
Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
#Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
#Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
# NOTE: not in the official library guide!
|
||||
Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
# Cell('RAMB8BWER', port_attrs={'CLKAWRCLK': ['clkbuf_sink'], 'CLKBRDCLK': ['clkbuf_sink']}),
|
||||
# Cell('RAMB16BWER', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
|
||||
Cell('ROM128X1'),
|
||||
Cell('ROM256X1'),
|
||||
Cell('ROM32X1'),
|
||||
Cell('ROM64X1'),
|
||||
|
||||
# Registers/latches.
|
||||
# Cell('FDCE'),
|
||||
# Cell('FDPE'),
|
||||
# Cell('FDRE'),
|
||||
# Cell('FDSE'),
|
||||
Cell('IDDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}),
|
||||
Cell('LDCE'),
|
||||
Cell('LDPE'),
|
||||
Cell('ODDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}),
|
||||
|
||||
# Slice/CLB primitives.
|
||||
# Cell('CARRY4'),
|
||||
Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
|
||||
# Cell('LUT1'),
|
||||
# Cell('LUT2'),
|
||||
# Cell('LUT3'),
|
||||
# Cell('LUT4'),
|
||||
# Cell('LUT5'),
|
||||
# Cell('LUT6'),
|
||||
# Cell('LUT6_2'),
|
||||
# Cell('MUXF7'),
|
||||
# Cell('MUXF8'),
|
||||
# Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
|
||||
# Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
|
||||
]
|
||||
|
||||
|
||||
XC6V_CELLS = [
|
||||
# Design elements types listed in Xilinx UG623.
|
||||
|
||||
# Advanced.
|
||||
Cell('PCIE_2_0'),
|
||||
Cell('SYSMON'),
|
||||
|
||||
# Arithmetic functions.
|
||||
Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
|
||||
|
||||
# Clock components.
|
||||
# Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}),
|
||||
#Cell('BUFGCTRL', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFGMUX_CTRL', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFH', port_attrs={'O': ['clkbuf_driver']}),
|
||||
#Cell('BUFHCE', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFIO', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFIODQS', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFR', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('IBUFDS_GTXE1', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('MMCM_ADV'),
|
||||
Cell('MMCM_BASE'),
|
||||
|
||||
# Config/BSCAN components.
|
||||
Cell('BSCAN_VIRTEX6', keep=True),
|
||||
Cell('CAPTURE_VIRTEX6', keep=True),
|
||||
Cell('DNA_PORT'),
|
||||
Cell('EFUSE_USR'),
|
||||
Cell('FRAME_ECC_VIRTEX6'),
|
||||
Cell('ICAP_VIRTEX6', keep=True),
|
||||
Cell('STARTUP_VIRTEX6', keep=True),
|
||||
Cell('USR_ACCESS_VIRTEX6'),
|
||||
|
||||
# I/O components.
|
||||
Cell('DCIRESET', keep=True),
|
||||
Cell('GTHE1_QUAD'),
|
||||
Cell('GTXE1'),
|
||||
# Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}),
|
||||
Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFDS_GTHE1', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}),
|
||||
Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}),
|
||||
Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
|
||||
Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}),
|
||||
Cell('IODELAYE1', port_attrs={'C': ['clkbuf_sink']}),
|
||||
Cell('ISERDESE1', port_attrs={
|
||||
'CLK': ['clkbuf_sink'],
|
||||
'CLKB': ['clkbuf_sink'],
|
||||
'OCLK': ['clkbuf_sink'],
|
||||
'CLKDIV': ['clkbuf_sink'],
|
||||
}),
|
||||
Cell('KEEPER'),
|
||||
# Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}),
|
||||
Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
||||
Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
|
||||
Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
||||
Cell('OSERDESE1', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
|
||||
Cell('PULLDOWN'),
|
||||
Cell('PULLUP'),
|
||||
Cell('TEMAC_SINGLE'),
|
||||
|
||||
# RAM/ROM.
|
||||
Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
||||
Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
||||
#Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
#Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
#Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
# NOTE: not in the official library guide!
|
||||
Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
# Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
|
||||
# Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
|
||||
Cell('ROM128X1'),
|
||||
Cell('ROM256X1'),
|
||||
Cell('ROM32X1'),
|
||||
Cell('ROM64X1'),
|
||||
|
||||
# Registers/latches.
|
||||
# Cell('FDCE'),
|
||||
# Cell('FDPE'),
|
||||
# Cell('FDRE'),
|
||||
# Cell('FDSE'),
|
||||
Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}),
|
||||
Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
|
||||
Cell('LDCE'),
|
||||
Cell('LDPE'),
|
||||
Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}),
|
||||
|
||||
# Slice/CLB primitives.
|
||||
# Cell('CARRY4'),
|
||||
Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
|
||||
# Cell('LUT1'),
|
||||
# Cell('LUT2'),
|
||||
# Cell('LUT3'),
|
||||
# Cell('LUT4'),
|
||||
# Cell('LUT5'),
|
||||
# Cell('LUT6'),
|
||||
# Cell('LUT6_2'),
|
||||
# Cell('MUXF7'),
|
||||
# Cell('MUXF8'),
|
||||
# Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
|
||||
# Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
|
||||
]
|
||||
|
||||
|
||||
XC7_CELLS = [
|
||||
# Design elements types listed in Xilinx UG953.
|
||||
|
||||
# Advanced.
|
||||
Cell('GTHE2_CHANNEL'),
|
||||
Cell('GTHE2_COMMON'),
|
||||
Cell('GTPE2_CHANNEL'),
|
||||
Cell('GTPE2_COMMON'),
|
||||
Cell('GTXE2_CHANNEL'),
|
||||
Cell('GTXE2_COMMON'),
|
||||
Cell('PCIE_2_1'),
|
||||
Cell('PCIE_3_0'),
|
||||
Cell('XADC'),
|
||||
|
||||
# Arithmetic functions.
|
||||
Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
|
||||
|
||||
# Clock components.
|
||||
# Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}),
|
||||
#Cell('BUFGCTRL', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFGMUX_CTRL', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFH', port_attrs={'O': ['clkbuf_driver']}),
|
||||
#Cell('BUFHCE', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFIO', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFMR', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFMRCE', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFR', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('MMCME2_ADV'),
|
||||
Cell('MMCME2_BASE'),
|
||||
Cell('PLLE2_ADV'),
|
||||
Cell('PLLE2_BASE'),
|
||||
|
||||
# Config/BSCAN components.
|
||||
Cell('BSCANE2', keep=True),
|
||||
Cell('CAPTUREE2', keep=True),
|
||||
Cell('DNA_PORT'),
|
||||
Cell('EFUSE_USR'),
|
||||
Cell('FRAME_ECCE2'),
|
||||
Cell('ICAPE2', keep=True),
|
||||
Cell('STARTUPE2', keep=True),
|
||||
Cell('USR_ACCESSE2'),
|
||||
|
||||
# I/O components.
|
||||
Cell('DCIRESET', keep=True),
|
||||
# Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}),
|
||||
Cell('IBUF_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin']}),
|
||||
Cell('IBUF_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin']}),
|
||||
Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFDS_DIFF_OUT_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFDS_GTE2', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFDS_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFDS_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}),
|
||||
Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}),
|
||||
Cell('IDELAYE2', port_attrs={'C': ['clkbuf_sink']}),
|
||||
Cell('IN_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
||||
Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
|
||||
Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}),
|
||||
Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}),
|
||||
Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}),
|
||||
Cell('IOBUFDS_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
|
||||
Cell('IOBUFDS_DIFF_OUT', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
|
||||
Cell('IOBUFDS_DIFF_OUT_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
|
||||
Cell('IOBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
|
||||
Cell('IOBUFDS_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
|
||||
Cell('ISERDESE2', port_attrs={
|
||||
'CLK': ['clkbuf_sink'],
|
||||
'CLKB': ['clkbuf_sink'],
|
||||
'OCLK': ['clkbuf_sink'],
|
||||
'OCLKB': ['clkbuf_sink'],
|
||||
'CLKDIV': ['clkbuf_sink'],
|
||||
'CLKDIVP': ['clkbuf_sink'],
|
||||
}),
|
||||
Cell('KEEPER'),
|
||||
# Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}),
|
||||
Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
||||
Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
|
||||
Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
||||
Cell('ODELAYE2', port_attrs={'C': ['clkbuf_sink']}),
|
||||
Cell('OSERDESE2', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
|
||||
Cell('OUT_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
||||
Cell('PHASER_IN'),
|
||||
Cell('PHASER_IN_PHY'),
|
||||
Cell('PHASER_OUT'),
|
||||
Cell('PHASER_OUT_PHY'),
|
||||
Cell('PHASER_REF'),
|
||||
Cell('PHY_CONTROL'),
|
||||
Cell('PULLDOWN'),
|
||||
Cell('PULLUP'),
|
||||
|
||||
# RAM/ROM.
|
||||
Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
||||
Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
||||
#Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
#Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
#Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
# NOTE: not in the official library guide!
|
||||
Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
# Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
|
||||
# Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
|
||||
Cell('ROM128X1'),
|
||||
Cell('ROM256X1'),
|
||||
Cell('ROM32X1'),
|
||||
Cell('ROM64X1'),
|
||||
|
||||
# Registers/latches.
|
||||
# Cell('FDCE'),
|
||||
# Cell('FDPE'),
|
||||
# Cell('FDRE'),
|
||||
# Cell('FDSE'),
|
||||
Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}),
|
||||
Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
|
||||
Cell('LDCE'),
|
||||
Cell('LDPE'),
|
||||
Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}),
|
||||
|
||||
# Slice/CLB primitives.
|
||||
# Cell('CARRY4'),
|
||||
Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
|
||||
# Cell('LUT1'),
|
||||
# Cell('LUT2'),
|
||||
# Cell('LUT3'),
|
||||
# Cell('LUT4'),
|
||||
# Cell('LUT5'),
|
||||
# Cell('LUT6'),
|
||||
# Cell('LUT6_2'),
|
||||
# Cell('MUXF7'),
|
||||
# Cell('MUXF8'),
|
||||
# Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
|
||||
# Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
|
||||
|
||||
# NOTE: not in the official library guide!
|
||||
Cell('PS7', keep=True),
|
||||
]
|
||||
|
||||
|
||||
XCU_CELLS = [
|
||||
# Design elements types listed in Xilinx UG974.
|
||||
|
||||
# Advanced.
|
||||
Cell('CMAC'),
|
||||
Cell('CMACE4'),
|
||||
Cell('GTHE3_CHANNEL'),
|
||||
Cell('GTHE3_COMMON'),
|
||||
Cell('GTHE4_CHANNEL'),
|
||||
Cell('GTHE4_COMMON'),
|
||||
Cell('GTYE3_CHANNEL'),
|
||||
Cell('GTYE3_COMMON'),
|
||||
Cell('GTYE4_CHANNEL'),
|
||||
Cell('GTYE4_COMMON'),
|
||||
Cell('IBUFDS_GTE3', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFDS_GTE4', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('ILKN'),
|
||||
Cell('ILKNE4'),
|
||||
Cell('OBUFDS_GTE3', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
||||
Cell('OBUFDS_GTE3_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
||||
Cell('OBUFDS_GTE4', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
||||
Cell('OBUFDS_GTE4_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
||||
Cell('PCIE40E4'),
|
||||
Cell('PCIE_3_1'),
|
||||
Cell('SYSMONE1'),
|
||||
Cell('SYSMONE4'),
|
||||
|
||||
# Arithmetic functions.
|
||||
Cell('DSP48E2', port_attrs={'CLK': ['clkbuf_sink']}),
|
||||
|
||||
# Blockram.
|
||||
Cell('FIFO18E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
||||
Cell('FIFO36E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
|
||||
Cell('RAMB18E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
|
||||
Cell('RAMB36E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
|
||||
Cell('URAM288', port_attrs={'CLK': ['clkbuf_sink']}),
|
||||
Cell('URAM288_BASE', port_attrs={'CLK': ['clkbuf_sink']}),
|
||||
|
||||
# CLB.
|
||||
# Cell('LUT6_2'),
|
||||
#Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM256X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM32M16', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
#Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM512X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM64M8', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
#Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
|
||||
Cell('AND2B1L'),
|
||||
Cell('CARRY8'),
|
||||
Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
|
||||
# Cell('LUT1'),
|
||||
# Cell('LUT2'),
|
||||
# Cell('LUT3'),
|
||||
# Cell('LUT4'),
|
||||
# Cell('LUT5'),
|
||||
# Cell('LUT6'),
|
||||
# Cell('MUXF7'),
|
||||
# Cell('MUXF8'),
|
||||
Cell('MUXF9'),
|
||||
Cell('OR2L'),
|
||||
# Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
|
||||
# Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
|
||||
|
||||
# Clock.
|
||||
# Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFG_GT', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFG_GT_SYNC'),
|
||||
Cell('BUFG_PS', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFGCE_DIV', port_attrs={'O': ['clkbuf_driver']}),
|
||||
#Cell('BUFGCTRL', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('BUFGMUX_CTRL', port_attrs={'O': ['clkbuf_driver']}),
|
||||
Cell('MMCME3_ADV'),
|
||||
Cell('MMCME3_BASE'),
|
||||
Cell('MMCME4_ADV'),
|
||||
Cell('MMCME4_BASE'),
|
||||
Cell('PLLE3_ADV'),
|
||||
Cell('PLLE3_BASE'),
|
||||
Cell('PLLE4_ADV'),
|
||||
Cell('PLLE4_BASE'),
|
||||
|
||||
# Configuration.
|
||||
Cell('BSCANE2', keep=True),
|
||||
Cell('DNA_PORTE2'),
|
||||
Cell('EFUSE_USR'),
|
||||
Cell('FRAME_ECCE3'),
|
||||
Cell('ICAPE3', keep=True),
|
||||
Cell('MASTER_JTAG', keep=True),
|
||||
Cell('STARTUPE3', keep=True),
|
||||
Cell('USR_ACCESSE2'),
|
||||
|
||||
# I/O.
|
||||
Cell('BITSLICE_CONTROL', keep=True),
|
||||
Cell('DCIRESET', keep=True),
|
||||
Cell('HPIO_VREF'),
|
||||
# XXX
|
||||
# Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}),
|
||||
Cell('IBUF_ANALOG', port_attrs={'I': ['iopad_external_pin']}),
|
||||
Cell('IBUF_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin']}),
|
||||
Cell('IBUF_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin']}),
|
||||
Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFDS_DIFF_OUT_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFDS_DPHY', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFDS_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFDS_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFDSE3', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
|
||||
Cell('IBUFE3', port_attrs={'I': ['iopad_external_pin']}),
|
||||
Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}),
|
||||
Cell('IDELAYE3', port_attrs={'CLK': ['clkbuf_sink']}),
|
||||
Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
|
||||
Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}),
|
||||
Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}),
|
||||
Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}),
|
||||
Cell('IOBUFDS_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
|
||||
Cell('IOBUFDS_DIFF_OUT', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
|
||||
Cell('IOBUFDS_DIFF_OUT_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
|
||||
Cell('IOBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
|
||||
Cell('IOBUFDS_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
|
||||
Cell('IOBUFDSE3', port_attrs={'IO': ['iopad_external_pin']}),
|
||||
Cell('IOBUFE3', port_attrs={'IO': ['iopad_external_pin']}),
|
||||
Cell('ISERDESE3', port_attrs={
|
||||
'CLK': ['clkbuf_sink'],
|
||||
'CLK_B': ['clkbuf_sink'],
|
||||
'FIFO_RD_CLK': ['clkbuf_sink'],
|
||||
'CLKDIV': ['clkbuf_sink'],
|
||||
}),
|
||||
Cell('KEEPER'),
|
||||
# Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}),
|
||||
Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
||||
Cell('OBUFDS_DPHY', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
||||
Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
|
||||
Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
|
||||
Cell('ODELAYE3', port_attrs={'CLK': ['clkbuf_sink']}),
|
||||
Cell('OSERDESE3', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
|
||||
Cell('PULLDOWN'),
|
||||
Cell('PULLUP'),
|
||||
Cell('RIU_OR'),
|
||||
Cell('RX_BITSLICE'),
|
||||
Cell('RXTX_BITSLICE'),
|
||||
Cell('TX_BITSLICE'),
|
||||
Cell('TX_BITSLICE_TRI'),
|
||||
|
||||
# Registers.
|
||||
# Cell('FDCE'),
|
||||
# Cell('FDPE'),
|
||||
# Cell('FDRE'),
|
||||
# Cell('FDSE'),
|
||||
Cell('HARD_SYNC', port_attrs={'CLK': ['clkbuf_sink']}),
|
||||
Cell('IDDRE1', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
|
||||
Cell('LDCE'),
|
||||
Cell('LDPE'),
|
||||
Cell('ODDRE1', port_attrs={'C': ['clkbuf_sink']}),
|
||||
|
||||
# NOTE: not in the official library guide!
|
||||
Cell('PS8', keep=True),
|
||||
]
|
||||
|
||||
|
||||
class State(Enum):
|
||||
OUTSIDE = auto()
|
||||
IN_MODULE = auto()
|
||||
IN_OTHER_MODULE = auto()
|
||||
IN_FUNCTION = auto()
|
||||
IN_TASK = auto()
|
||||
|
||||
def xtract_cell_decl(cell, dirs, outf):
|
||||
for dir in dirs:
|
||||
fname = os.path.join(dir, cell.name + '.v')
|
||||
try:
|
||||
with open(fname) as f:
|
||||
state = State.OUTSIDE
|
||||
found = False
|
||||
# Probably the most horrible Verilog "parser" ever written.
|
||||
module_ports = []
|
||||
invertible_ports = set()
|
||||
for l in f:
|
||||
l = l.partition('//')[0]
|
||||
l = l.strip()
|
||||
if l == 'module {}'.format(cell.name) or l.startswith('module {} '.format(cell.name)):
|
||||
if found:
|
||||
print('Multiple modules in {}.'.format(fname))
|
||||
sys.exit(1)
|
||||
elif state != State.OUTSIDE:
|
||||
print('Nested modules in {}.'.format(fname))
|
||||
sys.exit(1)
|
||||
found = True
|
||||
state = State.IN_MODULE
|
||||
if cell.keep:
|
||||
outf.write('(* keep *)\n')
|
||||
outf.write('module {} (...);\n'.format(cell.name))
|
||||
elif l.startswith('module '):
|
||||
if state != State.OUTSIDE:
|
||||
print('Nested modules in {}.'.format(fname))
|
||||
sys.exit(1)
|
||||
state = State.IN_OTHER_MODULE
|
||||
elif l.startswith('task '):
|
||||
if state == State.IN_MODULE:
|
||||
state = State.IN_TASK
|
||||
elif l.startswith('function '):
|
||||
if state == State.IN_MODULE:
|
||||
state = State.IN_FUNCTION
|
||||
elif l == 'endtask':
|
||||
if state == State.IN_TASK:
|
||||
state = State.IN_MODULE
|
||||
elif l == 'endfunction':
|
||||
if state == State.IN_FUNCTION:
|
||||
state = State.IN_MODULE
|
||||
elif l == 'endmodule':
|
||||
if state == State.IN_MODULE:
|
||||
for kind, rng, port in module_ports:
|
||||
for attr in cell.port_attrs.get(port, []):
|
||||
outf.write(' (* {} *)\n'.format(attr))
|
||||
if port in invertible_ports:
|
||||
outf.write(' (* invertible_pin = "IS_{}_INVERTED" *)\n'.format(port))
|
||||
if rng is None:
|
||||
outf.write(' {} {};\n'.format(kind, port))
|
||||
else:
|
||||
outf.write(' {} {} {};\n'.format(kind, rng, port))
|
||||
outf.write(l + '\n')
|
||||
outf.write('\n')
|
||||
elif state != State.IN_OTHER_MODULE:
|
||||
print('endmodule in weird place in {}.'.format(cell.name, fname))
|
||||
sys.exit(1)
|
||||
state = State.OUTSIDE
|
||||
elif l.startswith(('input ', 'output ', 'inout ')) and state == State.IN_MODULE:
|
||||
if l.endswith((';', ',')):
|
||||
l = l[:-1]
|
||||
if ';' in l:
|
||||
print('Weird port line in {} [{}].'.format(fname, l))
|
||||
sys.exit(1)
|
||||
kind, _, ports = l.partition(' ')
|
||||
for port in ports.split(','):
|
||||
port = port.strip()
|
||||
if port.startswith('['):
|
||||
rng, port = port.split()
|
||||
else:
|
||||
rng = None
|
||||
module_ports.append((kind, rng, port))
|
||||
elif l.startswith('parameter ') and state == State.IN_MODULE:
|
||||
if 'UNPLACED' in l:
|
||||
continue
|
||||
if l.endswith((';', ',')):
|
||||
l = l[:-1]
|
||||
while ' ' in l:
|
||||
l = l.replace(' ', ' ')
|
||||
if ';' in l:
|
||||
print('Weird parameter line in {} [{}].'.format(fname, l))
|
||||
sys.exit(1)
|
||||
outf.write(' {};\n'.format(l))
|
||||
match = re.search('IS_([a-zA-Z0-9_]+)_INVERTED', l)
|
||||
if match:
|
||||
invertible_ports.add(match[1])
|
||||
if state != State.OUTSIDE:
|
||||
print('endmodule not found in {}.'.format(fname))
|
||||
sys.exit(1)
|
||||
if not found:
|
||||
print('Cannot find module {} in {}.'.format(cell.name, fname))
|
||||
sys.exit(1)
|
||||
return
|
||||
except FileNotFoundError:
|
||||
continue
|
||||
print('Cannot find {}.'.format(cell.name))
|
||||
sys.exit(1)
|
||||
|
||||
if __name__ == '__main__':
|
||||
parser = ArgumentParser(description='Extract Xilinx blackbox cell definitions from ISE and Vivado.')
|
||||
parser.add_argument('vivado_dir', nargs='?', default='/opt/Xilinx/Vivado/2018.1')
|
||||
parser.add_argument('ise_dir', nargs='?', default='/opt/Xilinx/ISE/14.7')
|
||||
args = parser.parse_args()
|
||||
|
||||
dirs = [
|
||||
os.path.join(args.vivado_dir, 'data/verilog/src/xeclib'),
|
||||
os.path.join(args.vivado_dir, 'data/verilog/src/retarget'),
|
||||
os.path.join(args.ise_dir, 'ISE_DS/ISE/verilog/xeclib/unisims'),
|
||||
]
|
||||
for dir in dirs:
|
||||
if not os.path.isdir(dir):
|
||||
print('{} is not a directory'.format(dir))
|
||||
|
||||
for ofile, cells in [
|
||||
('xc6s_cells_xtra.v', XC6S_CELLS),
|
||||
('xc6v_cells_xtra.v', XC6V_CELLS),
|
||||
('xc7_cells_xtra.v', XC7_CELLS),
|
||||
('xcu_cells_xtra.v', XCU_CELLS),
|
||||
]:
|
||||
out = StringIO()
|
||||
for cell in cells:
|
||||
xtract_cell_decl(cell, dirs, out)
|
||||
|
||||
with open(ofile, 'w') as f:
|
||||
f.write('// Created by cells_xtra.py from Xilinx models\n')
|
||||
f.write('\n')
|
||||
f.write(out.getvalue())
|
||||
|
|
@ -1,147 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
set -e
|
||||
libdir="/opt/Xilinx/Vivado/2018.1/data/verilog/src"
|
||||
|
||||
function xtract_cell_decl()
|
||||
{
|
||||
for dir in $libdir/xeclib $libdir/retarget; do
|
||||
[ -f $dir/$1.v ] || continue
|
||||
[ -z "$2" ] || echo $2
|
||||
egrep '^\s*((end)?module|parameter|input|inout|output|(end)?function|(end)?task)' $dir/$1.v |
|
||||
sed -re '/UNPLACED/ d; /^\s*function/,/endfunction/ d; /^\s*task/,/endtask/ d;
|
||||
s,//.*,,; s/#?\(.*/(...);/; s/^(input|output|parameter)/ \1/;
|
||||
s/\s+$//; s/,$/;/; /input|output|parameter/ s/[^;]$/&;/; s/\s+/ /g;
|
||||
s/^ ((end)?module)/\1/; s/^ / /; /module.*_bb/,/endmodule/ d;'
|
||||
echo; return
|
||||
done
|
||||
echo "Can't find $1."
|
||||
exit 1
|
||||
}
|
||||
|
||||
{
|
||||
echo "// Created by cells_xtra.sh from Xilinx models"
|
||||
echo
|
||||
|
||||
# Design elements types listed in Xilinx UG953
|
||||
xtract_cell_decl BSCANE2
|
||||
# xtract_cell_decl BUFG
|
||||
xtract_cell_decl BUFGCE
|
||||
xtract_cell_decl BUFGCE_1
|
||||
#xtract_cell_decl BUFGCTRL
|
||||
xtract_cell_decl BUFGMUX
|
||||
xtract_cell_decl BUFGMUX_1
|
||||
xtract_cell_decl BUFGMUX_CTRL
|
||||
xtract_cell_decl BUFH
|
||||
#xtract_cell_decl BUFHCE
|
||||
xtract_cell_decl BUFIO
|
||||
xtract_cell_decl BUFMR
|
||||
xtract_cell_decl BUFMRCE
|
||||
xtract_cell_decl BUFR
|
||||
xtract_cell_decl CAPTUREE2 "(* keep *)"
|
||||
# xtract_cell_decl CARRY4
|
||||
xtract_cell_decl CFGLUT5
|
||||
xtract_cell_decl DCIRESET "(* keep *)"
|
||||
xtract_cell_decl DNA_PORT
|
||||
xtract_cell_decl DSP48E1
|
||||
xtract_cell_decl EFUSE_USR
|
||||
# xtract_cell_decl FDCE
|
||||
# xtract_cell_decl FDPE
|
||||
# xtract_cell_decl FDRE
|
||||
# xtract_cell_decl FDSE
|
||||
xtract_cell_decl FIFO18E1
|
||||
xtract_cell_decl FIFO36E1
|
||||
xtract_cell_decl FRAME_ECCE2
|
||||
xtract_cell_decl GTHE2_CHANNEL
|
||||
xtract_cell_decl GTHE2_COMMON
|
||||
xtract_cell_decl GTPE2_CHANNEL
|
||||
xtract_cell_decl GTPE2_COMMON
|
||||
xtract_cell_decl GTXE2_CHANNEL
|
||||
xtract_cell_decl GTXE2_COMMON
|
||||
# xtract_cell_decl IBUF
|
||||
xtract_cell_decl IBUF_IBUFDISABLE
|
||||
xtract_cell_decl IBUF_INTERMDISABLE
|
||||
xtract_cell_decl IBUFDS
|
||||
xtract_cell_decl IBUFDS_DIFF_OUT
|
||||
xtract_cell_decl IBUFDS_DIFF_OUT_IBUFDISABLE
|
||||
xtract_cell_decl IBUFDS_DIFF_OUT_INTERMDISABLE
|
||||
xtract_cell_decl IBUFDS_GTE2
|
||||
xtract_cell_decl IBUFDS_IBUFDISABLE
|
||||
xtract_cell_decl IBUFDS_INTERMDISABLE
|
||||
xtract_cell_decl ICAPE2 "(* keep *)"
|
||||
xtract_cell_decl IDDR
|
||||
xtract_cell_decl IDDR_2CLK
|
||||
xtract_cell_decl IDELAYCTRL "(* keep *)"
|
||||
xtract_cell_decl IDELAYE2
|
||||
xtract_cell_decl IN_FIFO
|
||||
xtract_cell_decl IOBUF
|
||||
xtract_cell_decl IOBUF_DCIEN
|
||||
xtract_cell_decl IOBUF_INTERMDISABLE
|
||||
xtract_cell_decl IOBUFDS
|
||||
xtract_cell_decl IOBUFDS_DCIEN
|
||||
xtract_cell_decl IOBUFDS_DIFF_OUT
|
||||
xtract_cell_decl IOBUFDS_DIFF_OUT_DCIEN
|
||||
xtract_cell_decl IOBUFDS_DIFF_OUT_INTERMDISABLE
|
||||
xtract_cell_decl ISERDESE2
|
||||
xtract_cell_decl KEEPER
|
||||
xtract_cell_decl LDCE
|
||||
xtract_cell_decl LDPE
|
||||
# xtract_cell_decl LUT1
|
||||
# xtract_cell_decl LUT2
|
||||
# xtract_cell_decl LUT3
|
||||
# xtract_cell_decl LUT4
|
||||
# xtract_cell_decl LUT5
|
||||
# xtract_cell_decl LUT6
|
||||
#xtract_cell_decl LUT6_2
|
||||
xtract_cell_decl MMCME2_ADV
|
||||
xtract_cell_decl MMCME2_BASE
|
||||
# xtract_cell_decl MUXF7
|
||||
# xtract_cell_decl MUXF8
|
||||
# xtract_cell_decl OBUF
|
||||
xtract_cell_decl OBUFDS
|
||||
xtract_cell_decl OBUFT
|
||||
xtract_cell_decl OBUFTDS
|
||||
xtract_cell_decl ODDR
|
||||
xtract_cell_decl ODELAYE2
|
||||
xtract_cell_decl OSERDESE2
|
||||
xtract_cell_decl OUT_FIFO
|
||||
xtract_cell_decl PHASER_IN
|
||||
xtract_cell_decl PHASER_IN_PHY
|
||||
xtract_cell_decl PHASER_OUT
|
||||
xtract_cell_decl PHASER_OUT_PHY
|
||||
xtract_cell_decl PHASER_REF
|
||||
xtract_cell_decl PHY_CONTROL
|
||||
xtract_cell_decl PLLE2_ADV
|
||||
xtract_cell_decl PLLE2_BASE
|
||||
xtract_cell_decl PS7 "(* keep *)"
|
||||
xtract_cell_decl PULLDOWN
|
||||
xtract_cell_decl PULLUP
|
||||
#xtract_cell_decl RAM128X1D
|
||||
xtract_cell_decl RAM128X1S
|
||||
xtract_cell_decl RAM256X1S
|
||||
xtract_cell_decl RAM32M
|
||||
#xtract_cell_decl RAM32X1D
|
||||
xtract_cell_decl RAM32X1S
|
||||
xtract_cell_decl RAM32X1S_1
|
||||
xtract_cell_decl RAM32X2S
|
||||
xtract_cell_decl RAM64M
|
||||
#xtract_cell_decl RAM64X1D
|
||||
xtract_cell_decl RAM64X1S
|
||||
xtract_cell_decl RAM64X1S_1
|
||||
xtract_cell_decl RAM64X2S
|
||||
# xtract_cell_decl RAMB18E1
|
||||
# xtract_cell_decl RAMB36E1
|
||||
xtract_cell_decl ROM128X1
|
||||
xtract_cell_decl ROM256X1
|
||||
xtract_cell_decl ROM32X1
|
||||
xtract_cell_decl ROM64X1
|
||||
#xtract_cell_decl SRL16E
|
||||
#xtract_cell_decl SRLC32E
|
||||
xtract_cell_decl STARTUPE2 "(* keep *)"
|
||||
xtract_cell_decl USR_ACCESSE2
|
||||
xtract_cell_decl XADC
|
||||
} > cells_xtra.new
|
||||
|
||||
mv cells_xtra.new cells_xtra.v
|
||||
exit 0
|
||||
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
// ============================================================================
|
||||
// FF mapping
|
||||
|
||||
`ifndef _NO_FFS
|
||||
|
||||
module \$_DFF_N_ (input D, C, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
|
||||
module \$_DFF_P_ (input D, C, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
|
||||
|
||||
module \$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule
|
||||
module \$_DFFE_PP_ (input D, C, E, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule
|
||||
|
||||
module \$_DFF_NN0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule
|
||||
module \$_DFF_NP0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
|
||||
module \$_DFF_PN0_ (input D, C, R, output Q); FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule
|
||||
module \$_DFF_PP0_ (input D, C, R, output Q); FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
|
||||
|
||||
module \$_DFF_NN1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
|
||||
module \$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
|
||||
module \$_DFF_PN1_ (input D, C, R, output Q); FDPE #(.INIT(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
|
||||
module \$_DFF_PP1_ (input D, C, R, output Q); FDPE #(.INIT(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
|
||||
|
||||
`endif
|
||||
|
||||
|
|
@ -46,7 +46,7 @@ struct SynthXilinxPass : public ScriptPass
|
|||
log(" -top <module>\n");
|
||||
log(" use the specified module as top module\n");
|
||||
log("\n");
|
||||
log(" -family {xcup|xcu|xc7|xc6s}\n");
|
||||
log(" -family {xcup|xcu|xc7|xc6v|xc6s}\n");
|
||||
log(" run synthesis for the specified Xilinx architecture\n");
|
||||
log(" generate the synthesis netlist for the specified family.\n");
|
||||
log(" default: xc7\n");
|
||||
|
|
@ -63,6 +63,9 @@ struct SynthXilinxPass : public ScriptPass
|
|||
log(" generate an output netlist (and BLIF file) suitable for VPR\n");
|
||||
log(" (this feature is experimental and incomplete)\n");
|
||||
log("\n");
|
||||
log(" -ise\n");
|
||||
log(" generate an output netlist suitable for ISE (enables -iopad)\n");
|
||||
log("\n");
|
||||
log(" -nobram\n");
|
||||
log(" do not use block RAM cells in output netlist\n");
|
||||
log("\n");
|
||||
|
|
@ -78,6 +81,15 @@ struct SynthXilinxPass : public ScriptPass
|
|||
log(" -nowidelut\n");
|
||||
log(" do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
|
||||
log("\n");
|
||||
log(" -iopad\n");
|
||||
log(" enable I/O buffer insertion (selected automatically by -ise)\n");
|
||||
log("\n");
|
||||
log(" -noiopad\n");
|
||||
log(" disable I/O buffer insertion (only useful with -ise)\n");
|
||||
log("\n");
|
||||
log(" -noclkbuf\n");
|
||||
log(" disable automatic clock buffer insertion\n");
|
||||
log("\n");
|
||||
log(" -widemux <int>\n");
|
||||
log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n");
|
||||
log(" above this number of inputs (minimum value 2, recommended value >= 5).\n");
|
||||
|
|
@ -104,7 +116,8 @@ struct SynthXilinxPass : public ScriptPass
|
|||
}
|
||||
|
||||
std::string top_opt, edif_file, blif_file, family;
|
||||
bool flatten, retime, vpr, nobram, nolutram, nosrl, nocarry, nowidelut, abc9;
|
||||
bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, abc9;
|
||||
bool flatten_before_abc;
|
||||
int widemux;
|
||||
|
||||
void clear_flags() YS_OVERRIDE
|
||||
|
|
@ -116,6 +129,10 @@ struct SynthXilinxPass : public ScriptPass
|
|||
flatten = false;
|
||||
retime = false;
|
||||
vpr = false;
|
||||
ise = false;
|
||||
iopad = false;
|
||||
noiopad = false;
|
||||
noclkbuf = false;
|
||||
nocarry = false;
|
||||
nobram = false;
|
||||
nolutram = false;
|
||||
|
|
@ -123,6 +140,7 @@ struct SynthXilinxPass : public ScriptPass
|
|||
nocarry = false;
|
||||
nowidelut = false;
|
||||
abc9 = false;
|
||||
flatten_before_abc = false;
|
||||
widemux = 0;
|
||||
}
|
||||
|
||||
|
|
@ -162,6 +180,10 @@ struct SynthXilinxPass : public ScriptPass
|
|||
flatten = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-flatten_before_abc") {
|
||||
flatten_before_abc = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-retime") {
|
||||
retime = true;
|
||||
continue;
|
||||
|
|
@ -178,6 +200,22 @@ struct SynthXilinxPass : public ScriptPass
|
|||
vpr = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-ise") {
|
||||
ise = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-iopad") {
|
||||
iopad = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-noiopad") {
|
||||
noiopad = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-noclkbuf") {
|
||||
noclkbuf = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nocarry") {
|
||||
nocarry = true;
|
||||
continue;
|
||||
|
|
@ -206,7 +244,7 @@ struct SynthXilinxPass : public ScriptPass
|
|||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6s")
|
||||
if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" && family != "xc6s")
|
||||
log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str());
|
||||
|
||||
if (widemux != 0 && widemux < 2)
|
||||
|
|
@ -228,19 +266,36 @@ struct SynthXilinxPass : public ScriptPass
|
|||
|
||||
void script() YS_OVERRIDE
|
||||
{
|
||||
std::string ff_map_file;
|
||||
if (help_mode)
|
||||
ff_map_file = "+/xilinx/{family}_ff_map.v";
|
||||
else if (family == "xc6s")
|
||||
ff_map_file = "+/xilinx/xc6s_ff_map.v";
|
||||
else
|
||||
ff_map_file = "+/xilinx/xc7_ff_map.v";
|
||||
|
||||
if (check_label("begin")) {
|
||||
if (vpr)
|
||||
run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
|
||||
else
|
||||
run("read_verilog -lib +/xilinx/cells_sim.v");
|
||||
|
||||
run("read_verilog -lib +/xilinx/cells_xtra.v");
|
||||
if (help_mode)
|
||||
run("read_verilog -lib +/xilinx/{family}_cells_xtra.v");
|
||||
else if (family == "xc6s")
|
||||
run("read_verilog -lib +/xilinx/xc6s_cells_xtra.v");
|
||||
else if (family == "xc6v")
|
||||
run("read_verilog -lib +/xilinx/xc6v_cells_xtra.v");
|
||||
else if (family == "xc7")
|
||||
run("read_verilog -lib +/xilinx/xc7_cells_xtra.v");
|
||||
else if (family == "xcu" || family == "xcup")
|
||||
run("read_verilog -lib +/xilinx/xcu_cells_xtra.v");
|
||||
|
||||
if (help_mode) {
|
||||
run("read_verilog -lib +/xilinx/{family}_brams_bb.v");
|
||||
} else if (family == "xc6s") {
|
||||
run("read_verilog -lib +/xilinx/xc6s_brams_bb.v");
|
||||
} else if (family == "xc7") {
|
||||
} else if (family == "xc6v" || family == "xc7") {
|
||||
run("read_verilog -lib +/xilinx/xc7_brams_bb.v");
|
||||
}
|
||||
|
||||
|
|
@ -265,9 +320,8 @@ struct SynthXilinxPass : public ScriptPass
|
|||
if (widemux > 0 || help_mode)
|
||||
run("muxpack", " ('-widemux' only)");
|
||||
|
||||
// shregmap -tech xilinx can cope with $shiftx and $mux
|
||||
// cells for identifying variable-length shift registers,
|
||||
// so attempt to convert $pmux-es to the former
|
||||
// xilinx_srl looks for $shiftx cells for identifying variable-length
|
||||
// shift registers, so attempt to convert $pmux-es to this
|
||||
// Also: wide multiplexer inference benefits from this too
|
||||
if (!(nosrl && widemux == 0) || help_mode) {
|
||||
run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')");
|
||||
|
|
@ -292,7 +346,7 @@ struct SynthXilinxPass : public ScriptPass
|
|||
if (family == "xc6s") {
|
||||
run("memory_bram -rules +/xilinx/xc6s_brams.txt");
|
||||
run("techmap -map +/xilinx/xc6s_brams_map.v");
|
||||
} else if (family == "xc7") {
|
||||
} else if (family == "xc6v" || family == "xc7") {
|
||||
run("memory_bram -rules +/xilinx/xc7_brams.txt");
|
||||
run("techmap -map +/xilinx/xc7_brams_map.v");
|
||||
} else {
|
||||
|
|
@ -349,13 +403,8 @@ struct SynthXilinxPass : public ScriptPass
|
|||
}
|
||||
run("opt -full");
|
||||
|
||||
if (!nosrl || help_mode) {
|
||||
// shregmap operates on bit-level flops, not word-level,
|
||||
// so break those down here
|
||||
run("simplemap t:$dff t:$dffe", " (skip if '-nosrl')");
|
||||
// shregmap with '-tech xilinx' infers variable length shift regs
|
||||
run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
|
||||
}
|
||||
if (!nosrl || help_mode)
|
||||
run("xilinx_srl -variable -minlen 3", "(skip if '-nosrl')");
|
||||
|
||||
std::string techmap_args = " -map +/techmap.v";
|
||||
if (help_mode)
|
||||
|
|
@ -379,21 +428,27 @@ struct SynthXilinxPass : public ScriptPass
|
|||
std::string techmap_args = "-map +/techmap.v -map +/xilinx/cells_map.v";
|
||||
if (widemux > 0)
|
||||
techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
|
||||
if (abc9)
|
||||
techmap_args += " -map +/xilinx/ff_map.v";
|
||||
run("techmap " + techmap_args);
|
||||
run("clean");
|
||||
}
|
||||
|
||||
if (check_label("map_ffs")) {
|
||||
if (abc9 || help_mode) {
|
||||
run("techmap -map " + ff_map_file, "('-abc9' only)");
|
||||
}
|
||||
}
|
||||
|
||||
if (check_label("map_luts")) {
|
||||
run("opt_expr -mux_undef");
|
||||
if (flatten_before_abc)
|
||||
run("flatten");
|
||||
if (help_mode)
|
||||
run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut', option for '-retime')");
|
||||
run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut'; option for '-retime')");
|
||||
else if (abc9) {
|
||||
if (family != "xc7")
|
||||
log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
|
||||
run("techmap -map +/xilinx/abc_map.v -max_iter 1");
|
||||
run("read_verilog -icells -lib +/xilinx/abc_model.v");
|
||||
run("techmap -map +/xilinx/abc_map.v");
|
||||
if (nowidelut)
|
||||
run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
|
||||
else
|
||||
|
|
@ -410,18 +465,32 @@ struct SynthXilinxPass : public ScriptPass
|
|||
// This shregmap call infers fixed length shift registers after abc
|
||||
// has performed any necessary retiming
|
||||
if (!nosrl || help_mode)
|
||||
run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
|
||||
std::string techmap_args = "-map +/xilinx/lut_map.v";
|
||||
if (abc9)
|
||||
run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')");
|
||||
std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v";
|
||||
if (help_mode)
|
||||
techmap_args += " [-map " + ff_map_file + "]";
|
||||
else if (abc9)
|
||||
techmap_args += " -map +/xilinx/abc_unmap.v";
|
||||
else
|
||||
techmap_args += " -map +/xilinx/ff_map.v";
|
||||
techmap_args += " -map " + ff_map_file;
|
||||
run("techmap " + techmap_args);
|
||||
run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
|
||||
"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
|
||||
run("clean");
|
||||
}
|
||||
|
||||
if (check_label("finalize")) {
|
||||
bool do_iopad = iopad || (ise && !noiopad);
|
||||
if (help_mode || !noclkbuf) {
|
||||
if (help_mode || do_iopad)
|
||||
run("clkbufmap -buf BUFG O:I -inpad IBUFG O:I", "(skip if '-noclkbuf', '-inpad' passed if '-iopad' or '-ise' and not '-noiopad')");
|
||||
else
|
||||
run("clkbufmap -buf BUFG O:I");
|
||||
}
|
||||
if (help_mode || do_iopad)
|
||||
run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopad' or '-ise' and not '-noiopad')");
|
||||
if (help_mode || ise)
|
||||
run("extractinv -inv INV O:I", "(only if '-ise')");
|
||||
}
|
||||
|
||||
if (check_label("check")) {
|
||||
run("hierarchy -check");
|
||||
run("stat -tech xilinx");
|
||||
|
|
|
|||
|
|
@ -1,5 +1,7 @@
|
|||
module RAMB8BWER (
|
||||
(* clkbuf_sink *)
|
||||
input CLKAWRCLK,
|
||||
(* clkbuf_sink *)
|
||||
input CLKBRDCLK,
|
||||
input ENAWREN,
|
||||
input ENBRDEN,
|
||||
|
|
@ -87,7 +89,9 @@ module RAMB8BWER (
|
|||
endmodule
|
||||
|
||||
module RAMB16BWER (
|
||||
(* clkbuf_sink *)
|
||||
input CLKA,
|
||||
(* clkbuf_sink *)
|
||||
input CLKB,
|
||||
input ENA,
|
||||
input ENB,
|
||||
|
|
|
|||
1859
techlibs/xilinx/xc6s_cells_xtra.v
Normal file
1859
techlibs/xilinx/xc6s_cells_xtra.v
Normal file
File diff suppressed because it is too large
Load diff
126
techlibs/xilinx/xc6s_ff_map.v
Normal file
126
techlibs/xilinx/xc6s_ff_map.v
Normal file
|
|
@ -0,0 +1,126 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
// ============================================================================
|
||||
// FF mapping
|
||||
|
||||
`ifndef _NO_FFS
|
||||
|
||||
module \$_DFF_N_ (input D, C, output Q);
|
||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
||||
FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S(1'b0));
|
||||
else
|
||||
FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
|
||||
endgenerate
|
||||
endmodule
|
||||
module \$_DFF_P_ (input D, C, output Q);
|
||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
||||
FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S(1'b0));
|
||||
else
|
||||
FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
module \$_DFFE_NP_ (input D, C, E, output Q);
|
||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
||||
FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(1'b0));
|
||||
else
|
||||
FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0));
|
||||
endgenerate
|
||||
endmodule
|
||||
module \$_DFFE_PP_ (input D, C, E, output Q);
|
||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
||||
FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(1'b0));
|
||||
else
|
||||
FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0));
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
module \$_DFF_NN0_ (input D, C, R, output Q);
|
||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
||||
$error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
|
||||
else
|
||||
FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
|
||||
endgenerate
|
||||
endmodule
|
||||
module \$_DFF_NP0_ (input D, C, R, output Q);
|
||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
||||
$error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
|
||||
else
|
||||
FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
|
||||
endgenerate
|
||||
endmodule
|
||||
module \$_DFF_PN0_ (input D, C, R, output Q);
|
||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
||||
$error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
|
||||
else
|
||||
FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
|
||||
endgenerate
|
||||
endmodule
|
||||
module \$_DFF_PP0_ (input D, C, R, output Q);
|
||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
||||
$error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
|
||||
else
|
||||
FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
module \$_DFF_NN1_ (input D, C, R, output Q);
|
||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
|
||||
$error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
|
||||
else
|
||||
FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
|
||||
endgenerate
|
||||
endmodule
|
||||
module \$_DFF_NP1_ (input D, C, R, output Q);
|
||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
|
||||
$error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
|
||||
else
|
||||
FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
|
||||
endgenerate
|
||||
endmodule
|
||||
module \$_DFF_PN1_ (input D, C, R, output Q);
|
||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
|
||||
$error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
|
||||
else
|
||||
FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
|
||||
endgenerate
|
||||
endmodule
|
||||
module \$_DFF_PP1_ (input D, C, R, output Q);
|
||||
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
|
||||
$error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
|
||||
else
|
||||
FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
`endif
|
||||
|
||||
2720
techlibs/xilinx/xc6v_cells_xtra.v
Normal file
2720
techlibs/xilinx/xc6v_cells_xtra.v
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -1,15 +1,25 @@
|
|||
// Max delays from https://github.com/SymbiFlow/prjxray-db/blob/f8e0364116b2983ac72a3dc8c509ea1cc79e2e3d/artix7/timings/BRAM_L.sdf#L138-L147
|
||||
|
||||
module RAMB18E1 (
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
|
||||
input CLKARDCLK,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
|
||||
input CLKBWRCLK,
|
||||
(* invertible_pin = "IS_ENARDEN_INVERTED" *)
|
||||
input ENARDEN,
|
||||
(* invertible_pin = "IS_ENBWREN_INVERTED" *)
|
||||
input ENBWREN,
|
||||
input REGCEAREGCE,
|
||||
input REGCEB,
|
||||
(* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
|
||||
input RSTRAMARSTRAM,
|
||||
(* invertible_pin = "IS_RSTRAMB_INVERTED" *)
|
||||
input RSTRAMB,
|
||||
(* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
|
||||
input RSTREGARSTREG,
|
||||
(* invertible_pin = "IS_RSTREGB_INVERTED" *)
|
||||
input RSTREGB,
|
||||
|
||||
input [13:0] ADDRARDADDR,
|
||||
|
|
@ -21,10 +31,14 @@ module RAMB18E1 (
|
|||
input [1:0] WEA,
|
||||
input [3:0] WEBWE,
|
||||
|
||||
(* abc_arrival=2454 *) output [15:0] DOADO,
|
||||
(* abc_arrival=2454 *) output [15:0] DOBDO,
|
||||
(* abc_arrival=2454 *) output [1:0] DOPADOP,
|
||||
(* abc_arrival=2454 *) output [1:0] DOPBDOP
|
||||
(* abc_arrival=2454 *)
|
||||
output [15:0] DOADO,
|
||||
(* abc_arrival=2454 *)
|
||||
output [15:0] DOBDO,
|
||||
(* abc_arrival=2454 *)
|
||||
output [1:0] DOPADOP,
|
||||
(* abc_arrival=2454 *)
|
||||
output [1:0] DOPBDOP
|
||||
);
|
||||
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
|
|
@ -125,15 +139,25 @@ module RAMB18E1 (
|
|||
endmodule
|
||||
|
||||
module RAMB36E1 (
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
|
||||
input CLKARDCLK,
|
||||
(* clkbuf_sink *)
|
||||
(* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
|
||||
input CLKBWRCLK,
|
||||
(* invertible_pin = "IS_ENARDEN_INVERTED" *)
|
||||
input ENARDEN,
|
||||
(* invertible_pin = "IS_ENBWREN_INVERTED" *)
|
||||
input ENBWREN,
|
||||
input REGCEAREGCE,
|
||||
input REGCEB,
|
||||
(* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
|
||||
input RSTRAMARSTRAM,
|
||||
(* invertible_pin = "IS_RSTRAMB_INVERTED" *)
|
||||
input RSTRAMB,
|
||||
(* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
|
||||
input RSTREGARSTREG,
|
||||
(* invertible_pin = "IS_RSTREGB_INVERTED" *)
|
||||
input RSTREGB,
|
||||
|
||||
input [15:0] ADDRARDADDR,
|
||||
|
|
@ -145,10 +169,14 @@ module RAMB36E1 (
|
|||
input [3:0] WEA,
|
||||
input [7:0] WEBWE,
|
||||
|
||||
(* abc_arrival=2454 *) output [31:0] DOADO,
|
||||
(* abc_arrival=2454 *) output [31:0] DOBDO,
|
||||
(* abc_arrival=2454 *) output [3:0] DOPADOP,
|
||||
(* abc_arrival=2454 *) output [3:0] DOPBDOP
|
||||
(* abc_arrival=2454 *)
|
||||
output [31:0] DOADO,
|
||||
(* abc_arrival=2454 *)
|
||||
output [31:0] DOBDO,
|
||||
(* abc_arrival=2454 *)
|
||||
output [3:0] DOPADOP,
|
||||
(* abc_arrival=2454 *)
|
||||
output [3:0] DOPBDOP
|
||||
);
|
||||
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
78
techlibs/xilinx/xc7_ff_map.v
Normal file
78
techlibs/xilinx/xc7_ff_map.v
Normal file
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
// ============================================================================
|
||||
// FF mapping
|
||||
|
||||
`ifndef _NO_FFS
|
||||
|
||||
module \$_DFF_N_ (input D, C, output Q);
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
|
||||
endmodule
|
||||
module \$_DFF_P_ (input D, C, output Q);
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
|
||||
endmodule
|
||||
|
||||
module \$_DFFE_NP_ (input D, C, E, output Q);
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0));
|
||||
endmodule
|
||||
module \$_DFFE_PP_ (input D, C, E, output Q);
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0));
|
||||
endmodule
|
||||
|
||||
module \$_DFF_NN0_ (input D, C, R, output Q);
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
|
||||
endmodule
|
||||
module \$_DFF_NP0_ (input D, C, R, output Q);
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
|
||||
endmodule
|
||||
module \$_DFF_PN0_ (input D, C, R, output Q);
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
|
||||
endmodule
|
||||
module \$_DFF_PP0_ (input D, C, R, output Q);
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
|
||||
endmodule
|
||||
|
||||
module \$_DFF_NN1_ (input D, C, R, output Q);
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
|
||||
endmodule
|
||||
module \$_DFF_NP1_ (input D, C, R, output Q);
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
|
||||
endmodule
|
||||
module \$_DFF_PN1_ (input D, C, R, output Q);
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
|
||||
endmodule
|
||||
module \$_DFF_PP1_ (input D, C, R, output Q);
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
|
||||
endmodule
|
||||
|
||||
`endif
|
||||
|
||||
11798
techlibs/xilinx/xcu_cells_xtra.v
Normal file
11798
techlibs/xilinx/xcu_cells_xtra.v
Normal file
File diff suppressed because it is too large
Load diff
Loading…
Add table
Add a link
Reference in a new issue