diff --git a/Brewfile b/Brewfile
index 0c58ce161..8465d86f9 100644
--- a/Brewfile
+++ b/Brewfile
@@ -6,3 +6,5 @@ brew "git"
brew "graphviz"
brew "pkg-config"
brew "python3"
+brew "tcl-tk"
+brew "xdot"
diff --git a/CHANGELOG b/CHANGELOG
index ca42df71e..0adf1e813 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -12,7 +12,10 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added "synth_xilinx -abc9" (experimental)
- Added "synth_ice40 -abc9" (experimental)
- Added "synth -abc9" (experimental)
- - Added "script -scriptwire
+ - Added "script -scriptwire"
+ - Added "synth_xilinx -nocarry"
+ - Added "synth_xilinx -nowidelut"
+ - Added "synth_ecp5 -nowidelut"
- "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
- Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
- Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
@@ -23,37 +26,142 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added automatic gzip compression (based on filename extension) for backends
- Improve attribute and parameter encoding in JSON to avoid ambiguities between
bit vectors and strings containing [01xz]*
+ - Added "clkbufmap" pass
+ - Added "extractinv" pass and "invertible_pin" attribute
+ - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
+ - Added "synth_xilinx -ise" (experimental)
+ - Added "synth_xilinx -iopad"
+ - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
- Improvements in pmgen: subpattern and recursive matches
- Added "opt_share" pass, run as part of "opt -full"
- Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
- Removed "ice40_unlut"
+ - Improvements in pmgen: slices, choices, define, generate
+ - Added "xilinx_srl" for Xilinx shift register extraction
+ - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
+ - Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
+ - Added "-match-init" option to "dff2dffs" pass
+ - Added "techmap_autopurge" support to techmap
+ - Added "add -mod <modname[s]>"
-Yosys 0.8 .. Yosys 0.8-dev
---------------------------
+Yosys 0.8 .. Yosys 0.9
+----------------------
* Various
- - Added $changed support to read_verilog
+ - Many bugfixes and small improvements
+ - Added support for SystemVerilog interfaces and modports
- Added "write_edif -attrprop"
- - Added "ice40_unlut" pass
- Added "opt_lut" pass
- - Added "synth_ice40 -relut"
- - Added "synth_ice40 -noabc"
- Added "gate2lut.v" techmap rule
- Added "rename -src"
- Added "equiv_opt" pass
- - Added "shregmap -tech xilinx"
+ - Added "flowmap" LUT mapping pass
+ - Added "rename -wire" to rename cells based on the wires they drive
+ - Added "bugpoint" for creating minimised testcases
+ - Added "write_edif -gndvccy"
+ - "write_verilog" to escape Verilog keywords
+ - Fixed sign handling of real constants
+ - "write_verilog" to write initial statement for initial flop state
+ - Added pmgen pattern matcher generator
+ - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
+ - Added "setundef -params" to replace undefined cell parameters
+ - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
+ - Fixed handling of defparam when default_nettype is none
+ - Fixed "wreduce" flipflop handling
+ - Fixed FIRRTL to Verilog process instance subfield assignment
+ - Added "write_verilog -siminit"
+ - Several fixes and improvements for mem2reg memories
+ - Fixed handling of task output ports in clocked always blocks
+ - Improved handling of and-with-1 and or-with-0 in "opt_expr"
- Added "read_aiger" frontend
+ - Added "mutate" pass
+ - Added "hdlname" attribute
+ - Added "rename -output"
+ - Added "read_ilang -lib"
+ - Improved "proc" full_case detection and handling
+ - Added "whitebox" and "lib_whitebox" attributes
+ - Added "read_verilog -nowb", "flatten -wb" and "wbflip"
+ - Added Python bindings and support for Python plug-ins
+ - Added "pmux2shiftx"
+ - Added log_debug framework for reduced default verbosity
+ - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
+ - Added "peepopt" peephole optimisation pass using pmgen
+ - Added approximate support for SystemVerilog "var" keyword
+ - Added parsing of "specify" blocks into $specrule and $specify[23]
+ - Added support for attributes on parameters and localparams
+ - Added support for parsing attributes on port connections
+ - Added "wreduce -keepdc"
+ - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
+ - Added Verilog wand/wor wire type support
+ - Added support for elaboration system tasks
- Added "muxcover -mux{4,8,16}=<cost>"
- Added "muxcover -dmux=<cost>"
- Added "muxcover -nopartial"
- Added "muxpack" pass
- Added "pmux2shiftx -norange"
+ - Added support for "~" in filename parsing
+ - Added "read_verilog -pwires" feature to turn parameters into wires
+ - Fixed sign extension of unsized constants with 'bx and 'bz MSB
+ - Fixed genvar to be a signed type
+ - Added support for attributes on case rules
+ - Added "upto" and "offset" to JSON frontend and backend
+ - Several liberty file parser improvements
+ - Fixed handling of more complex BRAM patterns
+ - Add "write_aiger -I -O -B"
+
+ * Formal Verification
+ - Added $changed support to read_verilog
+ - Added "read_verilog -noassert -noassume -assert-assumes"
+ - Added btor ops for $mul, $div, $mod and $concat
+ - Added yosys-smtbmc support for btor witnesses
+ - Added "supercover" pass
+ - Fixed $global_clock handling vs autowire
+ - Added $dffsr support to "async2sync"
+ - Added "fmcombine" pass
+ - Added memory init support in "write_btor"
+ - Added "cutpoint" pass
+ - Changed "ne" to "neq" in btor2 output
+ - Added support for SVA "final" keyword
+ - Added "fmcombine -initeq -anyeq"
+ - Added timescale and generated-by header to yosys-smtbmc vcd output
+ - Improved BTOR2 handling of undriven wires
+
+ * Verific support
+ - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
+ - Improved support for asymmetric memories
+ - Added "verific -chparam"
+ - Fixed "verific -extnets" for more complex situations
+ - Added "read -verific" and "read -noverific"
+ - Added "hierarchy -chparam"
+
+ * New back-ends
+ - Added initial Anlogic support
+ - Added initial SmartFusion2 and IGLOO2 support
+
+ * ECP5 support
+ - Added "synth_ecp5 -nowidelut"
+ - Added BRAM inference support to "synth_ecp5"
+ - Added support for transforming Diamond IO and flipflop primitives
+
+ * iCE40 support
+ - Added "ice40_unlut" pass
+ - Added "synth_ice40 -relut"
+ - Added "synth_ice40 -noabc"
+ - Added "synth_ice40 -dffe_min_ce_use"
+ - Added DSP inference support using pmgen
+ - Added support for initialising BRAM primitives from a file
+ - Added iCE40 Ultra RGB LED driver cells
+
+ * Xilinx support
+ - Use "write_edif -pvector bra" for Xilinx EDIF files
+ - Fixes for VPR place and route support with "synth_xilinx"
+ - Added more cell simulation models
+ - Added "synth_xilinx -family"
+ - Added "stat -tech xilinx" to estimate logic cell usage
- Added "synth_xilinx -nocarry"
- Added "synth_xilinx -nowidelut"
- - Added "synth_ecp5 -nowidelut"
- "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
- - Fixed sign extension of unsized constants with 'bx and 'bz MSB
-
+ - Added support for mapping RAM32X1D
Yosys 0.7 .. Yosys 0.8
----------------------
diff --git a/COPYING b/COPYING
index a121cdfe9..0839088c3 100644
--- a/COPYING
+++ b/COPYING
@@ -1,4 +1,4 @@
-Copyright (C) 2012 - 2018 Clifford Wolf <clifford@clifford.at>
+Copyright (C) 2012 - 2019 Clifford Wolf <clifford@clifford.at>
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
diff --git a/CodingReadme b/CodingReadme
index b64e79178..8212436e5 100644
--- a/CodingReadme
+++ b/CodingReadme
@@ -390,6 +390,7 @@ Finally run all tests with "make config-{clang,gcc,gcc-4.8}":
Release:
- set YOSYS_VER to x.y.z in Makefile
+ - remove "bumpversion" target from Makefile
- update version string in CHANGELOG
git commit -am "Yosys x.y.z"
diff --git a/Makefile b/Makefile
index 666223076..bd69ce845 100644
--- a/Makefile
+++ b/Makefile
@@ -88,11 +88,13 @@ ifeq ($(OS), Darwin)
PLUGIN_LDFLAGS += -undefined dynamic_lookup
# homebrew search paths
-ifneq ($(shell which brew),)
+ifneq ($(shell :; command -v brew),)
BREW_PREFIX := $(shell brew --prefix)/opt
$(info $$BREW_PREFIX is [${BREW_PREFIX}])
+ifeq ($(ENABLE_PYOSYS),1)
CXXFLAGS += -I$(BREW_PREFIX)/boost/include/boost
LDFLAGS += -L$(BREW_PREFIX)/boost/lib
+endif
CXXFLAGS += -I$(BREW_PREFIX)/readline/include
LDFLAGS += -L$(BREW_PREFIX)/readline/lib
PKG_CONFIG_PATH := $(BREW_PREFIX)/libffi/lib/pkgconfig:$(PKG_CONFIG_PATH)
@@ -100,8 +102,8 @@ PKG_CONFIG_PATH := $(BREW_PREFIX)/tcl-tk/lib/pkgconfig:$(PKG_CONFIG_PATH)
export PATH := $(BREW_PREFIX)/bison/bin:$(BREW_PREFIX)/gettext/bin:$(BREW_PREFIX)/flex/bin:$(PATH)
# macports search paths
-else ifneq ($(shell which port),)
-PORT_PREFIX := $(patsubst %/bin/port,%,$(shell which port))
+else ifneq ($(shell :; command -v port),)
+PORT_PREFIX := $(patsubst %/bin/port,%,$(shell :; command -v port))
CXXFLAGS += -I$(PORT_PREFIX)/include
LDFLAGS += -L$(PORT_PREFIX)/lib
PKG_CONFIG_PATH := $(PORT_PREFIX)/lib/pkgconfig:$(PKG_CONFIG_PATH)
@@ -113,10 +115,13 @@ LDFLAGS += -rdynamic
LDLIBS += -lrt
endif
-YOSYS_VER := 0.8+$(shell cd $(YOSYS_SRC) && test -e .git && { git log --author=clifford@clifford.at --oneline 4d4665b.. 2> /dev/null | wc -l; })
+YOSYS_VER := 0.9+431
GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
OBJS = kernel/version_$(GIT_REV).o
+bumpversion:
+ sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 8a4c6e6.. | wc -l`/;" Makefile
+
# set 'ABCREV = default' to use abc/ as it is
#
# Note: If you do ABC development, make sure that 'abc' in this directory
@@ -704,6 +709,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
+cd tests/opt && bash run-test.sh
+cd tests/aiger && bash run-test.sh $(ABCOPT)
+cd tests/arch && bash run-test.sh
+ +cd tests/ice40 && bash run-test.sh $(SEEDOPT)
@echo ""
@echo " Passed \"make test\"."
@echo ""
diff --git a/README.md b/README.md
index fe30348eb..fdd4bb410 100644
--- a/README.md
+++ b/README.md
@@ -1,7 +1,7 @@
```
yosys -- Yosys Open SYnthesis Suite
-Copyright (C) 2012 - 2018 Clifford Wolf <clifford@clifford.at>
+Copyright (C) 2012 - 2019 Clifford Wolf <clifford@clifford.at>
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
@@ -69,11 +69,14 @@ prerequisites for building yosys:
graphviz xdot pkg-config python3 libboost-system-dev \
libboost-python-dev libboost-filesystem-dev zlib1g-dev
-Similarily, on Mac OS X MacPorts or Homebrew can be used to install dependencies:
+Similarily, on Mac OS X Homebrew can be used to install dependencies:
$ brew tap Homebrew/bundle && brew bundle
+
+or MacPorts:
+
$ sudo port install bison flex readline gawk libffi \
- git graphviz pkgconfig python36 boost zlib
+ git graphviz pkgconfig python36 boost zlib tcl
On FreeBSD use the following command to install all prerequisites:
@@ -327,7 +330,46 @@ Verilog Attributes and non-standard features
- The ``parameter`` and ``localparam`` attributes are used to mark wires
that represent module parameters or localparams (when the HDL front-end
- is run in -pwires mode).
+ is run in ``-pwires`` mode).
+
+- Wires marked with the ``hierconn`` attribute are connected to wires with the
+ same name (format ``cell_name.identifier``) when they are imported from
+ sub-modules by ``flatten``.
+
+- The ``clkbuf_driver`` attribute can be set on an output port of a blackbox
+ module to mark it as a clock buffer output, and thus prevent ``clkbufmap``
+ from inserting another clock buffer on a net driven by such output.
+
+- The ``clkbuf_sink`` attribute can be set on an input port of a module to
+ request clock buffer insertion by the ``clkbufmap`` pass.
+
+- The ``clkbuf_inhibit`` is the default attribute to set on a wire to prevent
+ automatic clock buffer insertion by ``clkbufmap``. This behaviour can be
+ overridden by providing a custom selection to ``clkbufmap``.
+
+- The ``invertible_pin`` attribute can be set on a port to mark it as
+ invertible via a cell parameter. The name of the inversion parameter
+ is specified as the value of this attribute. The value of the inversion
+ parameter must be of the same width as the port, with 1 indicating
+ an inverted bit and 0 indicating a non-inverted bit.
+
+- The ``iopad_external_pin`` attribute on a blackbox module's port marks
+ it as the external-facing pin of an I/O pad, and prevents ``iopadmap``
+ from inserting another pad cell on it.
+
+- The module attribute ``abc_box_id`` specifies a positive integer linking a
+ blackbox or whitebox definition to a corresponding entry in a `abc9`
+ box-file.
+
+- The port attribute ``abc_carry`` marks the carry-in (if an input port) and
+ carry-out (if output port) ports of a box. This information is necessary for
+ `abc9` to preserve the integrity of carry-chains. Specifying this attribute
+ onto a bus port will affect only its most significant bit.
+
+- The port attribute ``abc_arrival`` specifies an integer (for output ports
+ only) to be used as the arrival time of this sequential port. It can be used,
+ for example, to specify the clk-to-Q delay of a flip-flop for consideration
+ during techmapping.
- In addition to the ``(* ... *)`` attribute syntax, Yosys supports
the non-standard ``{* ... *}`` attribute syntax to set default attributes
@@ -405,15 +447,6 @@ Verilog Attributes and non-standard features
blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this
functionality. (By default specify .. endspecify blocks are ignored.)
-- The module attribute ``abc_box_id`` specifies a positive integer linking a
- blackbox or whitebox definition to a corresponding entry in a `abc9`
- box-file.
-
-- The port attribute ``abc_carry`` marks the carry-in (if an input port) and
- carry-out (if output port) ports of a box. This information is necessary for
- `abc9` to preserve the integrity of carry-chains. Specifying this attribute
- onto a bus port will affect only its most significant bit.
-
Non-standard or SystemVerilog features for formal verification
==============================================================
diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc
index 7c851bb91..0798fb35d 100644
--- a/backends/aiger/aiger.cc
+++ b/backends/aiger/aiger.cc
@@ -101,7 +101,7 @@ struct AigerWriter
return a;
}
- AigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
+ AigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode, bool lmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
{
pool<SigBit> undriven_bits;
pool<SigBit> unused_bits;
@@ -367,6 +367,12 @@ struct AigerWriter
aig_latchin.push_back(a);
}
+ if (lmode && aig_l == 0) {
+ aig_m++, aig_l++;
+ aig_latchinit.push_back(0);
+ aig_latchin.push_back(0);
+ }
+
if (!initstate_bits.empty() || !init_inputs.empty())
aig_latchin.push_back(1);
@@ -704,9 +710,9 @@ struct AigerBackend : public Backend {
log(" -vmap <filename>\n");
log(" like -map, but more verbose\n");
log("\n");
- log(" -I, -O, -B\n");
- log(" If the design contains no input/output/assert then create one\n");
- log(" dummy input/output/bad_state pin to make the tools reading the\n");
+ log(" -I, -O, -B, -L\n");
+ log(" If the design contains no input/output/assert/flip-flop then create one\n");
+ log(" dummy input/output/bad_state-pin or latch to make the tools reading the\n");
log(" AIGER file happy.\n");
log("\n");
}
@@ -720,6 +726,7 @@ struct AigerBackend : public Backend {
bool imode = false;
bool omode = false;
bool bmode = false;
+ bool lmode = false;
std::string map_filename;
log_header(design, "Executing AIGER backend.\n");
@@ -764,6 +771,10 @@ struct AigerBackend : public Backend {
bmode = true;
continue;
}
+ if (args[argidx] == "-L") {
+ lmode = true;
+ continue;
+ }
break;
}
extra_args(f, filename, args, argidx);
@@ -773,7 +784,7 @@ struct AigerBackend : public Backend {
if (top_module == nullptr)
log_error("Can't find top module in current design!\n");
- AigerWriter writer(top_module, zinit_mode, imode, omode, bmode);
+ AigerWriter writer(top_module, zinit_mode, imode, omode, bmode, lmode);
writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode);
if (!map_filename.empty()) {
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index d02997da4..cc0857896 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -345,12 +345,12 @@ struct XAigerWriter
}
}
else {
- bool cell_known = inst_module;
+ bool cell_known = inst_module || cell->known();
for (const auto &c : cell->connections()) {
if (c.second.is_fully_const()) continue;
auto port_wire = inst_module ? inst_module->wire(c.first) : nullptr;
- auto is_input = !cell_known || port_wire->port_input;
- auto is_output = !cell_known || port_wire->port_output;
+ auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first);
+ auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first);
if (!is_input && !is_output)
log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
@@ -653,6 +653,11 @@ struct XAigerWriter
aig_outputs.push_back(bit2aig(bit));
}
+ if (output_bits.empty()) {
+ output_bits.insert(State::S0);
+ omode = true;
+ }
+
for (auto bit : output_bits) {
ordered_outputs[bit] = aig_o++;
aig_outputs.push_back(bit2aig(bit));
@@ -749,6 +754,7 @@ struct XAigerWriter
f << "c";
+ log_assert(!output_bits.empty());
auto write_buffer = [](std::stringstream &buffer, int i32) {
int32_t i32_be = to_big_endian(i32);
buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
@@ -1024,6 +1030,8 @@ struct XAigerWriter
f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
output_lines.sort();
+ if (omode)
+ output_lines[State::S0] = "output 0 0 $__dummy__\n";
for (auto &it : output_lines)
f << it.second;
log_assert(output_lines.size() == output_bits.size());
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 7c054d655..4472993d4 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -685,7 +685,7 @@ struct BtorWorker
}
else
{
- int nid_init_val = next_nid++;
+ nid_init_val = next_nid++;
btorf("%d state %d\n", nid_init_val, sid);
for (int i = 0; i < nwords; i++) {
diff --git a/backends/smt2/Makefile.inc b/backends/smt2/Makefile.inc
index 92941d4cf..68394a909 100644
--- a/backends/smt2/Makefile.inc
+++ b/backends/smt2/Makefile.inc
@@ -16,7 +16,7 @@ yosys-smtbmc-script.py: backends/smt2/smtbmc.py
-e "s|#!/usr/bin/env python3|#!$(PYTHON)|" < $< > $@
yosys-smtbmc.exe: misc/launcher.c yosys-smtbmc-script.py
- $(P) gcc -DGUI=0 -O -s -o $@ $<
+ $(P) $(CXX) -DGUI=0 -O -s -o $@ $<
# Other targets
else
TARGETS += yosys-smtbmc
diff --git a/examples/mimas2/run_yosys.ys b/examples/mimas2/run_yosys.ys
index b3204b1ca..b48877811 100644
--- a/examples/mimas2/run_yosys.ys
+++ b/examples/mimas2/run_yosys.ys
@@ -1,4 +1,3 @@
read_verilog example.v
-synth_xilinx -top example -family xc6s
-iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I
+synth_xilinx -top example -family xc6s -ise
write_edif -pvector bra example.edif
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 82283fb5b..21279cbfa 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -158,6 +158,11 @@ std::string AST::type2str(AstNodeType type)
X(AST_POSEDGE)
X(AST_NEGEDGE)
X(AST_EDGE)
+ X(AST_INTERFACE)
+ X(AST_INTERFACEPORT)
+ X(AST_INTERFACEPORTTYPE)
+ X(AST_MODPORT)
+ X(AST_MODPORTMEMBER)
X(AST_PACKAGE)
#undef X
default:
@@ -1099,6 +1104,13 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
ignoreThisSignalsInInitial = RTLIL::SigSpec();
}
+ else {
+ for (auto &attr : ast->attributes) {
+ if (attr.second->type != AST_CONSTANT)
+ continue;
+ current_module->attributes[attr.first] = attr.second->asAttrConst();
+ }
+ }
if (ast->type == AST_INTERFACE)
current_module->set_bool_attribute("\\is_interface");
@@ -1284,6 +1296,8 @@ void AST::explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule
// from AST. The interface members are copied into the AST module with the prefix of the interface.
void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module*> local_interfaces)
{
+ loadconfig();
+
bool is_top = false;
AstNode *new_ast = ast->clone();
for (auto &intf : local_interfaces) {
@@ -1467,24 +1481,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString
stripped_name = stripped_name.substr(9);
log_header(design, "Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str());
-
- current_ast = NULL;
- flag_dump_ast1 = false;
- flag_dump_ast2 = false;
- flag_dump_vlog1 = false;
- flag_dump_vlog2 = false;
- flag_nolatches = nolatches;
- flag_nomeminit = nomeminit;
- flag_nomem2reg = nomem2reg;
- flag_mem2reg = mem2reg;
- flag_noblackbox = noblackbox;
- flag_lib = lib;
- flag_nowb = nowb;
- flag_noopt = noopt;
- flag_icells = icells;
- flag_pwires = pwires;
- flag_autowire = autowire;
- use_internal_line_num();
+ loadconfig();
std::string para_info;
AstNode *new_ast = ast->clone();
@@ -1565,6 +1562,27 @@ RTLIL::Module *AstModule::clone() const
return new_mod;
}
+void AstModule::loadconfig() const
+{
+ current_ast = NULL;
+ flag_dump_ast1 = false;
+ flag_dump_ast2 = false;
+ flag_dump_vlog1 = false;
+ flag_dump_vlog2 = false;
+ flag_nolatches = nolatches;
+ flag_nomeminit = nomeminit;
+ flag_nomem2reg = nomem2reg;
+ flag_mem2reg = mem2reg;
+ flag_noblackbox = noblackbox;
+ flag_lib = lib;
+ flag_nowb = nowb;
+ flag_noopt = noopt;
+ flag_icells = icells;
+ flag_pwires = pwires;
+ flag_autowire = autowire;
+ use_internal_line_num();
+}
+
// internal dummy line number callbacks
namespace {
int internal_line_num;
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 54b2fb319..93fee913e 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -299,6 +299,7 @@ namespace AST
std::string derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out, bool mayfail);
void reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces) YS_OVERRIDE;
RTLIL::Module *clone() const YS_OVERRIDE;
+ void loadconfig() const;
};
// this must be set by the language frontend before parsing the sources
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 54b9efaad..b1ee22f42 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -150,6 +150,11 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
reg->str = stringf("%s[%d]", node->str.c_str(), i);
reg->is_reg = true;
reg->is_signed = node->is_signed;
+ for (auto &it : node->attributes)
+ if (it.first != ID(mem2reg))
+ reg->attributes.emplace(it.first, it.second->clone());
+ reg->filename = node->filename;
+ reg->linenum = node->linenum;
children.push_back(reg);
while (reg->simplify(true, false, false, 1, -1, false, false)) { }
}
@@ -1525,10 +1530,16 @@ skip_dynamic_range_lvalue_expansion:;
current_scope[wire_en->str] = wire_en;
while (wire_en->simplify(true, false, false, 1, -1, false, false)) { }
- std::vector<RTLIL::State> x_bit;
- x_bit.push_back(RTLIL::State::Sx);
+ AstNode *check_defval;
+ if (type == AST_LIVE || type == AST_FAIR) {
+ check_defval = new AstNode(AST_REDUCE_BOOL, children[0]->clone());
+ } else {
+ std::vector<RTLIL::State> x_bit;
+ x_bit.push_back(RTLIL::State::Sx);
+ check_defval = mkconst_bits(x_bit, false);
+ }
- AstNode *assign_check = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bit, false));
+ AstNode *assign_check = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), check_defval);
assign_check->children[0]->str = id_check;
assign_check->children[0]->was_checked = true;
@@ -1541,9 +1552,13 @@ skip_dynamic_range_lvalue_expansion:;
default_signals->children.push_back(assign_en);
current_top_block->children.insert(current_top_block->children.begin(), default_signals);
- assign_check = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), new AstNode(AST_REDUCE_BOOL, children[0]->clone()));
- assign_check->children[0]->str = id_check;
- assign_check->children[0]->was_checked = true;
+ if (type == AST_LIVE || type == AST_FAIR) {
+ assign_check = nullptr;
+ } else {
+ assign_check = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), new AstNode(AST_REDUCE_BOOL, children[0]->clone()));
+ assign_check->children[0]->str = id_check;
+ assign_check->children[0]->was_checked = true;
+ }
if (current_always == nullptr || current_always->type != AST_INITIAL) {
assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(1, false, 1));
@@ -1555,7 +1570,8 @@ skip_dynamic_range_lvalue_expansion:;
assign_en->children[0]->was_checked = true;
newNode = new AstNode(AST_BLOCK);
- newNode->children.push_back(assign_check);
+ if (assign_check != nullptr)
+ newNode->children.push_back(assign_check);
newNode->children.push_back(assign_en);
AstNode *assertnode = new AstNode(type);
@@ -2879,8 +2895,15 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m
void AstNode::expand_genblock(std::string index_var, std::string prefix, std::map<std::string, std::string> &name_map)
{
if (!index_var.empty() && type == AST_IDENTIFIER && str == index_var) {
- current_scope[index_var]->children[0]->cloneInto(this);
- return;
+ if (children.empty()) {
+ current_scope[index_var]->children[0]->cloneInto(this);
+ } else {
+ AstNode *p = new AstNode(AST_LOCALPARAM, current_scope[index_var]->children[0]->clone());
+ p->str = stringf("$genval$%d", autoidx++);
+ current_ast_mod->children.push_back(p);
+ str = p->str;
+ id2ast = p;
+ }
}
if ((type == AST_IDENTIFIER || type == AST_FCALL || type == AST_TCALL) && name_map.count(str) > 0)
diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc
index 4bf5b1cf5..49281f7e7 100644
--- a/frontends/verilog/const2ast.cc
+++ b/frontends/verilog/const2ast.cc
@@ -85,10 +85,8 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
digits.push_back(10 + *str - 'A');
else if (*str == 'x' || *str == 'X')
digits.push_back(0xf0);
- else if (*str == 'z' || *str == 'Z')
+ else if (*str == 'z' || *str == 'Z' || *str == '?')
digits.push_back(0xf1);
- else if (*str == '?')
- digits.push_back(0xf2);
str++;
}
@@ -112,8 +110,6 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
data.push_back(case_type == 'x' ? RTLIL::Sa : RTLIL::Sx);
else if (*it == 0xf1)
data.push_back(case_type == 'x' || case_type == 'z' ? RTLIL::Sa : RTLIL::Sz);
- else if (*it == 0xf2)
- data.push_back(RTLIL::Sa);
else
data.push_back((*it & bitmask) ? State::S1 : State::S0);
}
@@ -199,13 +195,13 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn
if (str == endptr)
len_in_bits = -1;
- // The "<bits>'s?[bodhBODH]<digits>" syntax
+ // The "<bits>'[sS]?[bodhBODH]<digits>" syntax
if (*endptr == '\'')
{
std::vector<RTLIL::State> data;
bool is_signed = false;
bool is_unsized = len_in_bits < 0;
- if (*(endptr+1) == 's') {
+ if (*(endptr+1) == 's' || *(endptr+1) == 'S') {
is_signed = true;
endptr++;
}
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 57e55b1f4..4acfb414d 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -239,7 +239,7 @@ YOSYS_NAMESPACE_END
return TOK_CONSTVAL;
}
-[0-9]*[ \t]*\'s?[bodhBODH]*[ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
+[0-9]*[ \t]*\'[sS]?[bodhBODH]?[ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
frontend_verilog_yylval.string = new std::string(yytext);
return TOK_CONSTVAL;
}
diff --git a/kernel/register.cc b/kernel/register.cc
index 1fd1bad1d..8131fa279 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -48,7 +48,7 @@ using zlib to write gzip-compressed data every time the stream is flushed.
*/
class gzip_ostream : public std::ostream {
public:
- gzip_ostream()
+ gzip_ostream() : std::ostream(nullptr)
{
rdbuf(&outbuf);
}
@@ -71,7 +71,7 @@ private:
str("");
return 0;
}
- ~gzip_streambuf()
+ virtual ~gzip_streambuf()
{
sync();
gzclose(gzf);
@@ -498,7 +498,15 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector<s
if (f != NULL) {
// Check for gzip magic
unsigned char magic[3];
- int n = readsome(*ff, reinterpret_cast<char*>(magic), 3);
+ int n = 0;
+ while (n < 3)
+ {
+ int c = ff->get();
+ if (c != EOF) {
+ magic[n] = (unsigned char) c;
+ }
+ n++;
+ }
if (n == 3 && magic[0] == 0x1f && magic[1] == 0x8b) {
#ifdef YOSYS_ENABLE_ZLIB
log("Found gzip magic in file `%s', decompressing using zlib.\n", filename.c_str());
diff --git a/kernel/sigtools.h b/kernel/sigtools.h
index 4e97bb775..2517d6de3 100644
--- a/kernel/sigtools.h
+++ b/kernel/sigtools.h
@@ -135,9 +135,11 @@ struct SigPool
}
};
-template <typename T, class Compare = std::less<T>>
+template <typename T, class Compare = void>
struct SigSet
{
+ static_assert(!std::is_same<Compare,void>::value, "Default value for `Compare' class not found for SigSet<T>. Please specify.");
+
struct bitDef_t : public std::pair<RTLIL::Wire*, int> {
bitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }
bitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }
@@ -220,6 +222,13 @@ struct SigSet
}
};
+template<typename T>
+class SigSet<T, typename std::enable_if<!std::is_pointer<T>::value>::type> : public SigSet<T, std::less<T>> {};
+template<typename T>
+using sort_by_name_id_guard = typename std::enable_if<std::is_same<T,RTLIL::Cell*>::value>::type;
+template<typename T>
+class SigSet<T, sort_by_name_id_guard<T>> : public SigSet<T, RTLIL::sort_by_name_id<typename std::remove_pointer<T>::type>> {};
+
struct SigMap
{
mfp<SigBit> database;
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 747f2d739..5018a4888 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -129,7 +129,7 @@ void yosys_banner()
log(" | |\n");
log(" | yosys -- Yosys Open SYnthesis Suite |\n");
log(" | |\n");
- log(" | Copyright (C) 2012 - 2018 Clifford Wolf <clifford@clifford.at> |\n");
+ log(" | Copyright (C) 2012 - 2019 Clifford Wolf <clifford@clifford.at> |\n");
log(" | |\n");
log(" | Permission to use, copy, modify, and/or distribute this software for any |\n");
log(" | purpose with or without fee is hereby granted, provided that the above |\n");
diff --git a/misc/launcher.c b/misc/launcher.c
index e0d8208f1..49d6414e7 100644
--- a/misc/launcher.c
+++ b/misc/launcher.c
@@ -65,7 +65,7 @@ SOFTWARE. */
int child_pid=0;
-int fail(char *format, char *data) {
+int fail(const char *format, const char *data) {
/* Print error message to stderr and return 2 */
fprintf(stderr, format, data);
return 2;
@@ -76,7 +76,7 @@ char *quoted(char *data) {
/* We allocate twice as much space as needed to deal with worse-case
of having to escape everything. */
- char *result = calloc(ln*2+3, sizeof(char));
+ char *result = (char *)calloc(ln*2+3, sizeof(char));
char *presult = result;
*presult++ = '"';
@@ -120,7 +120,7 @@ char *loadable_exe(char *exename) {
if (!hPython) return NULL; */
/* Return the absolute filename for spawnv */
- result = calloc(MAX_PATH, sizeof(char));
+ result = (char *)calloc(MAX_PATH, sizeof(char));
strncpy(result, exename, MAX_PATH);
/*if (result) GetModuleFileNameA(hPython, result, MAX_PATH);
@@ -158,7 +158,7 @@ char **parse_argv(char *cmdline, int *argc)
{
/* Parse a command line in-place using MS C rules */
- char **result = calloc(strlen(cmdline), sizeof(char *));
+ char **result = (char **)calloc(strlen(cmdline), sizeof(char *));
char *output = cmdline;
char c;
int nb = 0;
diff --git a/misc/py_wrap_generator.py b/misc/py_wrap_generator.py
index 66d661fa1..2bf364470 100644
--- a/misc/py_wrap_generator.py
+++ b/misc/py_wrap_generator.py
@@ -508,23 +508,17 @@ class TupleTranslator(PythonDictTranslator):
#Generate c++ code to translate to a boost::python::tuple
@classmethod
def translate_cpp(c, varname, types, prefix, ref):
- text = prefix + TupleTranslator.typename + " " + varname + "___tmp = boost::python::make_tuple(" + varname + ".first, " + varname + ".second);"
- return text
- tmp_name = "tmp_" + str(Translator.tmp_cntr)
- Translator.tmp_cntr = Translator.tmp_cntr + 1
- if ref:
- text += prefix + "for(auto " + tmp_name + " : *" + varname + ")"
+ # if the tuple is a pair of SigSpecs (aka SigSig), then we need
+ # to call get_py_obj() on each item in the tuple
+ if types[0].name in classnames:
+ first_var = types[0].name + "::get_py_obj(" + varname + ".first)"
else:
- text += prefix + "for(auto " + tmp_name + " : " + varname + ")"
- text += prefix + "{"
- if types[0].name.split(" ")[-1] in primitive_types or types[0].name in enum_names:
- text += prefix + "\t" + varname + "___tmp.append(" + tmp_name + ");"
- elif types[0].name in known_containers:
- text += known_containers[types[0].name].translate_cpp(tmp_name, types[0].cont.args, prefix + "\t", types[1].attr_type == attr_types.star)
- text += prefix + "\t" + varname + "___tmp.append(" + types[0].name + "::get_py_obj(" + tmp_name + "___tmp);"
- elif types[0].name in classnames:
- text += prefix + "\t" + varname + "___tmp.append(" + types[0].name + "::get_py_obj(" + tmp_name + "));"
- text += prefix + "}"
+ first_var = varname + ".first"
+ if types[1].name in classnames:
+ second_var = types[1].name + "::get_py_obj(" + varname + ".second)"
+ else:
+ second_var = varname + ".second"
+ text = prefix + TupleTranslator.typename + " " + varname + "___tmp = boost::python::make_tuple(" + first_var + ", " + second_var + ");"
return text
#Associate the Translators with their c++ type
diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index c8067a8be..cf9663d1d 100644
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -25,6 +25,7 @@ OBJS += passes/cmds/plugin.o
OBJS += passes/cmds/check.o
OBJS += passes/cmds/qwp.o
OBJS += passes/cmds/edgetypes.o
+OBJS += passes/cmds/portlist.o
OBJS += passes/cmds/chformal.o
OBJS += passes/cmds/chtype.o
OBJS += passes/cmds/blackbox.o
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc
index af6f7043d..dd05ac81f 100644
--- a/passes/cmds/add.cc
+++ b/passes/cmds/add.cc
@@ -105,6 +105,11 @@ struct AddPass : public Pass {
log("Like 'add -input', but also connect the signal between instances of the\n");
log("selected modules.\n");
log("\n");
+ log("\n");
+ log(" add -mod <name[s]>\n");
+ log("\n");
+ log("Add module[s] with the specified name[s].\n");
+ log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
@@ -113,6 +118,7 @@ struct AddPass : public Pass {
bool arg_flag_input = false;
bool arg_flag_output = false;
bool arg_flag_global = false;
+ bool mod_mode = false;
int arg_width = 0;
size_t argidx;
@@ -133,8 +139,20 @@ struct AddPass : public Pass {
arg_width = atoi(args[++argidx].c_str());
continue;
}
+ if (arg == "-mod") {
+ mod_mode = true;
+ argidx++;
+ break;
+ }
break;
}
+
+ if (mod_mode) {
+ for (; argidx < args.size(); argidx++)
+ design->addModule(RTLIL::escape_id(args[argidx]));
+ return;
+ }
+
extra_args(args, argidx, design);
for (auto &mod : design->modules_)
diff --git a/passes/cmds/portlist.cc b/passes/cmds/portlist.cc
new file mode 100644
index 000000000..38c4a8597
--- /dev/null
+++ b/passes/cmds/portlist.cc
@@ -0,0 +1,93 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct PortlistPass : public Pass {
+ PortlistPass() : Pass("portlist", "list (top-level) ports") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" portlist [options] [selection]\n");
+ log("\n");
+ log("This command lists all module ports found in the selected modules.\n");
+ log("\n");
+ log("If no selection is provided then it lists the ports on the top module.\n");
+ log("\n");
+ log(" -m\n");
+ log(" print verilog blackbox module definitions instead of port lists\n");
+ log("\n");
+ }
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ bool m_mode = false;
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++) {
+ if (args[argidx] == "-m") {
+ m_mode = true;
+ continue;
+ }
+ break;
+ }
+
+ bool first_module = true;
+
+ auto handle_module = [&](RTLIL::Module *module) {
+ vector<string> ports;
+ if (first_module)
+ first_module = false;
+ else
+ log("\n");
+ for (auto port : module->ports) {
+ auto *w = module->wire(port);
+ ports.push_back(stringf("%s [%d:%d] %s", w->port_input ? w->port_output ? "inout" : "input" : "output",
+ w->upto ? w->start_offset : w->start_offset + w->width - 1,
+ w->upto ? w->start_offset + w->width - 1 : w->start_offset,
+ log_id(w)));
+ }
+ log("module %s%s\n", log_id(module), m_mode ? " (" : "");
+ for (int i = 0; i < GetSize(ports); i++)
+ log("%s%s\n", ports[i].c_str(), m_mode && i+1 < GetSize(ports) ? "," : "");
+ if (m_mode)
+ log(");\nendmodule\n");
+ };
+
+ if (argidx == args.size())
+ {
+ auto *top = design->top_module();
+ if (top == nullptr)
+ log_cmd_error("Can't find top module in current design!\n");
+ handle_module(top);
+ }
+ else
+ {
+ extra_args(args, argidx, design);
+ for (auto module : design->selected_modules())
+ handle_module(module);
+ }
+ }
+} PortlistPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index 59d10a1b8..0f1f05ccb 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -664,7 +664,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
} else
if (arg == "%D") {
if (work_stack.size() < 2)
- log_cmd_error("Must have at least two elements on the stack for operator %%d.\n");
+ log_cmd_error("Must have at least two elements on the stack for operator %%D.\n");
select_op_diff(design, work_stack[work_stack.size()-1], work_stack[work_stack.size()-2]);
work_stack[work_stack.size()-2] = work_stack[work_stack.size()-1];
work_stack.pop_back();
@@ -693,7 +693,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
} else
if (arg == "%C") {
if (work_stack.size() < 1)
- log_cmd_error("Must have at least one element on the stack for operator %%M.\n");
+ log_cmd_error("Must have at least one element on the stack for operator %%C.\n");
select_op_module_to_cells(design, work_stack[work_stack.size()-1]);
} else
if (arg == "%c") {
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index 2e9fc72af..a3e969ef1 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -26,6 +26,10 @@
# include <dirent.h>
#endif
+#ifdef __APPLE__
+# include <unistd.h>
+#endif
+
#ifdef YOSYS_ENABLE_READLINE
# include <readline/readline.h>
#endif
@@ -866,7 +870,11 @@ struct ShowPass : public Pass {
log_cmd_error("Shell command failed!\n");
} else
if (format.empty()) {
+ #ifdef __APPLE__
+ std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' &", getuid(), dot_file.c_str(), dot_file.c_str());
+ #else
std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid'; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' &", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str());
+ #endif
log("Exec: %s\n", cmd.c_str());
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index dbd8682e6..4855ce29e 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -532,10 +532,10 @@ struct EquivMakePass : public Pass {
log_cmd_error("Equiv module %s already exists.\n", args[argidx+2].c_str());
if (worker.gold_mod->has_memories() || worker.gold_mod->has_processes())
- log_cmd_error("Gold module contains memories or procresses. Run 'memory' or 'proc' respectively.\n");
+ log_cmd_error("Gold module contains memories or processes. Run 'memory' or 'proc' respectively.\n");
if (worker.gate_mod->has_memories() || worker.gate_mod->has_processes())
- log_cmd_error("Gate module contains memories or procresses. Run 'memory' or 'proc' respectively.\n");
+ log_cmd_error("Gate module contains memories or processes. Run 'memory' or 'proc' respectively.\n");
worker.read_blacklists();
worker.read_encfiles();
diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc
index 19d1c25ac..d4c7f7953 100644
--- a/passes/equiv/equiv_opt.cc
+++ b/passes/equiv/equiv_opt.cc
@@ -46,6 +46,9 @@ struct EquivOptPass:public ScriptPass
log(" -assert\n");
log(" produce an error if the circuits are not equivalent.\n");
log("\n");
+ log(" -multiclock\n");
+ log(" run clk2fflogic before equivalence checking.\n");
+ log("\n");
log(" -undef\n");
log(" enable modelling of undef states during equiv_induct.\n");
log("\n");
@@ -55,7 +58,7 @@ struct EquivOptPass:public ScriptPass
}
std::string command, techmap_opts;
- bool assert, undef;
+ bool assert, undef, multiclock;
void clear_flags() YS_OVERRIDE
{
@@ -63,6 +66,7 @@ struct EquivOptPass:public ScriptPass
techmap_opts = "";
assert = false;
undef = false;
+ multiclock = false;
}
void execute(std::vector < std::string > args, RTLIL::Design * design) YS_OVERRIDE
@@ -92,6 +96,10 @@ struct EquivOptPass:public ScriptPass
undef = true;
continue;
}
+ if (args[argidx] == "-multiclock") {
+ multiclock = true;
+ continue;
+ }
break;
}
@@ -146,6 +154,8 @@ struct EquivOptPass:public ScriptPass
}
if (check_label("prove")) {
+ if (multiclock || help_mode)
+ run("clk2fflogic", "(only with -multiclock)");
run("equiv_make gold gate equiv");
if (help_mode)
run("equiv_induct [-undef] equiv");
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index fd95b94b2..d8a628448 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -808,6 +808,30 @@ struct HierarchyPass : public Pass {
if (mod_it.second->get_bool_attribute("\\top"))
top_mod = mod_it.second;
+ if (top_mod != nullptr && top_mod->name.begins_with("$abstract")) {
+ IdString top_name = top_mod->name.substr(strlen("$abstract"));
+
+ dict<RTLIL::IdString, RTLIL::Const> top_parameters;
+ for (auto ¶ : parameters) {
+ SigSpec sig_value;
+ if (!RTLIL::SigSpec::parse(sig_value, NULL, para.second))
+ log_cmd_error("Can't decode value '%s'!\n", para.second.c_str());
+ top_parameters[RTLIL::escape_id(para.first)] = sig_value.as_const();
+ }
+
+ top_mod = design->module(top_mod->derive(design, top_parameters));
+
+ if (top_mod != nullptr && top_mod->name != top_name) {
+ Module *m = top_mod->clone();
+ m->name = top_name;
+ Module *old_mod = design->module(top_name);
+ if (old_mod)
+ design->remove(old_mod);
+ design->add(m);
+ top_mod = m;
+ }
+ }
+
if (top_mod == nullptr && auto_top_mode) {
log_header(design, "Finding top of design hierarchy..\n");
dict<Module*, int> db;
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 858b3560c..6cf66fb95 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -369,7 +369,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
for (auto cell : module->cells())
if (design->selected(module, cell) && cell->type[0] == '$') {
if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) &&
- cell->getPort(ID::A).size() == 1 && cell->getPort(ID::Y).size() == 1)
+ GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1)
invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID::A));
if (cell->type.in(ID($mux), ID($_MUX_)) &&
cell->getPort(ID::A) == SigSpec(State::S1) && cell->getPort(ID::B) == SigSpec(State::S0))
@@ -740,12 +740,34 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (cell->type.in(ID($reduce_xor), ID($reduce_xnor), ID($lt), ID($le), ID($ge), ID($gt)))
replace_cell(assign_map, module, cell, "x-bit in input", ID::Y, RTLIL::State::Sx);
else
- replace_cell(assign_map, module, cell, "x-bit in input", ID::Y, RTLIL::SigSpec(RTLIL::State::Sx, cell->getPort(ID::Y).size()));
+ replace_cell(assign_map, module, cell, "x-bit in input", ID::Y, RTLIL::SigSpec(RTLIL::State::Sx, GetSize(cell->getPort(ID::Y))));
goto next_cell;
}
}
- if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) && cell->getPort(ID::Y).size() == 1 &&
+ if (cell->type.in(ID($shiftx), ID($shift))) {
+ SigSpec sig_a = assign_map(cell->getPort(ID::A));
+ int width;
+ bool trim_x = cell->type == ID($shiftx) || !keepdc;
+ bool trim_0 = cell->type == ID($shift);
+ for (width = GetSize(sig_a); width > 1; width--) {
+ if ((trim_x && sig_a[width-1] == State::Sx) ||
+ (trim_0 && sig_a[width-1] == State::S0))
+ continue;
+ break;
+ }
+
+ if (width < GetSize(sig_a)) {
+ cover_list("opt.opt_expr.trim", "$shiftx", "$shift", cell->type.str());
+ sig_a.remove(width, GetSize(sig_a)-width);
+ cell->setPort(ID::A, sig_a);
+ cell->setParam(ID(A_WIDTH), width);
+ did_something = true;
+ goto next_cell;
+ }
+ }
+
+ if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) && GetSize(cell->getPort(ID::Y)) == 1 &&
invert_map.count(assign_map(cell->getPort(ID::A))) != 0) {
cover_list("opt.opt_expr.invert.double", "$_NOT_", "$not", "$logic_not", cell->type.str());
replace_cell(assign_map, module, cell, "double_invert", ID::Y, invert_map.at(assign_map(cell->getPort(ID::A))));
@@ -931,6 +953,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
if (b.is_fully_const()) {
+ if (b.is_fully_undef()) {
+ RTLIL::SigSpec input = b;
+ ACTION_DO(ID::Y, Const(State::Sx, GetSize(cell->getPort(ID::Y))));
+ } else
if (b.as_bool() == (cell->type == ID($eq))) {
RTLIL::SigSpec input = b;
ACTION_DO(ID::Y, cell->getPort(ID::A));
@@ -1142,7 +1168,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (mux_undef && cell->type.in(ID($mux), ID($pmux))) {
RTLIL::SigSpec new_a, new_b, new_s;
- int width = cell->getPort(ID::A).size();
+ int width = GetSize(cell->getPort(ID::A));
if ((cell->getPort(ID::A).is_fully_undef() && cell->getPort(ID::B).is_fully_undef()) ||
cell->getPort(ID(S)).is_fully_undef()) {
cover_list("opt.opt_expr.mux_undef", "$mux", "$pmux", cell->type.str());
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index c53fb3113..2c456705c 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -108,12 +108,13 @@ bool cell_supported(RTLIL::Cell *cell)
return false;
}
-std::map<IdString, IdString> mergeable_type_map{
- {ID($sub), ID($add)},
-};
+std::map<IdString, IdString> mergeable_type_map;
bool mergeable(RTLIL::Cell *a, RTLIL::Cell *b)
{
+ if (mergeable_type_map.empty()) {
+ mergeable_type_map.insert({ID($sub), ID($add)});
+ }
auto a_type = a->type;
if (mergeable_type_map.count(a_type))
a_type = mergeable_type_map.at(a_type);
diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc
index 790811d4c..98691d0fe 100644
--- a/passes/pmgen/Makefile.inc
+++ b/passes/pmgen/Makefile.inc
@@ -4,7 +4,7 @@
# --------------------------------------
OBJS += passes/pmgen/test_pmgen.o
-passes/pmgen/test_pmgen.o: passes/pmgen/test_pmgen_pm.h
+passes/pmgen/test_pmgen.o: passes/pmgen/test_pmgen_pm.h passes/pmgen/ice40_dsp_pm.h passes/pmgen/peepopt_pm.h passes/pmgen/xilinx_srl_pm.h
$(eval $(call add_extra_objs,passes/pmgen/test_pmgen_pm.h))
# --------------------------------------
@@ -17,7 +17,7 @@ $(eval $(call add_extra_objs,passes/pmgen/ice40_dsp_pm.h))
OBJS += passes/pmgen/ice40_wrapcarry.o
passes/pmgen/ice40_wrapcarry.o: passes/pmgen/ice40_wrapcarry_pm.h
-$(eval $(call add_extra_objs,passes/pmgen/test_pmgen_pm.h))
+$(eval $(call add_extra_objs,passes/pmgen/ice40_wrapcarry_pm.h))
# --------------------------------------
@@ -27,6 +27,13 @@ $(eval $(call add_extra_objs,passes/pmgen/peepopt_pm.h))
PEEPOPT_PATTERN = passes/pmgen/peepopt_shiftmul.pmg
PEEPOPT_PATTERN += passes/pmgen/peepopt_muldiv.pmg
+PEEPOPT_PATTERN += passes/pmgen/peepopt_dffmux.pmg
passes/pmgen/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
$(P) mkdir -p passes/pmgen && python3 $< -o $@ -p peepopt $(filter-out $<,$^)
+
+# --------------------------------------
+
+OBJS += passes/pmgen/xilinx_srl.o
+passes/pmgen/xilinx_srl.o: passes/pmgen/xilinx_srl_pm.h
+$(eval $(call add_extra_objs,passes/pmgen/xilinx_srl_pm.h))
diff --git a/passes/pmgen/README.md b/passes/pmgen/README.md
index 5f6a8ab1b..2f5b8d0b2 100644
--- a/passes/pmgen/README.md
+++ b/passes/pmgen/README.md
@@ -178,6 +178,45 @@ evaluates to `false`.
The `semioptional` statement marks matches that must match if at least one
matching cell exists, but if no matching cell exists it is set to `nullptr`.
+Slices and choices
+------------------
+
+Cell matches can contain "slices" and "choices". Slices can be used to
+create matches for different sections of a cell. For example:
+
+ state <int> pmux_slice
+
+ match pmux
+ select pmux->type == $pmux
+ slice idx GetSize(port(pmux, \S))
+ index <SigBit> port(pmux, \S)[idx] === port(eq, \Y)
+ set pmux_slice idx
+ endmatch
+
+The first argument to `slice` is the local variable name used to identify the
+slice. The second argument is the number of slices that should be created for
+this cell. The `set` statement can be used to copy that index into a state
+variable so that later matches and/or code blocks can refer to it.
+
+A similar mechanism is "choices", where a list of options is given as
+second argument, and the matcher will iterate over those options:
+
+ state <SigSpec> foo bar
+ state <IdString> eq_ab eq_ba
+
+ match eq
+ select eq->type == $eq
+ choice <IdString> AB {\A, \B}
+ define <IdString> BA (AB == \A ? \B : \A)
+ index <SigSpec> port(eq, AB) === foo
+ index <SigSpec> port(eq, BA) === bar
+ set eq_ab AB
+ set eq_ba BA
+ generate
+
+Notice how `define` can be used to define additional local variables similar
+to the loop variables defined by `slice` and `choice`.
+
Additional code
---------------
@@ -313,7 +352,7 @@ state variables used to pass arguments.
subpattern tail
...
-Subpatterns cann be called recursively.
+Subpatterns can be called recursively.
If a `subpattern` statement is preceded by a `fallthrough` statement, this is
equivalent to calling the subpattern at the end of the preceding block.
@@ -326,7 +365,7 @@ test-case generation. For example:
match mul
...
- generate 10
+ generate 10 0
SigSpec Y = port(ff, \D);
SigSpec A = module->addWire(NEW_ID, GetSize(Y) - rng(GetSize(Y)/2));
SigSpec B = module->addWire(NEW_ID, GetSize(Y) - rng(GetSize(Y)/2));
@@ -335,8 +374,11 @@ test-case generation. For example:
The expression `rng(n)` returns a non-negative integer less than `n`.
-The argument to `generate` is the chance of this generate block being executed
-when the match block did not match anything, in percent.
+The first argument to `generate` is the chance of this generate block being
+executed when the match block did not match anything, in percent.
+
+The second argument to `generate` is the chance of this generate block being
+executed when the match block did match something, in percent.
The special statement `finish` can be used within generate blocks to terminate
the current pattern matcher run.
diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 39d033a04..16bfe537f 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -64,11 +64,6 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
bool mul_signed = st.mul->getParam("\\A_SIGNED").as_bool();
- if (mul_signed) {
- log(" inference of signed iCE40 DSP arithmetic is currently not supported.\n");
- return;
- }
-
log(" replacing $mul with SB_MAC16 cell.\n");
Cell *cell = pm.module->addCell(NEW_ID, "\\SB_MAC16");
diff --git a/passes/pmgen/peepopt.cc b/passes/pmgen/peepopt.cc
index e7f95cf85..72b02127a 100644
--- a/passes/pmgen/peepopt.cc
+++ b/passes/pmgen/peepopt.cc
@@ -60,6 +60,7 @@ struct PeepoptPass : public Pass {
peepopt_pm pm(module, module->selected_cells());
pm.run_shiftmul();
pm.run_muldiv();
+ pm.run_dffmux();
}
}
}
diff --git a/passes/pmgen/peepopt_dffmux.pmg b/passes/pmgen/peepopt_dffmux.pmg
new file mode 100644
index 000000000..c88a52226
--- /dev/null
+++ b/passes/pmgen/peepopt_dffmux.pmg
@@ -0,0 +1,113 @@
+pattern dffmux
+
+state <IdString> cemuxAB rstmuxBA
+state <SigSpec> sigD
+
+match dff
+ select dff->type == $dff
+ select GetSize(port(dff, \D)) > 1
+endmatch
+
+match rstmux
+ select rstmux->type == $mux
+ select GetSize(port(rstmux, \Y)) > 1
+ index <SigSpec> port(rstmux, \Y) === port(dff, \D)
+ choice <IdString> BA {\B, \A}
+ select port(rstmux, BA).is_fully_const()
+ set rstmuxBA BA
+ optional
+endmatch
+
+code sigD
+ if (rstmux)
+ sigD = port(rstmux, rstmuxBA == \B ? \A : \B);
+ else
+ sigD = port(dff, \D);
+endcode
+
+match cemux
+ select cemux->type == $mux
+ select GetSize(port(cemux, \Y)) > 1
+ index <SigSpec> port(cemux, \Y) === sigD
+ choice <IdString> AB {\A, \B}
+ index <SigSpec> port(cemux, AB) === port(dff, \Q)
+ set cemuxAB AB
+endmatch
+
+code
+ SigSpec D = port(cemux, cemuxAB == \A ? \B : \A);
+ SigSpec Q = port(dff, \Q);
+ Const rst;
+ if (rstmux)
+ rst = port(rstmux, rstmuxBA).as_const();
+ int width = GetSize(D);
+
+ SigSpec &ceA = cemux->connections_.at(\A);
+ SigSpec &ceB = cemux->connections_.at(\B);
+ SigSpec &ceY = cemux->connections_.at(\Y);
+ SigSpec &dffD = dff->connections_.at(\D);
+ SigSpec &dffQ = dff->connections_.at(\Q);
+
+ if (D[width-1] == D[width-2]) {
+ did_something = true;
+
+ SigBit sign = D[width-1];
+ bool is_signed = sign.wire;
+ int i;
+ for (i = width-1; i >= 2; i--) {
+ if (!is_signed) {
+ module->connect(Q[i], sign);
+ if (D[i-1] != sign || (rst.size() && rst[i-1] != rst[width-1]))
+ break;
+ }
+ else {
+ module->connect(Q[i], Q[i-1]);
+ if (D[i-2] != sign || (rst.size() && rst[i-1] != rst[width-1]))
+ break;
+ }
+ }
+
+ ceA.remove(i, width-i);
+ ceB.remove(i, width-i);
+ ceY.remove(i, width-i);
+ cemux->fixup_parameters();
+ dffD.remove(i, width-i);
+ dffQ.remove(i, width-i);
+ dff->fixup_parameters();
+
+ log("dffcemux pattern in %s: dff=%s, cemux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux), width-i);
+ accept;
+ }
+ else {
+ int count = 0;
+ for (int i = width-1; i >= 0; i--) {
+ if (D[i].wire)
+ continue;
+ Wire *w = Q[i].wire;
+ auto it = w->attributes.find(\init);
+ State init;
+ if (it != w->attributes.end())
+ init = it->second[Q[i].offset];
+ else
+ init = State::Sx;
+
+ if (init == State::Sx || init == D[i].data) {
+ count++;
+ module->connect(Q[i], D[i]);
+ ceA.remove(i);
+ ceB.remove(i);
+ ceY.remove(i);
+ dffD.remove(i);
+ dffQ.remove(i);
+ }
+ }
+ if (count > 0) {
+ did_something = true;
+ cemux->fixup_parameters();
+ dff->fixup_parameters();
+ log("dffcemux pattern in %s: dff=%s, cemux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(cemux), count);
+ }
+
+ accept;
+ }
+endcode
diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py
index 18c3bf5a5..573722d68 100644
--- a/passes/pmgen/pmgen.py
+++ b/passes/pmgen/pmgen.py
@@ -207,9 +207,10 @@ def process_pmgfile(f, filename):
state_types[current_pattern][line[1]] = "Cell*";
block["if"] = list()
- block["select"] = list()
+ block["setup"] = list()
block["index"] = list()
block["filter"] = list()
+ block["sets"] = list()
block["optional"] = False
block["semioptional"] = False
@@ -228,7 +229,22 @@ def process_pmgfile(f, filename):
if a[0] == "select":
b = l.lstrip()[6:]
- block["select"].append(rewrite_cpp(b.strip()))
+ block["setup"].append(("select", rewrite_cpp(b.strip())))
+ continue
+
+ if a[0] == "slice":
+ m = re.match(r"^\s*slice\s+(\S+)\s+(.*?)\s*$", l)
+ block["setup"].append(("slice", m.group(1), rewrite_cpp(m.group(2))))
+ continue
+
+ if a[0] == "choice":
+ m = re.match(r"^\s*choice\s+<(.*?)>\s+(\S+)\s+(.*?)\s*$", l)
+ block["setup"].append(("choice", m.group(1), m.group(2), rewrite_cpp(m.group(3))))
+ continue
+
+ if a[0] == "define":
+ m = re.match(r"^\s*define\s+<(.*?)>\s+(\S+)\s+(.*?)\s*$", l)
+ block["setup"].append(("define", m.group(1), m.group(2), rewrite_cpp(m.group(3))))
continue
if a[0] == "index":
@@ -242,6 +258,11 @@ def process_pmgfile(f, filename):
block["filter"].append(rewrite_cpp(b.strip()))
continue
+ if a[0] == "set":
+ m = re.match(r"^\s*set\s+(\S+)\s+(.*?)\s*$", l)
+ block["sets"].append((m.group(1), rewrite_cpp(m.group(2))))
+ continue
+
if a[0] == "optional":
block["optional"] = True
continue
@@ -252,14 +273,16 @@ def process_pmgfile(f, filename):
if a[0] == "generate":
block["genargs"] = list([int(s) for s in a[1:]])
+ if len(block["genargs"]) == 0: block["genargs"].append(100)
+ if len(block["genargs"]) == 1: block["genargs"].append(0)
+ assert len(block["genargs"]) == 2
block["gencode"] = list()
- assert len(block["genargs"]) < 2
while True:
linenr += 1
l = f.readline()
assert l != ""
a = l.split()
- if a[0] == "endmatch": break
+ if len(a) == 1 and a[0] == "endmatch": break
block["gencode"].append(rewrite_cpp(l.rstrip()))
break
@@ -357,8 +380,17 @@ with open(outfile, "w") as f:
index_types = list()
for entry in block["index"]:
index_types.append(entry[0])
+ value_types = ["Cell*"]
+ for entry in block["setup"]:
+ if entry[0] == "slice":
+ value_types.append("int")
+ if entry[0] == "choice":
+ value_types.append(entry[1])
+ if entry[0] == "define":
+ value_types.append(entry[1])
print(" typedef std::tuple<{}> index_{}_key_type;".format(", ".join(index_types), index), file=f)
- print(" dict<index_{}_key_type, vector<Cell*>> index_{};".format(index, index), file=f)
+ print(" typedef std::tuple<{}> index_{}_value_type;".format(", ".join(value_types), index), file=f)
+ print(" dict<index_{}_key_type, vector<index_{}_value_type>> index_{};".format(index, index, index), file=f)
print(" dict<SigBit, pool<Cell*>> sigusers;", file=f)
print(" pool<Cell*> blacklist_cells;", file=f)
print(" pool<Cell*> autoremove_cells;", file=f)
@@ -390,8 +422,6 @@ with open(outfile, "w") as f:
print(" void add_siguser(const SigSpec &sig, Cell *cell) {", file=f)
print(" for (auto bit : sigmap(sig)) {", file=f)
print(" if (bit.wire == nullptr) continue;", file=f)
- print(" if (sigusers.count(bit) == 0 && bit.wire->port_id)", file=f)
- print(" sigusers[bit].insert(nullptr);", file=f)
print(" sigusers[bit].insert(cell);", file=f)
print(" }", file=f)
print(" }", file=f)
@@ -446,10 +476,11 @@ with open(outfile, "w") as f:
else:
print(" ud_{}.{} = {}();".format(current_pattern, s, t), file=f)
current_pattern = None
- print(" for (auto cell : module->cells()) {", file=f)
+ print(" for (auto port : module->ports)", file=f)
+ print(" add_siguser(module->wire(port), nullptr);", file=f)
+ print(" for (auto cell : module->cells())", file=f)
print(" for (auto &conn : cell->connections())", file=f)
print(" add_siguser(conn.second, cell);", file=f)
- print(" }", file=f)
print(" for (auto cell : cells) {", file=f)
for index in range(len(blocks)):
@@ -457,12 +488,34 @@ with open(outfile, "w") as f:
if block["type"] == "match":
print(" do {", file=f)
print(" Cell *{} = cell;".format(block["cell"]), file=f)
- for expr in block["select"]:
- print(" if (!({})) break;".format(expr), file=f)
+ print(" index_{}_value_type value;".format(index), file=f)
+ print(" std::get<0>(value) = cell;", file=f)
+ loopcnt = 0
+ valueidx = 1
+ for item in block["setup"]:
+ if item[0] == "select":
+ print(" if (!({})) continue;".format(item[1]), file=f)
+ if item[0] == "slice":
+ print(" int &{} = std::get<{}>(value);".format(item[1], valueidx), file=f)
+ print(" for ({} = 0; {} < {}; {}++) {{".format(item[1], item[1], item[2], item[1]), file=f)
+ valueidx += 1
+ loopcnt += 1
+ if item[0] == "choice":
+ print(" vector<{}> _pmg_choices_{} = {};".format(item[1], item[2], item[3]), file=f)
+ print(" for (const {} &{} : _pmg_choices_{}) {{".format(item[1], item[2], item[2]), file=f)
+ print(" std::get<{}>(value) = {};".format(valueidx, item[2]), file=f)
+ valueidx += 1
+ loopcnt += 1
+ if item[0] == "define":
+ print(" {} &{} = std::get<{}>(value);".format(item[1], item[2], valueidx), file=f)
+ print(" {} = {};".format(item[2], item[3]), file=f)
+ valueidx += 1
print(" index_{}_key_type key;".format(index), file=f)
for field, entry in enumerate(block["index"]):
print(" std::get<{}>(key) = {};".format(field, entry[1]), file=f)
- print(" index_{}[key].push_back(cell);".format(index), file=f)
+ print(" index_{}[key].push_back(value);".format(index), file=f)
+ for i in range(loopcnt):
+ print(" }", file=f)
print(" } while (0);", file=f)
print(" }", file=f)
@@ -535,6 +588,8 @@ with open(outfile, "w") as f:
const_st.add(s)
elif blocks[i]["type"] == "match":
const_st.add(blocks[i]["cell"])
+ for item in blocks[i]["sets"]:
+ const_st.add(item[0])
else:
assert False
@@ -548,6 +603,10 @@ with open(outfile, "w") as f:
s = block["cell"]
assert s not in const_st
nonconst_st.add(s)
+ for item in block["sets"]:
+ if item[0] in const_st:
+ const_st.remove(item[0])
+ nonconst_st.add(item[0])
else:
assert False
@@ -570,7 +629,7 @@ with open(outfile, "w") as f:
print("", file=f)
for s in sorted(restore_st):
t = state_types[current_pattern][s]
- print(" {} backup_{} = {};".format(t, s, s), file=f)
+ print(" {} _pmg_backup_{} = {};".format(t, s, s), file=f)
if block["type"] == "code":
print("", file=f)
@@ -610,7 +669,7 @@ with open(outfile, "w") as f:
print("", file=f)
for s in sorted(restore_st):
t = state_types[current_pattern][s]
- print(" {} = backup_{};".format(s, s), file=f)
+ print(" {} = _pmg_backup_{};".format(s, s), file=f)
for s in sorted(nonconst_st):
if s not in restore_st:
t = state_types[current_pattern][s]
@@ -622,7 +681,7 @@ with open(outfile, "w") as f:
elif block["type"] == "match":
assert len(restore_st) == 0
- print(" Cell* backup_{} = {};".format(block["cell"], block["cell"]), file=f)
+ print(" Cell* _pmg_backup_{} = {};".format(block["cell"], block["cell"]), file=f)
if len(block["if"]):
for expr in block["if"]:
@@ -630,7 +689,7 @@ with open(outfile, "w") as f:
print(" if (!({})) {{".format(expr), file=f)
print(" {} = nullptr;".format(block["cell"]), file=f)
print(" block_{}(recursion+1);".format(index+1), file=f)
- print(" {} = backup_{};".format(block["cell"], block["cell"]), file=f)
+ print(" {} = _pmg_backup_{};".format(block["cell"], block["cell"]), file=f)
print(" return;", file=f)
print(" }", file=f)
@@ -645,21 +704,37 @@ with open(outfile, "w") as f:
print("", file=f)
print(" if (cells_ptr != index_{}.end()) {{".format(index), file=f)
- print(" const vector<Cell*> &cells = cells_ptr->second;".format(index), file=f)
- print(" for (int idx = 0; idx < GetSize(cells); idx++) {", file=f)
- print(" {} = cells[idx];".format(block["cell"]), file=f)
+ print(" const vector<index_{}_value_type> &cells = cells_ptr->second;".format(index), file=f)
+ print(" for (int _pmg_idx = 0; _pmg_idx < GetSize(cells); _pmg_idx++) {", file=f)
+ print(" {} = std::get<0>(cells[_pmg_idx]);".format(block["cell"]), file=f)
+ valueidx = 1
+ for item in block["setup"]:
+ if item[0] == "slice":
+ print(" const int &{} YS_ATTRIBUTE(unused) = std::get<{}>(cells[_pmg_idx]);".format(item[1], valueidx), file=f)
+ valueidx += 1
+ if item[0] == "choice":
+ print(" const {} &{} YS_ATTRIBUTE(unused) = std::get<{}>(cells[_pmg_idx]);".format(item[1], item[2], valueidx), file=f)
+ valueidx += 1
+ if item[0] == "define":
+ print(" const {} &{} YS_ATTRIBUTE(unused) = std::get<{}>(cells[_pmg_idx]);".format(item[1], item[2], valueidx), file=f)
+ valueidx += 1
print(" if (blacklist_cells.count({})) continue;".format(block["cell"]), file=f)
for expr in block["filter"]:
print(" if (!({})) continue;".format(expr), file=f)
if block["semioptional"] or block["genargs"] is not None:
print(" found_any_match = true;", file=f)
- print(" auto rollback_ptr = rollback_cache.insert(make_pair(cells[idx], recursion));", file=f)
+ for item in block["sets"]:
+ print(" auto _pmg_backup_{} = {};".format(item[0], item[0]), file=f)
+ print(" {} = {};".format(item[0], item[1]), file=f)
+ print(" auto rollback_ptr = rollback_cache.insert(make_pair(std::get<0>(cells[_pmg_idx]), recursion));", file=f)
print(" block_{}(recursion+1);".format(index+1), file=f)
+ for item in block["sets"]:
+ print(" {} = _pmg_backup_{};".format(item[0], item[0]), file=f)
print(" if (rollback_ptr.second)", file=f)
print(" rollback_cache.erase(rollback_ptr.first);", file=f)
print(" if (rollback) {", file=f)
print(" if (rollback != recursion) {{".format(index+1), file=f)
- print(" {} = backup_{};".format(block["cell"], block["cell"]), file=f)
+ print(" {} = _pmg_backup_{};".format(block["cell"], block["cell"]), file=f)
print(" return;", file=f)
print(" }", file=f)
print(" rollback = 0;", file=f)
@@ -676,13 +751,11 @@ with open(outfile, "w") as f:
if block["semioptional"]:
print(" if (!found_any_match) block_{}(recursion+1);".format(index+1), file=f)
- print(" {} = backup_{};".format(block["cell"], block["cell"]), file=f)
+ print(" {} = _pmg_backup_{};".format(block["cell"], block["cell"]), file=f)
if block["genargs"] is not None:
print("#define finish do { rollback = -1; return; } while(0)", file=f)
- print(" if (generate_mode && !found_any_match) {", file=f)
- if len(block["genargs"]) == 1:
- print(" if (rng(100) >= {}) return;".format(block["genargs"][0]), file=f)
+ print(" if (generate_mode && rng(100) < (found_any_match ? {} : {})) {{".format(block["genargs"][1], block["genargs"][0]), file=f)
for line in block["gencode"]:
print(" " + line, file=f)
print(" }", file=f)
diff --git a/passes/pmgen/test_pmgen.cc b/passes/pmgen/test_pmgen.cc
index 9f42a95d0..4f3eec935 100644
--- a/passes/pmgen/test_pmgen.cc
+++ b/passes/pmgen/test_pmgen.cc
@@ -28,6 +28,7 @@ bool did_something;
#include "passes/pmgen/test_pmgen_pm.h"
#include "passes/pmgen/ice40_dsp_pm.h"
+#include "passes/pmgen/xilinx_srl_pm.h"
#include "passes/pmgen/peepopt_pm.h"
void reduce_chain(test_pmgen_pm &pm)
@@ -99,6 +100,24 @@ void reduce_tree(test_pmgen_pm &pm)
log(" -> %s (%s)\n", log_id(c), log_id(c->type));
}
+void opt_eqpmux(test_pmgen_pm &pm)
+{
+ auto &st = pm.st_eqpmux;
+
+ SigSpec Y = st.pmux->getPort(ID::Y);
+ int width = GetSize(Y);
+
+ SigSpec EQ = st.pmux->getPort(ID::B).extract(st.pmux_slice_eq*width, width);
+ SigSpec NE = st.pmux->getPort(ID::B).extract(st.pmux_slice_ne*width, width);
+
+ log("Found eqpmux circuit driving %s (eq=%s, ne=%s, pmux=%s).\n",
+ log_signal(Y), log_id(st.eq), log_id(st.ne), log_id(st.pmux));
+
+ pm.autoremove(st.pmux);
+ Cell *c = pm.module->addMux(NEW_ID, NE, EQ, st.eq->getPort(ID::Y), Y);
+ log(" -> %s (%s)\n", log_id(c), log_id(c->type));
+}
+
#define GENERATE_PATTERN(pmclass, pattern) \
generate_pattern<pmclass>([](pmclass &pm, std::function<void()> f){ return pm.run_ ## pattern(f); }, #pmclass, #pattern, design)
@@ -149,19 +168,20 @@ void generate_pattern(std::function<void(pm&,std::function<void()>)> run, const
log("Generating \"%s\" patterns for pattern matcher \"%s\".\n", pattern, pmclass);
int modcnt = 0;
+ int maxmodcnt = 100;
int maxsubcnt = 4;
int timeout = 0;
vector<Module*> mods;
- while (modcnt < 100)
+ while (modcnt < maxmodcnt)
{
int submodcnt = 0, itercnt = 0, cellcnt = 0;
Module *mod = design->addModule(NEW_ID);
- while (modcnt < 100 && submodcnt < maxsubcnt && itercnt++ < 1000)
+ while (modcnt < maxmodcnt && submodcnt < maxsubcnt && itercnt++ < 1000)
{
if (timeout++ > 10000)
- log_error("pmgen generator is stuck: 10000 iterations an no matching module generated.\n");
+ log_error("pmgen generator is stuck: 10000 iterations with no matching module generated.\n");
pm matcher(mod, mod->cells());
@@ -197,7 +217,7 @@ void generate_pattern(std::function<void(pm&,std::function<void()>)> run, const
run(matcher, [](){});
}
- if (submodcnt)
+ if (submodcnt && maxsubcnt < (1 << 16))
maxsubcnt *= 2;
design->remove(mod);
@@ -232,6 +252,12 @@ struct TestPmgenPass : public Pass {
log("Demo for recursive pmgen patterns. Map trees of AND/OR/XOR to $reduce_*.\n");
log("\n");
+ log("\n");
+ log(" test_pmgen -eqpmux [options] [selection]\n");
+ log("\n");
+ log("Demo for recursive pmgen patterns. Optimize EQ/NE/PMUX circuits.\n");
+ log("\n");
+
log("\n");
log(" test_pmgen -generate [options] <pattern_name>\n");
log("\n");
@@ -277,6 +303,25 @@ struct TestPmgenPass : public Pass {
test_pmgen_pm(module, module->selected_cells()).run_reduce(reduce_tree);
}
+ void execute_eqpmux(std::vector<std::string> args, RTLIL::Design *design)
+ {
+ log_header(design, "Executing TEST_PMGEN pass (-eqpmux).\n");
+
+ size_t argidx;
+ for (argidx = 2; argidx < args.size(); argidx++)
+ {
+ // if (args[argidx] == "-singleton") {
+ // singleton_mode = true;
+ // continue;
+ // }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ for (auto module : design->selected_modules())
+ test_pmgen_pm(module, module->selected_cells()).run_eqpmux(opt_eqpmux);
+ }
+
void execute_generate(std::vector<std::string> args, RTLIL::Design *design)
{
log_header(design, "Executing TEST_PMGEN pass (-generate).\n");
@@ -299,16 +344,24 @@ struct TestPmgenPass : public Pass {
if (pattern == "reduce")
return GENERATE_PATTERN(test_pmgen_pm, reduce);
+ if (pattern == "eqpmux")
+ return GENERATE_PATTERN(test_pmgen_pm, eqpmux);
+
if (pattern == "ice40_dsp")
return GENERATE_PATTERN(ice40_dsp_pm, ice40_dsp);
+ if (pattern == "xilinx_srl.fixed")
+ return GENERATE_PATTERN(xilinx_srl_pm, fixed);
+ if (pattern == "xilinx_srl.variable")
+ return GENERATE_PATTERN(xilinx_srl_pm, variable);
+
if (pattern == "peepopt-muldiv")
return GENERATE_PATTERN(peepopt_pm, muldiv);
if (pattern == "peepopt-shiftmul")
return GENERATE_PATTERN(peepopt_pm, shiftmul);
- log_cmd_error("Unkown pattern: %s\n", pattern.c_str());
+ log_cmd_error("Unknown pattern: %s\n", pattern.c_str());
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -319,6 +372,8 @@ struct TestPmgenPass : public Pass {
return execute_reduce_chain(args, design);
if (args[1] == "-reduce_tree")
return execute_reduce_tree(args, design);
+ if (args[1] == "-eqpmux")
+ return execute_eqpmux(args, design);
if (args[1] == "-generate")
return execute_generate(args, design);
}
diff --git a/passes/pmgen/test_pmgen.pmg b/passes/pmgen/test_pmgen.pmg
index 211477a62..287ed97d8 100644
--- a/passes/pmgen/test_pmgen.pmg
+++ b/passes/pmgen/test_pmgen.pmg
@@ -60,8 +60,8 @@ code portname
endcode
match next
- select nusers(port(next, \Y)) == 2
select next->type.in($_AND_, $_OR_, $_XOR_)
+ select nusers(port(next, \Y)) == 2
index <IdString> next->type === first->type
index <SigSpec> port(next, \Y) === port(first, portname)
endmatch
@@ -77,8 +77,8 @@ arg first
match next
semioptional
- select nusers(port(next, \Y)) == 2
select next->type.in($_AND_, $_OR_, $_XOR_)
+ select nusers(port(next, \Y)) == 2
index <IdString> next->type === chain.back().first->type
index <SigSpec> port(next, \Y) === port(chain.back().first, chain.back().second)
generate 10
@@ -104,3 +104,86 @@ finally
if (next)
chain.pop_back();
endcode
+
+// ==================================================================
+
+pattern eqpmux
+
+state <bool> eq_ne_signed
+state <SigSpec> eq_inA eq_inB
+state <int> pmux_slice_eq pmux_slice_ne
+
+match eq
+ select eq->type == $eq
+ choice <IdString> AB {\A, \B}
+ define <IdString> BA AB == \A ? \B : \A
+ set eq_inA port(eq, \A)
+ set eq_inB port(eq, \B)
+ set eq_ne_signed param(eq, \A_SIGNED).as_bool()
+generate 100 10
+ SigSpec A = module->addWire(NEW_ID, rng(7)+1);
+ SigSpec B = module->addWire(NEW_ID, rng(7)+1);
+ SigSpec Y = module->addWire(NEW_ID);
+ module->addEq(NEW_ID, A, B, Y, rng(2));
+endmatch
+
+match pmux
+ select pmux->type == $pmux
+ slice idx GetSize(port(pmux, \S))
+ index <SigBit> port(pmux, \S)[idx] === port(eq, \Y)
+ set pmux_slice_eq idx
+generate 100 10
+ int width = rng(7) + 1;
+ int numsel = rng(4) + 1;
+ int idx = rng(numsel);
+
+ SigSpec A = module->addWire(NEW_ID, width);
+ SigSpec Y = module->addWire(NEW_ID, width);
+
+ SigSpec B, S;
+ for (int i = 0; i < numsel; i++) {
+ B.append(module->addWire(NEW_ID, width));
+ S.append(i == idx ? port(eq, \Y) : module->addWire(NEW_ID));
+ }
+
+ module->addPmux(NEW_ID, A, B, S, Y);
+endmatch
+
+match ne
+ select ne->type == $ne
+ choice <IdString> AB {\A, \B}
+ define <IdString> BA (AB == \A ? \B : \A)
+ index <SigSpec> port(ne, AB) === eq_inA
+ index <SigSpec> port(ne, BA) === eq_inB
+ index <int> param(ne, \A_SIGNED).as_bool() === eq_ne_signed
+generate 100 10
+ SigSpec A = eq_inA, B = eq_inB, Y;
+ if (rng(2)) {
+ std::swap(A, B);
+ }
+ if (rng(2)) {
+ for (auto bit : port(pmux, \S)) {
+ if (nusers(bit) < 2)
+ Y.append(bit);
+ }
+ if (GetSize(Y))
+ Y = Y[rng(GetSize(Y))];
+ else
+ Y = module->addWire(NEW_ID);
+ } else {
+ Y = module->addWire(NEW_ID);
+ }
+ module->addNe(NEW_ID, A, B, Y, rng(2));
+endmatch
+
+match pmux2
+ select pmux2->type == $pmux
+ slice idx GetSize(port(pmux2, \S))
+ index <Cell*> pmux2 === pmux
+ index <SigBit> port(pmux2, \S)[idx] === port(ne, \Y)
+ set pmux_slice_ne idx
+endmatch
+
+code
+ accept;
+endcode
diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc
new file mode 100644
index 000000000..3d264e8d4
--- /dev/null
+++ b/passes/pmgen/xilinx_srl.cc
@@ -0,0 +1,258 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * (C) 2019 Eddie Hung <eddie@fpgeh.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+#include "passes/pmgen/xilinx_srl_pm.h"
+
+void run_fixed(xilinx_srl_pm &pm)
+{
+ auto &st = pm.st_fixed;
+ auto &ud = pm.ud_fixed;
+ log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type));
+
+ SigSpec initval;
+ for (auto cell : ud.longest_chain) {
+ log_debug(" %s\n", log_id(cell));
+ if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) {
+ SigBit Q = cell->getPort(ID(Q));
+ log_assert(Q.wire);
+ auto it = Q.wire->attributes.find(ID(init));
+ if (it != Q.wire->attributes.end()) {
+ auto &i = it->second[Q.offset];
+ initval.append(i);
+ i = State::Sx;
+ }
+ else
+ initval.append(State::Sx);
+ }
+ else if (cell->type.in(ID(FDRE), ID(FDRE_1))) {
+ if (cell->parameters.at(ID(INIT), State::S0).as_bool())
+ initval.append(State::S1);
+ else
+ initval.append(State::S0);
+ }
+ else
+ log_abort();
+ pm.autoremove(cell);
+ }
+
+ auto first_cell = ud.longest_chain.back();
+ auto last_cell = ud.longest_chain.front();
+ Cell *c = pm.module->addCell(NEW_ID, ID($__XILINX_SHREG_));
+ pm.module->swap_names(c, first_cell);
+
+ if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) {
+ c->setParam(ID(DEPTH), GetSize(ud.longest_chain));
+ c->setParam(ID(INIT), initval.as_const());
+ if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
+ c->setParam(ID(CLKPOL), 1);
+ else if (first_cell->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1)))
+ c->setParam(ID(CLKPOL), 0);
+ else if (first_cell->type.in(ID(FDRE))) {
+ if (!first_cell->parameters.at(ID(IS_C_INVERTED), State::S0).as_bool())
+ c->setParam(ID(CLKPOL), 1);
+ else
+ c->setParam(ID(CLKPOL), 0);
+ }
+ else
+ log_abort();
+ if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
+ c->setParam(ID(ENPOL), 1);
+ else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
+ c->setParam(ID(ENPOL), 0);
+ else
+ c->setParam(ID(ENPOL), 2);
+
+ c->setPort(ID(C), first_cell->getPort(ID(C)));
+ c->setPort(ID(D), first_cell->getPort(ID(D)));
+ c->setPort(ID(Q), last_cell->getPort(ID(Q)));
+ c->setPort(ID(L), GetSize(ud.longest_chain)-1);
+ if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
+ c->setPort(ID(E), State::S1);
+ else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
+ c->setPort(ID(E), first_cell->getPort(ID(E)));
+ else if (first_cell->type.in(ID(FDRE), ID(FDRE_1)))
+ c->setPort(ID(E), first_cell->getPort(ID(CE)));
+ else
+ log_abort();
+ }
+ else
+ log_abort();
+
+ log(" -> %s (%s)\n", log_id(c), log_id(c->type));
+}
+
+void run_variable(xilinx_srl_pm &pm)
+{
+ auto &st = pm.st_variable;
+ auto &ud = pm.ud_variable;
+
+ log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), log_id(st.first->type));
+
+ SigSpec initval;
+ for (const auto &i : ud.chain) {
+ auto cell = i.first;
+ auto slice = i.second;
+ log_debug(" %s\n", log_id(cell));
+ if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
+ SigBit Q = cell->getPort(ID(Q))[slice];
+ log_assert(Q.wire);
+ auto it = Q.wire->attributes.find(ID(init));
+ if (it != Q.wire->attributes.end()) {
+ auto &i = it->second[Q.offset];
+ initval.append(i);
+ i = State::Sx;
+ }
+ else
+ initval.append(State::Sx);
+ }
+ else
+ log_abort();
+ }
+ pm.autoremove(st.shiftx);
+
+ auto first_cell = ud.chain.back().first;
+ auto first_slice = ud.chain.back().second;
+
+ Cell *c = pm.module->addCell(NEW_ID, ID($__XILINX_SHREG_));
+ pm.module->swap_names(c, first_cell);
+
+ if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
+ c->setParam(ID(DEPTH), GetSize(ud.chain));
+ c->setParam(ID(INIT), initval.as_const());
+ Const clkpol, enpol;
+ if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
+ clkpol = 1;
+ else if (first_cell->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_)))
+ clkpol = 0;
+ else if (first_cell->type.in(ID($dff), ID($dffe)))
+ clkpol = first_cell->getParam(ID(CLK_POLARITY));
+ else
+ log_abort();
+ if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
+ enpol = 1;
+ else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
+ enpol = 0;
+ else if (first_cell->type.in(ID($dffe)))
+ enpol = first_cell->getParam(ID(EN_POLARITY));
+ else
+ enpol = 2;
+ c->setParam(ID(CLKPOL), clkpol);
+ c->setParam(ID(ENPOL), enpol);
+
+ if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
+ c->setPort(ID(C), first_cell->getPort(ID(C)));
+ else if (first_cell->type.in(ID($dff), ID($dffe)))
+ c->setPort(ID(C), first_cell->getPort(ID(CLK)));
+ else
+ log_abort();
+ c->setPort(ID(D), first_cell->getPort(ID(D))[first_slice]);
+ c->setPort(ID(Q), st.shiftx->getPort(ID(Y)));
+ c->setPort(ID(L), st.shiftx->getPort(ID(B)));
+ if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($dff)))
+ c->setPort(ID(E), State::S1);
+ else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
+ c->setPort(ID(E), first_cell->getPort(ID(E)));
+ else if (first_cell->type.in(ID($dffe)))
+ c->setPort(ID(E), first_cell->getPort(ID(EN)));
+ else
+ log_abort();
+ }
+ else
+ log_abort();
+
+ log(" -> %s (%s)\n", log_id(c), log_id(c->type));
+}
+
+struct XilinxSrlPass : public Pass {
+ XilinxSrlPass() : Pass("xilinx_srl", "Xilinx shift register extraction") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" xilinx_srl [options] [selection]\n");
+ log("\n");
+ log("This pass converts chains of built-in flops (bit-level: $_DFF_[NP]_, $_DFFE_*\n");
+ log("and word-level: $dff, $dffe) as well as Xilinx flops (FDRE, FDRE_1) into a\n");
+ log("$__XILINX_SHREG cell. Chains must be of the same cell type, clock, clock polarity,\n");
+ log("enable, and enable polarity (where relevant).\n");
+ log("Flops with resets cannot be mapped to Xilinx devices and will not be inferred.");
+ log("\n");
+ log(" -minlen N\n");
+ log(" min length of shift register (default = 3)\n");
+ log("\n");
+ log(" -fixed\n");
+ log(" infer fixed-length shift registers.\n");
+ log("\n");
+ log(" -variable\n");
+ log(" infer variable-length shift registers (i.e. fixed-length shifts where\n");
+ log(" each element also fans-out to a $shiftx cell).\n");
+ log("\n");
+ }
+
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ log_header(design, "Executing XILINX_SRL pass (Xilinx shift register extraction).\n");
+
+ bool fixed = false;
+ bool variable = false;
+ int minlen = 3;
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ if (args[argidx] == "-minlen" && argidx+1 < args.size()) {
+ minlen = atoi(args[++argidx].c_str());
+ continue;
+ }
+ if (args[argidx] == "-fixed") {
+ fixed = true;
+ continue;
+ }
+ if (args[argidx] == "-variable") {
+ variable = true;
+ continue;
+ }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ if (!fixed && !variable)
+ log_cmd_error("'-fixed' and/or '-variable' must be specified.\n");
+
+ for (auto module : design->selected_modules()) {
+ auto pm = xilinx_srl_pm(module, module->selected_cells());
+ pm.ud_fixed.minlen = minlen;
+ pm.ud_variable.minlen = minlen;
+
+ if (fixed)
+ pm.run_fixed(run_fixed);
+ if (variable)
+ pm.run_variable(run_variable);
+ }
+ }
+} XilinxSrlPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg
new file mode 100644
index 000000000..b18119b87
--- /dev/null
+++ b/passes/pmgen/xilinx_srl.pmg
@@ -0,0 +1,326 @@
+pattern fixed
+
+state <IdString> clk_port en_port
+udata <vector<Cell*>> chain longest_chain
+udata <pool<Cell*>> non_first_cells
+udata <int> minlen
+
+code
+ non_first_cells.clear();
+ subpattern(setup);
+endcode
+
+match first
+ select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
+ select !first->has_keep_attr()
+ select !first->type.in(\FDRE) || !first->parameters.at(\IS_R_INVERTED, State::S0).as_bool()
+ select !first->type.in(\FDRE) || !first->parameters.at(\IS_D_INVERTED, State::S0).as_bool()
+ select !first->type.in(\FDRE, \FDRE_1) || first->connections_.at(\R, State::S0).is_fully_zero()
+ filter !non_first_cells.count(first)
+generate
+ SigSpec C = module->addWire(NEW_ID);
+ SigSpec D = module->addWire(NEW_ID);
+ SigSpec Q = module->addWire(NEW_ID);
+ auto r = rng(8);
+ Cell* cell;
+ switch (r)
+ {
+ case 0:
+ case 1:
+ cell = module->addCell(NEW_ID, \FDRE);
+ cell->setPort(\C, C);
+ cell->setPort(\D, D);
+ cell->setPort(\Q, Q);
+ cell->setPort(\CE, module->addWire(NEW_ID));
+ if (r & 1)
+ cell->setPort(\R, module->addWire(NEW_ID));
+ else {
+ if (rng(2) == 0)
+ cell->setPort(\R, State::S0);
+ }
+ break;
+ case 2:
+ case 3:
+ cell = module->addDffGate(NEW_ID, C, D, Q, r & 1);
+ break;
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ cell = module->addDffeGate(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 2);
+ break;
+ default: log_abort();
+ }
+endmatch
+
+code clk_port en_port
+ if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1))
+ clk_port = \C;
+ else log_abort();
+ if (first->type.in($_DFF_N_, $_DFF_P_))
+ en_port = IdString();
+ else if (first->type.in($_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
+ en_port = \E;
+ else if (first->type.in(\FDRE, \FDRE_1))
+ en_port = \CE;
+ else log_abort();
+
+ longest_chain.clear();
+ chain.push_back(first);
+ subpattern(tail);
+finally
+ chain.pop_back();
+ log_assert(chain.empty());
+ if (GetSize(longest_chain) >= minlen)
+ accept;
+endcode
+
+// ------------------------------------------------------------------
+
+subpattern setup
+arg clk_port
+arg en_port
+
+match first
+ select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
+ select !first->has_keep_attr()
+ select !first->type.in(\FDRE) || !first->parameters.at(\IS_R_INVERTED, State::S0).as_bool()
+ select !first->type.in(\FDRE) || !first->parameters.at(\IS_D_INVERTED, State::S0).as_bool()
+ select !first->type.in(\FDRE, \FDRE_1) || first->connections_.at(\R, State::S0).is_fully_zero()
+endmatch
+
+code clk_port en_port
+ if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1))
+ clk_port = \C;
+ else log_abort();
+ if (first->type.in($_DFF_N_, $_DFF_P_))
+ en_port = IdString();
+ else if (first->type.in($_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
+ en_port = \E;
+ else if (first->type.in(\FDRE, \FDRE_1))
+ en_port = \CE;
+ else log_abort();
+endcode
+
+match next
+ select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
+ select !next->has_keep_attr()
+ select port(next, \D)[0].wire && !port(next, \D)[0].wire->get_bool_attribute(\keep)
+ select nusers(port(next, \Q)) == 2
+ index <IdString> next->type === first->type
+ index <SigBit> port(next, \Q) === port(first, \D)
+ filter port(next, clk_port) == port(first, clk_port)
+ filter en_port == IdString() || port(next, en_port) == port(first, en_port)
+ filter !first->type.in(\FDRE) || next->parameters.at(\IS_C_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_C_INVERTED, State::S0).as_bool()
+ filter !first->type.in(\FDRE) || next->parameters.at(\IS_D_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_D_INVERTED, State::S0).as_bool()
+ filter !first->type.in(\FDRE) || next->parameters.at(\IS_R_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_R_INVERTED, State::S0).as_bool()
+ filter !first->type.in(\FDRE, \FDRE_1) || next->connections_.at(\R, State::S0).is_fully_zero()
+endmatch
+
+code
+ non_first_cells.insert(next);
+endcode
+
+// ------------------------------------------------------------------
+
+subpattern tail
+arg first
+arg clk_port
+arg en_port
+
+match next
+ semioptional
+ select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
+ select !next->has_keep_attr()
+ select port(next, \D)[0].wire && !port(next, \D)[0].wire->get_bool_attribute(\keep)
+ select nusers(port(next, \Q)) == 2
+ index <IdString> next->type === chain.back()->type
+ index <SigBit> port(next, \Q) === port(chain.back(), \D)
+ filter port(next, clk_port) == port(first, clk_port)
+ filter en_port == IdString() || port(next, en_port) == port(first, en_port)
+ filter !first->type.in(\FDRE) || next->parameters.at(\IS_C_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_C_INVERTED, State::S0).as_bool()
+ filter !first->type.in(\FDRE) || next->parameters.at(\IS_D_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_D_INVERTED, State::S0).as_bool()
+ filter !first->type.in(\FDRE) || next->parameters.at(\IS_R_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_R_INVERTED, State::S0).as_bool()
+ filter !first->type.in(\FDRE, \FDRE_1) || next->connections_.at(\R, State::S0).is_fully_zero()
+generate
+ Cell *cell = module->addCell(NEW_ID, chain.back()->type);
+ cell->setPort(\C, chain.back()->getPort(\C));
+ cell->setPort(\D, module->addWire(NEW_ID));
+ cell->setPort(\Q, chain.back()->getPort(\D));
+ if (cell->type == \FDRE) {
+ if (rng(2) == 0)
+ cell->setPort(\R, chain.back()->connections_.at(\R, State::S0));
+ cell->setPort(\CE, chain.back()->getPort(\CE));
+ }
+ else if (cell->type.begins_with("$_DFFE_"))
+ cell->setPort(\E, chain.back()->getPort(\E));
+endmatch
+
+code
+ if (next) {
+ chain.push_back(next);
+ subpattern(tail);
+ } else {
+ if (GetSize(chain) > GetSize(longest_chain))
+ longest_chain = chain;
+ }
+finally
+ if (next)
+ chain.pop_back();
+endcode
+
+// -----------
+
+pattern variable
+
+state <IdString> clk_port en_port
+state <int> shiftx_width
+state <int> slice
+udata <int> minlen
+udata <vector<pair<Cell*,int>>> chain
+udata <pool<SigBit>> chain_bits
+
+code
+ chain_bits.clear();
+endcode
+
+match shiftx
+ select shiftx->type.in($shiftx)
+ select !shiftx->has_keep_attr()
+ select param(shiftx, \Y_WIDTH).as_int() == 1
+ filter param(shiftx, \A_WIDTH).as_int() >= minlen
+generate
+ minlen = 3;
+ module->addShiftx(NEW_ID, module->addWire(NEW_ID, rng(6)+minlen), module->addWire(NEW_ID, 3), module->addWire(NEW_ID));
+endmatch
+
+code shiftx_width
+ shiftx_width = param(shiftx, \A_WIDTH).as_int();
+endcode
+
+match first
+ select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe)
+ select !first->has_keep_attr()
+ select port(first, \Q)[0].wire && !port(first, \Q)[0].wire->get_bool_attribute(\keep)
+ slice idx GetSize(port(first, \Q))
+ select nusers(port(first, \Q)[idx]) <= 2
+ index <SigBit> port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1]
+ set slice idx
+generate
+ SigSpec C = module->addWire(NEW_ID);
+ auto WIDTH = rng(3)+1;
+ SigSpec D = module->addWire(NEW_ID, WIDTH);
+ SigSpec Q = module->addWire(NEW_ID, WIDTH);
+ auto r = rng(8);
+ Cell *cell = nullptr;
+ switch (r)
+ {
+ case 0:
+ case 1:
+ cell = module->addDff(NEW_ID, C, D, Q, r & 1);
+ break;
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ //cell = module->addDffe(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 4);
+ //break;
+ case 6:
+ case 7:
+ WIDTH = 1;
+ cell = module->addDffGate(NEW_ID, C, D[0], Q[0], r & 1);
+ break;
+ default: log_abort();
+ }
+ shiftx->connections_.at(\A)[shiftx_width-1] = port(cell, \Q)[rng(WIDTH)];
+endmatch
+
+code clk_port en_port
+ if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
+ clk_port = \C;
+ else if (first->type.in($dff, $dffe))
+ clk_port = \CLK;
+ else log_abort();
+ if (first->type.in($_DFF_N_, $_DFF_P_, $dff))
+ en_port = IdString();
+ else if (first->type.in($_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
+ en_port = \E;
+ else if (first->type.in($dffe))
+ en_port = \EN;
+ else log_abort();
+
+ chain_bits.insert(port(first, \Q)[slice]);
+ chain.emplace_back(first, slice);
+ subpattern(tail);
+finally
+ if (GetSize(chain) == shiftx_width)
+ accept;
+ chain.clear();
+endcode
+
+// ------------------------------------------------------------------
+
+subpattern tail
+arg first
+arg shiftx
+arg shiftx_width
+arg slice
+arg clk_port
+arg en_port
+
+match next
+ semioptional
+ select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe)
+ select !next->has_keep_attr()
+ select port(next, \D)[0].wire && !port(next, \D)[0].wire->get_bool_attribute(\keep)
+ slice idx GetSize(port(next, \Q))
+ select nusers(port(next, \Q)[idx]) <= 3
+ index <IdString> next->type === chain.back().first->type
+ index <SigBit> port(next, \Q)[idx] === port(chain.back().first, \D)[chain.back().second]
+ index <SigBit> port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)]
+ filter port(next, clk_port) == port(first, clk_port)
+ filter en_port == IdString() || port(next, en_port) == port(first, en_port)
+ filter !next->type.in($dff, $dffe) || param(next, \CLK_POLARITY).as_bool() == param(first, \CLK_POLARITY).as_bool()
+ filter !next->type.in($dffe) || param(next, \EN_POLARITY).as_bool() == param(first, \EN_POLARITY).as_bool()
+ filter !chain_bits.count(port(next, \D)[idx])
+ set slice idx
+generate
+ if (GetSize(chain) < shiftx_width) {
+ auto back = chain.back().first;
+ auto slice = chain.back().second;
+ if (back->type.in($dff, $dffe)) {
+ auto WIDTH = GetSize(port(back, \D));
+ if (rng(2) == 0 && slice < WIDTH-1) {
+ auto new_slice = slice + rng(WIDTH-1-slice);
+ back->connections_.at(\D)[slice] = port(back, \Q)[new_slice];
+ }
+ else {
+ auto D = module->addWire(NEW_ID, WIDTH);
+ if (back->type == $dff)
+ module->addDff(NEW_ID, port(back, \CLK), D, port(back, \D), param(back, \CLK_POLARITY).as_bool());
+ else if (back->type == $dffe)
+ module->addDffe(NEW_ID, port(back, \CLK), port(back, \EN), D, port(back, \D), param(back, \CLK_POLARITY).as_bool(), param(back, \EN_POLARITY).as_bool());
+ else
+ log_abort();
+ }
+ }
+ else if (back->type.begins_with("$_DFF_")) {
+ Cell *cell = module->addCell(NEW_ID, back->type);
+ cell->setPort(\C, back->getPort(\C));
+ cell->setPort(\D, module->addWire(NEW_ID));
+ cell->setPort(\Q, back->getPort(\D));
+ }
+ else
+ log_abort();
+ shiftx->connections_.at(\A)[shiftx_width-1-GetSize(chain)] = port(back, \D)[slice];
+ }
+endmatch
+
+code
+ if (next) {
+ chain_bits.insert(port(next, \Q)[slice]);
+ chain.emplace_back(next, slice);
+ if (GetSize(chain) < shiftx_width)
+ subpattern(tail);
+ }
+endcode
diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc
index d045d0dcb..24ae6e448 100644
--- a/passes/sat/async2sync.cc
+++ b/passes/sat/async2sync.cc
@@ -39,7 +39,7 @@ struct Async2syncPass : public Pass {
log("reset value in the next cycle regardless of the data-in value at the time of\n");
log("the clock edge.\n");
log("\n");
- log("Currently only $adff and $dffsr cells are supported by this pass.\n");
+ log("Currently only $adff, $dffsr, and $dlatch cells are supported by this pass.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -169,6 +169,41 @@ struct Async2syncPass : public Pass {
cell->type = "$dff";
continue;
}
+
+ if (cell->type.in("$dlatch"))
+ {
+ bool en_pol = cell->parameters["\\EN_POLARITY"].as_bool();
+
+ SigSpec sig_en = cell->getPort("\\EN");
+ SigSpec sig_d = cell->getPort("\\D");
+ SigSpec sig_q = cell->getPort("\\Q");
+
+ log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
+ log_id(module), log_id(cell), log_id(cell->type),
+ log_signal(sig_en), log_signal(sig_d), log_signal(sig_q));
+
+ Const init_val;
+ for (int i = 0; i < GetSize(sig_q); i++) {
+ SigBit bit = sigmap(sig_q[i]);
+ init_val.bits.push_back(initbits.count(bit) ? initbits.at(bit) : State::Sx);
+ del_initbits.insert(bit);
+ }
+
+ Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
+ new_q->attributes["\\init"] = init_val;
+
+ if (en_pol) {
+ module->addMux(NEW_ID, new_q, sig_d, sig_en, sig_q);
+ } else {
+ module->addMux(NEW_ID, sig_d, new_q, sig_en, sig_q);
+ }
+
+ cell->setPort("\\Q", new_q);
+ cell->unsetPort("\\EN");
+ cell->unsetParam("\\EN_POLARITY");
+ cell->type = "$ff";
+ continue;
+ }
}
for (auto wire : module->wires())
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index dd56d8c71..430bba1e8 100644
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -268,7 +268,7 @@ struct SatHelper
RTLIL::SigSpec removed_bits;
for (int i = 0; i < lhs.size(); i++) {
RTLIL::SigSpec bit = lhs.extract(i, 1);
- if (!satgen.initial_state.check_all(bit)) {
+ if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit)) {
removed_bits.append(bit);
lhs.remove(i, 1);
rhs.remove(i, 1);
diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index 56f05eca4..cd357d72a 100644
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -16,6 +16,7 @@ endif
ifneq ($(SMALL),1)
OBJS += passes/techmap/iopadmap.o
+OBJS += passes/techmap/clkbufmap.o
OBJS += passes/techmap/hilomap.o
OBJS += passes/techmap/extract.o
OBJS += passes/techmap/extract_fa.o
@@ -39,6 +40,7 @@ OBJS += passes/techmap/attrmap.o
OBJS += passes/techmap/zinit.o
OBJS += passes/techmap/dff2dffs.o
OBJS += passes/techmap/flowmap.o
+OBJS += passes/techmap/extractinv.o
endif
GENFILES += passes/techmap/techmap.inc
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 29929f80b..97d4c5ef3 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -76,8 +76,7 @@ inline std::string remap_name(RTLIL::IdString abc_name)
return stringf("$abc$%d$%s", map_autoidx, abc_name.c_str()+1);
}
-void handle_loops(RTLIL::Design *design,
- const dict<IdString,pool<IdString>> &scc_break_inputs)
+void handle_loops(RTLIL::Design *design)
{
Pass::call(design, "scc -set_attr abc_scc_id {}");
@@ -85,7 +84,7 @@ void handle_loops(RTLIL::Design *design,
// cell in the component, and select (and mark) all its output
// wires
pool<RTLIL::Const> ids_seen;
- for (auto cell : module->selected_cells()) {
+ for (auto cell : module->cells()) {
auto it = cell->attributes.find(ID(abc_scc_id));
if (it != cell->attributes.end()) {
auto r = ids_seen.insert(it->second);
@@ -114,30 +113,6 @@ void handle_loops(RTLIL::Design *design,
}
cell->attributes.erase(it);
}
-
- auto jt = scc_break_inputs.find(cell->type);
- if (jt != scc_break_inputs.end())
- for (auto port_name : jt->second) {
- RTLIL::SigSpec sig;
- auto &rhs = cell->connections_.at(port_name);
- for (auto b : rhs) {
- Wire *w = b.wire;
- if (!w) continue;
- w->port_output = true;
- w->set_bool_attribute(ID(abc_scc_break));
- w = module->wire(stringf("%s.abci", w->name.c_str()));
- if (!w) {
- w = module->addWire(stringf("%s.abci", b.wire->name.c_str()), GetSize(b.wire));
- w->port_input = true;
- }
- else {
- log_assert(b.offset < GetSize(w));
- log_assert(w->port_input);
- }
- sig.append(RTLIL::SigBit(w, b.offset));
- }
- rhs = sig;
- }
}
module->fixup_ports();
@@ -269,11 +244,10 @@ struct abc_output_filter
};
void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
- bool cleanup, vector<int> lut_costs, bool /*dff_mode*/, std::string clk_str,
+ bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
bool /*keepff*/, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
bool show_tempdir, std::string box_file, std::string lut_file,
- std::string wire_delay, const dict<int,IdString> &box_lookup,
- const dict<IdString,pool<IdString>> &scc_break_inputs
+ std::string wire_delay, const dict<int,IdString> &box_lookup
)
{
module = current_module;
@@ -309,8 +283,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
clk_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(clk_str)), 0));
}
- //if (dff_mode && clk_sig.empty())
- // log_cmd_error("Clock domain %s not found.\n", clk_str.c_str());
+ if (dff_mode && clk_sig.empty())
+ log_cmd_error("Clock domain %s not found.\n", clk_str.c_str());
std::string tempdir_name = "/tmp/yosys-abc-XXXXXX";
if (!cleanup)
@@ -383,7 +357,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
fprintf(f, "%s\n", abc_script.c_str());
fclose(f);
- if (/*dff_mode ||*/ !clk_str.empty())
+ if (dff_mode || !clk_str.empty())
{
if (clk_sig.size() == 0)
log("No%s clock domain found. Not extracting any FF cells.\n", clk_str.empty() ? "" : " matching");
@@ -413,16 +387,13 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::Selection& sel = design->selection_stack.back();
sel.select(module);
- handle_loops(design, scc_break_inputs);
+ handle_loops(design);
Pass::call(design, "aigmap");
//log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
// count_gates, GetSize(signal_list), count_input, count_output);
-#if 0
- Pass::call(design, stringf("write_verilog -noexpr -norename %s/before.v", tempdir_name.c_str()));
-#endif
Pass::call(design, stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()));
std::string buffer;
@@ -531,12 +502,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
for (int i = 0; i < GetSize(w); i++)
output_bits.insert({wire, i});
}
-
- auto jt = w->attributes.find("\\init");
- if (jt != w->attributes.end()) {
- auto r = remap_wire->attributes.insert(std::make_pair("\\init", jt->second));
- log_assert(r.second);
- }
}
for (auto &it : module->connections_) {
@@ -578,6 +543,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
if (mapped_cell->type == ID($_NOT_)) {
RTLIL::SigBit a_bit = mapped_cell->getPort(ID::A);
RTLIL::SigBit y_bit = mapped_cell->getPort(ID::Y);
+ bit_users[a_bit].insert(mapped_cell->name);
+ bit_drivers[y_bit].insert(mapped_cell->name);
if (!a_bit.wire) {
mapped_cell->setPort(ID::Y, module->addWire(NEW_ID));
@@ -585,8 +552,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
log_assert(wire);
module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
}
- else {
- RTLIL::Cell* driving_lut = nullptr;
+ else if (!lut_costs.empty() || !lut_file.empty()) {
+ RTLIL::Cell* driver_lut = nullptr;
// ABC can return NOT gates that drive POs
if (!a_bit.wire->port_input) {
// If it's not a NOT gate that that comes from a PI directly,
@@ -598,10 +565,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
driver_name = stringf("%s$lut", a_bit.wire->name.c_str());
else
driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset);
- driving_lut = mapped_mod->cell(driver_name);
+ driver_lut = mapped_mod->cell(driver_name);
}
- if (!driving_lut) {
+ if (!driver_lut) {
// If a driver couldn't be found (could be from PI or box CI)
// then implement using a LUT
cell = module->addLut(remap_name(stringf("%s$lut", mapped_cell->name.c_str())),
@@ -610,13 +577,13 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
RTLIL::Const::from_string("01"));
bit2sinks[cell->getPort(ID::A)].push_back(cell);
cell_stats[ID($lut)]++;
- bit_users[a_bit].insert(mapped_cell->name);
- bit_drivers[y_bit].insert(mapped_cell->name);
}
else
- not2drivers[mapped_cell] = driving_lut;
+ not2drivers[mapped_cell] = driver_lut;
continue;
}
+ else
+ log_abort();
if (cell && markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
continue;
}
@@ -700,32 +667,31 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
}
for (auto &it : cell_stats)
- log("ABC RESULTS: %15s cells: %8d\n", log_id(it.first), it.second);
+ log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
int in_wires = 0, out_wires = 0;
// Stitch in mapped_mod's inputs/outputs into module
- for (auto port_name : mapped_mod->ports) {
- RTLIL::Wire *port = mapped_mod->wire(port_name);
- log_assert(port);
- RTLIL::Wire *wire = module->wire(port->name);
+ for (auto port : mapped_mod->ports) {
+ RTLIL::Wire *w = mapped_mod->wire(port);
+ RTLIL::Wire *wire = module->wire(port);
log_assert(wire);
- RTLIL::Wire *remap_wire = module->wire(remap_name(port->name));
+ RTLIL::Wire *remap_wire = module->wire(remap_name(port));
RTLIL::SigSpec signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire));
log_assert(GetSize(signal) >= GetSize(remap_wire));
RTLIL::SigSig conn;
- if (port->port_input) {
- conn.first = remap_wire;
- conn.second = signal;
- in_wires++;
- module->connect(conn);
- }
- if (port->port_output) {
+ if (w->port_output) {
conn.first = signal;
conn.second = remap_wire;
out_wires++;
module->connect(conn);
}
+ else if (w->port_input) {
+ conn.first = remap_wire;
+ conn.second = signal;
+ in_wires++;
+ module->connect(conn);
+ }
}
for (auto &it : bit_users)
@@ -733,21 +699,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
for (auto driver_cell : bit_drivers.at(it.first))
for (auto user_cell : it.second)
toposort.edge(driver_cell, user_cell);
-#if 0
- toposort.analyze_loops = true;
-#endif
bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
-#if 0
- unsigned i = 0;
- for (auto &it : toposort.loops) {
- log(" loop %d\n", i++);
- for (auto cell_name : it) {
- auto cell = mapped_mod->cell(cell_name);
- log_assert(cell);
- log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
- }
- }
-#endif
log_assert(no_loops);
for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) {
@@ -1048,7 +1000,7 @@ struct Abc9Pass : public Pass {
fast_mode = true;
continue;
}
- //if (arg == "-retime") {
+ //if (arg == "-dff") {
// dff_mode = true;
// continue;
//}
@@ -1075,9 +1027,6 @@ struct Abc9Pass : public Pass {
}
if (arg == "-box" && argidx+1 < args.size()) {
box_file = args[++argidx];
- rewrite_filename(box_file);
- if (!box_file.empty() && !is_absolute_path(box_file))
- box_file = std::string(pwd) + "/" + box_file;
continue;
}
if (arg == "-W" && argidx+1 < args.size()) {
@@ -1088,11 +1037,15 @@ struct Abc9Pass : public Pass {
}
extra_args(args, argidx, design);
- if (lut_costs.empty() && lut_file.empty())
- log_cmd_error("abc9 must be called with '-lut' or '-luts'\n");
+ // ABC expects a box file for XAIG
+ if (box_file.empty())
+ box_file = "+/dummy.box";
+
+ rewrite_filename(box_file);
+ if (!box_file.empty() && !is_absolute_path(box_file))
+ box_file = std::string(pwd) + "/" + box_file;
dict<int,IdString> box_lookup;
- dict<IdString,pool<IdString>> scc_break_inputs;
for (auto m : design->modules()) {
auto it = m->attributes.find(ID(abc_box_id));
if (it == m->attributes.end())
@@ -1110,17 +1063,13 @@ struct Abc9Pass : public Pass {
for (auto p : m->ports) {
auto w = m->wire(p);
log_assert(w);
- if (w->port_input) {
- if (w->attributes.count(ID(abc_scc_break)))
- scc_break_inputs[m->name].insert(p);
- if (w->attributes.count(ID(abc_carry))) {
+ if (w->attributes.count(ID(abc_carry))) {
+ if (w->port_input) {
if (carry_in)
log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m));
carry_in = w;
}
- }
- if (w->port_output) {
- if (w->attributes.count(ID(abc_carry))) {
+ else if (w->port_output) {
if (carry_out)
log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m));
carry_out = w;
@@ -1177,7 +1126,8 @@ struct Abc9Pass : public Pass {
abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, false, clk_str, keepff,
delay_target, lutin_shared, fast_mode, show_tempdir,
- box_file, lut_file, wire_delay, box_lookup, scc_break_inputs);
+ box_file, lut_file, wire_delay, box_lookup);
+
design->selection_stack.pop_back();
continue;
}
@@ -1361,36 +1311,20 @@ struct Abc9Pass : public Pass {
std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)));
- design->selection_stack.emplace_back(false);
-
for (auto &it : assigned_cells) {
- // FIXME: abc9_module calls below can delete cells,
- // leaving a dangling pointer here...
clk_polarity = std::get<0>(it.first);
clk_sig = assign_map(std::get<1>(it.first));
en_polarity = std::get<2>(it.first);
en_sig = assign_map(std::get<3>(it.first));
-
- pool<RTLIL::IdString> assigned_names;
- for (auto i : it.second)
- assigned_names.insert(i->name);
- RTLIL::Selection& sel = design->selection_stack.back();
- sel.selected_members[mod->name] = std::move(assigned_names);
-
abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, !clk_sig.empty(), "$",
keepff, delay_target, lutin_shared, fast_mode, show_tempdir,
- box_file, lut_file, wire_delay, box_lookup, scc_break_inputs);
+ box_file, lut_file, wire_delay, box_lookup);
assign_map.set(mod);
}
-
- design->selection_stack.pop_back();
}
assign_map.clear();
- // The "clean" pass also contains a design->check() call
- Pass::call(design, "clean");
-
log_pop();
}
} Abc9Pass;
diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index 5b168d524..034731b87 100644
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -48,14 +48,25 @@ struct AlumaccWorker
RTLIL::SigSpec cached_cf, cached_of, cached_sf;
RTLIL::SigSpec get_lt() {
- if (GetSize(cached_lt) == 0)
- cached_lt = is_signed ? alu_cell->module->Xor(NEW_ID, get_of(), get_sf()) : get_cf();
+ if (GetSize(cached_lt) == 0) {
+ if (is_signed) {
+ get_of();
+ get_sf();
+ cached_lt = alu_cell->module->Xor(NEW_ID, cached_of, cached_sf);
+ }
+ else
+ cached_lt = get_cf();
+ }
return cached_lt;
}
RTLIL::SigSpec get_gt() {
- if (GetSize(cached_gt) == 0)
- cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()), false, alu_cell->get_src_attribute());
+ if (GetSize(cached_gt) == 0) {
+ get_lt();
+ get_eq();
+ SigSpec Or = alu_cell->module->Or(NEW_ID, cached_lt, cached_eq);
+ cached_gt = alu_cell->module->Not(NEW_ID, Or, false, alu_cell->get_src_attribute());
+ }
return cached_gt;
}
diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc
index a38638e0b..5f30817d4 100644
--- a/passes/techmap/attrmap.cc
+++ b/passes/techmap/attrmap.cc
@@ -143,6 +143,82 @@ void attrmap_apply(string objname, vector<std::unique_ptr<AttrmapAction>> &actio
attributes.swap(new_attributes);
}
+void log_attrmap_paramap_options()
+{
+ log(" -tocase <name>\n");
+ log(" Match attribute names case-insensitively and set it to the specified\n");
+ log(" name.\n");
+ log("\n");
+ log(" -rename <old_name> <new_name>\n");
+ log(" Rename attributes as specified\n");
+ log("\n");
+ log(" -map <old_name>=<old_value> <new_name>=<new_value>\n");
+ log(" Map key/value pairs as indicated.\n");
+ log("\n");
+ log(" -imap <old_name>=<old_value> <new_name>=<new_value>\n");
+ log(" Like -map, but use case-insensitive match for <old_value> when\n");
+ log(" it is a string value.\n");
+ log("\n");
+ log(" -remove <name>=<value>\n");
+ log(" Remove attributes matching this pattern.\n");
+}
+
+bool parse_attrmap_paramap_options(size_t &argidx, std::vector<std::string> &args, vector<std::unique_ptr<AttrmapAction>> &actions)
+{
+ std::string arg = args[argidx];
+ if (arg == "-tocase" && argidx+1 < args.size()) {
+ auto action = new AttrmapTocase;
+ action->name = args[++argidx];
+ actions.push_back(std::unique_ptr<AttrmapAction>(action));
+ return true;
+ }
+ if (arg == "-rename" && argidx+2 < args.size()) {
+ auto action = new AttrmapRename;
+ action->old_name = args[++argidx];
+ action->new_name = args[++argidx];
+ actions.push_back(std::unique_ptr<AttrmapAction>(action));
+ return true;
+ }
+ if ((arg == "-map" || arg == "-imap") && argidx+2 < args.size()) {
+ string arg1 = args[++argidx];
+ string arg2 = args[++argidx];
+ string val1, val2;
+ size_t p = arg1.find("=");
+ if (p != string::npos) {
+ val1 = arg1.substr(p+1);
+ arg1 = arg1.substr(0, p);
+ }
+ p = arg2.find("=");
+ if (p != string::npos) {
+ val2 = arg2.substr(p+1);
+ arg2 = arg2.substr(0, p);
+ }
+ auto action = new AttrmapMap;
+ action->imap = (arg == "-map");
+ action->old_name = arg1;
+ action->new_name = arg2;
+ action->old_value = val1;
+ action->new_value = val2;
+ actions.push_back(std::unique_ptr<AttrmapAction>(action));
+ return true;
+ }
+ if (arg == "-remove" && argidx+1 < args.size()) {
+ string arg1 = args[++argidx], val1;
+ size_t p = arg1.find("=");
+ if (p != string::npos) {
+ val1 = arg1.substr(p+1);
+ arg1 = arg1.substr(0, p);
+ }
+ auto action = new AttrmapRemove;
+ action->name = arg1;
+ action->has_value = (p != string::npos);
+ action->value = val1;
+ actions.push_back(std::unique_ptr<AttrmapAction>(action));
+ return true;
+ }
+ return false;
+}
+
struct AttrmapPass : public Pass {
AttrmapPass() : Pass("attrmap", "renaming attributes") { }
void help() YS_OVERRIDE
@@ -151,25 +227,10 @@ struct AttrmapPass : public Pass {
log("\n");
log(" attrmap [options] [selection]\n");
log("\n");
- log("This command renames attributes and/or mapps key/value pairs to\n");
+ log("This command renames attributes and/or maps key/value pairs to\n");
log("other key/value pairs.\n");
log("\n");
- log(" -tocase <name>\n");
- log(" Match attribute names case-insensitively and set it to the specified\n");
- log(" name.\n");
- log("\n");
- log(" -rename <old_name> <new_name>\n");
- log(" Rename attributes as specified\n");
- log("\n");
- log(" -map <old_name>=<old_value> <new_name>=<new_value>\n");
- log(" Map key/value pairs as indicated.\n");
- log("\n");
- log(" -imap <old_name>=<old_value> <new_name>=<new_value>\n");
- log(" Like -map, but use case-insensitive match for <old_value> when\n");
- log(" it is a string value.\n");
- log("\n");
- log(" -remove <name>=<value>\n");
- log(" Remove attributes matching this pattern.\n");
+ log_attrmap_paramap_options();
log("\n");
log(" -modattr\n");
log(" Operate on module attributes instead of attributes on wires and cells.\n");
@@ -190,58 +251,9 @@ struct AttrmapPass : public Pass {
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
- std::string arg = args[argidx];
- if (arg == "-tocase" && argidx+1 < args.size()) {
- auto action = new AttrmapTocase;
- action->name = args[++argidx];
- actions.push_back(std::unique_ptr<AttrmapAction>(action));
+ if (parse_attrmap_paramap_options(argidx, args, actions))
continue;
- }
- if (arg == "-rename" && argidx+2 < args.size()) {
- auto action = new AttrmapRename;
- action->old_name = args[++argidx];
- action->new_name = args[++argidx];
- actions.push_back(std::unique_ptr<AttrmapAction>(action));
- continue;
- }
- if ((arg == "-map" || arg == "-imap") && argidx+2 < args.size()) {
- string arg1 = args[++argidx];
- string arg2 = args[++argidx];
- string val1, val2;
- size_t p = arg1.find("=");
- if (p != string::npos) {
- val1 = arg1.substr(p+1);
- arg1 = arg1.substr(0, p);
- }
- p = arg2.find("=");
- if (p != string::npos) {
- val2 = arg2.substr(p+1);
- arg2 = arg2.substr(0, p);
- }
- auto action = new AttrmapMap;
- action->imap = (arg == "-map");
- action->old_name = arg1;
- action->new_name = arg2;
- action->old_value = val1;
- action->new_value = val2;
- actions.push_back(std::unique_ptr<AttrmapAction>(action));
- continue;
- }
- if (arg == "-remove" && argidx+1 < args.size()) {
- string arg1 = args[++argidx], val1;
- size_t p = arg1.find("=");
- if (p != string::npos) {
- val1 = arg1.substr(p+1);
- arg1 = arg1.substr(0, p);
- }
- auto action = new AttrmapRemove;
- action->name = arg1;
- action->has_value = (p != string::npos);
- action->value = val1;
- actions.push_back(std::unique_ptr<AttrmapAction>(action));
- continue;
- }
- if (arg == "-modattr") {
+ if (args[argidx] == "-modattr") {
modattr_mode = true;
continue;
}
@@ -287,4 +299,43 @@ struct AttrmapPass : public Pass {
}
} AttrmapPass;
+struct ParamapPass : public Pass {
+ ParamapPass() : Pass("paramap", "renaming cell parameters") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" paramap [options] [selection]\n");
+ log("\n");
+ log("This command renames cell parameters and/or maps key/value pairs to\n");
+ log("other key/value pairs.\n");
+ log("\n");
+ log_attrmap_paramap_options();
+ log("\n");
+ log("For example, mapping Diamond-style ECP5 \"init\" attributes to Yosys-style:\n");
+ log("\n");
+ log(" paramap -tocase INIT t:LUT4\n");
+ log("\n");
+ }
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ log_header(design, "Executing PARAMAP pass (move or copy cell parameters).\n");
+
+ vector<std::unique_ptr<AttrmapAction>> actions;
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ if (parse_attrmap_paramap_options(argidx, args, actions))
+ continue;
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ for (auto module : design->selected_modules())
+ for (auto cell : module->selected_cells())
+ attrmap_apply(stringf("%s.%s", log_id(module), log_id(cell)), actions, cell->parameters);
+ }
+} ParamapPass;
+
PRIVATE_NAMESPACE_END
diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc
new file mode 100644
index 000000000..246932d81
--- /dev/null
+++ b/passes/techmap/clkbufmap.cc
@@ -0,0 +1,298 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2019 Marcin Kościelnicki <mwk@0x04.net>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+void split_portname_pair(std::string &port1, std::string &port2)
+{
+ size_t pos = port1.find_first_of(':');
+ if (pos != std::string::npos) {
+ port2 = port1.substr(pos+1);
+ port1 = port1.substr(0, pos);
+ }
+}
+
+struct ClkbufmapPass : public Pass {
+ ClkbufmapPass() : Pass("clkbufmap", "insert global buffers on clock networks") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" clkbufmap [options] [selection]\n");
+ log("\n");
+ log("Inserts global buffers between nets connected to clock inputs and their drivers.\n");
+ log("\n");
+ log("In the absence of any selection, all wires without the 'clkbuf_inhibit'\n");
+ log("attribute will be considered for global buffer insertion.\n");
+ log("Alternatively, to consider all wires without the 'buffer_type' attribute set to\n");
+ log("'none' or 'bufr' one would specify:\n");
+ log(" 'w:* a:buffer_type=none a:buffer_type=bufr %%u %%d'\n");
+ log("as the selection.\n");
+ log("\n");
+ log(" -buf <celltype> <portname_out>:<portname_in>\n");
+ log(" Specifies the cell type to use for the global buffers\n");
+ log(" and its port names. The first port will be connected to\n");
+ log(" the clock network sinks, and the second will be connected\n");
+ log(" to the actual clock source. This option is required.\n");
+ log("\n");
+ log(" -inpad <celltype> <portname_out>:<portname_in>\n");
+ log(" If specified, a PAD cell of the given type is inserted on\n");
+ log(" clock nets that are also top module's inputs (in addition\n");
+ log(" to the global buffer).\n");
+ log("\n");
+ }
+
+ void module_queue(Design *design, Module *module, std::vector<Module *> &modules_sorted, pool<Module *> &modules_processed) {
+ if (modules_processed.count(module))
+ return;
+ for (auto cell : module->cells()) {
+ Module *submodule = design->module(cell->type);
+ if (!submodule)
+ continue;
+ module_queue(design, submodule, modules_sorted, modules_processed);
+ }
+ modules_sorted.push_back(module);
+ modules_processed.insert(module);
+ }
+
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ log_header(design, "Executing CLKBUFMAP pass (inserting global clock buffers).\n");
+
+ std::string buf_celltype, buf_portname, buf_portname2;
+ std::string inpad_celltype, inpad_portname, inpad_portname2;
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ std::string arg = args[argidx];
+ if (arg == "-buf" && argidx+2 < args.size()) {
+ buf_celltype = args[++argidx];
+ buf_portname = args[++argidx];
+ split_portname_pair(buf_portname, buf_portname2);
+ continue;
+ }
+ if (arg == "-inpad" && argidx+2 < args.size()) {
+ inpad_celltype = args[++argidx];
+ inpad_portname = args[++argidx];
+ split_portname_pair(inpad_portname, inpad_portname2);
+ continue;
+ }
+ break;
+ }
+
+ bool select = false;
+ if (argidx < args.size()) {
+ if (args[argidx].compare(0, 1, "-") != 0)
+ select = true;
+ extra_args(args, argidx, design);
+ }
+
+ if (buf_celltype.empty())
+ log_error("The -buf option is required.\n");
+
+ // Cell type, port name, bit index.
+ pool<pair<IdString, pair<IdString, int>>> sink_ports;
+ pool<pair<IdString, pair<IdString, int>>> buf_ports;
+
+ // Process submodules before module using them.
+ std::vector<Module *> modules_sorted;
+ pool<Module *> modules_processed;
+ for (auto module : design->selected_modules())
+ module_queue(design, module, modules_sorted, modules_processed);
+
+ for (auto module : modules_sorted)
+ {
+ if (module->get_blackbox_attribute()) {
+ for (auto port : module->ports) {
+ auto wire = module->wire(port);
+ if (wire->get_bool_attribute("\\clkbuf_driver"))
+ for (int i = 0; i < GetSize(wire); i++)
+ buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
+ if (wire->get_bool_attribute("\\clkbuf_sink"))
+ for (int i = 0; i < GetSize(wire); i++)
+ sink_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
+ }
+ continue;
+ }
+ pool<SigBit> sink_wire_bits;
+ pool<SigBit> buf_wire_bits;
+ pool<SigBit> driven_wire_bits;
+ SigMap sigmap(module);
+ // bit -> (buffer, buffer's input)
+ dict<SigBit, pair<Cell *, Wire *>> buffered_bits;
+
+ // First, collect nets that could use a clock buffer.
+ for (auto cell : module->cells())
+ for (auto port : cell->connections())
+ for (int i = 0; i < port.second.size(); i++)
+ if (sink_ports.count(make_pair(cell->type, make_pair(port.first, i))))
+ sink_wire_bits.insert(sigmap(port.second[i]));
+
+ // Second, collect ones that already have a clock buffer.
+ for (auto cell : module->cells())
+ for (auto port : cell->connections())
+ for (int i = 0; i < port.second.size(); i++)
+ if (buf_ports.count(make_pair(cell->type, make_pair(port.first, i))))
+ buf_wire_bits.insert(sigmap(port.second[i]));
+
+ // Collect all driven bits.
+ for (auto cell : module->cells())
+ for (auto port : cell->connections())
+ if (cell->output(port.first))
+ for (int i = 0; i < port.second.size(); i++)
+ driven_wire_bits.insert(port.second[i]);
+
+ // Insert buffers.
+ std::vector<pair<Wire *, Wire *>> input_queue;
+ // Copy current wire list, as we will be adding new ones during iteration.
+ std::vector<Wire *> wires(module->wires());
+ for (auto wire : wires)
+ {
+ // Should not happen.
+ if (wire->port_input && wire->port_output)
+ continue;
+ bool process_wire = module->selected(wire);
+ if (!select && wire->get_bool_attribute("\\clkbuf_inhibit"))
+ process_wire = false;
+ if (!process_wire) {
+ // This wire is supposed to be bypassed, so make sure we don't buffer it in
+ // some buffer higher up in the hierarchy.
+ if (wire->port_output)
+ for (int i = 0; i < GetSize(wire); i++)
+ buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
+ continue;
+ }
+
+ pool<int> input_bits;
+
+ for (int i = 0; i < GetSize(wire); i++)
+ {
+ SigBit wire_bit(wire, i);
+ SigBit mapped_wire_bit = sigmap(wire_bit);
+ if (buf_wire_bits.count(mapped_wire_bit)) {
+ // Already buffered downstream. If this is an output, mark it.
+ if (wire->port_output)
+ buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
+ } else if (!sink_wire_bits.count(mapped_wire_bit)) {
+ // Nothing to do.
+ } else if (driven_wire_bits.count(wire_bit) || (wire->port_input && module->get_bool_attribute("\\top"))) {
+ // Clock network not yet buffered, driven by one of
+ // our cells or a top-level input -- buffer it.
+
+ log("Inserting %s on %s.%s[%d].\n", buf_celltype.c_str(), log_id(module), log_id(wire), i);
+ RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(buf_celltype));
+ Wire *iwire = module->addWire(NEW_ID);
+ cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit);
+ cell->setPort(RTLIL::escape_id(buf_portname2), iwire);
+ if (wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute("\\top")) {
+ log("Inserting %s on %s.%s[%d].\n", inpad_celltype.c_str(), log_id(module), log_id(wire), i);
+ RTLIL::Cell *cell2 = module->addCell(NEW_ID, RTLIL::escape_id(inpad_celltype));
+ cell2->setPort(RTLIL::escape_id(inpad_portname), iwire);
+ iwire = module->addWire(NEW_ID);
+ cell2->setPort(RTLIL::escape_id(inpad_portname2), iwire);
+ }
+ buffered_bits[mapped_wire_bit] = make_pair(cell, iwire);
+
+ if (wire->port_input) {
+ input_bits.insert(i);
+ }
+ } else if (wire->port_input) {
+ // A clock input in a submodule -- mark it, let higher level
+ // worry about it.
+ if (wire->port_input)
+ sink_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
+ }
+ }
+ if (!input_bits.empty()) {
+ // This is an input port and some buffers were inserted -- we need
+ // to create a new input wire and transfer attributes.
+ Wire *new_wire = module->addWire(NEW_ID, wire);
+
+ for (int i = 0; i < wire->width; i++) {
+ SigBit wire_bit(wire, i);
+ SigBit mapped_wire_bit = sigmap(wire_bit);
+ auto it = buffered_bits.find(mapped_wire_bit);
+ if (it != buffered_bits.end()) {
+
+ module->connect(it->second.second, SigSpec(new_wire, i));
+ } else {
+ module->connect(SigSpec(wire, i), SigSpec(new_wire, i));
+ }
+ }
+ input_queue.push_back(make_pair(wire, new_wire));
+ }
+ }
+
+ // Mark any newly-buffered output ports as such.
+ for (auto wire : module->selected_wires()) {
+ if (wire->port_input || !wire->port_output)
+ continue;
+ for (int i = 0; i < GetSize(wire); i++)
+ {
+ SigBit wire_bit(wire, i);
+ SigBit mapped_wire_bit = sigmap(wire_bit);
+ if (buffered_bits.count(mapped_wire_bit))
+ buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
+ }
+ }
+
+ // Reconnect the drivers to buffer inputs.
+ for (auto cell : module->cells())
+ for (auto port : cell->connections()) {
+ if (!cell->output(port.first))
+ continue;
+ SigSpec sig = port.second;
+ bool newsig = false;
+ for (auto &bit : sig) {
+ const auto it = buffered_bits.find(sigmap(bit));
+ if (it == buffered_bits.end())
+ continue;
+ // Avoid substituting buffer's own output pin.
+ if (cell == it->second.first)
+ continue;
+ bit = it->second.second;
+ newsig = true;
+ }
+ if (newsig)
+ cell->setPort(port.first, sig);
+ }
+
+ // This has to be done last, to avoid upsetting sigmap before the port reconnections.
+ for (auto &it : input_queue) {
+ Wire *wire = it.first;
+ Wire *new_wire = it.second;
+ module->swap_names(new_wire, wire);
+ wire->attributes.clear();
+ wire->port_id = 0;
+ wire->port_input = false;
+ wire->port_output = false;
+ }
+
+ module->fixup_ports();
+ }
+ }
+} ClkbufmapPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/techmap/dff2dffs.cc b/passes/techmap/dff2dffs.cc
index 0ea033513..3fa1ed5cf 100644
--- a/passes/techmap/dff2dffs.cc
+++ b/passes/techmap/dff2dffs.cc
@@ -34,11 +34,16 @@ struct Dff2dffsPass : public Pass {
log("Merge synchronous set/reset $_MUX_ cells to create $__DFFS_[NP][NP][01], to be run before\n");
log("dff2dffe for SR over CE priority.\n");
log("\n");
+ log(" -match-init\n");
+ log(" Disallow merging synchronous set/reset that has polarity opposite of the\n");
+ log(" output wire's init attribute (if any).\n");
+ log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
log_header(design, "Executing dff2dffs pass (merge synchronous set/reset into FF cells).\n");
+ bool match_init = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
@@ -46,6 +51,10 @@ struct Dff2dffsPass : public Pass {
// singleton_mode = true;
// continue;
// }
+ if (args[argidx] == "-match-init") {
+ match_init = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
@@ -96,9 +105,6 @@ struct Dff2dffsPass : public Pass {
SigBit bit_b = sigmap(mux_cell->getPort(ID::B));
SigBit bit_s = sigmap(mux_cell->getPort(ID(S)));
- log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
- log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type));
-
SigBit sr_val, sr_sig;
bool invert_sr;
sr_sig = bit_s;
@@ -113,6 +119,23 @@ struct Dff2dffsPass : public Pass {
invert_sr = false;
}
+ if (match_init) {
+ SigBit bit_q = cell->getPort(ID(Q));
+ if (bit_q.wire) {
+ auto it = bit_q.wire->attributes.find(ID(init));
+ if (it != bit_q.wire->attributes.end()) {
+ auto init_val = it->second[bit_q.offset];
+ if (init_val == State::S1 && sr_val != State::S1)
+ continue;
+ if (init_val == State::S0 && sr_val != State::S0)
+ continue;
+ }
+ }
+ }
+
+ log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
+ log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type));
+
if (sr_val == State::S1) {
if (cell->type == ID($_DFF_N_)) {
if (invert_sr) cell->type = ID($__DFFS_NN1_);
diff --git a/passes/techmap/extractinv.cc b/passes/techmap/extractinv.cc
new file mode 100644
index 000000000..dda71f12a
--- /dev/null
+++ b/passes/techmap/extractinv.cc
@@ -0,0 +1,123 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2019 Marcin Kościelnicki <mwk@0x04.net>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+void split_portname_pair(std::string &port1, std::string &port2)
+{
+ size_t pos = port1.find_first_of(':');
+ if (pos != std::string::npos) {
+ port2 = port1.substr(pos+1);
+ port1 = port1.substr(0, pos);
+ }
+}
+
+struct ExtractinvPass : public Pass {
+ ExtractinvPass() : Pass("extractinv", "extract explicit inverter cells for invertible cell pins") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" extractinv [options] [selection]\n");
+ log("\n");
+ log("Searches the design for all cells with invertible pins controlled by a cell\n");
+ log("parameter (eg. IS_CLK_INVERTED on many Xilinx cells) and removes the parameter.\n");
+ log("If the parameter was set to 1, inserts an explicit inverter cell in front of\n");
+ log("the pin instead. Normally used for output to ISE, which does not support the\n");
+ log("inversion parameters.\n");
+ log("\n");
+ log("To mark a cell port as invertible, use (* invertible_pin = \"param_name\" *)\n");
+ log("on the wire in the blackbox module. The parameter value should have\n");
+ log("the same width as the port, and will be effectively XORed with it.\n");
+ log("\n");
+ log(" -inv <celltype> <portname_out>:<portname_in>\n");
+ log(" Specifies the cell type to use for the inverters and its port names.\n");
+ log(" This option is required.\n");
+ log("\n");
+ }
+
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ log_header(design, "Executing EXTRACTINV pass (extracting pin inverters).\n");
+
+ std::string inv_celltype, inv_portname, inv_portname2;
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ std::string arg = args[argidx];
+ if (arg == "-inv" && argidx+2 < args.size()) {
+ inv_celltype = args[++argidx];
+ inv_portname = args[++argidx];
+ split_portname_pair(inv_portname, inv_portname2);
+ continue;
+ }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ if (inv_celltype.empty())
+ log_error("The -inv option is required.\n");
+
+ for (auto module : design->selected_modules())
+ {
+ for (auto cell : module->selected_cells())
+ for (auto port : cell->connections()) {
+ auto cell_module = design->module(cell->type);
+ if (!cell_module)
+ continue;
+ auto cell_wire = cell_module->wire(port.first);
+ if (!cell_wire)
+ continue;
+ auto it = cell_wire->attributes.find("\\invertible_pin");
+ if (it == cell_wire->attributes.end())
+ continue;
+ IdString param_name = RTLIL::escape_id(it->second.decode_string());
+ auto it2 = cell->parameters.find(param_name);
+ // Inversion not used -- skip.
+ if (it2 == cell->parameters.end())
+ continue;
+ SigSpec sig = port.second;
+ if (it2->second.size() != sig.size())
+ log_error("The inversion parameter needs to be the same width as the port (%s.%s port %s parameter %s)", log_id(module->name), log_id(cell->type), log_id(port.first), log_id(param_name));
+ RTLIL::Const invmask = it2->second;
+ cell->parameters.erase(param_name);
+ if (invmask.is_fully_zero())
+ continue;
+ Wire *iwire = module->addWire(NEW_ID, sig.size());
+ for (int i = 0; i < sig.size(); i++)
+ if (invmask[i] == State::S1) {
+ RTLIL::Cell *icell = module->addCell(NEW_ID, RTLIL::escape_id(inv_celltype));
+ icell->setPort(RTLIL::escape_id(inv_portname), SigSpec(iwire, i));
+ icell->setPort(RTLIL::escape_id(inv_portname2), sig[i]);
+ log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype.c_str(), log_id(module), log_id(cell->type), log_id(port.first), i);
+ sig[i] = SigBit(iwire, i);
+ }
+ cell->setPort(port.first, sig);
+ }
+ }
+ }
+} ExtractinvPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index a2551316f..c868b9a87 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -64,6 +64,11 @@ struct IopadmapPass : public Pass {
log(" of the tristate driver and the 2nd portname is the internal output\n");
log(" buffering the external signal.\n");
log("\n");
+ log(" -ignore <celltype> <portname>[:<portname>]*\n");
+ log(" Skips mapping inputs/outputs that are already connected to given\n");
+ log(" ports of the given cell. Can be used multiple times. This is in\n");
+ log(" addition to the cells specified as mapping targets.\n");
+ log("\n");
log(" -widthparam <param_name>\n");
log(" Use the specified parameter name to set the port width.\n");
log("\n");
@@ -88,6 +93,7 @@ struct IopadmapPass : public Pass {
std::string toutpad_celltype, toutpad_portname, toutpad_portname2, toutpad_portname3;
std::string tinoutpad_celltype, tinoutpad_portname, tinoutpad_portname2, tinoutpad_portname3, tinoutpad_portname4;
std::string widthparam, nameparam;
+ pool<pair<IdString, IdString>> ignore;
bool flag_bits = false;
size_t argidx;
@@ -127,6 +133,18 @@ struct IopadmapPass : public Pass {
split_portname_pair(tinoutpad_portname3, tinoutpad_portname4);
continue;
}
+ if (arg == "-ignore" && argidx+2 < args.size()) {
+ std::string ignore_celltype = args[++argidx];
+ std::string ignore_portname = args[++argidx];
+ std::string ignore_portname2;
+ while (!ignore_portname.empty()) {
+ split_portname_pair(ignore_portname, ignore_portname2);
+ ignore.insert(make_pair(RTLIL::escape_id(ignore_celltype), RTLIL::escape_id(ignore_portname)));
+
+ ignore_portname = ignore_portname2;
+ }
+ continue;
+ }
if (arg == "-widthparam" && argidx+1 < args.size()) {
widthparam = args[++argidx];
continue;
@@ -143,6 +161,23 @@ struct IopadmapPass : public Pass {
}
extra_args(args, argidx, design);
+ if (!inpad_portname2.empty())
+ ignore.insert(make_pair(RTLIL::escape_id(inpad_celltype), RTLIL::escape_id(inpad_portname2)));
+ if (!outpad_portname2.empty())
+ ignore.insert(make_pair(RTLIL::escape_id(outpad_celltype), RTLIL::escape_id(outpad_portname2)));
+ if (!inoutpad_portname2.empty())
+ ignore.insert(make_pair(RTLIL::escape_id(inoutpad_celltype), RTLIL::escape_id(inoutpad_portname2)));
+ if (!toutpad_portname3.empty())
+ ignore.insert(make_pair(RTLIL::escape_id(toutpad_celltype), RTLIL::escape_id(toutpad_portname3)));
+ if (!tinoutpad_portname4.empty())
+ ignore.insert(make_pair(RTLIL::escape_id(tinoutpad_celltype), RTLIL::escape_id(tinoutpad_portname4)));
+
+ for (auto module : design->modules())
+ if (module->get_blackbox_attribute())
+ for (auto wire : module->wires())
+ if (wire->get_bool_attribute("\\iopad_external_pin"))
+ ignore.insert(make_pair(module->name, wire->name));
+
for (auto module : design->selected_modules())
{
dict<IdString, pool<int>> skip_wires;
@@ -150,28 +185,11 @@ struct IopadmapPass : public Pass {
SigMap sigmap(module);
for (auto cell : module->cells())
- {
- if (cell->type == RTLIL::escape_id(inpad_celltype) && cell->hasPort(RTLIL::escape_id(inpad_portname2)))
- for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(inpad_portname2))))
+ for (auto port : cell->connections())
+ if (ignore.count(make_pair(cell->type, port.first)))
+ for (auto bit : sigmap(port.second))
skip_wire_bits.insert(bit);
- if (cell->type == RTLIL::escape_id(outpad_celltype) && cell->hasPort(RTLIL::escape_id(outpad_portname2)))
- for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(outpad_portname2))))
- skip_wire_bits.insert(bit);
-
- if (cell->type == RTLIL::escape_id(inoutpad_celltype) && cell->hasPort(RTLIL::escape_id(inoutpad_portname2)))
- for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(inoutpad_portname2))))
- skip_wire_bits.insert(bit);
-
- if (cell->type == RTLIL::escape_id(toutpad_celltype) && cell->hasPort(RTLIL::escape_id(toutpad_portname3)))
- for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(toutpad_portname3))))
- skip_wire_bits.insert(bit);
-
- if (cell->type == RTLIL::escape_id(tinoutpad_celltype) && cell->hasPort(RTLIL::escape_id(tinoutpad_portname4)))
- for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(tinoutpad_portname4))))
- skip_wire_bits.insert(bit);
- }
-
if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty())
{
dict<SigBit, pair<IdString, pool<IdString>>> tbuf_bits;
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc
index 5e298d8dd..be00e5030 100644
--- a/passes/techmap/shregmap.cc
+++ b/passes/techmap/shregmap.cc
@@ -26,9 +26,7 @@ PRIVATE_NAMESPACE_BEGIN
struct ShregmapTech
{
virtual ~ShregmapTech() { }
- virtual void init(const Module * /*module*/, const SigMap &/*sigmap*/) {}
- virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {}
- virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) = 0;
+ virtual bool analyze(vector<int> &taps) = 0;
virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) = 0;
};
@@ -56,7 +54,7 @@ struct ShregmapOptions
struct ShregmapTechGreenpak4 : ShregmapTech
{
- bool analyze(vector<int> &taps, const vector<SigBit> &/*qbits*/)
+ bool analyze(vector<int> &taps)
{
if (GetSize(taps) > 2 && taps[0] == 0 && taps[2] < 17) {
taps.clear();
@@ -93,155 +91,6 @@ struct ShregmapTechGreenpak4 : ShregmapTech
}
};
-struct ShregmapTechXilinx7 : ShregmapTech
-{
- dict<SigBit, std::tuple<Cell*,int,int>> sigbit_to_shiftx_offset;
- const ShregmapOptions &opts;
-
- ShregmapTechXilinx7(const ShregmapOptions &opts) : opts(opts) {}
-
- virtual void init(const Module* module, const SigMap &sigmap) override
- {
- for (const auto &i : module->cells_) {
- auto cell = i.second;
- if (cell->type == ID($shiftx)) {
- if (cell->getParam(ID(Y_WIDTH)) != 1) continue;
- int j = 0;
- for (auto bit : sigmap(cell->getPort(ID::A)))
- sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, j++, 0);
- log_assert(j == cell->getParam(ID(A_WIDTH)).as_int());
- }
- else if (cell->type == ID($mux)) {
- int j = 0;
- for (auto bit : sigmap(cell->getPort(ID::A)))
- sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 0, j++);
- j = 0;
- for (auto bit : sigmap(cell->getPort(ID::B)))
- sigbit_to_shiftx_offset[bit] = std::make_tuple(cell, 1, j++);
- }
- }
- }
-
- virtual void non_chain_user(const SigBit &bit, const Cell *cell, IdString port) override
- {
- auto it = sigbit_to_shiftx_offset.find(bit);
- if (it == sigbit_to_shiftx_offset.end())
- return;
- if (cell) {
- if (cell->type == ID($shiftx) && port == ID::A)
- return;
- if (cell->type == ID($mux) && port.in(ID::A, ID::B))
- return;
- }
- sigbit_to_shiftx_offset.erase(it);
- }
-
- virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) override
- {
- if (GetSize(taps) == 1)
- return taps[0] >= opts.minlen-1 && sigbit_to_shiftx_offset.count(qbits[0]);
-
- if (taps.back() < opts.minlen-1)
- return false;
-
- Cell *shiftx = nullptr;
- int group = 0;
- for (int i = 0; i < GetSize(taps); ++i) {
- auto it = sigbit_to_shiftx_offset.find(qbits[i]);
- if (it == sigbit_to_shiftx_offset.end())
- return false;
-
- // Check taps are sequential
- if (i != taps[i])
- return false;
- // Check taps are not connected to a shift register,
- // or sequential to the same shift register
- if (i == 0) {
- int offset;
- std::tie(shiftx,offset,group) = it->second;
- if (offset != i)
- return false;
- }
- else {
- Cell *shiftx_ = std::get<0>(it->second);
- if (shiftx_ != shiftx)
- return false;
- int offset = std::get<1>(it->second);
- if (offset != i)
- return false;
- int group_ = std::get<2>(it->second);
- if (group_ != group)
- return false;
- }
- }
- log_assert(shiftx);
-
- // Only map if $shiftx exclusively covers the shift register
- if (shiftx->type == ID($shiftx)) {
- if (GetSize(taps) > shiftx->getParam(ID(A_WIDTH)).as_int())
- return false;
- // Due to padding the most significant bits of A may be 1'bx,
- // and if so, discount them
- if (GetSize(taps) < shiftx->getParam(ID(A_WIDTH)).as_int()) {
- const SigSpec A = shiftx->getPort(ID::A);
- const int A_width = shiftx->getParam(ID(A_WIDTH)).as_int();
- for (int i = GetSize(taps); i < A_width; ++i)
- if (A[i] != RTLIL::Sx) return false;
- }
- else if (GetSize(taps) != shiftx->getParam(ID(A_WIDTH)).as_int())
- return false;
- }
- else if (shiftx->type == ID($mux)) {
- if (GetSize(taps) != 2)
- return false;
- }
- else log_abort();
-
- return true;
- }
-
- virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) override
- {
- const auto &tap = *taps.begin();
- auto bit = tap.second;
-
- auto it = sigbit_to_shiftx_offset.find(bit);
- log_assert(it != sigbit_to_shiftx_offset.end());
-
- auto newcell = cell->module->addCell(NEW_ID, ID($__XILINX_SHREG_));
- newcell->set_src_attribute(cell->get_src_attribute());
- newcell->setParam(ID(DEPTH), cell->getParam(ID(DEPTH)));
- newcell->setParam(ID(INIT), cell->getParam(ID(INIT)));
- newcell->setParam(ID(CLKPOL), cell->getParam(ID(CLKPOL)));
- newcell->setParam(ID(ENPOL), cell->getParam(ID(ENPOL)));
-
- newcell->setPort(ID(C), cell->getPort(ID(C)));
- newcell->setPort(ID(D), cell->getPort(ID(D)));
- if (cell->hasPort(ID(E)))
- newcell->setPort(ID(E), cell->getPort(ID(E)));
-
- Cell* shiftx = std::get<0>(it->second);
- RTLIL::SigSpec l_wire, q_wire;
- if (shiftx->type == ID($shiftx)) {
- l_wire = shiftx->getPort(ID::B);
- q_wire = shiftx->getPort(ID::Y);
- shiftx->setPort(ID::Y, cell->module->addWire(NEW_ID));
- }
- else if (shiftx->type == ID($mux)) {
- l_wire = shiftx->getPort(ID(S));
- q_wire = shiftx->getPort(ID::Y);
- shiftx->setPort(ID::Y, cell->module->addWire(NEW_ID));
- }
- else log_abort();
-
- newcell->setPort(ID(Q), q_wire);
- newcell->setPort(ID(L), l_wire);
-
- return false;
- }
-};
-
-
struct ShregmapWorker
{
Module *module;
@@ -264,10 +113,8 @@ struct ShregmapWorker
for (auto wire : module->wires())
{
if (wire->port_output || wire->get_bool_attribute(ID::keep)) {
- for (auto bit : sigmap(wire)) {
+ for (auto bit : sigmap(wire))
sigbit_with_non_chain_users.insert(bit);
- if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {});
- }
}
if (wire->attributes.count(ID(init))) {
@@ -317,10 +164,8 @@ struct ShregmapWorker
for (auto conn : cell->connections())
if (cell->input(conn.first))
- for (auto bit : sigmap(conn.second)) {
+ for (auto bit : sigmap(conn.second))
sigbit_with_non_chain_users.insert(bit);
- if (opts.tech) opts.tech->non_chain_user(bit, cell, conn.first);
- }
}
}
@@ -346,7 +191,7 @@ struct ShregmapWorker
IdString q_port = opts.ffcells.at(c1->type).second;
auto c1_conn = c1->connections();
- auto c2_conn = c1->connections();
+ auto c2_conn = c2->connections();
c1_conn.erase(d_port);
c1_conn.erase(q_port);
@@ -425,7 +270,7 @@ struct ShregmapWorker
if (taps.empty() || taps.back() < depth-1)
taps.push_back(depth-1);
- if (opts.tech->analyze(taps, qbits))
+ if (opts.tech->analyze(taps))
break;
taps.pop_back();
@@ -544,9 +389,6 @@ struct ShregmapWorker
ShregmapWorker(Module *module, const ShregmapOptions &opts) :
module(module), sigmap(module), opts(opts), dff_count(0), shreg_count(0)
{
- if (opts.tech)
- opts.tech->init(module, sigmap);
-
make_sigbit_chain_next_prev();
find_chain_start_cells();
@@ -617,11 +459,6 @@ struct ShregmapPass : public Pass {
log("\n");
log(" -tech greenpak4\n");
log(" map to greenpak4 shift registers.\n");
- log(" this option also implies -clkpol pos -zinit\n");
- log("\n");
- log(" -tech xilinx\n");
- log(" map to xilinx dynamic-length shift registers.\n");
- log(" this option also implies -params -init\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -676,12 +513,6 @@ struct ShregmapPass : public Pass {
clkpol = "pos";
opts.zinit = true;
opts.tech = new ShregmapTechGreenpak4;
- }
- else if (tech == "xilinx") {
- opts.init = true;
- opts.params = true;
- enpol = "any_or_none";
- opts.tech = new ShregmapTechXilinx7(opts);
} else {
argidx--;
break;
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index b271c8781..08a1af2d5 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -205,20 +205,57 @@ struct TechmapWorker
}
std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
+ dict<Wire*, IdString> temp_renamed_wires;
+ pool<SigBit> autopurge_tpl_bits;
- for (auto &it : tpl->wires_) {
+ for (auto &it : tpl->wires_)
+ {
if (it.second->port_id > 0)
- positional_ports[stringf("$%d", it.second->port_id)] = it.first;
+ {
+ IdString posportname = stringf("$%d", it.second->port_id);
+ positional_ports[posportname] = it.first;
+
+ if (!flatten_mode && it.second->get_bool_attribute(ID(techmap_autopurge)) &&
+ (!cell->hasPort(it.second->name) || !GetSize(cell->getPort(it.second->name))) &&
+ (!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname))))
+ {
+ if (sigmaps.count(tpl) == 0)
+ sigmaps[tpl].set(tpl);
+
+ for (auto bit : sigmaps.at(tpl)(it.second))
+ if (bit.wire != nullptr)
+ autopurge_tpl_bits.insert(bit);
+ }
+ }
IdString w_name = it.second->name;
apply_prefix(cell->name, w_name);
- RTLIL::Wire *w = module->addWire(w_name, it.second);
- w->port_input = false;
- w->port_output = false;
- w->port_id = 0;
- if (it.second->get_bool_attribute(ID(_techmap_special_)))
- w->attributes.clear();
- if (w->attributes.count(ID(src)))
- w->add_strpool_attribute(ID(src), extra_src_attrs);
+ RTLIL::Wire *w = module->wire(w_name);
+ if (w != nullptr) {
+ if (!flatten_mode || !w->get_bool_attribute(ID(hierconn))) {
+ temp_renamed_wires[w] = w->name;
+ module->rename(w, NEW_ID);
+ w = nullptr;
+ } else {
+ w->attributes.erase(ID(hierconn));
+ if (GetSize(w) < GetSize(it.second)) {
+ log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w),
+ log_id(tpl), log_id(it.second), log_id(module), log_id(cell));
+ w->width = GetSize(it.second);
+ }
+ }
+ }
+ if (w == nullptr) {
+ w = module->addWire(w_name, it.second);
+ w->port_input = false;
+ w->port_output = false;
+ w->port_id = 0;
+ if (!flatten_mode)
+ w->attributes.erase(ID(techmap_autopurge));
+ if (it.second->get_bool_attribute(ID(_techmap_special_)))
+ w->attributes.clear();
+ if (w->attributes.count(ID(src)))
+ w->add_strpool_attribute(ID(src), extra_src_attrs);
+ }
design->select(module, w);
}
@@ -322,6 +359,12 @@ struct TechmapWorker
for (auto &attr : w->attributes) {
if (attr.first == ID(src))
continue;
+ auto lhs = GetSize(extra_connect.first);
+ auto rhs = GetSize(extra_connect.second);
+ if (lhs > rhs)
+ extra_connect.first.remove(rhs, lhs-rhs);
+ else if (rhs > lhs)
+ extra_connect.second.remove(lhs, rhs-lhs);
module->connect(extra_connect);
break;
}
@@ -344,11 +387,31 @@ struct TechmapWorker
if (!flatten_mode && c->type.begins_with("\\$"))
c->type = c->type.substr(1);
- for (auto &it2 : c->connections_) {
- apply_prefix(cell->name, it2.second, module);
- port_signal_map.apply(it2.second);
+ vector<IdString> autopurge_ports;
+
+ for (auto &it2 : c->connections_)
+ {
+ bool autopurge = false;
+ if (!autopurge_tpl_bits.empty()) {
+ autopurge = GetSize(it2.second) != 0;
+ for (auto &bit : sigmaps.at(tpl)(it2.second))
+ if (!autopurge_tpl_bits.count(bit)) {
+ autopurge = false;
+ break;
+ }
+ }
+
+ if (autopurge) {
+ autopurge_ports.push_back(it2.first);
+ } else {
+ apply_prefix(cell->name, it2.second, module);
+ port_signal_map.apply(it2.second);
+ }
}
+ for (auto &it2 : autopurge_ports)
+ c->unsetPort(it2);
+
if (c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
IdString memid = c->getParam(ID(MEMID)).decode_string();
log_assert(memory_renames.count(memid) != 0);
@@ -380,6 +443,16 @@ struct TechmapWorker
}
module->remove(cell);
+
+ for (auto &it : temp_renamed_wires)
+ {
+ Wire *w = it.first;
+ IdString name = it.second;
+ IdString altname = module->uniquify(name);
+ Wire *other_w = module->wire(name);
+ module->rename(other_w, altname);
+ module->rename(w, name);
+ }
}
bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
@@ -396,6 +469,18 @@ struct TechmapWorker
SigMap sigmap(module);
+ dict<SigBit, State> init_bits;
+ pool<SigBit> remove_init_bits;
+
+ for (auto wire : module->wires()) {
+ if (wire->attributes.count("\\init")) {
+ Const value = wire->attributes.at("\\init");
+ for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
+ if (value[i] != State::Sx)
+ init_bits[sigmap(SigBit(wire, i))] = value[i];
+ }
+ }
+
TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
@@ -633,6 +718,17 @@ struct TechmapWorker
bit = RTLIL::SigBit(RTLIL::State::Sx);
parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
}
+ if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn.first))) != 0) {
+ auto sig = sigmap(conn.second);
+ RTLIL::Const value(State::Sx, sig.size());
+ for (int i = 0; i < sig.size(); i++) {
+ auto it = init_bits.find(sig[i]);
+ if (it != init_bits.end()) {
+ value[i] = it->second;
+ }
+ }
+ parameters[stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn.first))] = value;
+ }
}
int unique_bit_id_counter = 0;
@@ -833,7 +929,7 @@ struct TechmapWorker
TechmapWires twd = techmap_find_special_wires(tpl);
for (auto &it : twd) {
- if (it.first != "_TECHMAP_FAIL_" && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_")
+ if (it.first != "_TECHMAP_FAIL_" && (it.first.substr(0, 20) != "_TECHMAP_REMOVEINIT_" || it.first[it.first.size()-1] != '_') && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_")
log_error("Techmap yielded unknown config wire %s.\n", it.first.c_str());
if (techmap_do_cache[tpl])
for (auto &it2 : it.second)
@@ -864,6 +960,23 @@ struct TechmapWorker
mkdebug.off();
}
+ TechmapWires twd = techmap_find_special_wires(tpl);
+ for (auto &it : twd) {
+ if (it.first.substr(0, 20) == "_TECHMAP_REMOVEINIT_") {
+ for (auto &it2 : it.second) {
+ auto val = it2.value.as_const();
+ auto wirename = RTLIL::escape_id(it.first.substr(20, it.first.size() - 20 - 1));
+ auto it = cell->connections().find(wirename);
+ if (it != cell->connections().end()) {
+ auto sig = sigmap(it->second);
+ for (int i = 0; i < sig.size(); i++)
+ if (val[i] == State::S1)
+ remove_init_bits.insert(sig[i]);
+ }
+ }
+ }
+ }
+
if (extern_mode && !in_recursion)
{
std::string m_name = stringf("$extern:%s", log_id(tpl));
@@ -907,6 +1020,25 @@ struct TechmapWorker
handled_cells.insert(cell);
}
+ if (!remove_init_bits.empty()) {
+ for (auto wire : module->wires())
+ if (wire->attributes.count("\\init")) {
+ Const &value = wire->attributes.at("\\init");
+ bool do_cleanup = true;
+ for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
+ SigBit bit = sigmap(SigBit(wire, i));
+ if (remove_init_bits.count(bit))
+ value[i] = State::Sx;
+ else if (value[i] != State::Sx)
+ do_cleanup = false;
+ }
+ if (do_cleanup) {
+ log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire));
+ wire->attributes.erase("\\init");
+ }
+ }
+ }
+
if (log_continue) {
log_header(design, "Continuing TECHMAP pass.\n");
log_continue = false;
@@ -943,7 +1075,8 @@ struct TechmapPass : public Pass {
log(" instead of inlining them.\n");
log("\n");
log(" -max_iter <number>\n");
- log(" only run the specified number of iterations.\n");
+ log(" only run the specified number of iterations on each module.\n");
+ log(" default: unlimited\n");
log("\n");
log(" -recursive\n");
log(" instead of the iterative breadth-first algorithm use a recursive\n");
@@ -980,6 +1113,11 @@ struct TechmapPass : public Pass {
log("will create a wrapper for the cell and then run the command string that the\n");
log("attribute is set to on the wrapper module.\n");
log("\n");
+ log("When a port on a module in the map file has the 'techmap_autopurge' attribute\n");
+ log("set, and that port is not connected in the instantiation that is mapped, then\n");
+ log("then a cell port connected only to such wires will be omitted in the mapped\n");
+ log("version of the circuit.\n");
+ log("\n");
log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
log("the mapping module to the techmap command. At the moment the following special\n");
@@ -1018,6 +1156,13 @@ struct TechmapPass : public Pass {
log("\n");
log(" It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.\n");
log("\n");
+ log(" _TECHMAP_REMOVEINIT_<port-name>_\n");
+ log(" When this wire is set to a constant value, the init attribute of the wire(s)\n");
+ log(" connected to this port will be consumed. This wire must have the same\n");
+ log(" width as the given port, and for every bit that is set to 1 in the value,\n");
+ log(" the corresponding init attribute bit will be changed to 1'bx. If all\n");
+ log(" bits of an init attribute are left as x, it will be removed.\n");
+ log("\n");
log("In addition to this special wires, techmap also supports special parameters in\n");
log("modules in the map file:\n");
log("\n");
@@ -1031,6 +1176,13 @@ struct TechmapPass : public Pass {
log(" former has a 1-bit for each constant input bit and the latter has the\n");
log(" value for this bit. The unused bits of the latter are set to undef (x).\n");
log("\n");
+ log(" _TECHMAP_WIREINIT_<port-name>_\n");
+ log(" When a parameter with this name exists, it will be set to the initial\n");
+ log(" value of the wire(s) connected to the given port, as specified by the init\n");
+ log(" attribute. If the attribute doesn't exist, x will be filled for the\n");
+ log(" missing bits. To remove the init attribute bits used, use the\n");
+ log(" _TECHMAP_REMOVEINIT_*_ wires.\n");
+ log("\n");
log(" _TECHMAP_BITS_CONNMAP_\n");
log(" _TECHMAP_CONNMAP_<port-name>_\n");
log(" For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it\n");
@@ -1157,15 +1309,16 @@ struct TechmapPass : public Pass {
RTLIL::Module *module = *worker.module_queue.begin();
worker.module_queue.erase(module);
+ int module_max_iter = max_iter;
bool did_something = true;
std::set<RTLIL::Cell*> handled_cells;
while (did_something) {
did_something = false;
- if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false))
- did_something = true;
+ if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false))
+ did_something = true;
if (did_something)
module->check();
- if (max_iter > 0 && --max_iter == 0)
+ if (module_max_iter > 0 && --module_max_iter == 0)
break;
}
}
diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc
index bfb1d6642..a5ac3130f 100644
--- a/passes/tests/test_autotb.cc
+++ b/passes/tests/test_autotb.cc
@@ -345,6 +345,9 @@ struct TestAutotbBackend : public Backend {
log("value after initialization. This can e.g. be used to force a reset signal\n");
log("low in order to explore more inner states in a state machine.\n");
log("\n");
+ log("The attribute 'gentb_skip' can be attached to modules to suppress testbench\n");
+ log("generation.\n");
+ log("\n");
log(" -n <int>\n");
log(" number of iterations the test bench should run (default = 1000)\n");
log("\n");
diff --git a/techlibs/anlogic/Makefile.inc b/techlibs/anlogic/Makefile.inc
index 67cf9cf10..9426b5ca5 100644
--- a/techlibs/anlogic/Makefile.inc
+++ b/techlibs/anlogic/Makefile.inc
@@ -1,7 +1,7 @@
OBJS += techlibs/anlogic/synth_anlogic.o
OBJS += techlibs/anlogic/anlogic_eqn.o
-OBJS += techlibs/anlogic/anlogic_determine_init.o
+OBJS += techlibs/anlogic/anlogic_fixcarry.o
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
diff --git a/techlibs/anlogic/anlogic_determine_init.cc b/techlibs/anlogic/anlogic_determine_init.cc
deleted file mode 100644
index c4089dac2..000000000
--- a/techlibs/anlogic/anlogic_determine_init.cc
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "kernel/yosys.h"
-#include "kernel/sigtools.h"
-
-USING_YOSYS_NAMESPACE
-PRIVATE_NAMESPACE_BEGIN
-
-struct AnlogicDetermineInitPass : public Pass {
- AnlogicDetermineInitPass() : Pass("anlogic_determine_init", "Anlogic: Determine the init value of cells") { }
- void help() YS_OVERRIDE
- {
- log("\n");
- log(" anlogic_determine_init [selection]\n");
- log("\n");
- log("Determine the init value of cells that doesn't allow unknown init value.\n");
- log("\n");
- }
-
- Const determine_init(Const init)
- {
- for (int i = 0; i < GetSize(init); i++) {
- if (init[i] != State::S0 && init[i] != State::S1)
- init[i] = State::S0;
- }
-
- return init;
- }
-
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
- {
- log_header(design, "Executing ANLOGIC_DETERMINE_INIT pass (determine init value for cells).\n");
-
- extra_args(args, args.size(), design);
-
- int cnt = 0;
- for (auto module : design->selected_modules())
- {
- for (auto cell : module->selected_cells())
- {
- if (cell->type == "\\EG_LOGIC_DRAM16X4")
- {
- cell->setParam("\\INIT_D0", determine_init(cell->getParam("\\INIT_D0")));
- cell->setParam("\\INIT_D1", determine_init(cell->getParam("\\INIT_D1")));
- cell->setParam("\\INIT_D2", determine_init(cell->getParam("\\INIT_D2")));
- cell->setParam("\\INIT_D3", determine_init(cell->getParam("\\INIT_D3")));
- cnt++;
- }
- }
- }
- log_header(design, "Updated %d cells with determined init value.\n", cnt);
- }
-} AnlogicDetermineInitPass;
-
-PRIVATE_NAMESPACE_END
diff --git a/techlibs/anlogic/anlogic_fixcarry.cc b/techlibs/anlogic/anlogic_fixcarry.cc
new file mode 100644
index 000000000..87164d375
--- /dev/null
+++ b/techlibs/anlogic/anlogic_fixcarry.cc
@@ -0,0 +1,130 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2019 Miodrag Milanovic <miodrag@symbioticeda.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+static SigBit get_bit_or_zero(const SigSpec &sig)
+{
+ if (GetSize(sig) == 0)
+ return State::S0;
+ return sig[0];
+}
+
+static void fix_carry_chain(Module *module)
+{
+ SigMap sigmap(module);
+
+ pool<SigBit> ci_bits;
+ dict<SigBit, SigBit> mapping_bits;
+
+ for (auto cell : module->cells())
+ {
+ if (cell->type == "\\AL_MAP_ADDER") {
+ if (cell->getParam("\\ALUTYPE") != Const("ADD")) continue;
+ SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\a"));
+ SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\b"));
+ if (bit_i0 == State::S0 && bit_i1== State::S0) {
+ SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c"));
+ SigSpec o = cell->getPort("\\o");
+ if (GetSize(o) == 2) {
+ SigBit bit_o = o[0];
+ ci_bits.insert(bit_ci);
+ mapping_bits[bit_ci] = bit_o;
+ }
+ }
+ }
+ }
+ vector<Cell*> adders_to_fix_cells;
+ for (auto cell : module->cells())
+ {
+ if (cell->type == "\\AL_MAP_ADDER") {
+ if (cell->getParam("\\ALUTYPE") != Const("ADD")) continue;
+ SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c"));
+ SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\a"));
+ SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\b"));
+ SigBit canonical_bit = sigmap(bit_ci);
+ if (!ci_bits.count(canonical_bit))
+ continue;
+ if (bit_i0 == State::S0 && bit_i1== State::S0)
+ continue;
+
+ adders_to_fix_cells.push_back(cell);
+ log("Found %s cell named %s with invalid 'c' signal.\n", log_id(cell->type), log_id(cell));
+ }
+ }
+
+ for (auto cell : adders_to_fix_cells)
+ {
+ SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c"));
+ SigBit canonical_bit = sigmap(bit_ci);
+ auto bit = mapping_bits.at(canonical_bit);
+ log("Fixing %s cell named %s breaking carry chain.\n", log_id(cell->type), log_id(cell));
+ Cell *c = module->addCell(NEW_ID, "\\AL_MAP_ADDER");
+ SigBit new_bit = module->addWire(NEW_ID);
+ SigBit dummy_bit = module->addWire(NEW_ID);
+ SigSpec bits;
+ bits.append(dummy_bit);
+ bits.append(new_bit);
+ c->setParam("\\ALUTYPE", Const("ADD_CARRY"));
+ c->setPort("\\a", bit);
+ c->setPort("\\b", State::S0);
+ c->setPort("\\c", State::S0);
+ c->setPort("\\o", bits);
+
+ cell->setPort("\\c", new_bit);
+ }
+
+}
+
+struct AnlogicCarryFixPass : public Pass {
+ AnlogicCarryFixPass() : Pass("anlogic_fixcarry", "Anlogic: fix carry chain") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" anlogic_fixcarry [options] [selection]\n");
+ log("\n");
+ log("Add Anlogic adders to fix carry chain if needed.\n");
+ log("\n");
+ }
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ log_header(design, "Executing anlogic_fixcarry pass (fix invalid carry chain).\n");
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ Module *module = design->top_module();
+
+ if (module == nullptr)
+ log_cmd_error("No top module found.\n");
+
+ fix_carry_chain(module);
+ }
+} AnlogicCarryFixPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/anlogic/arith_map.v b/techlibs/anlogic/arith_map.v
index 6d6a7ca37..1186543da 100644
--- a/techlibs/anlogic/arith_map.v
+++ b/techlibs/anlogic/arith_map.v
@@ -31,7 +31,10 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
- output CO;
+ output [Y_WIDTH-1:0] CO;
+
+ wire CIx;
+ wire [Y_WIDTH-1:0] COx;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
@@ -41,15 +44,16 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
- wire [Y_WIDTH+1:0] COx;
- wire [Y_WIDTH+2:0] C = {COx, CI};
+ wire [Y_WIDTH-1:0] C = { COx, CIx };
wire dummy;
AL_MAP_ADDER #(
.ALUTYPE("ADD_CARRY"))
adder_cin (
- .a(C[0]),
- .o({COx[0], dummy})
+ .a(CI),
+ .b(1'b0),
+ .c(1'b0),
+ .o({CIx, dummy})
);
genvar i;
@@ -59,18 +63,22 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
) adder_i (
.a(AA[i]),
.b(BB[i]),
- .c(C[i+1]),
- .o({COx[i+1],Y[i]})
+ .c(C[i]),
+ .o({COx[i],Y[i]})
);
- end: slice
+
+ wire cout;
+ AL_MAP_ADDER #(
+ .ALUTYPE("ADD"))
+ adder_cout (
+ .a(1'b0),
+ .b(1'b0),
+ .c(COx[i]),
+ .o({cout, CO[i]})
+ );
+ end: slice
endgenerate
- /* End implementation */
- AL_MAP_ADDER #(
- .ALUTYPE("ADD"))
- adder_cout (
- .c(C[Y_WIDTH+1]),
- .o(COx[Y_WIDTH+1])
- );
- assign CO = COx[Y_WIDTH+1];
- assign X = AA ^ BB;
-endmodule
\ No newline at end of file
+
+ /* End implementation */
+ assign X = AA ^ BB;
+endmodule
diff --git a/techlibs/anlogic/cells_sim.v b/techlibs/anlogic/cells_sim.v
index 058e76605..0fba43572 100644
--- a/techlibs/anlogic/cells_sim.v
+++ b/techlibs/anlogic/cells_sim.v
@@ -1,5 +1,5 @@
module AL_MAP_SEQ (
- output q,
+ output reg q,
input ce,
input clk,
input sr,
@@ -9,6 +9,71 @@ module AL_MAP_SEQ (
parameter REGSET = "RESET"; //RESET/SET
parameter SRMUX = "SR"; //SR/INV
parameter SRMODE = "SYNC"; //SYNC/ASYNC
+
+ wire clk_ce;
+ assign clk_ce = ce ? clk : 1'b0;
+
+ wire srmux;
+ generate
+ case (SRMUX)
+ "SR": assign srmux = sr;
+ "INV": assign srmux = ~sr;
+ default: assign srmux = sr;
+ endcase
+ endgenerate
+
+ wire regset;
+ generate
+ case (REGSET)
+ "RESET": assign regset = 1'b0;
+ "SET": assign regset = 1'b1;
+ default: assign regset = 1'b0;
+ endcase
+ endgenerate
+
+ initial q = regset;
+
+ generate
+ if (DFFMODE == "FF")
+ begin
+ if (SRMODE == "ASYNC")
+ begin
+ always @(posedge clk_ce, posedge srmux)
+ if (srmux)
+ q <= regset;
+ else
+ q <= d;
+ end
+ else
+ begin
+ always @(posedge clk_ce)
+ if (srmux)
+ q <= regset;
+ else
+ q <= d;
+ end
+ end
+ else
+ begin
+ // DFFMODE == "LATCH"
+ if (SRMODE == "ASYNC")
+ begin
+ always @(clk_ce, srmux)
+ if (srmux)
+ q <= regset;
+ else
+ q <= d;
+ end
+ else
+ begin
+ always @(clk_ce)
+ if (srmux)
+ q <= regset;
+ else
+ q <= d;
+ end
+ end
+ endgenerate
endmodule
module AL_MAP_LUT1 (
@@ -17,7 +82,8 @@ module AL_MAP_LUT1 (
);
parameter [1:0] INIT = 2'h0;
parameter EQN = "(A)";
- assign o = INIT >> a;
+
+ assign o = a ? INIT[1] : INIT[0];
endmodule
module AL_MAP_LUT2 (
@@ -27,7 +93,9 @@ module AL_MAP_LUT2 (
);
parameter [3:0] INIT = 4'h0;
parameter EQN = "(A)";
- assign o = INIT >> {b, a};
+
+ wire [1:0] s1 = b ? INIT[ 3:2] : INIT[1:0];
+ assign o = a ? s1[1] : s1[0];
endmodule
module AL_MAP_LUT3 (
@@ -38,7 +106,10 @@ module AL_MAP_LUT3 (
);
parameter [7:0] INIT = 8'h0;
parameter EQN = "(A)";
- assign o = INIT >> {c, b, a};
+
+ wire [3:0] s2 = c ? INIT[ 7:4] : INIT[3:0];
+ wire [1:0] s1 = b ? s2[ 3:2] : s2[1:0];
+ assign o = a ? s1[1] : s1[0];
endmodule
module AL_MAP_LUT4 (
@@ -50,7 +121,11 @@ module AL_MAP_LUT4 (
);
parameter [15:0] INIT = 16'h0;
parameter EQN = "(A)";
- assign o = INIT >> {d, c, b, a};
+
+ wire [7:0] s3 = d ? INIT[15:8] : INIT[7:0];
+ wire [3:0] s2 = c ? s3[ 7:4] : s3[3:0];
+ wire [1:0] s1 = b ? s2[ 3:2] : s2[1:0];
+ assign o = a ? s1[1] : s1[0];
endmodule
module AL_MAP_LUT5 (
@@ -100,4 +175,18 @@ module AL_MAP_ADDER (
output [1:0] o
);
parameter ALUTYPE = "ADD";
+
+ generate
+ case (ALUTYPE)
+ "ADD": assign o = a + b + c;
+ "SUB": assign o = a - b - c;
+ "A_LE_B": assign o = a - b - c;
+
+ "ADD_CARRY": assign o = { a, 1'b0 };
+ "SUB_CARRY": assign o = { ~a, 1'b0 };
+ "A_LE_B_CARRY": assign o = { a, 1'b0 };
+ default: assign o = a + b + c;
+ endcase
+ endgenerate
+
endmodule
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
index 620bf3965..b87fc8566 100644
--- a/techlibs/anlogic/synth_anlogic.cc
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -154,7 +154,7 @@ struct SynthAnlogicPass : public ScriptPass
{
run("memory_bram -rules +/anlogic/drams.txt");
run("techmap -map +/anlogic/drams_map.v");
- run("anlogic_determine_init");
+ run("setundef -zero -params t:EG_LOGIC_DRAM16X4");
}
if (check_label("fine"))
@@ -186,6 +186,11 @@ struct SynthAnlogicPass : public ScriptPass
{
run("techmap -map +/anlogic/cells_map.v");
run("clean");
+ }
+
+ if (check_label("map_anlogic"))
+ {
+ run("anlogic_fixcarry");
run("anlogic_eqn");
}
diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index 0e05620bc..de94798af 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -28,3 +28,4 @@ $(eval $(call add_share_file,share,techlibs/common/dff2ff.v))
$(eval $(call add_share_file,share,techlibs/common/gate2lut.v))
$(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
$(eval $(call add_share_file,share,techlibs/common/cells.lib))
+$(eval $(call add_share_file,share,techlibs/common/dummy.box))
diff --git a/techlibs/common/dummy.box b/techlibs/common/dummy.box
new file mode 100644
index 000000000..0c18070a0
--- /dev/null
+++ b/techlibs/common/dummy.box
@@ -0,0 +1 @@
+(dummy) 1 0 0 0
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index 555de9fba..a176357a7 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -175,7 +175,7 @@ struct SynthPass : public ScriptPass
log_cmd_error("This command only operates on fully selected designs!\n");
if (abc == "abc9" && !lut)
- log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)");
+ log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)\n");
log_header(design, "Executing SYNTH pass.\n");
log_push();
diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 73e18112f..9efb6347f 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -1,6 +1,9 @@
-OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o
+OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o \
+ techlibs/ecp5/ecp5_gsr.o
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_ff.vh))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_io.vh))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_bb.v))
@@ -11,6 +14,9 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_unmap.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_model.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g_nowide.lut))
diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box
index c757d137d..a336b4a85 100644
--- a/techlibs/ecp5/abc_5g.box
+++ b/techlibs/ecp5/abc_5g.box
@@ -15,16 +15,16 @@ CCU2C 1 1 9 3
630 379 630 379 526 275 392 141 273
516 516 516 516 412 412 278 278 43
-# Box 2 : TRELLIS_DPR16X4 (16x4 dist ram)
+# Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
# Outputs: DO0, DO1, DO2, DO3
-# name ID w/b ins outs
-TRELLIS_DPR16X4 2 0 14 4
+# name ID w/b ins outs
+$__ABC_DPR16X4_COMB 2 0 8 4
-#DI0 DI1 DI2 DI3 RAD0 RAD1 RAD2 RAD3 WAD0 WAD1 WAD2 WAD3 WCK WRE
-- - - - 141 379 275 379 - - - - - -
-- - - - 141 379 275 379 - - - - - -
-- - - - 141 379 275 379 - - - - - -
-- - - - 141 379 275 379 - - - - - -
+#A0 A1 A2 A3 RAD0 RAD1 RAD2 RAD3
+0 0 0 0 141 379 275 379
+0 0 0 0 141 379 275 379
+0 0 0 0 141 379 275 379
+0 0 0 0 141 379 275 379
# Box 3 : PFUMX (MUX2)
# Outputs: Z
diff --git a/techlibs/ecp5/abc_map.v b/techlibs/ecp5/abc_map.v
new file mode 100644
index 000000000..ffd25f06d
--- /dev/null
+++ b/techlibs/ecp5/abc_map.v
@@ -0,0 +1,24 @@
+// ---------------------------------------
+
+module TRELLIS_DPR16X4 (
+ input [3:0] DI,
+ input [3:0] WAD,
+ input WRE,
+ input WCK,
+ input [3:0] RAD,
+ output [3:0] DO
+);
+ parameter WCKMUX = "WCK";
+ parameter WREMUX = "WRE";
+ parameter [63:0] INITVAL = 64'h0000000000000000;
+ wire [3:0] \$DO ;
+
+ TRELLIS_DPR16X4 #(
+ .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
+ ) _TECHMAP_REPLACE_ (
+ .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
+ .RAD(RAD), .DO(\$DO )
+ );
+
+ \$__ABC_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO));
+endmodule
diff --git a/techlibs/ecp5/abc_model.v b/techlibs/ecp5/abc_model.v
new file mode 100644
index 000000000..56a733b75
--- /dev/null
+++ b/techlibs/ecp5/abc_model.v
@@ -0,0 +1,5 @@
+// ---------------------------------------
+
+(* abc_box_id=2 *)
+module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
+endmodule
diff --git a/techlibs/ecp5/abc_unmap.v b/techlibs/ecp5/abc_unmap.v
new file mode 100644
index 000000000..d43cdd93f
--- /dev/null
+++ b/techlibs/ecp5/abc_unmap.v
@@ -0,0 +1,5 @@
+// ---------------------------------------
+
+module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
+ assign Y = A;
+endmodule
diff --git a/techlibs/ecp5/brams_map.v b/techlibs/ecp5/brams_map.v
index b2c136863..0353cbadb 100644
--- a/techlibs/ecp5/brams_map.v
+++ b/techlibs/ecp5/brams_map.v
@@ -33,7 +33,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
.CLKBMUX(CLKBMUX),
.WRITEMODE_A(WRITEMODE_A),
.WRITEMODE_B("READBEFOREWRITE"),
- .GSR("DISABLED")
+ .GSR("AUTO")
) _TECHMAP_REPLACE_ (
`include "bram_conn_1.vh"
.CLKA(CLK2), .CLKB(CLK3),
@@ -50,7 +50,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
.CLKBMUX(CLKBMUX),
.WRITEMODE_A(WRITEMODE_A),
.WRITEMODE_B("READBEFOREWRITE"),
- .GSR("DISABLED")
+ .GSR("AUTO")
) _TECHMAP_REPLACE_ (
`include "bram_conn_2.vh"
.CLKA(CLK2), .CLKB(CLK3),
@@ -67,7 +67,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
.CLKBMUX(CLKBMUX),
.WRITEMODE_A(WRITEMODE_A),
.WRITEMODE_B("READBEFOREWRITE"),
- .GSR("DISABLED")
+ .GSR("AUTO")
) _TECHMAP_REPLACE_ (
`include "bram_conn_4.vh"
.CLKA(CLK2), .CLKB(CLK3),
@@ -84,7 +84,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
.CLKBMUX(CLKBMUX),
.WRITEMODE_A(WRITEMODE_A),
.WRITEMODE_B("READBEFOREWRITE"),
- .GSR("DISABLED")
+ .GSR("AUTO")
) _TECHMAP_REPLACE_ (
`include "bram_conn_9.vh"
.CLKA(CLK2), .CLKB(CLK3),
@@ -101,7 +101,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
.CLKBMUX(CLKBMUX),
.WRITEMODE_A(WRITEMODE_A),
.WRITEMODE_B("READBEFOREWRITE"),
- .GSR("DISABLED")
+ .GSR("AUTO")
) _TECHMAP_REPLACE_ (
`include "bram_conn_18.vh"
.CLKA(CLK2), .CLKB(CLK3),
diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 223e19b9e..8557053b6 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -664,3 +664,23 @@ module PCSCLKDIV (
);
parameter GSR = "DISABLED";
endmodule
+
+// Note: this module is not marked keep as we want it swept away in synth (sim use only)
+(* blackbox *)
+module PUR (
+ input PUR
+);
+ parameter RST_PULSE = 1;
+endmodule
+
+(* blackbox, keep *)
+module GSR (
+ input GSR
+);
+endmodule
+
+(* blackbox, keep *)
+module SGSR (
+ input GSR, CLK
+);
+endmodule
\ No newline at end of file
diff --git a/techlibs/ecp5/cells_ff.vh b/techlibs/ecp5/cells_ff.vh
new file mode 100644
index 000000000..0c9689ebd
--- /dev/null
+++ b/techlibs/ecp5/cells_ff.vh
@@ -0,0 +1,40 @@
+// Diamond flip-flops
+module FD1P3AX(input D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3AY(input D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3BX(input PD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3DX(input CD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3IX(input CD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1P3JX(input PD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module FD1S3AX(input D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0), .DI(D), .Q(Q)); endmodule
+module FD1S3AY(input D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(0), .DI(D), .Q(Q)); endmodule
+module FD1S3BX(input PD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
+module FD1S3DX(input CD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule
+module FD1S3IX(input CD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule
+module FD1S3JX(input PD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
+
+// TODO: Diamond latches
+// module FL1P3AY(); endmodule
+// module FL1P3AZ(); endmodule
+// module FL1P3BX(); endmodule
+// module FL1P3DX(); endmodule
+// module FL1P3IY(); endmodule
+// module FL1P3JY(); endmodule
+// module FL1S3AX(); endmodule
+// module FL1S3AY(); endmodule
+
+// Diamond I/O registers
+module IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+
+module OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
+module OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
+
+// TODO: Diamond I/O latches
+// module IFS1S1B(input PD, D, SCLK, output Q); endmodule
+// module IFS1S1D(input CD, D, SCLK, output Q); endmodule
+// module IFS1S1I(input PD, D, SCLK, output Q); endmodule
+// module IFS1S1J(input CD, D, SCLK, output Q); endmodule
diff --git a/techlibs/ecp5/cells_io.vh b/techlibs/ecp5/cells_io.vh
new file mode 100644
index 000000000..02e66e8a5
--- /dev/null
+++ b/techlibs/ecp5/cells_io.vh
@@ -0,0 +1,14 @@
+// Diamond I/O buffers
+module IB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module IBPU (input I, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module IBPD (input I, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module OB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule
+module OBZ (input I, T, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBZPU(input I, T, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBZPD(input I, T, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBCO (input I, output OT, OC); OLVDS olvds (.A(I), .Z(OT), .ZN(OC)); endmodule
+module BB (input I, T, output O, inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module BBPU (input I, T, output O, inout B); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module BBPD (input I, T, output O, inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module ILVDS(input A, AN, output Z ); TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule
+module OLVDS(input A, output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule
diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 6985fbbc8..71ae9237b 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -1,105 +1,54 @@
-module \$_DFF_N_ (input D, C, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
-module \$_DFF_P_ (input D, C, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+module \$_DFF_N_ (input D, C, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+module \$_DFF_P_ (input D, C, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
-module \$_DFFE_NN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
-module \$_DFFE_PN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+module \$_DFFE_NN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+module \$_DFFE_PN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
-module \$_DFFE_NP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
-module \$_DFFE_PP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+module \$_DFFE_NP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+module \$_DFFE_PP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
-module \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$__DFFS_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$__DFFS_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$__DFFS_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$__DFFS_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$__DFFS_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$__DFFS_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$__DFFS_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFS_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFS_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFS_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$__DFFS_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$__DFFS_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$__DFFS_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$__DFFS_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFSE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$__DFFSE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$__DFFSE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$__DFFSE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$__DFFSE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$__DFFSE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$__DFFSE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$__DFFSE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$__DFFSE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$__DFFSE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-// TODO: Diamond flip-flops
-// module FD1P3AX(); endmodule
-// module FD1P3AY(); endmodule
-// module FD1P3BX(); endmodule
-// module FD1P3DX(); endmodule
-// module FD1P3IX(); endmodule
-// module FD1P3JX(); endmodule
-// module FD1S3AX(); endmodule
-// module FD1S3AY(); endmodule
-module FD1S3BX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
-module FD1S3DX(input CD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule
-module FD1S3IX(input CD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule
-module FD1S3JX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
-// module FL1P3AY(); endmodule
-// module FL1P3AZ(); endmodule
-// module FL1P3BX(); endmodule
-// module FL1P3DX(); endmodule
-// module FL1P3IY(); endmodule
-// module FL1P3JY(); endmodule
-// module FL1S3AX(); endmodule
-// module FL1S3AY(); endmodule
-
-// Diamond I/O buffers
-module IB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
-module IBPU (input I, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
-module IBPD (input I, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
-module OB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule
-module OBZ (input I, T, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
-module OBZPU(input I, T, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
-module OBZPD(input I, T, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
-module OBCO (input I, output OT, OC); OLVDS _TECHMAP_REPLACE_ (.A(I), .Z(OT), .ZN(OC)); endmodule
-module BB (input I, T, output O, inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
-module BBPU (input I, T, output O, inout B); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
-module BBPD (input I, T, output O, inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
-module ILVDS(input A, AN, output Z); TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule
-module OLVDS(input A, output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule
-
-// Diamond I/O registers
-module IFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-
-module OFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-
-// TODO: Diamond I/O latches
-// module IFS1S1B(input PD, D, SCLK, output Q); endmodule
-// module IFS1S1D(input CD, D, SCLK, output Q); endmodule
-// module IFS1S1I(input PD, D, SCLK, output Q); endmodule
-// module IFS1S1J(input CD, D, SCLK, output Q); endmodule
+`include "cells_ff.vh"
+`include "cells_io.vh"
`ifndef NO_LUT
module \$lut (A, Y);
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 2fcb0369e..db77dc127 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -17,10 +17,12 @@ endmodule
// ---------------------------------------
(* abc_box_id=1, lib_whitebox *)
module CCU2C(
- (* abc_carry *) input CIN,
+ (* abc_carry *)
+ input CIN,
input A0, B0, C0, D0, A1, B1, C1, D1,
output S0, S1,
- (* abc_carry *) output COUT
+ (* abc_carry *)
+ output COUT
);
parameter [15:0] INIT0 = 16'h0000;
parameter [15:0] INIT1 = 16'h0000;
@@ -107,13 +109,13 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
endmodule
// ---------------------------------------
-//(* abc_box_id=2 *)
module TRELLIS_DPR16X4 (
- (* abc_scc_break *) input [3:0] DI,
- (* abc_scc_break *) input [3:0] WAD,
- (* abc_scc_break *) input WRE,
+ input [3:0] DI,
+ input [3:0] WAD,
+ input WRE,
input WCK,
input [3:0] RAD,
+ /* (* abc_arrival=<TODO> *) */
output [3:0] DO
);
parameter WCKMUX = "WCK";
@@ -224,14 +226,15 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
parameter REGSET = "RESET";
parameter [127:0] LSRMODE = "LSR";
- reg muxce;
- always @(*)
+ wire muxce;
+ generate
case (CEMUX)
- "1": muxce = 1'b1;
- "0": muxce = 1'b0;
- "INV": muxce = ~CE;
- default: muxce = CE;
+ "1": assign muxce = 1'b1;
+ "0": assign muxce = 1'b0;
+ "INV": assign muxce = ~CE;
+ default: assign muxce = CE;
endcase
+ endgenerate
wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
@@ -688,56 +691,9 @@ module DP16KD(
parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
endmodule
-// TODO: Diamond flip-flops
-// module FD1P3AX(); endmodule
-// module FD1P3AY(); endmodule
-// module FD1P3BX(); endmodule
-// module FD1P3DX(); endmodule
-// module FD1P3IX(); endmodule
-// module FD1P3JX(); endmodule
-// module FD1S3AX(); endmodule
-// module FD1S3AY(); endmodule
-module FD1S3BX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) tff (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
-module FD1S3DX(input CD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) tff (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule
-module FD1S3IX(input CD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) tff (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule
-module FD1S3JX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) tff (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
-// module FL1P3AY(); endmodule
-// module FL1P3AZ(); endmodule
-// module FL1P3BX(); endmodule
-// module FL1P3DX(); endmodule
-// module FL1P3IY(); endmodule
-// module FL1P3JY(); endmodule
-// module FL1S3AX(); endmodule
-// module FL1S3AY(); endmodule
+`ifndef NO_INCLUDES
-// Diamond I/O buffers
-module IB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT")) tio (.B(I), .O(O)); endmodule
-module IBPU (input I, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("INPUT")) tio (.B(I), .O(O)); endmodule
-module IBPD (input I, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT")) tio (.B(I), .O(O)); endmodule
-module OB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(O), .I(I)); endmodule
-module OBZ (input I, T, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(O), .I(I), .T(T)); endmodule
-module OBZPU(input I, T, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(O), .I(I), .T(T)); endmodule
-module OBZPD(input I, T, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(O), .I(I), .T(T)); endmodule
-module OBCO (input I, output OT, OC); OLVDS olvds (.A(I), .Z(OT), .ZN(OC)); endmodule
-module BB (input I, T, output O, inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) tio (.B(B), .I(I), .O(O), .T(T)); endmodule
-module BBPU (input I, T, output O, inout B); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("BIDIR")) tio (.B(B), .I(I), .O(O), .T(T)); endmodule
-module BBPD (input I, T, output O, inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) tio (.B(B), .I(I), .O(O), .T(T)); endmodule
-module ILVDS(input A, AN, output Z); TRELLIS_IO #(.DIR("INPUT")) tio (.B(A), .O(Z)); endmodule
-module OLVDS(input A, output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) tio (.B(Z), .I(A)); endmodule
+`include "cells_ff.vh"
+`include "cells_io.vh"
-// Diamond I/O registers
-module IFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module IFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-
-module OFS1P3BX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3DX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3IX(input CD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) tff (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule
-module OFS1P3JX(input PD, D, SP, SCLK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) tff (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule
-
-// TODO: Diamond I/O latches
-// module IFS1S1B(input PD, D, SCLK, output Q); endmodule
-// module IFS1S1D(input CD, D, SCLK, output Q); endmodule
-// module IFS1S1I(input PD, D, SCLK, output Q); endmodule
-// module IFS1S1J(input CD, D, SCLK, output Q); endmodule
+`endif
diff --git a/techlibs/ecp5/ecp5_gsr.cc b/techlibs/ecp5/ecp5_gsr.cc
new file mode 100644
index 000000000..2bc714b6f
--- /dev/null
+++ b/techlibs/ecp5/ecp5_gsr.cc
@@ -0,0 +1,135 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2019 David Shah <david@symbioticeda.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct Ecp5GsrPass : public Pass {
+ Ecp5GsrPass() : Pass("ecp5_gsr", "ECP5: handle GSR") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" ecp5_gsr [options] [selection]\n");
+ log("\n");
+ log("Trim active low async resets connected to GSR and resolve GSR parameter,\n");
+ log("if a GSR or SGSR primitive is used in the design.\n");
+ log("\n");
+ log("If any cell has the GSR parameter set to \"AUTO\", this will be resolved\n");
+ log("to \"ENABLED\" if a GSR primitive is present and the (* nogsr *) attribute\n");
+ log("is not set, otherwise it will be resolved to \"DISABLED\".\n");
+ log("\n");
+ }
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ log_header(design, "Executing ECP5_GSR pass (implement FF init values).\n");
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ // if (args[argidx] == "-singleton") {
+ // singleton_mode = true;
+ // continue;
+ // }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ for (auto module : design->selected_modules())
+ {
+ log("Handling GSR in %s.\n", log_id(module));
+
+ SigMap sigmap(module);
+
+ SigBit gsr;
+ bool found_gsr = false;
+
+ for (auto cell : module->selected_cells())
+ {
+ if (cell->type != ID(GSR) && cell->type != ID(SGSR))
+ continue;
+ if (found_gsr)
+ log_error("Found more than one GSR or SGSR cell in module %s.\n", log_id(module));
+ found_gsr = true;
+ SigSpec sig_gsr = cell->getPort(ID(GSR));
+ if (GetSize(sig_gsr) < 1)
+ log_error("GSR cell %s has disconnected GSR input.\n", log_id(cell));
+ gsr = sigmap(sig_gsr[0]);
+ }
+
+ // Resolve GSR parameter
+
+ for (auto cell : module->selected_cells())
+ {
+ if (!cell->hasParam(ID(GSR)) || cell->getParam(ID(GSR)).decode_string() != "AUTO")
+ continue;
+
+ bool gsren = found_gsr;
+ if (cell->get_bool_attribute("\\nogsr"))
+ gsren = false;
+ cell->setParam(ID(GSR), gsren ? Const("ENABLED") : Const("DISABLED"));
+
+ }
+
+ if (!found_gsr)
+ continue;
+
+ // For finding active low FF inputs
+ pool<SigBit> inverted_gsr;
+
+ log_debug("GSR net in module %s is %s.\n", log_id(module), log_signal(gsr));
+ for (auto cell : module->selected_cells())
+ {
+ if (cell->type != ID($_NOT_))
+ continue;
+ SigSpec sig_a = cell->getPort(ID(A)), sig_y = cell->getPort(ID(Y));
+ if (GetSize(sig_a) < 1 || GetSize(sig_y) < 1)
+ continue;
+ SigBit a = sigmap(sig_a[0]);
+ if (a == gsr)
+ inverted_gsr.insert(sigmap(sig_y[0]));
+ }
+
+ for (auto cell : module->selected_cells())
+ {
+ if (cell->type != ID(TRELLIS_FF))
+ continue;
+ if (!cell->hasParam(ID(GSR)) || cell->getParam(ID(GSR)).decode_string() != "ENABLED")
+ continue;
+ if (!cell->hasParam(ID(SRMODE)) || cell->getParam(ID(SRMODE)).decode_string() != "ASYNC")
+ continue;
+ SigSpec sig_lsr = cell->getPort(ID(LSR));
+ if (GetSize(sig_lsr) < 1)
+ continue;
+ SigBit lsr = sigmap(sig_lsr[0]);
+ if (!inverted_gsr.count(lsr))
+ continue;
+ cell->setParam(ID(SRMODE), Const("LSR_OVER_CE"));
+ cell->unsetPort(ID(LSR));
+ }
+
+ }
+ }
+} Ecp5GsrPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 143d1f95c..2593546e0 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -271,6 +271,8 @@ struct SynthEcp5Pass : public ScriptPass
run("opt_expr -undriven -mux_undef");
run("simplemap");
run("ecp5_ffinit");
+ run("ecp5_gsr");
+ run("opt_clean");
}
if (check_label("map_luts"))
@@ -278,12 +280,17 @@ struct SynthEcp5Pass : public ScriptPass
if (abc2 || help_mode) {
run("abc", " (only if -abc2)");
}
- run("techmap -map +/ecp5/latches_map.v");
+ std::string techmap_args = "-map +/ecp5/latches_map.v";
+ if (abc9)
+ techmap_args += " -map +/ecp5/abc_map.v -max_iter 1";
+ run("techmap " + techmap_args);
+
if (abc9) {
if (nowidelut)
run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
else
run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200");
+ run("techmap -map +/ecp5/abc_unmap.v");
} else {
if (nowidelut)
run("abc -lut 4 -dress");
diff --git a/techlibs/ecp5/tests/.gitignore b/techlibs/ecp5/tests/.gitignore
new file mode 100644
index 000000000..0e18132cc
--- /dev/null
+++ b/techlibs/ecp5/tests/.gitignore
@@ -0,0 +1 @@
+work_*
diff --git a/techlibs/ecp5/tests/test_diamond_ffs.py b/techlibs/ecp5/tests/test_diamond_ffs.py
new file mode 100644
index 000000000..1ed85ce8b
--- /dev/null
+++ b/techlibs/ecp5/tests/test_diamond_ffs.py
@@ -0,0 +1,82 @@
+import os
+import subprocess
+
+if not os.path.exists("work_ff"):
+ os.mkdir("work_ff")
+
+modules = []
+
+with open("../cells_ff.vh", "r") as f:
+ with open("work_ff/cells_ff_gate.v", "w") as g:
+ for line in f:
+ if not line.startswith("module"):
+ g.write(line)
+ continue
+ else:
+ spidx = line.find(" ")
+ bridx = line.find("(")
+ modname = line[spidx+1 : bridx]
+ g.write("module %s_gate" % modname)
+ g.write(line[bridx:])
+ inpidx = line.find("input ")
+ outpidx = line.find(", output")
+ modules.append((modname, [x.strip() for x in line[inpidx+6:outpidx].split(",")]))
+
+with open("work_ff/testbench.v", "w") as f:
+ print("""
+`timescale 1ns/ 1ps
+
+module testbench;
+reg pur = 0, clk, rst, cen, d;
+
+// Needed for Diamond sim models
+GSR GSR_INST (.GSR(1'b1));
+PUR PUR_INST (.PUR(pur));
+
+
+initial begin
+ $dumpfile("work_ff/ffs.vcd");
+ $dumpvars(0, testbench);
+ #5;
+ pur = 1;
+ #95;
+ repeat (2500) begin
+ {clk, rst, cen, d} = $random;
+ #10;
+ check_outputs;
+ #1;
+ end
+ $finish;
+end
+ """, file=f)
+
+ for modname, inputs in modules:
+ print(" wire %s_gold_q, %s_gate_q;" % (modname, modname), file=f)
+ portconns = []
+ for inp in inputs:
+ if inp in ("SCLK", "CK"):
+ portconns.append(".%s(clk)" % inp)
+ elif inp in ("CD", "PD"):
+ portconns.append(".%s(rst)" % inp)
+ elif inp == "SP":
+ portconns.append(".%s(cen)" % inp)
+ elif inp == "D":
+ portconns.append(".%s(d)" % inp)
+ else:
+ assert False
+ portconns.append(".Q(%s_gold_q)" % modname)
+ print(" %s %s_gold_i (%s);" % (modname, modname, ", ".join(portconns)), file=f)
+ portconns[-1] = (".Q(%s_gate_q)" % modname)
+ print(" %s_gate %s_gate_i (%s);" % (modname, modname, ", ".join(portconns)), file=f)
+ print("", file=f)
+ print(" task check_outputs;", file=f)
+ print(" begin", file=f)
+ print(" if (%s_gold_q != %s_gate_q) $display(\"MISMATCH at %%1t: %s_gold_q=%%b, %s_gate_q=%%b\", $time, %s_gold_q, %s_gate_q);" %
+ (modname, modname, modname, modname, modname, modname), file=f)
+ print(" end", file=f)
+ print(" endtask", file=f)
+ print("endmodule", file=f)
+
+diamond_models = "/usr/local/diamond/3.10_x64/cae_library/simulation/verilog/ecp5u"
+subprocess.call(["iverilog", "-s", "testbench", "-o", "work_ff/testbench", "-Dmixed_hdl", "-DNO_INCLUDES", "-y", diamond_models, "work_ff/cells_ff_gate.v", "../cells_sim.v", "work_ff/testbench.v"])
+subprocess.call(["vvp", "work_ff/testbench"])
diff --git a/techlibs/efinix/Makefile.inc b/techlibs/efinix/Makefile.inc
new file mode 100644
index 000000000..5013f7fc1
--- /dev/null
+++ b/techlibs/efinix/Makefile.inc
@@ -0,0 +1,10 @@
+
+OBJS += techlibs/efinix/synth_efinix.o
+OBJS += techlibs/efinix/efinix_gbuf.o
+OBJS += techlibs/efinix/efinix_fixcarry.o
+
+$(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v))
+$(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v))
+$(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_sim.v))
+$(eval $(call add_share_file,share/efinix,techlibs/efinix/brams_map.v))
+$(eval $(call add_share_file,share/efinix,techlibs/efinix/bram.txt))
diff --git a/techlibs/efinix/arith_map.v b/techlibs/efinix/arith_map.v
new file mode 100644
index 000000000..178f57bc5
--- /dev/null
+++ b/techlibs/efinix/arith_map.v
@@ -0,0 +1,79 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2018 Miodrag Milanovic <miodrag@symbioticeda.com>
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+(* techmap_celltype = "$alu" *)
+module _80_efinix_alu (A, B, CI, BI, X, Y, CO);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ input [A_WIDTH-1:0] A;
+ input [B_WIDTH-1:0] B;
+ output [Y_WIDTH-1:0] X, Y;
+
+ input CI, BI;
+ output [Y_WIDTH-1:0] CO;
+
+ wire CIx;
+ wire [Y_WIDTH-1:0] COx;
+
+ wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+ wire [Y_WIDTH-1:0] A_buf, B_buf;
+ \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+ \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+ wire [Y_WIDTH-1:0] AA = A_buf;
+ wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
+ wire [Y_WIDTH-1:0] C = { COx, CIx };
+
+ EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
+ adder_cin (
+ .I0(CI),
+ .I1(1'b1),
+ .CI(1'b0),
+ .CO(CIx)
+ );
+
+ genvar i;
+ generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
+ EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
+ adder_i (
+ .I0(AA[i]),
+ .I1(BB[i]),
+ .CI(C[i]),
+ .O(Y[i]),
+ .CO(COx[i])
+ );
+ EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
+ adder_cout (
+ .I0(1'b0),
+ .I1(1'b0),
+ .CI(COx[i]),
+ .O(CO[i])
+ );
+ end: slice
+ endgenerate
+
+ /* End implementation */
+ assign X = AA ^ BB;
+endmodule
\ No newline at end of file
diff --git a/techlibs/efinix/bram.txt b/techlibs/efinix/bram.txt
new file mode 100644
index 000000000..0b3fd9308
--- /dev/null
+++ b/techlibs/efinix/bram.txt
@@ -0,0 +1,32 @@
+bram $__EFINIX_5K
+ init 1
+
+ abits 8 @a8d16
+ dbits 16 @a8d16
+ abits 9 @a9d8
+ dbits 8 @a9d8
+ abits 10 @a10d4
+ dbits 4 @a10d4
+ abits 11 @a11d2
+ dbits 2 @a11d2
+ abits 12 @a12d1
+ dbits 1 @a12d1
+ abits 8 @a8d20
+ dbits 20 @a8d20
+ abits 9 @a9d10
+ dbits 10 @a9d10
+
+ groups 2
+ ports 1 1
+ wrmode 1 0
+ enable 1 1
+ transp 0 2
+ clocks 2 3
+ clkpol 2 3
+endbram
+
+match $__EFINIX_5K
+ min bits 256
+ min efficiency 5
+ shuffle_enable B
+endmatch
diff --git a/techlibs/efinix/brams_map.v b/techlibs/efinix/brams_map.v
new file mode 100644
index 000000000..6786ae769
--- /dev/null
+++ b/techlibs/efinix/brams_map.v
@@ -0,0 +1,65 @@
+module \$__EFINIX_5K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
+ parameter CFG_ABITS = 8;
+ parameter CFG_DBITS = 20;
+ parameter CFG_ENABLE_A = 1;
+
+ parameter CLKPOL2 = 1;
+ parameter CLKPOL3 = 1;
+ parameter [5119:0] INIT = 5119'bx;
+ parameter TRANSP2 = 0;
+
+ input CLK2;
+ input CLK3;
+
+ input [CFG_ABITS-1:0] A1ADDR;
+ input [CFG_DBITS-1:0] A1DATA;
+ input [CFG_ENABLE_A-1:0] A1EN;
+
+ input [CFG_ABITS-1:0] B1ADDR;
+ output [CFG_DBITS-1:0] B1DATA;
+ input B1EN;
+
+ localparam WRITEMODE_A = TRANSP2 ? "WRITE_FIRST" : "READ_FIRST";
+
+ EFX_RAM_5K #(
+ .READ_WIDTH(CFG_DBITS),
+ .WRITE_WIDTH(CFG_DBITS),
+ .OUTPUT_REG(1'b0),
+ .RCLK_POLARITY(1'b1),
+ .RE_POLARITY(1'b1),
+ .WCLK_POLARITY(1'b1),
+ .WE_POLARITY(1'b1),
+ .WCLKE_POLARITY(1'b1),
+ .WRITE_MODE(WRITEMODE_A),
+ .INIT_0(INIT[ 0*256 +: 256]),
+ .INIT_1(INIT[ 1*256 +: 256]),
+ .INIT_2(INIT[ 2*256 +: 256]),
+ .INIT_3(INIT[ 3*256 +: 256]),
+ .INIT_4(INIT[ 4*256 +: 256]),
+ .INIT_5(INIT[ 5*256 +: 256]),
+ .INIT_6(INIT[ 6*256 +: 256]),
+ .INIT_7(INIT[ 7*256 +: 256]),
+ .INIT_8(INIT[ 8*256 +: 256]),
+ .INIT_9(INIT[ 9*256 +: 256]),
+ .INIT_A(INIT[10*256 +: 256]),
+ .INIT_B(INIT[11*256 +: 256]),
+ .INIT_C(INIT[12*256 +: 256]),
+ .INIT_D(INIT[13*256 +: 256]),
+ .INIT_E(INIT[14*256 +: 256]),
+ .INIT_F(INIT[15*256 +: 256]),
+ .INIT_10(INIT[16*256 +: 256]),
+ .INIT_11(INIT[17*256 +: 256]),
+ .INIT_12(INIT[18*256 +: 256]),
+ .INIT_13(INIT[19*256 +: 256])
+ ) _TECHMAP_REPLACE_ (
+ .WDATA(A1DATA),
+ .WADDR(A1ADDR),
+ .WE(A1EN),
+ .WCLK(CLK2),
+ .WCLKE(1'b1),
+ .RDATA(B1DATA),
+ .RADDR(B1ADDR),
+ .RE(B1EN),
+ .RCLK(CLK3)
+ );
+endmodule
diff --git a/techlibs/efinix/cells_map.v b/techlibs/efinix/cells_map.v
new file mode 100644
index 000000000..0aeab1902
--- /dev/null
+++ b/techlibs/efinix/cells_map.v
@@ -0,0 +1,45 @@
+module \$_DFF_N_ (input D, C, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(1'b0), .Q(Q)); endmodule
+module \$_DFF_P_ (input D, C, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(1'b0), .Q(Q)); endmodule
+
+module \$_DFFE_NN_ (input D, C, E, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b0), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(1'b0), .Q(Q)); endmodule
+module \$_DFFE_NP_ (input D, C, E, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(1'b0), .Q(Q)); endmodule
+
+module \$_DFFE_PN_ (input D, C, E, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b0), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(1'b0), .Q(Q)); endmodule
+module \$_DFFE_PP_ (input D, C, E, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b1), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(1'b0), .Q(Q)); endmodule
+
+module \$_DFF_NN0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
+module \$_DFF_NN1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b1), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
+module \$_DFF_PN0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
+module \$_DFF_PN1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b0), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b1), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
+
+module \$_DFF_NP0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
+module \$_DFF_NP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b1), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
+module \$_DFF_PP0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
+module \$_DFF_PP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b1), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule
+
+`ifndef NO_LUT
+module \$lut (A, Y);
+ parameter WIDTH = 0;
+ parameter LUT = 0;
+
+ input [WIDTH-1:0] A;
+ output Y;
+
+ generate
+ if (WIDTH == 1) begin
+ EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(1'b0), .I2(1'b0), .I3(1'b0));
+ end else
+ if (WIDTH == 2) begin
+ EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(1'b0), .I3(1'b0));
+ end else
+ if (WIDTH == 3) begin
+ EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(1'b0));
+ end else
+ if (WIDTH == 4) begin
+ EFX_LUT4 #(.LUTMASK(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
+ end else begin
+ wire _TECHMAP_FAIL_ = 1;
+ end
+ endgenerate
+endmodule
+`endif
diff --git a/techlibs/efinix/cells_sim.v b/techlibs/efinix/cells_sim.v
new file mode 100644
index 000000000..2fc2034a6
--- /dev/null
+++ b/techlibs/efinix/cells_sim.v
@@ -0,0 +1,173 @@
+module EFX_LUT4(
+ output O,
+ input I0,
+ input I1,
+ input I2,
+ input I3
+);
+ parameter LUTMASK = 16'h0000;
+
+ wire [7:0] s3 = I3 ? LUTMASK[15:8] : LUTMASK[7:0];
+ wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
+ wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];
+ assign O = I0 ? s1[1] : s1[0];
+endmodule
+
+module EFX_ADD(
+ output O,
+ output CO,
+ input I0,
+ input I1,
+ input CI
+);
+ parameter I0_POLARITY = 1;
+ parameter I1_POLARITY = 1;
+
+ wire i0;
+ wire i1;
+
+ assign i0 = I0_POLARITY ? I0 : ~I0;
+ assign i1 = I1_POLARITY ? I1 : ~I1;
+
+ assign {CO, O} = i0 + i1 + CI;
+endmodule
+
+module EFX_FF(
+ output reg Q,
+ input D,
+ input CE,
+ input CLK,
+ input SR
+);
+ parameter CLK_POLARITY = 1;
+ parameter CE_POLARITY = 1;
+ parameter SR_POLARITY = 1;
+ parameter SR_SYNC = 0;
+ parameter SR_VALUE = 0;
+ parameter SR_SYNC_PRIORITY = 0;
+ parameter D_POLARITY = 1;
+
+ wire clk;
+ wire ce;
+ wire sr;
+ wire d;
+ wire prio;
+ wire sync;
+ wire async;
+
+ assign clk = CLK_POLARITY ? CLK : ~CLK;
+ assign ce = CE_POLARITY ? CE : ~CE;
+ assign sr = SR_POLARITY ? SR : ~SR;
+ assign d = D_POLARITY ? D : ~D;
+
+ generate
+ if (SR_SYNC == 1)
+ begin
+ if (SR_SYNC_PRIORITY == 1)
+ begin
+ always @(posedge clk)
+ if (sr)
+ Q <= SR_VALUE;
+ else if (ce)
+ Q <= d;
+ end
+ else
+ begin
+ always @(posedge clk)
+ if (ce)
+ begin
+ if (sr)
+ Q <= SR_VALUE;
+ else
+ Q <= d;
+ end
+ end
+ end
+ else
+ begin
+ always @(posedge clk or posedge sr)
+ if (sr)
+ Q <= SR_VALUE;
+ else if (ce)
+ Q <= d;
+
+ end
+ endgenerate
+endmodule
+
+module EFX_GBUFCE(
+ input CE,
+ input I,
+ output O
+);
+ parameter CE_POLARITY = 1'b1;
+
+ wire ce;
+ assign ce = CE_POLARITY ? CE : ~CE;
+
+ assign O = I & ce;
+
+endmodule
+
+module EFX_RAM_5K(
+ input [WRITE_WIDTH-1:0] WDATA,
+ input [WRITE_ADDR_WIDTH-1:0] WADDR,
+ input WE,
+ input WCLK,
+ input WCLKE,
+ output [READ_WIDTH-1:0] RDATA,
+ input [READ_ADDR_WIDTH-1:0] RADDR,
+ input RE,
+ input RCLK
+);
+ parameter READ_WIDTH = 20;
+ parameter WRITE_WIDTH = 20;
+ parameter OUTPUT_REG = 1'b0;
+ parameter RCLK_POLARITY = 1'b1;
+ parameter RE_POLARITY = 1'b1;
+ parameter WCLK_POLARITY = 1'b1;
+ parameter WE_POLARITY = 1'b1;
+ parameter WCLKE_POLARITY = 1'b1;
+ parameter WRITE_MODE = "READ_FIRST";
+ parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+ localparam READ_ADDR_WIDTH =
+ (READ_WIDTH == 16) ? 8 : // 256x16
+ (READ_WIDTH == 8) ? 9 : // 512x8
+ (READ_WIDTH == 4) ? 10 : // 1024x4
+ (READ_WIDTH == 2) ? 11 : // 2048x2
+ (READ_WIDTH == 1) ? 12 : // 4096x1
+ (READ_WIDTH == 20) ? 8 : // 256x20
+ (READ_WIDTH == 10) ? 9 : // 512x10
+ (READ_WIDTH == 5) ? 10 : -1; // 1024x5
+
+ localparam WRITE_ADDR_WIDTH =
+ (WRITE_WIDTH == 16) ? 8 : // 256x16
+ (WRITE_WIDTH == 8) ? 9 : // 512x8
+ (WRITE_WIDTH == 4) ? 10 : // 1024x4
+ (WRITE_WIDTH == 2) ? 11 : // 2048x2
+ (WRITE_WIDTH == 1) ? 12 : // 4096x1
+ (WRITE_WIDTH == 20) ? 8 : // 256x20
+ (WRITE_WIDTH == 10) ? 9 : // 512x10
+ (WRITE_WIDTH == 5) ? 10 : -1; // 1024x5
+
+endmodule
\ No newline at end of file
diff --git a/techlibs/efinix/efinix_fixcarry.cc b/techlibs/efinix/efinix_fixcarry.cc
new file mode 100644
index 000000000..b7cd995b8
--- /dev/null
+++ b/techlibs/efinix/efinix_fixcarry.cc
@@ -0,0 +1,122 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2019 Miodrag Milanovic <miodrag@symbioticeda.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+static SigBit get_bit_or_zero(const SigSpec &sig)
+{
+ if (GetSize(sig) == 0)
+ return State::S0;
+ return sig[0];
+}
+
+static void fix_carry_chain(Module *module)
+{
+ SigMap sigmap(module);
+
+ pool<SigBit> ci_bits;
+ dict<SigBit, SigBit> mapping_bits;
+
+ for (auto cell : module->cells())
+ {
+ if (cell->type == "\\EFX_ADD") {
+ SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\I0"));
+ SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\I1"));
+ if (bit_i0 == State::S0 && bit_i1== State::S0) {
+ SigBit bit_ci = get_bit_or_zero(cell->getPort("\\CI"));
+ SigBit bit_o = sigmap(cell->getPort("\\O"));
+ ci_bits.insert(bit_ci);
+ mapping_bits[bit_ci] = bit_o;
+ }
+ }
+ }
+
+ vector<Cell*> adders_to_fix_cells;
+ for (auto cell : module->cells())
+ {
+ if (cell->type == "\\EFX_ADD") {
+ SigBit bit_ci = get_bit_or_zero(cell->getPort("\\CI"));
+ SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\I0"));
+ SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\I1"));
+ SigBit canonical_bit = sigmap(bit_ci);
+ if (!ci_bits.count(canonical_bit))
+ continue;
+ if (bit_i0 == State::S0 && bit_i1== State::S0)
+ continue;
+
+ adders_to_fix_cells.push_back(cell);
+ log("Found %s cell named %s with invalid CI signal.\n", log_id(cell->type), log_id(cell));
+ }
+ }
+
+ for (auto cell : adders_to_fix_cells)
+ {
+ SigBit bit_ci = get_bit_or_zero(cell->getPort("\\CI"));
+ SigBit canonical_bit = sigmap(bit_ci);
+ auto bit = mapping_bits.at(canonical_bit);
+ log("Fixing %s cell named %s breaking carry chain.\n", log_id(cell->type), log_id(cell));
+ Cell *c = module->addCell(NEW_ID, "\\EFX_ADD");
+ SigBit new_bit = module->addWire(NEW_ID);
+ c->setParam("\\I0_POLARITY", State::S1);
+ c->setParam("\\I1_POLARITY", State::S1);
+ c->setPort("\\I0", bit);
+ c->setPort("\\I1", State::S1);
+ c->setPort("\\CI", State::S0);
+ c->setPort("\\CO", new_bit);
+
+ cell->setPort("\\CI", new_bit);
+ }
+}
+
+struct EfinixCarryFixPass : public Pass {
+ EfinixCarryFixPass() : Pass("efinix_fixcarry", "Efinix: fix carry chain") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" efinix_fixcarry [options] [selection]\n");
+ log("\n");
+ log("Add Efinix adders to fix carry chain if needed.\n");
+ log("\n");
+ }
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ log_header(design, "Executing efinix_fixcarry pass (fix invalid carry chain).\n");
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ Module *module = design->top_module();
+
+ if (module == nullptr)
+ log_cmd_error("No top module found.\n");
+
+ fix_carry_chain(module);
+ }
+} EfinixCarryFixPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/efinix/efinix_gbuf.cc b/techlibs/efinix/efinix_gbuf.cc
new file mode 100644
index 000000000..e75fb3f4d
--- /dev/null
+++ b/techlibs/efinix/efinix_gbuf.cc
@@ -0,0 +1,119 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2019 Miodrag Milanovic <miodrag@symbioticeda.com>
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+static void handle_gbufs(Module *module)
+{
+ SigMap sigmap(module);
+
+ pool<SigBit> clk_bits;
+ dict<SigBit, SigBit> rewrite_bits;
+ vector<pair<Cell*, SigBit>> pad_bits;
+
+ for (auto cell : module->cells())
+ {
+ if (cell->type == "\\EFX_FF") {
+ for (auto bit : sigmap(cell->getPort("\\CLK")))
+ clk_bits.insert(bit);
+ }
+ if (cell->type == "\\EFX_RAM_5K") {
+ for (auto bit : sigmap(cell->getPort("\\RCLK")))
+ clk_bits.insert(bit);
+ for (auto bit : sigmap(cell->getPort("\\WCLK")))
+ clk_bits.insert(bit);
+ }
+ }
+
+ for (auto wire : vector<Wire*>(module->wires()))
+ {
+ if (!wire->port_input)
+ continue;
+
+ for (int index = 0; index < GetSize(wire); index++)
+ {
+ SigBit bit(wire, index);
+ SigBit canonical_bit = sigmap(bit);
+
+ if (!clk_bits.count(canonical_bit))
+ continue;
+
+ Cell *c = module->addCell(NEW_ID, "\\EFX_GBUFCE");
+ SigBit new_bit = module->addWire(NEW_ID);
+ c->setParam("\\CE_POLARITY", State::S1);
+ c->setPort("\\O", new_bit);
+ c->setPort("\\CE", State::S1);
+ pad_bits.push_back(make_pair(c, bit));
+ rewrite_bits[canonical_bit] = new_bit;
+
+ log("Added %s cell %s for port bit %s.\n", log_id(c->type), log_id(c), log_signal(bit));
+ }
+ }
+
+ auto rewrite_function = [&](SigSpec &s) {
+ for (auto &bit : s) {
+ SigBit canonical_bit = sigmap(bit);
+ if (rewrite_bits.count(canonical_bit))
+ bit = rewrite_bits.at(canonical_bit);
+ }
+ };
+
+ module->rewrite_sigspecs(rewrite_function);
+
+ for (auto &it : pad_bits)
+ it.first->setPort("\\I", it.second);
+}
+
+struct EfinixGbufPass : public Pass {
+ EfinixGbufPass() : Pass("efinix_gbuf", "Efinix: insert global clock buffers") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" efinix_gbuf [options] [selection]\n");
+ log("\n");
+ log("Add Efinix global clock buffers to top module as needed.\n");
+ log("\n");
+ }
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ log_header(design, "Executing efinix_gbuf pass (insert global clock buffers).\n");
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ Module *module = design->top_module();
+
+ if (module == nullptr)
+ log_cmd_error("No top module found.\n");
+
+ handle_gbufs(module);
+ }
+} EfinixGbufPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc
new file mode 100644
index 000000000..26a8d4eda
--- /dev/null
+++ b/techlibs/efinix/synth_efinix.cc
@@ -0,0 +1,219 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2019 Miodrag Milanovic <miodrag@symbioticeda.com>
+ * Copyright (C) 2019 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/celltypes.h"
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct SynthEfinixPass : public ScriptPass
+{
+ SynthEfinixPass() : ScriptPass("synth_efinix", "synthesis for Efinix FPGAs") { }
+
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" synth_efinix [options]\n");
+ log("\n");
+ log("This command runs synthesis for Efinix FPGAs.\n");
+ log("\n");
+ log(" -top <module>\n");
+ log(" use the specified module as top module\n");
+ log("\n");
+ log(" -edif <file>\n");
+ log(" write the design to the specified EDIF file. writing of an output file\n");
+ log(" is omitted if this parameter is not specified.\n");
+ log("\n");
+ log(" -json <file>\n");
+ log(" write the design to the specified JSON file. writing of an output file\n");
+ log(" is omitted if this parameter is not specified.\n");
+ log("\n");
+ log(" -run <from_label>:<to_label>\n");
+ log(" only run the commands between the labels (see below). an empty\n");
+ log(" from label is synonymous to 'begin', and empty to label is\n");
+ log(" synonymous to the end of the command list.\n");
+ log("\n");
+ log(" -noflatten\n");
+ log(" do not flatten design before synthesis\n");
+ log("\n");
+ log(" -retime\n");
+ log(" run 'abc' with -dff option\n");
+ log("\n");
+ log("\n");
+ log("The following commands are executed by this synthesis command:\n");
+ help_script();
+ log("\n");
+ }
+
+ string top_opt, edif_file, json_file;
+ bool flatten, retime;
+
+ void clear_flags() YS_OVERRIDE
+ {
+ top_opt = "-auto-top";
+ edif_file = "";
+ json_file = "";
+ flatten = true;
+ retime = false;
+ }
+
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ string run_from, run_to;
+ clear_flags();
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ if (args[argidx] == "-top" && argidx+1 < args.size()) {
+ top_opt = "-top " + args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-edif" && argidx+1 < args.size()) {
+ edif_file = args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-json" && argidx+1 < args.size()) {
+ json_file = args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-run" && argidx+1 < args.size()) {
+ size_t pos = args[argidx+1].find(':');
+ if (pos == std::string::npos)
+ break;
+ run_from = args[++argidx].substr(0, pos);
+ run_to = args[argidx].substr(pos+1);
+ continue;
+ }
+ if (args[argidx] == "-noflatten") {
+ flatten = false;
+ continue;
+ }
+ if (args[argidx] == "-retime") {
+ retime = true;
+ continue;
+ }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ if (!design->full_selection())
+ log_cmd_error("This command only operates on fully selected designs!\n");
+
+ log_header(design, "Executing SYNTH_EFINIX pass.\n");
+ log_push();
+
+ run_script(design, run_from, run_to);
+
+ log_pop();
+ }
+
+ void script() YS_OVERRIDE
+ {
+ if (check_label("begin"))
+ {
+ run("read_verilog -lib +/efinix/cells_sim.v");
+ run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
+ }
+
+ if (flatten && check_label("flatten", "(unless -noflatten)"))
+ {
+ run("proc");
+ run("flatten");
+ run("tribuf -logic");
+ run("deminout");
+ }
+
+ if (check_label("coarse"))
+ {
+ run("synth -run coarse");
+ }
+
+ if (check_label("map_bram", "(skip if -nobram)"))
+ {
+ run("memory_bram -rules +/efinix/bram.txt");
+ run("techmap -map +/efinix/brams_map.v");
+ run("setundef -zero -params t:EFX_RAM_5K");
+ }
+
+ if (check_label("fine"))
+ {
+ run("opt -fast -mux_undef -undriven -fine");
+ run("memory_map");
+ run("opt -undriven -fine");
+ run("techmap -map +/techmap.v -map +/efinix/arith_map.v");
+ if (retime || help_mode)
+ run("abc -dff", "(only if -retime)");
+ }
+
+ if (check_label("map_ffs"))
+ {
+ run("dffsr2dff");
+ run("techmap -D NO_LUT -map +/efinix/cells_map.v");
+ run("dffinit -strinit SET RESET -ff AL_MAP_SEQ q REGSET -noreinit");
+ run("opt_expr -mux_undef");
+ run("simplemap");
+ }
+
+ if (check_label("map_luts"))
+ {
+ run("abc -lut 4");
+ run("clean");
+ }
+
+ if (check_label("map_cells"))
+ {
+ run("techmap -map +/efinix/cells_map.v");
+ run("clean");
+ }
+
+ if (check_label("map_gbuf"))
+ {
+ run("efinix_gbuf");
+ run("efinix_fixcarry");
+ run("clean");
+ }
+
+ if (check_label("check"))
+ {
+ run("hierarchy -check");
+ run("stat");
+ run("check -noinit");
+ }
+
+ if (check_label("edif"))
+ {
+ if (!edif_file.empty() || help_mode)
+ run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
+ }
+
+ if (check_label("json"))
+ {
+ if (!json_file.empty() || help_mode)
+ run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
+ }
+ }
+} SynthEfinixPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box
index c0ea742e2..3ea70bc91 100644
--- a/techlibs/ice40/abc_hx.box
+++ b/techlibs/ice40/abc_hx.box
@@ -3,11 +3,11 @@
# NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out)
-# Inputs: A B CI
+# Inputs: A B I0 I3 CI
# Outputs: O CO
# (NB: carry chain input/output must be last
# input/output and have been moved there
# overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 3 2
-400 379 316
-259 231 126
+$__ICE40_CARRY_WRAPPER 1 1 5 2
+400 379 449 316 316
+259 231 - - 126
diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box
index d73b6d649..473e92fe9 100644
--- a/techlibs/ice40/abc_lp.box
+++ b/techlibs/ice40/abc_lp.box
@@ -3,11 +3,11 @@
# NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out)
-# Inputs: A B CI
+# Inputs: A B I0 I3 CI
# Outputs: O CO
# (NB: carry chain input/output must be last
# input/output and have been moved there
# overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 3 2
-589 558 465
-675 609 186
+$__ICE40_CARRY_WRAPPER 1 1 5 2
+589 558 661 465 465
+675 609 - - 186
diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box
index 42d666051..f00e247b8 100644
--- a/techlibs/ice40/abc_u.box
+++ b/techlibs/ice40/abc_u.box
@@ -3,11 +3,11 @@
# NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out)
-# Inputs: A B CI
+# Inputs: A B I0 I3 CI
# Outputs: O CO
# (NB: carry chain input/output must be last
# input/output and have been moved there
# overriding the alphabetical ordering)
-$__ICE40_FULL_ADDER 1 1 3 2
-1231 1205 874
-675 609 278
+$__ICE40_CARRY_WRAPPER 1 1 5 2
+1231 1205 1285 874 874
+675 609 - - 278
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index ab04808f4..8e5e0358e 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -2,6 +2,10 @@
`define SB_DFF_REG reg Q = 0
// `define SB_DFF_REG reg Q
+`define ABC_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc_arrival=TIME *) `endif
+`define ABC_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc_arrival=TIME *) `endif
+`define ABC_ARRIVAL_U(TIME) `ifdef ICE40_U (* abc_arrival=TIME *) `endif
+
// SiliconBlue IO Cells
module SB_IO (
@@ -142,13 +146,16 @@ module SB_CARRY (output CO, input I0, I1, CI);
endmodule
(* abc_box_id = 1, lib_whitebox *)
-module \$__ICE40_FULL_ADDER (
- (* abc_carry *) output CO,
+module \$__ICE40_CARRY_WRAPPER (
+ (* abc_carry *)
+ output CO,
output O,
- input A,
- input B,
- (* abc_carry *) input CI
+ input A, B,
+ (* abc_carry *)
+ input CI,
+ input I0, I3
);
+ parameter LUT = 0;
SB_CARRY carry (
.I0(A),
.I1(B),
@@ -156,34 +163,52 @@ module \$__ICE40_FULL_ADDER (
.CO(CO)
);
SB_LUT4 #(
- // I0: 1010 1010 1010 1010
- // I1: 1100 1100 1100 1100
- // I2: 1111 0000 1111 0000
- // I3: 1111 1111 0000 0000
- .LUT_INIT(16'b 0110_1001_1001_0110)
+ .LUT_INIT(LUT)
) adder (
- .I0(1'b0),
+ .I0(I0),
.I1(A),
.I2(B),
- .I3(CI),
+ .I3(I3),
.O(O)
);
endmodule
+// Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+
// Positive Edge SiliconBlue FF Cells
-module SB_DFF (output `SB_DFF_REG, input C, D);
+module SB_DFF (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, D
+);
always @(posedge C)
Q <= D;
endmodule
-module SB_DFFE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFE (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, D
+);
always @(posedge C)
if (E)
Q <= D;
endmodule
-module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFSR (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, R, D
+);
always @(posedge C)
if (R)
Q <= 0;
@@ -191,7 +216,13 @@ module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
Q <= D;
endmodule
-module SB_DFFR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFR (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, R, D
+);
always @(posedge C, posedge R)
if (R)
Q <= 0;
@@ -199,7 +230,13 @@ module SB_DFFR (output `SB_DFF_REG, input C, R, D);
Q <= D;
endmodule
-module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFSS (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, S, D
+);
always @(posedge C)
if (S)
Q <= 1;
@@ -207,7 +244,13 @@ module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
Q <= D;
endmodule
-module SB_DFFS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFS (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, S, D
+);
always @(posedge C, posedge S)
if (S)
Q <= 1;
@@ -215,7 +258,13 @@ module SB_DFFS (output `SB_DFF_REG, input C, S, D);
Q <= D;
endmodule
-module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFESR (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, R, D
+);
always @(posedge C)
if (E) begin
if (R)
@@ -225,7 +274,13 @@ module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
end
endmodule
-module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFER (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, R, D
+);
always @(posedge C, posedge R)
if (R)
Q <= 0;
@@ -233,7 +288,13 @@ module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
Q <= D;
endmodule
-module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFESS (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, S, D
+);
always @(posedge C)
if (E) begin
if (S)
@@ -243,7 +304,13 @@ module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
end
endmodule
-module SB_DFFES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFES (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, S, D
+);
always @(posedge C, posedge S)
if (S)
Q <= 1;
@@ -253,18 +320,36 @@ endmodule
// Negative Edge SiliconBlue FF Cells
-module SB_DFFN (output `SB_DFF_REG, input C, D);
+module SB_DFFN (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, D
+);
always @(negedge C)
Q <= D;
endmodule
-module SB_DFFNE (output `SB_DFF_REG, input C, E, D);
+module SB_DFFNE (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, D
+);
always @(negedge C)
if (E)
Q <= D;
endmodule
-module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNSR (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, R, D
+);
always @(negedge C)
if (R)
Q <= 0;
@@ -272,7 +357,13 @@ module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
Q <= D;
endmodule
-module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
+module SB_DFFNR (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, R, D
+);
always @(negedge C, posedge R)
if (R)
Q <= 0;
@@ -280,7 +371,13 @@ module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
Q <= D;
endmodule
-module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNSS (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, S, D
+);
always @(negedge C)
if (S)
Q <= 1;
@@ -288,7 +385,13 @@ module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
Q <= D;
endmodule
-module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
+module SB_DFFNS (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, S, D
+);
always @(negedge C, posedge S)
if (S)
Q <= 1;
@@ -296,7 +399,13 @@ module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
Q <= D;
endmodule
-module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNESR (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, R, D
+);
always @(negedge C)
if (E) begin
if (R)
@@ -306,7 +415,13 @@ module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
end
endmodule
-module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
+module SB_DFFNER (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, R, D
+);
always @(negedge C, posedge R)
if (R)
Q <= 0;
@@ -314,7 +429,13 @@ module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
Q <= D;
endmodule
-module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNESS (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, S, D
+);
always @(negedge C)
if (E) begin
if (S)
@@ -324,7 +445,13 @@ module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
end
endmodule
-module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D);
+module SB_DFFNES (
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output `SB_DFF_REG,
+ input C, E, S, D
+);
always @(negedge C, posedge S)
if (S)
Q <= 1;
@@ -335,6 +462,9 @@ endmodule
// SiliconBlue RAM Cells
module SB_RAM40_4K (
+ `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+ `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+ `ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
output [15:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
@@ -503,6 +633,9 @@ module SB_RAM40_4K (
endmodule
module SB_RAM40_4KNR (
+ `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+ `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+ `ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
output [15:0] RDATA,
input RCLKN, RCLKE, RE,
input [10:0] RADDR,
@@ -568,6 +701,9 @@ module SB_RAM40_4KNR (
endmodule
module SB_RAM40_4KNW (
+ `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+ `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+ `ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
output [15:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
@@ -633,6 +769,9 @@ module SB_RAM40_4KNW (
endmodule
module SB_RAM40_4KNRNW (
+ `ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+ `ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+ `ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
output [15:0] RDATA,
input RCLKN, RCLKE, RE,
input [10:0] RADDR,
@@ -701,7 +840,12 @@ endmodule
module ICESTORM_LC (
input I0, I1, I2, I3, CIN, CLK, CEN, SR,
- output LO, O, COUT
+ output LO,
+ `ABC_ARRIVAL_HX(540)
+ `ABC_ARRIVAL_LP(796)
+ `ABC_ARRIVAL_U(1391)
+ output O,
+ output COUT
);
parameter [15:0] LUT_INIT = 0;
@@ -1301,6 +1445,7 @@ module SB_MAC16 (
input ADDSUBTOP, ADDSUBBOT,
input OHOLDTOP, OHOLDBOT,
input CI, ACCUMCI, SIGNEXTIN,
+ //`ABC_ARRIVAL_U(1984) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
output [31:0] O,
output CO, ACCUMCO, SIGNEXTOUT
);
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index d5106b805..ea56d3f4d 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -84,7 +84,7 @@ static void run_ice40_opts(Module *module)
continue;
}
- if (cell->type == "$__ICE40_FULL_ADDER")
+ if (cell->type == "$__ICE40_CARRY_WRAPPER")
{
SigSpec non_const_inputs, replacement_output;
int count_zeros = 0, count_ones = 0;
@@ -114,16 +114,17 @@ static void run_ice40_opts(Module *module)
optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
module->connect(cell->getPort("\\CO")[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true);
- log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
+ log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
cell->type = "$lut";
- cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] });
+ cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], cell->getPort("\\I3") });
cell->setPort("\\Y", cell->getPort("\\O"));
cell->unsetPort("\\B");
cell->unsetPort("\\CI");
+ cell->unsetPort("\\I0");
+ cell->unsetPort("\\I3");
cell->unsetPort("\\CO");
cell->unsetPort("\\O");
- cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
cell->setParam("\\WIDTH", 4);
}
continue;
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index c6de81bd9..a3890268a 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -238,7 +238,14 @@ struct SynthIce40Pass : public ScriptPass
{
if (check_label("begin"))
{
- run("read_verilog -icells -lib +/ice40/cells_sim.v");
+ std::string define;
+ if (device_opt == "lp")
+ define = "-D ICE40_LP";
+ else if (device_opt == "u")
+ define = "-D ICE40_U";
+ else
+ define = "-D ICE40_HX";
+ run("read_verilog -icells " + define + " -lib +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run("proc");
}
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 2efcf7d90..c26e1f4db 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -25,7 +25,10 @@ techlibs/xilinx/brams_init_8.vh: techlibs/xilinx/brams_init.mk
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_xtra.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_cells_xtra.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6v_cells_xtra.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_cells_xtra.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_cells_xtra.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_bb.v))
@@ -35,7 +38,8 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_ff_map.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_ff_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index a760b3d6d..9f96d16be 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -128,7 +128,7 @@ module RAM32X1D (
parameter INIT = 32'h0;
parameter IS_WCLK_INVERTED = 1'b0;
wire \$DPO , \$SPO ;
- \$__ABC_RAM32X1D #(
+ RAM32X1D #(
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) _TECHMAP_REPLACE_ (
.DPO(\$DPO ), .SPO(\$SPO ),
@@ -136,8 +136,8 @@ module RAM32X1D (
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
);
- \$__ABC_LUTMUX6 dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO));
- \$__ABC_LUTMUX6 spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO));
+ \$__ABC_LUT6 dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO));
+ \$__ABC_LUT6 spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO));
endmodule
module RAM64X1D (
@@ -151,7 +151,7 @@ module RAM64X1D (
parameter INIT = 64'h0;
parameter IS_WCLK_INVERTED = 1'b0;
wire \$DPO , \$SPO ;
- \$__ABC_RAM64X1D #(
+ RAM64X1D #(
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) _TECHMAP_REPLACE_ (
.DPO(\$DPO ), .SPO(\$SPO ),
@@ -159,8 +159,8 @@ module RAM64X1D (
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
);
- \$__ABC_LUTMUX6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO));
- \$__ABC_LUTMUX6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO));
+ \$__ABC_LUT6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO));
+ \$__ABC_LUT6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO));
endmodule
module RAM128X1D (
@@ -173,7 +173,7 @@ module RAM128X1D (
parameter INIT = 128'h0;
parameter IS_WCLK_INVERTED = 1'b0;
wire \$DPO , \$SPO ;
- \$__ABC_RAM128X1D #(
+ RAM128X1D #(
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) _TECHMAP_REPLACE_ (
.DPO(\$DPO ), .SPO(\$SPO ),
@@ -181,8 +181,8 @@ module RAM128X1D (
.A(A),
.DPRA(DPRA)
);
- \$__ABC_LUTMUX7 dpo (.A(\$DPO ), .S(A), .Y(DPO));
- \$__ABC_LUTMUX7 spo (.A(\$SPO ), .S(A), .Y(SPO));
+ \$__ABC_LUT7 dpo (.A(\$DPO ), .S(A), .Y(DPO));
+ \$__ABC_LUT7 spo (.A(\$SPO ), .S(A), .Y(SPO));
endmodule
module SRL16E (
@@ -192,14 +192,13 @@ module SRL16E (
parameter [15:0] INIT = 16'h0000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
wire \$Q ;
- \$__ABC_SRL16E #(
+ SRL16E #(
.INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
) _TECHMAP_REPLACE_ (
.Q(\$Q ),
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
);
- // TODO: Check if SRL uses fast inputs or slow inputs
- \$__ABC_LUTMUX6 q (.A(\$Q ), .S({A0, A1, A2, A3, 1'b0, 1'b0}), .Y(Q));
+ \$__ABC_LUT6 q (.A(\$Q ), .S({1'b1, A0, A1, A2, A3, 1'b1}), .Y(Q));
endmodule
module SRLC32E (
@@ -211,12 +210,11 @@ module SRLC32E (
parameter [31:0] INIT = 32'h00000000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
wire \$Q ;
- \$__ABC_SRLC32E #(
+ SRLC32E #(
.INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
) _TECHMAP_REPLACE_ (
.Q(\$Q ), .Q31(Q31),
.A(A), .CE(CE), .CLK(CLK), .D(D)
);
- // TODO: Check if SRL uses fast inputs or slow inputs
- \$__ABC_LUTMUX6 q (.A(\$Q ), .S({A, 1'b0}), .Y(Q));
+ \$__ABC_LUT6 q (.A(\$Q ), .S({1'b1, A}), .Y(Q));
endmodule
diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v
index 7162bd213..d94ddb7e5 100644
--- a/techlibs/xilinx/abc_model.v
+++ b/techlibs/xilinx/abc_model.v
@@ -115,65 +115,8 @@ module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
endmodule
(* abc_box_id=2000 *)
-module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
+module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
endmodule
(* abc_box_id=2001 *)
-module \$__ABC_LUTMUX7 (input A, input [6:0] S, output Y);
-endmodule
-
-
-module \$__ABC_RAM32X1D (
- // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
- (* abc_arrival=1153 *) output DPO, SPO,
- input D,
- input WCLK,
- input WE,
- input A0, A1, A2, A3, A4,
- input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
-);
-endmodule
-
-module \$__ABC_RAM64X1D (
- // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
- (* abc_arrival=1153 *) output DPO, SPO,
- input D,
- input WCLK,
- input WE,
- input A0, A1, A2, A3, A4, A5,
- input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
-);
- parameter INIT = 64'h0;
- parameter IS_WCLK_INVERTED = 1'b0;
-endmodule
-
-module \$__ABC_RAM128X1D (
- // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
- (* abc_arrival=1153 *) output DPO, SPO,
- input D,
- input WCLK,
- input WE,
- input [6:0] A, DPRA
-);
- parameter INIT = 128'h0;
- parameter IS_WCLK_INVERTED = 1'b0;
-endmodule
-
-module SRL16E (
- // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
- (* abc_arrival=1472 *) output Q,
- input A0, A1, A2, A3, CE, CLK, D
-);
- parameter [15:0] INIT = 16'h0000;
- parameter [0:0] IS_CLK_INVERTED = 1'b0;
-endmodule
-
-module SRLC32E (
- // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
- (* abc_arrival=1472 *) output Q,
- (* abc_arrival=1114 *) output Q31,
- input [4:0] A,
- input CE, CLK, D
-);
- parameter [31:0] INIT = 32'h00000000;
- parameter [0:0] IS_CLK_INVERTED = 1'b0;
+module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
endmodule
diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v
index d00d27e2e..c24571747 100644
--- a/techlibs/xilinx/abc_unmap.v
+++ b/techlibs/xilinx/abc_unmap.v
@@ -139,101 +139,9 @@ module \$__ABC_FDPE_1 (output Q,
);
endmodule
-module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
+module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
assign Y = A;
endmodule
-module \$__ABC_LUTMUX7 (input A, input [6:0] S, output Y);
+module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
assign Y = A;
endmodule
-
-module \$__ABC_RAM32X1D (
- output DPO, SPO,
- input D,
- input WCLK,
- input WE,
- input A0, A1, A2, A3, A4,
- input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
-);
- parameter INIT = 32'h0;
- parameter IS_WCLK_INVERTED = 1'b0;
- RAM32X1D #(
- .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .DPO(DPO), .SPO(SPO),
- .D(D), .WCLK(WCLK), .WE(WE),
- .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
- .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
- );
-endmodule
-
-module \$__ABC_RAM64X1D (
- output DPO, SPO,
- input D,
- input WCLK,
- input WE,
- input A0, A1, A2, A3, A4, A5,
- input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
-);
- parameter INIT = 64'h0;
- parameter IS_WCLK_INVERTED = 1'b0;
- RAM64X1D #(
- .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .DPO(DPO), .SPO(SPO),
- .D(D), .WCLK(WCLK), .WE(WE),
- .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
- .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
- );
-endmodule
-
-module \$__ABC_RAM128X1D (
- output DPO, SPO,
- input D,
- input WCLK,
- input WE,
- input A,
- input DPRA,
-);
- parameter INIT = 128'h0;
- parameter IS_WCLK_INVERTED = 1'b0;
- RAM128X1D #(
- .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .DPO(DPO), .SPO(SPO),
- .D(D), .WCLK(WCLK), .WE(WE),
- .A(A),
- .DPRA(DPRA)
- );
-endmodule
-
-module \$__ABC_SRL16E (
- output Q,
- input A0, A1, A2, A3, CE, CLK, D
-);
- parameter [15:0] INIT = 16'h0000;
- parameter [0:0] IS_CLK_INVERTED = 1'b0;
-
- SRL16E #(
- .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .Q(Q),
- .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
- );
-endmodule
-
-module \$__ABC_SRLC32E (
- output Q,
- output Q31,
- input [4:0] A,
- input CE, CLK, D
-);
- parameter [31:0] INIT = 32'h00000000;
- parameter [0:0] IS_CLK_INVERTED = 1'b0;
-
- SRLC32E #(
- .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .Q(Q), .Q31(Q31),
- .A(A), .CE(CE), .CLK(CLK), .D(D)
- );
-endmodule
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index c08af6320..aebb8b975 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -15,7 +15,10 @@ F7MUX 1 1 3 1
MUXF8 2 1 3 1
104 94 273
-# Box containing MUXF7.[AB] + MUXF8
+# Box containing MUXF7.[AB] + MUXF8,
+# Necessary to make these an atomic unit so that
+# ABC cannot optimise just one of the MUXF7 away
+# and expect to save on its delay
# Inputs: I0 I1 I2 I3 S0 S1
# Outputs: O
$__MUXF78 3 1 6 1
@@ -81,14 +84,19 @@ FDPE_1 1006 1 5 1
# SLICEM/A6LUT
# Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
+# Necessary since RAMD* and SRL* have both combinatorial (i.e.
+# same-cycle read operation) and sequential (write operation
+# is only committed on the next clock edge).
+# To model the combinatorial path, such cells have to be split
+# into comb and seq parts, with this box modelling only the former.
# Inputs: A S0 S1 S2 S3 S4 S5
# Outputs: Y
-$__ABC_LUTRAM6 2000 0 7 1
+$__ABC_LUT6 2000 0 7 1
0 642 631 472 407 238 127
# SLICEM/A6LUT + F7BMUX
# Box to emulate comb/seq behaviour of RAMD128
# Inputs: A S0 S1 S2 S3 S4 S5 S6
# Outputs: DPO SPO
-$__ABC_LUTRAM7 2001 0 8 1
+$__ABC_LUT7 2001 0 8 1
0 1047 1036 877 812 643 532 478
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 1ab718ccc..ef4340d10 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -29,29 +29,49 @@ module GND(output G);
assign G = 0;
endmodule
-module IBUF(output O, input I);
+module IBUF(
+ output O,
+ (* iopad_external_pin *)
+ input I);
parameter IOSTANDARD = "default";
parameter IBUF_LOW_PWR = 0;
assign O = I;
endmodule
-module OBUF(output O, input I);
+module OBUF(
+ (* iopad_external_pin *)
+ output O,
+ input I);
parameter IOSTANDARD = "default";
parameter DRIVE = 12;
parameter SLEW = "SLOW";
assign O = I;
endmodule
-module BUFG(output O, input I);
+module BUFG(
+ (* clkbuf_driver *)
+ output O,
+ input I);
+
assign O = I;
endmodule
module BUFGCTRL(
+ (* clkbuf_driver *)
output O,
input I0, input I1,
- input S0, input S1,
- input CE0, input CE1,
- input IGNORE0, input IGNORE1);
+ (* invertible_pin = "IS_S0_INVERTED" *)
+ input S0,
+ (* invertible_pin = "IS_S1_INVERTED" *)
+ input S1,
+ (* invertible_pin = "IS_CE0_INVERTED" *)
+ input CE0,
+ (* invertible_pin = "IS_CE1_INVERTED" *)
+ input CE1,
+ (* invertible_pin = "IS_IGNORE0_INVERTED" *)
+ input IGNORE0,
+ (* invertible_pin = "IS_IGNORE1_INVERTED" *)
+ input IGNORE1);
parameter [0:0] INIT_OUT = 1'b0;
parameter PRESELECT_I0 = "FALSE";
@@ -72,7 +92,12 @@ assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
endmodule
-module BUFHCE(output O, input I, input CE);
+module BUFHCE(
+ (* clkbuf_driver *)
+ output O,
+ input I,
+ (* invertible_pin = "IS_CE_INVERTED" *)
+ input CE);
parameter [0:0] INIT_OUT = 1'b0;
parameter CE_TYPE = "SYNC";
@@ -175,9 +200,11 @@ endmodule
(* abc_box_id = 4, lib_whitebox *)
module CARRY4(
- (* abc_carry *) output [3:0] CO,
+ (* abc_carry *)
+ output [3:0] CO,
output [3:0] O,
- (* abc_carry *) input CI,
+ (* abc_carry *)
+ input CI,
input CYINIT,
input [3:0] DI, S
);
@@ -211,7 +238,20 @@ endmodule
`endif
-module FDRE (output reg Q, input C, CE, D, R);
+// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
+
+module FDRE (
+ (* abc_arrival=303 *)
+ output reg Q,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C,
+ input CE,
+ (* invertible_pin = "IS_D_INVERTED" *)
+ input D,
+ (* invertible_pin = "IS_R_INVERTED" *)
+ input R
+);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -223,7 +263,18 @@ module FDRE (output reg Q, input C, CE, D, R);
endcase endgenerate
endmodule
-module FDSE (output reg Q, input C, CE, D, S);
+module FDSE (
+ (* abc_arrival=303 *)
+ output reg Q,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C,
+ input CE,
+ (* invertible_pin = "IS_D_INVERTED" *)
+ input D,
+ (* invertible_pin = "IS_S_INVERTED" *)
+ input S
+);
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -235,7 +286,18 @@ module FDSE (output reg Q, input C, CE, D, S);
endcase endgenerate
endmodule
-module FDCE (output reg Q, input C, CE, D, CLR);
+module FDCE (
+ (* abc_arrival=303 *)
+ output reg Q,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C,
+ input CE,
+ (* invertible_pin = "IS_D_INVERTED" *)
+ input D,
+ (* invertible_pin = "IS_CLR_INVERTED" *)
+ input CLR
+);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -249,7 +311,18 @@ module FDCE (output reg Q, input C, CE, D, CLR);
endcase endgenerate
endmodule
-module FDPE (output reg Q, input C, CE, D, PRE);
+module FDPE (
+ (* abc_arrival=303 *)
+ output reg Q,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C,
+ input CE,
+ (* invertible_pin = "IS_D_INVERTED" *)
+ input D,
+ (* invertible_pin = "IS_PRE_INVERTED" *)
+ input PRE
+);
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -263,33 +336,61 @@ module FDPE (output reg Q, input C, CE, D, PRE);
endcase endgenerate
endmodule
-module FDRE_1 (output reg Q, input C, CE, D, R);
+module FDRE_1 (
+ (* abc_arrival=303 *)
+ output reg Q,
+ (* clkbuf_sink *)
+ input C,
+ input CE, D, R
+);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
endmodule
-module FDSE_1 (output reg Q, input C, CE, D, S);
+module FDSE_1 (
+ (* abc_arrival=303 *)
+ output reg Q,
+ (* clkbuf_sink *)
+ input C,
+ input CE, D, S
+);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
endmodule
-module FDCE_1 (output reg Q, input C, CE, D, CLR);
+module FDCE_1 (
+ (* abc_arrival=303 *)
+ output reg Q,
+ (* clkbuf_sink *)
+ input C,
+ input CE, D, CLR
+);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
endmodule
-module FDPE_1 (output reg Q, input C, CE, D, PRE);
+module FDPE_1 (
+ (* abc_arrival=303 *)
+ output reg Q,
+ (* clkbuf_sink *)
+ input C,
+ input CE, D, PRE
+);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule
module RAM32X1D (
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+ (* abc_arrival=1153 *)
output DPO, SPO,
input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE,
input A0, A1, A2, A3, A4,
@@ -307,8 +408,12 @@ module RAM32X1D (
endmodule
module RAM64X1D (
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+ (* abc_arrival=1153 *)
output DPO, SPO,
input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE,
input A0, A1, A2, A3, A4, A5,
@@ -326,8 +431,12 @@ module RAM64X1D (
endmodule
module RAM128X1D (
- output DPO, SPO,
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+ (* abc_arrival=1153 *)
+ output DPO, SPO,
input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE,
input [6:0] A, DPRA
@@ -342,8 +451,14 @@ module RAM128X1D (
endmodule
module SRL16E (
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+ (* abc_arrival=1472 *)
output Q,
- input A0, A1, A2, A3, CE, CLK, D
+ input A0, A1, A2, A3, CE,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLK_INVERTED" *)
+ input CLK,
+ input D
);
parameter [15:0] INIT = 16'h0000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
@@ -355,15 +470,46 @@ module SRL16E (
always @(negedge CLK) if (CE) r <= { r[14:0], D };
end
else
- always @(posedge CLK) if (CE) r <= { r[14:0], D };
+ always @(posedge CLK) if (CE) r <= { r[14:0], D };
+ endgenerate
+endmodule
+
+module SRLC16E (
+ output Q,
+ output Q15,
+ input A0, A1, A2, A3, CE,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLK_INVERTED" *)
+ input CLK,
+ input D
+);
+ parameter [15:0] INIT = 16'h0000;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+
+ reg [15:0] r = INIT;
+ assign Q15 = r[15];
+ assign Q = r[{A3,A2,A1,A0}];
+ generate
+ if (IS_CLK_INVERTED) begin
+ always @(negedge CLK) if (CE) r <= { r[14:0], D };
+ end
+ else
+ always @(posedge CLK) if (CE) r <= { r[14:0], D };
endgenerate
endmodule
module SRLC32E (
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+ (* abc_arrival=1472 *)
output Q,
+ (* abc_arrival=1114 *)
output Q31,
input [4:0] A,
- input CE, CLK, D
+ input CE,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLK_INVERTED" *)
+ input CLK,
+ input D
);
parameter [31:0] INIT = 32'h00000000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py
new file mode 100644
index 000000000..561a61943
--- /dev/null
+++ b/techlibs/xilinx/cells_xtra.py
@@ -0,0 +1,708 @@
+#!/usr/bin/env python3
+
+from argparse import ArgumentParser
+from io import StringIO
+from enum import Enum, auto
+import os.path
+import sys
+import re
+
+
+class Cell:
+ def __init__(self, name, keep=False, port_attrs={}):
+ self.name = name
+ self.keep = keep
+ self.port_attrs = port_attrs
+
+
+XC6S_CELLS = [
+ # Design elements types listed in Xilinx UG615.
+
+ # Advanced.
+ Cell('MCB'),
+ Cell('PCIE_A1'),
+
+ # Arithmetic functions.
+ Cell('DSP48A1', port_attrs={'CLK': ['clkbuf_sink']}),
+
+ # Clock components.
+ # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFH', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFIO2', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}),
+ Cell('BUFIO2_2CLK', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}),
+ Cell('BUFIO2FB', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFPLL_MCB', port_attrs={'IOCLK0': ['clkbuf_driver'], 'IOCLK1': ['clkbuf_driver']}),
+ Cell('DCM_CLKGEN'),
+ Cell('DCM_SP'),
+ Cell('PLL_BASE'),
+
+ # Config/BSCAN components.
+ Cell('BSCAN_SPARTAN6', keep=True),
+ Cell('DNA_PORT'),
+ Cell('ICAP_SPARTAN6', keep=True),
+ Cell('POST_CRC_INTERNAL'),
+ Cell('STARTUP_SPARTAN6', keep=True),
+ Cell('SUSPEND_SYNC', keep=True),
+
+ # I/O components.
+ Cell('GTPA1_DUAL'),
+ # Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}),
+ Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}),
+ Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
+ Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}),
+ Cell('IODELAY2', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}),
+ Cell('IODRP2', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}),
+ Cell('IODRP2_MCB', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}),
+ Cell('ISERDES2', port_attrs={
+ 'CLK0': ['clkbuf_sink'],
+ 'CLK1': ['clkbuf_sink'],
+ 'CLKDIV': ['clkbuf_sink'],
+ }),
+ Cell('KEEPER'),
+ # Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}),
+ Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+ Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
+ Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+ Cell('OSERDES2', port_attrs={
+ 'CLK0': ['clkbuf_sink'],
+ 'CLK1': ['clkbuf_sink'],
+ 'CLKDIV': ['clkbuf_sink'],
+ }),
+ Cell('PULLDOWN'),
+ Cell('PULLUP'),
+
+ # RAM/ROM.
+ #Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # NOTE: not in the official library guide!
+ Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
+ #Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
+ #Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # NOTE: not in the official library guide!
+ Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAMB8BWER', port_attrs={'CLKAWRCLK': ['clkbuf_sink'], 'CLKBRDCLK': ['clkbuf_sink']}),
+ # Cell('RAMB16BWER', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
+ Cell('ROM128X1'),
+ Cell('ROM256X1'),
+ Cell('ROM32X1'),
+ Cell('ROM64X1'),
+
+ # Registers/latches.
+ # Cell('FDCE'),
+ # Cell('FDPE'),
+ # Cell('FDRE'),
+ # Cell('FDSE'),
+ Cell('IDDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}),
+ Cell('LDCE'),
+ Cell('LDPE'),
+ Cell('ODDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}),
+
+ # Slice/CLB primitives.
+ # Cell('CARRY4'),
+ Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
+ # Cell('LUT1'),
+ # Cell('LUT2'),
+ # Cell('LUT3'),
+ # Cell('LUT4'),
+ # Cell('LUT5'),
+ # Cell('LUT6'),
+ # Cell('LUT6_2'),
+ # Cell('MUXF7'),
+ # Cell('MUXF8'),
+ # Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
+ # Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
+]
+
+
+XC6V_CELLS = [
+ # Design elements types listed in Xilinx UG623.
+
+ # Advanced.
+ Cell('PCIE_2_0'),
+ Cell('SYSMON'),
+
+ # Arithmetic functions.
+ Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
+
+ # Clock components.
+ # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}),
+ #Cell('BUFGCTRL', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFGMUX_CTRL', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFH', port_attrs={'O': ['clkbuf_driver']}),
+ #Cell('BUFHCE', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFIO', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFIODQS', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFR', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('IBUFDS_GTXE1', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('MMCM_ADV'),
+ Cell('MMCM_BASE'),
+
+ # Config/BSCAN components.
+ Cell('BSCAN_VIRTEX6', keep=True),
+ Cell('CAPTURE_VIRTEX6', keep=True),
+ Cell('DNA_PORT'),
+ Cell('EFUSE_USR'),
+ Cell('FRAME_ECC_VIRTEX6'),
+ Cell('ICAP_VIRTEX6', keep=True),
+ Cell('STARTUP_VIRTEX6', keep=True),
+ Cell('USR_ACCESS_VIRTEX6'),
+
+ # I/O components.
+ Cell('DCIRESET', keep=True),
+ Cell('GTHE1_QUAD'),
+ Cell('GTXE1'),
+ # Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}),
+ Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFDS_GTHE1', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}),
+ Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}),
+ Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
+ Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}),
+ Cell('IODELAYE1', port_attrs={'C': ['clkbuf_sink']}),
+ Cell('ISERDESE1', port_attrs={
+ 'CLK': ['clkbuf_sink'],
+ 'CLKB': ['clkbuf_sink'],
+ 'OCLK': ['clkbuf_sink'],
+ 'CLKDIV': ['clkbuf_sink'],
+ }),
+ Cell('KEEPER'),
+ # Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}),
+ Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+ Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
+ Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+ Cell('OSERDESE1', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
+ Cell('PULLDOWN'),
+ Cell('PULLUP'),
+ Cell('TEMAC_SINGLE'),
+
+ # RAM/ROM.
+ Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
+ Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
+ #Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
+ #Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
+ #Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # NOTE: not in the official library guide!
+ Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
+ # Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
+ Cell('ROM128X1'),
+ Cell('ROM256X1'),
+ Cell('ROM32X1'),
+ Cell('ROM64X1'),
+
+ # Registers/latches.
+ # Cell('FDCE'),
+ # Cell('FDPE'),
+ # Cell('FDRE'),
+ # Cell('FDSE'),
+ Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}),
+ Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
+ Cell('LDCE'),
+ Cell('LDPE'),
+ Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}),
+
+ # Slice/CLB primitives.
+ # Cell('CARRY4'),
+ Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
+ # Cell('LUT1'),
+ # Cell('LUT2'),
+ # Cell('LUT3'),
+ # Cell('LUT4'),
+ # Cell('LUT5'),
+ # Cell('LUT6'),
+ # Cell('LUT6_2'),
+ # Cell('MUXF7'),
+ # Cell('MUXF8'),
+ # Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
+ # Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
+]
+
+
+XC7_CELLS = [
+ # Design elements types listed in Xilinx UG953.
+
+ # Advanced.
+ Cell('GTHE2_CHANNEL'),
+ Cell('GTHE2_COMMON'),
+ Cell('GTPE2_CHANNEL'),
+ Cell('GTPE2_COMMON'),
+ Cell('GTXE2_CHANNEL'),
+ Cell('GTXE2_COMMON'),
+ Cell('PCIE_2_1'),
+ Cell('PCIE_3_0'),
+ Cell('XADC'),
+
+ # Arithmetic functions.
+ Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
+
+ # Clock components.
+ # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}),
+ #Cell('BUFGCTRL', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFGMUX_CTRL', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFH', port_attrs={'O': ['clkbuf_driver']}),
+ #Cell('BUFHCE', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFIO', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFMR', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFMRCE', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFR', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('MMCME2_ADV'),
+ Cell('MMCME2_BASE'),
+ Cell('PLLE2_ADV'),
+ Cell('PLLE2_BASE'),
+
+ # Config/BSCAN components.
+ Cell('BSCANE2', keep=True),
+ Cell('CAPTUREE2', keep=True),
+ Cell('DNA_PORT'),
+ Cell('EFUSE_USR'),
+ Cell('FRAME_ECCE2'),
+ Cell('ICAPE2', keep=True),
+ Cell('STARTUPE2', keep=True),
+ Cell('USR_ACCESSE2'),
+
+ # I/O components.
+ Cell('DCIRESET', keep=True),
+ # Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}),
+ Cell('IBUF_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin']}),
+ Cell('IBUF_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin']}),
+ Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFDS_DIFF_OUT_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFDS_GTE2', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFDS_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFDS_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}),
+ Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}),
+ Cell('IDELAYE2', port_attrs={'C': ['clkbuf_sink']}),
+ Cell('IN_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
+ Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
+ Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}),
+ Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}),
+ Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}),
+ Cell('IOBUFDS_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+ Cell('IOBUFDS_DIFF_OUT', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+ Cell('IOBUFDS_DIFF_OUT_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+ Cell('IOBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+ Cell('IOBUFDS_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+ Cell('ISERDESE2', port_attrs={
+ 'CLK': ['clkbuf_sink'],
+ 'CLKB': ['clkbuf_sink'],
+ 'OCLK': ['clkbuf_sink'],
+ 'OCLKB': ['clkbuf_sink'],
+ 'CLKDIV': ['clkbuf_sink'],
+ 'CLKDIVP': ['clkbuf_sink'],
+ }),
+ Cell('KEEPER'),
+ # Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}),
+ Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+ Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
+ Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+ Cell('ODELAYE2', port_attrs={'C': ['clkbuf_sink']}),
+ Cell('OSERDESE2', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
+ Cell('OUT_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
+ Cell('PHASER_IN'),
+ Cell('PHASER_IN_PHY'),
+ Cell('PHASER_OUT'),
+ Cell('PHASER_OUT_PHY'),
+ Cell('PHASER_REF'),
+ Cell('PHY_CONTROL'),
+ Cell('PULLDOWN'),
+ Cell('PULLUP'),
+
+ # RAM/ROM.
+ Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
+ Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
+ #Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
+ #Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
+ #Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # NOTE: not in the official library guide!
+ Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
+ # Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
+ Cell('ROM128X1'),
+ Cell('ROM256X1'),
+ Cell('ROM32X1'),
+ Cell('ROM64X1'),
+
+ # Registers/latches.
+ # Cell('FDCE'),
+ # Cell('FDPE'),
+ # Cell('FDRE'),
+ # Cell('FDSE'),
+ Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}),
+ Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
+ Cell('LDCE'),
+ Cell('LDPE'),
+ Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}),
+
+ # Slice/CLB primitives.
+ # Cell('CARRY4'),
+ Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
+ # Cell('LUT1'),
+ # Cell('LUT2'),
+ # Cell('LUT3'),
+ # Cell('LUT4'),
+ # Cell('LUT5'),
+ # Cell('LUT6'),
+ # Cell('LUT6_2'),
+ # Cell('MUXF7'),
+ # Cell('MUXF8'),
+ # Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
+ # Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
+
+ # NOTE: not in the official library guide!
+ Cell('PS7', keep=True),
+]
+
+
+XCU_CELLS = [
+ # Design elements types listed in Xilinx UG974.
+
+ # Advanced.
+ Cell('CMAC'),
+ Cell('CMACE4'),
+ Cell('GTHE3_CHANNEL'),
+ Cell('GTHE3_COMMON'),
+ Cell('GTHE4_CHANNEL'),
+ Cell('GTHE4_COMMON'),
+ Cell('GTYE3_CHANNEL'),
+ Cell('GTYE3_COMMON'),
+ Cell('GTYE4_CHANNEL'),
+ Cell('GTYE4_COMMON'),
+ Cell('IBUFDS_GTE3', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFDS_GTE4', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('ILKN'),
+ Cell('ILKNE4'),
+ Cell('OBUFDS_GTE3', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+ Cell('OBUFDS_GTE3_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+ Cell('OBUFDS_GTE4', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+ Cell('OBUFDS_GTE4_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+ Cell('PCIE40E4'),
+ Cell('PCIE_3_1'),
+ Cell('SYSMONE1'),
+ Cell('SYSMONE4'),
+
+ # Arithmetic functions.
+ Cell('DSP48E2', port_attrs={'CLK': ['clkbuf_sink']}),
+
+ # Blockram.
+ Cell('FIFO18E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
+ Cell('FIFO36E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
+ Cell('RAMB18E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
+ Cell('RAMB36E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}),
+ Cell('URAM288', port_attrs={'CLK': ['clkbuf_sink']}),
+ Cell('URAM288_BASE', port_attrs={'CLK': ['clkbuf_sink']}),
+
+ # CLB.
+ # Cell('LUT6_2'),
+ #Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM256X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM32M16', port_attrs={'WCLK': ['clkbuf_sink']}),
+ #Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM512X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM64M8', port_attrs={'WCLK': ['clkbuf_sink']}),
+ #Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ Cell('AND2B1L'),
+ Cell('CARRY8'),
+ Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}),
+ # Cell('LUT1'),
+ # Cell('LUT2'),
+ # Cell('LUT3'),
+ # Cell('LUT4'),
+ # Cell('LUT5'),
+ # Cell('LUT6'),
+ # Cell('MUXF7'),
+ # Cell('MUXF8'),
+ Cell('MUXF9'),
+ Cell('OR2L'),
+ # Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}),
+ # Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}),
+
+ # Clock.
+ # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFG_GT', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFG_GT_SYNC'),
+ Cell('BUFG_PS', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFGCE_DIV', port_attrs={'O': ['clkbuf_driver']}),
+ #Cell('BUFGCTRL', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('BUFGMUX_CTRL', port_attrs={'O': ['clkbuf_driver']}),
+ Cell('MMCME3_ADV'),
+ Cell('MMCME3_BASE'),
+ Cell('MMCME4_ADV'),
+ Cell('MMCME4_BASE'),
+ Cell('PLLE3_ADV'),
+ Cell('PLLE3_BASE'),
+ Cell('PLLE4_ADV'),
+ Cell('PLLE4_BASE'),
+
+ # Configuration.
+ Cell('BSCANE2', keep=True),
+ Cell('DNA_PORTE2'),
+ Cell('EFUSE_USR'),
+ Cell('FRAME_ECCE3'),
+ Cell('ICAPE3', keep=True),
+ Cell('MASTER_JTAG', keep=True),
+ Cell('STARTUPE3', keep=True),
+ Cell('USR_ACCESSE2'),
+
+ # I/O.
+ Cell('BITSLICE_CONTROL', keep=True),
+ Cell('DCIRESET', keep=True),
+ Cell('HPIO_VREF'),
+ # XXX
+ # Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}),
+ Cell('IBUF_ANALOG', port_attrs={'I': ['iopad_external_pin']}),
+ Cell('IBUF_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin']}),
+ Cell('IBUF_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin']}),
+ Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFDS_DIFF_OUT_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFDS_DPHY', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFDS_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFDS_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFDSE3', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
+ Cell('IBUFE3', port_attrs={'I': ['iopad_external_pin']}),
+ Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}),
+ Cell('IDELAYE3', port_attrs={'CLK': ['clkbuf_sink']}),
+ Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
+ Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}),
+ Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}),
+ Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}),
+ Cell('IOBUFDS_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+ Cell('IOBUFDS_DIFF_OUT', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+ Cell('IOBUFDS_DIFF_OUT_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+ Cell('IOBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+ Cell('IOBUFDS_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
+ Cell('IOBUFDSE3', port_attrs={'IO': ['iopad_external_pin']}),
+ Cell('IOBUFE3', port_attrs={'IO': ['iopad_external_pin']}),
+ Cell('ISERDESE3', port_attrs={
+ 'CLK': ['clkbuf_sink'],
+ 'CLK_B': ['clkbuf_sink'],
+ 'FIFO_RD_CLK': ['clkbuf_sink'],
+ 'CLKDIV': ['clkbuf_sink'],
+ }),
+ Cell('KEEPER'),
+ # Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}),
+ Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+ Cell('OBUFDS_DPHY', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+ Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
+ Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
+ Cell('ODELAYE3', port_attrs={'CLK': ['clkbuf_sink']}),
+ Cell('OSERDESE3', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}),
+ Cell('PULLDOWN'),
+ Cell('PULLUP'),
+ Cell('RIU_OR'),
+ Cell('RX_BITSLICE'),
+ Cell('RXTX_BITSLICE'),
+ Cell('TX_BITSLICE'),
+ Cell('TX_BITSLICE_TRI'),
+
+ # Registers.
+ # Cell('FDCE'),
+ # Cell('FDPE'),
+ # Cell('FDRE'),
+ # Cell('FDSE'),
+ Cell('HARD_SYNC', port_attrs={'CLK': ['clkbuf_sink']}),
+ Cell('IDDRE1', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}),
+ Cell('LDCE'),
+ Cell('LDPE'),
+ Cell('ODDRE1', port_attrs={'C': ['clkbuf_sink']}),
+
+ # NOTE: not in the official library guide!
+ Cell('PS8', keep=True),
+]
+
+
+class State(Enum):
+ OUTSIDE = auto()
+ IN_MODULE = auto()
+ IN_OTHER_MODULE = auto()
+ IN_FUNCTION = auto()
+ IN_TASK = auto()
+
+def xtract_cell_decl(cell, dirs, outf):
+ for dir in dirs:
+ fname = os.path.join(dir, cell.name + '.v')
+ try:
+ with open(fname) as f:
+ state = State.OUTSIDE
+ found = False
+ # Probably the most horrible Verilog "parser" ever written.
+ module_ports = []
+ invertible_ports = set()
+ for l in f:
+ l = l.partition('//')[0]
+ l = l.strip()
+ if l == 'module {}'.format(cell.name) or l.startswith('module {} '.format(cell.name)):
+ if found:
+ print('Multiple modules in {}.'.format(fname))
+ sys.exit(1)
+ elif state != State.OUTSIDE:
+ print('Nested modules in {}.'.format(fname))
+ sys.exit(1)
+ found = True
+ state = State.IN_MODULE
+ if cell.keep:
+ outf.write('(* keep *)\n')
+ outf.write('module {} (...);\n'.format(cell.name))
+ elif l.startswith('module '):
+ if state != State.OUTSIDE:
+ print('Nested modules in {}.'.format(fname))
+ sys.exit(1)
+ state = State.IN_OTHER_MODULE
+ elif l.startswith('task '):
+ if state == State.IN_MODULE:
+ state = State.IN_TASK
+ elif l.startswith('function '):
+ if state == State.IN_MODULE:
+ state = State.IN_FUNCTION
+ elif l == 'endtask':
+ if state == State.IN_TASK:
+ state = State.IN_MODULE
+ elif l == 'endfunction':
+ if state == State.IN_FUNCTION:
+ state = State.IN_MODULE
+ elif l == 'endmodule':
+ if state == State.IN_MODULE:
+ for kind, rng, port in module_ports:
+ for attr in cell.port_attrs.get(port, []):
+ outf.write(' (* {} *)\n'.format(attr))
+ if port in invertible_ports:
+ outf.write(' (* invertible_pin = "IS_{}_INVERTED" *)\n'.format(port))
+ if rng is None:
+ outf.write(' {} {};\n'.format(kind, port))
+ else:
+ outf.write(' {} {} {};\n'.format(kind, rng, port))
+ outf.write(l + '\n')
+ outf.write('\n')
+ elif state != State.IN_OTHER_MODULE:
+ print('endmodule in weird place in {}.'.format(cell.name, fname))
+ sys.exit(1)
+ state = State.OUTSIDE
+ elif l.startswith(('input ', 'output ', 'inout ')) and state == State.IN_MODULE:
+ if l.endswith((';', ',')):
+ l = l[:-1]
+ if ';' in l:
+ print('Weird port line in {} [{}].'.format(fname, l))
+ sys.exit(1)
+ kind, _, ports = l.partition(' ')
+ for port in ports.split(','):
+ port = port.strip()
+ if port.startswith('['):
+ rng, port = port.split()
+ else:
+ rng = None
+ module_ports.append((kind, rng, port))
+ elif l.startswith('parameter ') and state == State.IN_MODULE:
+ if 'UNPLACED' in l:
+ continue
+ if l.endswith((';', ',')):
+ l = l[:-1]
+ while ' ' in l:
+ l = l.replace(' ', ' ')
+ if ';' in l:
+ print('Weird parameter line in {} [{}].'.format(fname, l))
+ sys.exit(1)
+ outf.write(' {};\n'.format(l))
+ match = re.search('IS_([a-zA-Z0-9_]+)_INVERTED', l)
+ if match:
+ invertible_ports.add(match[1])
+ if state != State.OUTSIDE:
+ print('endmodule not found in {}.'.format(fname))
+ sys.exit(1)
+ if not found:
+ print('Cannot find module {} in {}.'.format(cell.name, fname))
+ sys.exit(1)
+ return
+ except FileNotFoundError:
+ continue
+ print('Cannot find {}.'.format(cell.name))
+ sys.exit(1)
+
+if __name__ == '__main__':
+ parser = ArgumentParser(description='Extract Xilinx blackbox cell definitions from ISE and Vivado.')
+ parser.add_argument('vivado_dir', nargs='?', default='/opt/Xilinx/Vivado/2018.1')
+ parser.add_argument('ise_dir', nargs='?', default='/opt/Xilinx/ISE/14.7')
+ args = parser.parse_args()
+
+ dirs = [
+ os.path.join(args.vivado_dir, 'data/verilog/src/xeclib'),
+ os.path.join(args.vivado_dir, 'data/verilog/src/retarget'),
+ os.path.join(args.ise_dir, 'ISE_DS/ISE/verilog/xeclib/unisims'),
+ ]
+ for dir in dirs:
+ if not os.path.isdir(dir):
+ print('{} is not a directory'.format(dir))
+
+ for ofile, cells in [
+ ('xc6s_cells_xtra.v', XC6S_CELLS),
+ ('xc6v_cells_xtra.v', XC6V_CELLS),
+ ('xc7_cells_xtra.v', XC7_CELLS),
+ ('xcu_cells_xtra.v', XCU_CELLS),
+ ]:
+ out = StringIO()
+ for cell in cells:
+ xtract_cell_decl(cell, dirs, out)
+
+ with open(ofile, 'w') as f:
+ f.write('// Created by cells_xtra.py from Xilinx models\n')
+ f.write('\n')
+ f.write(out.getvalue())
diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh
deleted file mode 100644
index 53b528820..000000000
--- a/techlibs/xilinx/cells_xtra.sh
+++ /dev/null
@@ -1,147 +0,0 @@
-#!/bin/bash
-
-set -e
-libdir="/opt/Xilinx/Vivado/2018.1/data/verilog/src"
-
-function xtract_cell_decl()
-{
- for dir in $libdir/xeclib $libdir/retarget; do
- [ -f $dir/$1.v ] || continue
- [ -z "$2" ] || echo $2
- egrep '^\s*((end)?module|parameter|input|inout|output|(end)?function|(end)?task)' $dir/$1.v |
- sed -re '/UNPLACED/ d; /^\s*function/,/endfunction/ d; /^\s*task/,/endtask/ d;
- s,//.*,,; s/#?\(.*/(...);/; s/^(input|output|parameter)/ \1/;
- s/\s+$//; s/,$/;/; /input|output|parameter/ s/[^;]$/&;/; s/\s+/ /g;
- s/^ ((end)?module)/\1/; s/^ / /; /module.*_bb/,/endmodule/ d;'
- echo; return
- done
- echo "Can't find $1."
- exit 1
-}
-
-{
- echo "// Created by cells_xtra.sh from Xilinx models"
- echo
-
- # Design elements types listed in Xilinx UG953
- xtract_cell_decl BSCANE2
- # xtract_cell_decl BUFG
- xtract_cell_decl BUFGCE
- xtract_cell_decl BUFGCE_1
- #xtract_cell_decl BUFGCTRL
- xtract_cell_decl BUFGMUX
- xtract_cell_decl BUFGMUX_1
- xtract_cell_decl BUFGMUX_CTRL
- xtract_cell_decl BUFH
- #xtract_cell_decl BUFHCE
- xtract_cell_decl BUFIO
- xtract_cell_decl BUFMR
- xtract_cell_decl BUFMRCE
- xtract_cell_decl BUFR
- xtract_cell_decl CAPTUREE2 "(* keep *)"
- # xtract_cell_decl CARRY4
- xtract_cell_decl CFGLUT5
- xtract_cell_decl DCIRESET "(* keep *)"
- xtract_cell_decl DNA_PORT
- xtract_cell_decl DSP48E1
- xtract_cell_decl EFUSE_USR
- # xtract_cell_decl FDCE
- # xtract_cell_decl FDPE
- # xtract_cell_decl FDRE
- # xtract_cell_decl FDSE
- xtract_cell_decl FIFO18E1
- xtract_cell_decl FIFO36E1
- xtract_cell_decl FRAME_ECCE2
- xtract_cell_decl GTHE2_CHANNEL
- xtract_cell_decl GTHE2_COMMON
- xtract_cell_decl GTPE2_CHANNEL
- xtract_cell_decl GTPE2_COMMON
- xtract_cell_decl GTXE2_CHANNEL
- xtract_cell_decl GTXE2_COMMON
- # xtract_cell_decl IBUF
- xtract_cell_decl IBUF_IBUFDISABLE
- xtract_cell_decl IBUF_INTERMDISABLE
- xtract_cell_decl IBUFDS
- xtract_cell_decl IBUFDS_DIFF_OUT
- xtract_cell_decl IBUFDS_DIFF_OUT_IBUFDISABLE
- xtract_cell_decl IBUFDS_DIFF_OUT_INTERMDISABLE
- xtract_cell_decl IBUFDS_GTE2
- xtract_cell_decl IBUFDS_IBUFDISABLE
- xtract_cell_decl IBUFDS_INTERMDISABLE
- xtract_cell_decl ICAPE2 "(* keep *)"
- xtract_cell_decl IDDR
- xtract_cell_decl IDDR_2CLK
- xtract_cell_decl IDELAYCTRL "(* keep *)"
- xtract_cell_decl IDELAYE2
- xtract_cell_decl IN_FIFO
- xtract_cell_decl IOBUF
- xtract_cell_decl IOBUF_DCIEN
- xtract_cell_decl IOBUF_INTERMDISABLE
- xtract_cell_decl IOBUFDS
- xtract_cell_decl IOBUFDS_DCIEN
- xtract_cell_decl IOBUFDS_DIFF_OUT
- xtract_cell_decl IOBUFDS_DIFF_OUT_DCIEN
- xtract_cell_decl IOBUFDS_DIFF_OUT_INTERMDISABLE
- xtract_cell_decl ISERDESE2
- xtract_cell_decl KEEPER
- xtract_cell_decl LDCE
- xtract_cell_decl LDPE
- # xtract_cell_decl LUT1
- # xtract_cell_decl LUT2
- # xtract_cell_decl LUT3
- # xtract_cell_decl LUT4
- # xtract_cell_decl LUT5
- # xtract_cell_decl LUT6
- #xtract_cell_decl LUT6_2
- xtract_cell_decl MMCME2_ADV
- xtract_cell_decl MMCME2_BASE
- # xtract_cell_decl MUXF7
- # xtract_cell_decl MUXF8
- # xtract_cell_decl OBUF
- xtract_cell_decl OBUFDS
- xtract_cell_decl OBUFT
- xtract_cell_decl OBUFTDS
- xtract_cell_decl ODDR
- xtract_cell_decl ODELAYE2
- xtract_cell_decl OSERDESE2
- xtract_cell_decl OUT_FIFO
- xtract_cell_decl PHASER_IN
- xtract_cell_decl PHASER_IN_PHY
- xtract_cell_decl PHASER_OUT
- xtract_cell_decl PHASER_OUT_PHY
- xtract_cell_decl PHASER_REF
- xtract_cell_decl PHY_CONTROL
- xtract_cell_decl PLLE2_ADV
- xtract_cell_decl PLLE2_BASE
- xtract_cell_decl PS7 "(* keep *)"
- xtract_cell_decl PULLDOWN
- xtract_cell_decl PULLUP
- #xtract_cell_decl RAM128X1D
- xtract_cell_decl RAM128X1S
- xtract_cell_decl RAM256X1S
- xtract_cell_decl RAM32M
- #xtract_cell_decl RAM32X1D
- xtract_cell_decl RAM32X1S
- xtract_cell_decl RAM32X1S_1
- xtract_cell_decl RAM32X2S
- xtract_cell_decl RAM64M
- #xtract_cell_decl RAM64X1D
- xtract_cell_decl RAM64X1S
- xtract_cell_decl RAM64X1S_1
- xtract_cell_decl RAM64X2S
- # xtract_cell_decl RAMB18E1
- # xtract_cell_decl RAMB36E1
- xtract_cell_decl ROM128X1
- xtract_cell_decl ROM256X1
- xtract_cell_decl ROM32X1
- xtract_cell_decl ROM64X1
- #xtract_cell_decl SRL16E
- #xtract_cell_decl SRLC32E
- xtract_cell_decl STARTUPE2 "(* keep *)"
- xtract_cell_decl USR_ACCESSE2
- xtract_cell_decl XADC
-} > cells_xtra.new
-
-mv cells_xtra.new cells_xtra.v
-exit 0
-
diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v
deleted file mode 100644
index 4571f6d5c..000000000
--- a/techlibs/xilinx/ff_map.v
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-// ============================================================================
-// FF mapping
-
-`ifndef _NO_FFS
-
-module \$_DFF_N_ (input D, C, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
-module \$_DFF_P_ (input D, C, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
-
-module \$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule
-module \$_DFFE_PP_ (input D, C, E, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule
-
-module \$_DFF_NN0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule
-module \$_DFF_NP0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
-module \$_DFF_PN0_ (input D, C, R, output Q); FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule
-module \$_DFF_PP0_ (input D, C, R, output Q); FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
-
-module \$_DFF_NN1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
-module \$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
-module \$_DFF_PN1_ (input D, C, R, output Q); FDPE #(.INIT(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
-module \$_DFF_PP1_ (input D, C, R, output Q); FDPE #(.INIT(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
-
-`endif
-
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index d28cd2428..888b5ed7b 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -46,7 +46,7 @@ struct SynthXilinxPass : public ScriptPass
log(" -top <module>\n");
log(" use the specified module as top module\n");
log("\n");
- log(" -family {xcup|xcu|xc7|xc6s}\n");
+ log(" -family {xcup|xcu|xc7|xc6v|xc6s}\n");
log(" run synthesis for the specified Xilinx architecture\n");
log(" generate the synthesis netlist for the specified family.\n");
log(" default: xc7\n");
@@ -63,6 +63,9 @@ struct SynthXilinxPass : public ScriptPass
log(" generate an output netlist (and BLIF file) suitable for VPR\n");
log(" (this feature is experimental and incomplete)\n");
log("\n");
+ log(" -ise\n");
+ log(" generate an output netlist suitable for ISE (enables -iopad)\n");
+ log("\n");
log(" -nobram\n");
log(" do not use block RAM cells in output netlist\n");
log("\n");
@@ -78,6 +81,15 @@ struct SynthXilinxPass : public ScriptPass
log(" -nowidelut\n");
log(" do not use MUXF[78] resources to implement LUTs larger than LUT6s\n");
log("\n");
+ log(" -iopad\n");
+ log(" enable I/O buffer insertion (selected automatically by -ise)\n");
+ log("\n");
+ log(" -noiopad\n");
+ log(" disable I/O buffer insertion (only useful with -ise)\n");
+ log("\n");
+ log(" -noclkbuf\n");
+ log(" disable automatic clock buffer insertion\n");
+ log("\n");
log(" -widemux <int>\n");
log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n");
log(" above this number of inputs (minimum value 2, recommended value >= 5).\n");
@@ -104,7 +116,8 @@ struct SynthXilinxPass : public ScriptPass
}
std::string top_opt, edif_file, blif_file, family;
- bool flatten, retime, vpr, nobram, nolutram, nosrl, nocarry, nowidelut, abc9;
+ bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, abc9;
+ bool flatten_before_abc;
int widemux;
void clear_flags() YS_OVERRIDE
@@ -116,6 +129,10 @@ struct SynthXilinxPass : public ScriptPass
flatten = false;
retime = false;
vpr = false;
+ ise = false;
+ iopad = false;
+ noiopad = false;
+ noclkbuf = false;
nocarry = false;
nobram = false;
nolutram = false;
@@ -123,6 +140,7 @@ struct SynthXilinxPass : public ScriptPass
nocarry = false;
nowidelut = false;
abc9 = false;
+ flatten_before_abc = false;
widemux = 0;
}
@@ -162,6 +180,10 @@ struct SynthXilinxPass : public ScriptPass
flatten = true;
continue;
}
+ if (args[argidx] == "-flatten_before_abc") {
+ flatten_before_abc = true;
+ continue;
+ }
if (args[argidx] == "-retime") {
retime = true;
continue;
@@ -178,6 +200,22 @@ struct SynthXilinxPass : public ScriptPass
vpr = true;
continue;
}
+ if (args[argidx] == "-ise") {
+ ise = true;
+ continue;
+ }
+ if (args[argidx] == "-iopad") {
+ iopad = true;
+ continue;
+ }
+ if (args[argidx] == "-noiopad") {
+ noiopad = true;
+ continue;
+ }
+ if (args[argidx] == "-noclkbuf") {
+ noclkbuf = true;
+ continue;
+ }
if (args[argidx] == "-nocarry") {
nocarry = true;
continue;
@@ -206,7 +244,7 @@ struct SynthXilinxPass : public ScriptPass
}
extra_args(args, argidx, design);
- if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6s")
+ if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" && family != "xc6s")
log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str());
if (widemux != 0 && widemux < 2)
@@ -228,19 +266,36 @@ struct SynthXilinxPass : public ScriptPass
void script() YS_OVERRIDE
{
+ std::string ff_map_file;
+ if (help_mode)
+ ff_map_file = "+/xilinx/{family}_ff_map.v";
+ else if (family == "xc6s")
+ ff_map_file = "+/xilinx/xc6s_ff_map.v";
+ else
+ ff_map_file = "+/xilinx/xc7_ff_map.v";
+
if (check_label("begin")) {
if (vpr)
run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
else
run("read_verilog -lib +/xilinx/cells_sim.v");
- run("read_verilog -lib +/xilinx/cells_xtra.v");
+ if (help_mode)
+ run("read_verilog -lib +/xilinx/{family}_cells_xtra.v");
+ else if (family == "xc6s")
+ run("read_verilog -lib +/xilinx/xc6s_cells_xtra.v");
+ else if (family == "xc6v")
+ run("read_verilog -lib +/xilinx/xc6v_cells_xtra.v");
+ else if (family == "xc7")
+ run("read_verilog -lib +/xilinx/xc7_cells_xtra.v");
+ else if (family == "xcu" || family == "xcup")
+ run("read_verilog -lib +/xilinx/xcu_cells_xtra.v");
if (help_mode) {
run("read_verilog -lib +/xilinx/{family}_brams_bb.v");
} else if (family == "xc6s") {
run("read_verilog -lib +/xilinx/xc6s_brams_bb.v");
- } else if (family == "xc7") {
+ } else if (family == "xc6v" || family == "xc7") {
run("read_verilog -lib +/xilinx/xc7_brams_bb.v");
}
@@ -265,9 +320,8 @@ struct SynthXilinxPass : public ScriptPass
if (widemux > 0 || help_mode)
run("muxpack", " ('-widemux' only)");
- // shregmap -tech xilinx can cope with $shiftx and $mux
- // cells for identifying variable-length shift registers,
- // so attempt to convert $pmux-es to the former
+ // xilinx_srl looks for $shiftx cells for identifying variable-length
+ // shift registers, so attempt to convert $pmux-es to this
// Also: wide multiplexer inference benefits from this too
if (!(nosrl && widemux == 0) || help_mode) {
run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')");
@@ -292,7 +346,7 @@ struct SynthXilinxPass : public ScriptPass
if (family == "xc6s") {
run("memory_bram -rules +/xilinx/xc6s_brams.txt");
run("techmap -map +/xilinx/xc6s_brams_map.v");
- } else if (family == "xc7") {
+ } else if (family == "xc6v" || family == "xc7") {
run("memory_bram -rules +/xilinx/xc7_brams.txt");
run("techmap -map +/xilinx/xc7_brams_map.v");
} else {
@@ -349,13 +403,8 @@ struct SynthXilinxPass : public ScriptPass
}
run("opt -full");
- if (!nosrl || help_mode) {
- // shregmap operates on bit-level flops, not word-level,
- // so break those down here
- run("simplemap t:$dff t:$dffe", " (skip if '-nosrl')");
- // shregmap with '-tech xilinx' infers variable length shift regs
- run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
- }
+ if (!nosrl || help_mode)
+ run("xilinx_srl -variable -minlen 3", "(skip if '-nosrl')");
std::string techmap_args = " -map +/techmap.v";
if (help_mode)
@@ -379,21 +428,27 @@ struct SynthXilinxPass : public ScriptPass
std::string techmap_args = "-map +/techmap.v -map +/xilinx/cells_map.v";
if (widemux > 0)
techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
- if (abc9)
- techmap_args += " -map +/xilinx/ff_map.v";
run("techmap " + techmap_args);
run("clean");
}
+ if (check_label("map_ffs")) {
+ if (abc9 || help_mode) {
+ run("techmap -map " + ff_map_file, "('-abc9' only)");
+ }
+ }
+
if (check_label("map_luts")) {
run("opt_expr -mux_undef");
+ if (flatten_before_abc)
+ run("flatten");
if (help_mode)
- run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut', option for '-retime')");
+ run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut'; option for '-retime')");
else if (abc9) {
if (family != "xc7")
log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
+ run("techmap -map +/xilinx/abc_map.v -max_iter 1");
run("read_verilog -icells -lib +/xilinx/abc_model.v");
- run("techmap -map +/xilinx/abc_map.v");
if (nowidelut)
run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
else
@@ -410,18 +465,32 @@ struct SynthXilinxPass : public ScriptPass
// This shregmap call infers fixed length shift registers after abc
// has performed any necessary retiming
if (!nosrl || help_mode)
- run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
- std::string techmap_args = "-map +/xilinx/lut_map.v";
- if (abc9)
+ run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')");
+ std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v";
+ if (help_mode)
+ techmap_args += " [-map " + ff_map_file + "]";
+ else if (abc9)
techmap_args += " -map +/xilinx/abc_unmap.v";
else
- techmap_args += " -map +/xilinx/ff_map.v";
+ techmap_args += " -map " + ff_map_file;
run("techmap " + techmap_args);
- run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
- "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
run("clean");
}
+ if (check_label("finalize")) {
+ bool do_iopad = iopad || (ise && !noiopad);
+ if (help_mode || !noclkbuf) {
+ if (help_mode || do_iopad)
+ run("clkbufmap -buf BUFG O:I -inpad IBUFG O:I", "(skip if '-noclkbuf', '-inpad' passed if '-iopad' or '-ise' and not '-noiopad')");
+ else
+ run("clkbufmap -buf BUFG O:I");
+ }
+ if (help_mode || do_iopad)
+ run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I A:top", "(only if '-iopad' or '-ise' and not '-noiopad')");
+ if (help_mode || ise)
+ run("extractinv -inv INV O:I", "(only if '-ise')");
+ }
+
if (check_label("check")) {
run("hierarchy -check");
run("stat -tech xilinx");
diff --git a/techlibs/xilinx/xc6s_brams_bb.v b/techlibs/xilinx/xc6s_brams_bb.v
index eb1a29579..041d6b54f 100644
--- a/techlibs/xilinx/xc6s_brams_bb.v
+++ b/techlibs/xilinx/xc6s_brams_bb.v
@@ -1,5 +1,7 @@
module RAMB8BWER (
+ (* clkbuf_sink *)
input CLKAWRCLK,
+ (* clkbuf_sink *)
input CLKBRDCLK,
input ENAWREN,
input ENBRDEN,
@@ -87,7 +89,9 @@ module RAMB8BWER (
endmodule
module RAMB16BWER (
+ (* clkbuf_sink *)
input CLKA,
+ (* clkbuf_sink *)
input CLKB,
input ENA,
input ENB,
diff --git a/techlibs/xilinx/xc6s_cells_xtra.v b/techlibs/xilinx/xc6s_cells_xtra.v
new file mode 100644
index 000000000..014e73df0
--- /dev/null
+++ b/techlibs/xilinx/xc6s_cells_xtra.v
@@ -0,0 +1,1859 @@
+// Created by cells_xtra.py from Xilinx models
+
+module MCB (...);
+ parameter integer ARB_NUM_TIME_SLOTS = 12;
+ parameter [17:0] ARB_TIME_SLOT_0 = 18'b111111111111111111;
+ parameter [17:0] ARB_TIME_SLOT_1 = 18'b111111111111111111;
+ parameter [17:0] ARB_TIME_SLOT_10 = 18'b111111111111111111;
+ parameter [17:0] ARB_TIME_SLOT_11 = 18'b111111111111111111;
+ parameter [17:0] ARB_TIME_SLOT_2 = 18'b111111111111111111;
+ parameter [17:0] ARB_TIME_SLOT_3 = 18'b111111111111111111;
+ parameter [17:0] ARB_TIME_SLOT_4 = 18'b111111111111111111;
+ parameter [17:0] ARB_TIME_SLOT_5 = 18'b111111111111111111;
+ parameter [17:0] ARB_TIME_SLOT_6 = 18'b111111111111111111;
+ parameter [17:0] ARB_TIME_SLOT_7 = 18'b111111111111111111;
+ parameter [17:0] ARB_TIME_SLOT_8 = 18'b111111111111111111;
+ parameter [17:0] ARB_TIME_SLOT_9 = 18'b111111111111111111;
+ parameter [2:0] CAL_BA = 3'h0;
+ parameter CAL_BYPASS = "YES";
+ parameter [11:0] CAL_CA = 12'h000;
+ parameter CAL_CALIBRATION_MODE = "NOCALIBRATION";
+ parameter integer CAL_CLK_DIV = 1;
+ parameter CAL_DELAY = "QUARTER";
+ parameter [14:0] CAL_RA = 15'h0000;
+ parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN";
+ parameter integer MEM_BA_SIZE = 3;
+ parameter integer MEM_BURST_LEN = 8;
+ parameter integer MEM_CAS_LATENCY = 4;
+ parameter integer MEM_CA_SIZE = 11;
+ parameter MEM_DDR1_2_ODS = "FULL";
+ parameter MEM_DDR2_3_HIGH_TEMP_SR = "NORMAL";
+ parameter MEM_DDR2_3_PA_SR = "FULL";
+ parameter integer MEM_DDR2_ADD_LATENCY = 0;
+ parameter MEM_DDR2_DIFF_DQS_EN = "YES";
+ parameter MEM_DDR2_RTT = "50OHMS";
+ parameter integer MEM_DDR2_WRT_RECOVERY = 4;
+ parameter MEM_DDR3_ADD_LATENCY = "OFF";
+ parameter MEM_DDR3_AUTO_SR = "ENABLED";
+ parameter integer MEM_DDR3_CAS_LATENCY = 7;
+ parameter integer MEM_DDR3_CAS_WR_LATENCY = 5;
+ parameter MEM_DDR3_DYN_WRT_ODT = "OFF";
+ parameter MEM_DDR3_ODS = "DIV7";
+ parameter MEM_DDR3_RTT = "DIV2";
+ parameter integer MEM_DDR3_WRT_RECOVERY = 7;
+ parameter MEM_MDDR_ODS = "FULL";
+ parameter MEM_MOBILE_PA_SR = "FULL";
+ parameter integer MEM_MOBILE_TC_SR = 0;
+ parameter integer MEM_RAS_VAL = 0;
+ parameter integer MEM_RA_SIZE = 13;
+ parameter integer MEM_RCD_VAL = 1;
+ parameter integer MEM_REFI_VAL = 0;
+ parameter integer MEM_RFC_VAL = 0;
+ parameter integer MEM_RP_VAL = 0;
+ parameter integer MEM_RTP_VAL = 0;
+ parameter MEM_TYPE = "DDR3";
+ parameter integer MEM_WIDTH = 4;
+ parameter integer MEM_WR_VAL = 0;
+ parameter integer MEM_WTR_VAL = 3;
+ parameter PORT_CONFIG = "B32_B32_B32_B32";
+ output CAS;
+ output CKE;
+ output DQIOWEN0;
+ output DQSIOWEN90N;
+ output DQSIOWEN90P;
+ output IOIDRPADD;
+ output IOIDRPBROADCAST;
+ output IOIDRPCLK;
+ output IOIDRPCS;
+ output IOIDRPSDO;
+ output IOIDRPTRAIN;
+ output IOIDRPUPDATE;
+ output LDMN;
+ output LDMP;
+ output ODT;
+ output P0CMDEMPTY;
+ output P0CMDFULL;
+ output P0RDEMPTY;
+ output P0RDERROR;
+ output P0RDFULL;
+ output P0RDOVERFLOW;
+ output P0WREMPTY;
+ output P0WRERROR;
+ output P0WRFULL;
+ output P0WRUNDERRUN;
+ output P1CMDEMPTY;
+ output P1CMDFULL;
+ output P1RDEMPTY;
+ output P1RDERROR;
+ output P1RDFULL;
+ output P1RDOVERFLOW;
+ output P1WREMPTY;
+ output P1WRERROR;
+ output P1WRFULL;
+ output P1WRUNDERRUN;
+ output P2CMDEMPTY;
+ output P2CMDFULL;
+ output P2EMPTY;
+ output P2ERROR;
+ output P2FULL;
+ output P2RDOVERFLOW;
+ output P2WRUNDERRUN;
+ output P3CMDEMPTY;
+ output P3CMDFULL;
+ output P3EMPTY;
+ output P3ERROR;
+ output P3FULL;
+ output P3RDOVERFLOW;
+ output P3WRUNDERRUN;
+ output P4CMDEMPTY;
+ output P4CMDFULL;
+ output P4EMPTY;
+ output P4ERROR;
+ output P4FULL;
+ output P4RDOVERFLOW;
+ output P4WRUNDERRUN;
+ output P5CMDEMPTY;
+ output P5CMDFULL;
+ output P5EMPTY;
+ output P5ERROR;
+ output P5FULL;
+ output P5RDOVERFLOW;
+ output P5WRUNDERRUN;
+ output RAS;
+ output RST;
+ output SELFREFRESHMODE;
+ output UDMN;
+ output UDMP;
+ output UOCALSTART;
+ output UOCMDREADYIN;
+ output UODATAVALID;
+ output UODONECAL;
+ output UOREFRSHFLAG;
+ output UOSDO;
+ output WE;
+ output [14:0] ADDR;
+ output [15:0] DQON;
+ output [15:0] DQOP;
+ output [2:0] BA;
+ output [31:0] P0RDDATA;
+ output [31:0] P1RDDATA;
+ output [31:0] P2RDDATA;
+ output [31:0] P3RDDATA;
+ output [31:0] P4RDDATA;
+ output [31:0] P5RDDATA;
+ output [31:0] STATUS;
+ output [4:0] IOIDRPADDR;
+ output [6:0] P0RDCOUNT;
+ output [6:0] P0WRCOUNT;
+ output [6:0] P1RDCOUNT;
+ output [6:0] P1WRCOUNT;
+ output [6:0] P2COUNT;
+ output [6:0] P3COUNT;
+ output [6:0] P4COUNT;
+ output [6:0] P5COUNT;
+ output [7:0] UODATA;
+ input DQSIOIN;
+ input DQSIOIP;
+ input IOIDRPSDI;
+ input P0ARBEN;
+ input P0CMDCLK;
+ input P0CMDEN;
+ input P0RDCLK;
+ input P0RDEN;
+ input P0WRCLK;
+ input P0WREN;
+ input P1ARBEN;
+ input P1CMDCLK;
+ input P1CMDEN;
+ input P1RDCLK;
+ input P1RDEN;
+ input P1WRCLK;
+ input P1WREN;
+ input P2ARBEN;
+ input P2CLK;
+ input P2CMDCLK;
+ input P2CMDEN;
+ input P2EN;
+ input P3ARBEN;
+ input P3CLK;
+ input P3CMDCLK;
+ input P3CMDEN;
+ input P3EN;
+ input P4ARBEN;
+ input P4CLK;
+ input P4CMDCLK;
+ input P4CMDEN;
+ input P4EN;
+ input P5ARBEN;
+ input P5CLK;
+ input P5CMDCLK;
+ input P5CMDEN;
+ input P5EN;
+ input PLLLOCK;
+ input RECAL;
+ input SELFREFRESHENTER;
+ input SYSRST;
+ input UDQSIOIN;
+ input UDQSIOIP;
+ input UIADD;
+ input UIBROADCAST;
+ input UICLK;
+ input UICMD;
+ input UICMDEN;
+ input UICMDIN;
+ input UICS;
+ input UIDONECAL;
+ input UIDQLOWERDEC;
+ input UIDQLOWERINC;
+ input UIDQUPPERDEC;
+ input UIDQUPPERINC;
+ input UIDRPUPDATE;
+ input UILDQSDEC;
+ input UILDQSINC;
+ input UIREAD;
+ input UISDI;
+ input UIUDQSDEC;
+ input UIUDQSINC;
+ input [11:0] P0CMDCA;
+ input [11:0] P1CMDCA;
+ input [11:0] P2CMDCA;
+ input [11:0] P3CMDCA;
+ input [11:0] P4CMDCA;
+ input [11:0] P5CMDCA;
+ input [14:0] P0CMDRA;
+ input [14:0] P1CMDRA;
+ input [14:0] P2CMDRA;
+ input [14:0] P3CMDRA;
+ input [14:0] P4CMDRA;
+ input [14:0] P5CMDRA;
+ input [15:0] DQI;
+ input [1:0] PLLCE;
+ input [1:0] PLLCLK;
+ input [2:0] P0CMDBA;
+ input [2:0] P0CMDINSTR;
+ input [2:0] P1CMDBA;
+ input [2:0] P1CMDINSTR;
+ input [2:0] P2CMDBA;
+ input [2:0] P2CMDINSTR;
+ input [2:0] P3CMDBA;
+ input [2:0] P3CMDINSTR;
+ input [2:0] P4CMDBA;
+ input [2:0] P4CMDINSTR;
+ input [2:0] P5CMDBA;
+ input [2:0] P5CMDINSTR;
+ input [31:0] P0WRDATA;
+ input [31:0] P1WRDATA;
+ input [31:0] P2WRDATA;
+ input [31:0] P3WRDATA;
+ input [31:0] P4WRDATA;
+ input [31:0] P5WRDATA;
+ input [3:0] P0RWRMASK;
+ input [3:0] P1RWRMASK;
+ input [3:0] P2WRMASK;
+ input [3:0] P3WRMASK;
+ input [3:0] P4WRMASK;
+ input [3:0] P5WRMASK;
+ input [3:0] UIDQCOUNT;
+ input [4:0] UIADDR;
+ input [5:0] P0CMDBL;
+ input [5:0] P1CMDBL;
+ input [5:0] P2CMDBL;
+ input [5:0] P3CMDBL;
+ input [5:0] P4CMDBL;
+ input [5:0] P5CMDBL;
+endmodule
+
+module PCIE_A1 (...);
+ parameter [31:0] BAR0 = 32'h00000000;
+ parameter [31:0] BAR1 = 32'h00000000;
+ parameter [31:0] BAR2 = 32'h00000000;
+ parameter [31:0] BAR3 = 32'h00000000;
+ parameter [31:0] BAR4 = 32'h00000000;
+ parameter [31:0] BAR5 = 32'h00000000;
+ parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000;
+ parameter [23:0] CLASS_CODE = 24'h000000;
+ parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 7;
+ parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 7;
+ parameter DEV_CAP_EXT_TAG_SUPPORTED = "FALSE";
+ parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2;
+ parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0;
+ parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE";
+ parameter DISABLE_BAR_FILTERING = "FALSE";
+ parameter DISABLE_ID_CHECK = "FALSE";
+ parameter DISABLE_SCRAMBLING = "FALSE";
+ parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE";
+ parameter [21:0] EXPANSION_ROM = 22'h000000;
+ parameter FAST_TRAIN = "FALSE";
+ parameter integer GTP_SEL = 0;
+ parameter integer LINK_CAP_ASPM_SUPPORT = 1;
+ parameter integer LINK_CAP_L0S_EXIT_LATENCY = 7;
+ parameter integer LINK_CAP_L1_EXIT_LATENCY = 7;
+ parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "FALSE";
+ parameter [14:0] LL_ACK_TIMEOUT = 15'h0204;
+ parameter LL_ACK_TIMEOUT_EN = "FALSE";
+ parameter [14:0] LL_REPLAY_TIMEOUT = 15'h060D;
+ parameter LL_REPLAY_TIMEOUT_EN = "FALSE";
+ parameter integer MSI_CAP_MULTIMSGCAP = 0;
+ parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0;
+ parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h1;
+ parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0;
+ parameter [4:0] PCIE_CAP_INT_MSG_NUM = 5'b00000;
+ parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE";
+ parameter [11:0] PCIE_GENERIC = 12'h000;
+ parameter PLM_AUTO_CONFIG = "FALSE";
+ parameter integer PM_CAP_AUXCURRENT = 0;
+ parameter PM_CAP_D1SUPPORT = "TRUE";
+ parameter PM_CAP_D2SUPPORT = "TRUE";
+ parameter PM_CAP_DSI = "FALSE";
+ parameter [4:0] PM_CAP_PMESUPPORT = 5'b01111;
+ parameter PM_CAP_PME_CLOCK = "FALSE";
+ parameter integer PM_CAP_VERSION = 3;
+ parameter [7:0] PM_DATA0 = 8'h1E;
+ parameter [7:0] PM_DATA1 = 8'h1E;
+ parameter [7:0] PM_DATA2 = 8'h1E;
+ parameter [7:0] PM_DATA3 = 8'h1E;
+ parameter [7:0] PM_DATA4 = 8'h1E;
+ parameter [7:0] PM_DATA5 = 8'h1E;
+ parameter [7:0] PM_DATA6 = 8'h1E;
+ parameter [7:0] PM_DATA7 = 8'h1E;
+ parameter [1:0] PM_DATA_SCALE0 = 2'b01;
+ parameter [1:0] PM_DATA_SCALE1 = 2'b01;
+ parameter [1:0] PM_DATA_SCALE2 = 2'b01;
+ parameter [1:0] PM_DATA_SCALE3 = 2'b01;
+ parameter [1:0] PM_DATA_SCALE4 = 2'b01;
+ parameter [1:0] PM_DATA_SCALE5 = 2'b01;
+ parameter [1:0] PM_DATA_SCALE6 = 2'b01;
+ parameter [1:0] PM_DATA_SCALE7 = 2'b01;
+ parameter SIM_VERSION = "1.0";
+ parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE";
+ parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE";
+ parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE";
+ parameter integer TL_RX_RAM_RADDR_LATENCY = 1;
+ parameter integer TL_RX_RAM_RDATA_LATENCY = 2;
+ parameter integer TL_RX_RAM_WRITE_LATENCY = 0;
+ parameter TL_TFC_DISABLE = "FALSE";
+ parameter TL_TX_CHECKS_DISABLE = "FALSE";
+ parameter integer TL_TX_RAM_RADDR_LATENCY = 0;
+ parameter integer TL_TX_RAM_RDATA_LATENCY = 2;
+ parameter USR_CFG = "FALSE";
+ parameter USR_EXT_CFG = "FALSE";
+ parameter VC0_CPL_INFINITE = "TRUE";
+ parameter [11:0] VC0_RX_RAM_LIMIT = 12'h01E;
+ parameter integer VC0_TOTAL_CREDITS_CD = 104;
+ parameter integer VC0_TOTAL_CREDITS_CH = 36;
+ parameter integer VC0_TOTAL_CREDITS_NPH = 8;
+ parameter integer VC0_TOTAL_CREDITS_PD = 288;
+ parameter integer VC0_TOTAL_CREDITS_PH = 32;
+ parameter integer VC0_TX_LASTPACKET = 31;
+ output CFGCOMMANDBUSMASTERENABLE;
+ output CFGCOMMANDINTERRUPTDISABLE;
+ output CFGCOMMANDIOENABLE;
+ output CFGCOMMANDMEMENABLE;
+ output CFGCOMMANDSERREN;
+ output CFGDEVCONTROLAUXPOWEREN;
+ output CFGDEVCONTROLCORRERRREPORTINGEN;
+ output CFGDEVCONTROLENABLERO;
+ output CFGDEVCONTROLEXTTAGEN;
+ output CFGDEVCONTROLFATALERRREPORTINGEN;
+ output CFGDEVCONTROLNONFATALREPORTINGEN;
+ output CFGDEVCONTROLNOSNOOPEN;
+ output CFGDEVCONTROLPHANTOMEN;
+ output CFGDEVCONTROLURERRREPORTINGEN;
+ output CFGDEVSTATUSCORRERRDETECTED;
+ output CFGDEVSTATUSFATALERRDETECTED;
+ output CFGDEVSTATUSNONFATALERRDETECTED;
+ output CFGDEVSTATUSURDETECTED;
+ output CFGERRCPLRDYN;
+ output CFGINTERRUPTMSIENABLE;
+ output CFGINTERRUPTRDYN;
+ output CFGLINKCONTOLRCB;
+ output CFGLINKCONTROLCOMMONCLOCK;
+ output CFGLINKCONTROLEXTENDEDSYNC;
+ output CFGRDWRDONEN;
+ output CFGTOTURNOFFN;
+ output DBGBADDLLPSTATUS;
+ output DBGBADTLPLCRC;
+ output DBGBADTLPSEQNUM;
+ output DBGBADTLPSTATUS;
+ output DBGDLPROTOCOLSTATUS;
+ output DBGFCPROTOCOLERRSTATUS;
+ output DBGMLFRMDLENGTH;
+ output DBGMLFRMDMPS;
+ output DBGMLFRMDTCVC;
+ output DBGMLFRMDTLPSTATUS;
+ output DBGMLFRMDUNRECTYPE;
+ output DBGPOISTLPSTATUS;
+ output DBGRCVROVERFLOWSTATUS;
+ output DBGREGDETECTEDCORRECTABLE;
+ output DBGREGDETECTEDFATAL;
+ output DBGREGDETECTEDNONFATAL;
+ output DBGREGDETECTEDUNSUPPORTED;
+ output DBGRPLYROLLOVERSTATUS;
+ output DBGRPLYTIMEOUTSTATUS;
+ output DBGURNOBARHIT;
+ output DBGURPOISCFGWR;
+ output DBGURSTATUS;
+ output DBGURUNSUPMSG;
+ output MIMRXREN;
+ output MIMRXWEN;
+ output MIMTXREN;
+ output MIMTXWEN;
+ output PIPEGTTXELECIDLEA;
+ output PIPEGTTXELECIDLEB;
+ output PIPERXPOLARITYA;
+ output PIPERXPOLARITYB;
+ output PIPERXRESETA;
+ output PIPERXRESETB;
+ output PIPETXRCVRDETA;
+ output PIPETXRCVRDETB;
+ output RECEIVEDHOTRESET;
+ output TRNLNKUPN;
+ output TRNREOFN;
+ output TRNRERRFWDN;
+ output TRNRSOFN;
+ output TRNRSRCDSCN;
+ output TRNRSRCRDYN;
+ output TRNTCFGREQN;
+ output TRNTDSTRDYN;
+ output TRNTERRDROPN;
+ output USERRSTN;
+ output [11:0] MIMRXRADDR;
+ output [11:0] MIMRXWADDR;
+ output [11:0] MIMTXRADDR;
+ output [11:0] MIMTXWADDR;
+ output [11:0] TRNFCCPLD;
+ output [11:0] TRNFCNPD;
+ output [11:0] TRNFCPD;
+ output [15:0] PIPETXDATAA;
+ output [15:0] PIPETXDATAB;
+ output [1:0] CFGLINKCONTROLASPMCONTROL;
+ output [1:0] PIPEGTPOWERDOWNA;
+ output [1:0] PIPEGTPOWERDOWNB;
+ output [1:0] PIPETXCHARDISPMODEA;
+ output [1:0] PIPETXCHARDISPMODEB;
+ output [1:0] PIPETXCHARDISPVALA;
+ output [1:0] PIPETXCHARDISPVALB;
+ output [1:0] PIPETXCHARISKA;
+ output [1:0] PIPETXCHARISKB;
+ output [2:0] CFGDEVCONTROLMAXPAYLOAD;
+ output [2:0] CFGDEVCONTROLMAXREADREQ;
+ output [2:0] CFGFUNCTIONNUMBER;
+ output [2:0] CFGINTERRUPTMMENABLE;
+ output [2:0] CFGPCIELINKSTATEN;
+ output [31:0] CFGDO;
+ output [31:0] TRNRD;
+ output [34:0] MIMRXWDATA;
+ output [35:0] MIMTXWDATA;
+ output [4:0] CFGDEVICENUMBER;
+ output [4:0] CFGLTSSMSTATE;
+ output [5:0] TRNTBUFAV;
+ output [6:0] TRNRBARHITN;
+ output [7:0] CFGBUSNUMBER;
+ output [7:0] CFGINTERRUPTDO;
+ output [7:0] TRNFCCPLH;
+ output [7:0] TRNFCNPH;
+ output [7:0] TRNFCPH;
+ input CFGERRCORN;
+ input CFGERRCPLABORTN;
+ input CFGERRCPLTIMEOUTN;
+ input CFGERRECRCN;
+ input CFGERRLOCKEDN;
+ input CFGERRPOSTEDN;
+ input CFGERRURN;
+ input CFGINTERRUPTASSERTN;
+ input CFGINTERRUPTN;
+ input CFGPMWAKEN;
+ input CFGRDENN;
+ input CFGTRNPENDINGN;
+ input CFGTURNOFFOKN;
+ input CLOCKLOCKED;
+ input MGTCLK;
+ input PIPEGTRESETDONEA;
+ input PIPEGTRESETDONEB;
+ input PIPEPHYSTATUSA;
+ input PIPEPHYSTATUSB;
+ input PIPERXENTERELECIDLEA;
+ input PIPERXENTERELECIDLEB;
+ input SYSRESETN;
+ input TRNRDSTRDYN;
+ input TRNRNPOKN;
+ input TRNTCFGGNTN;
+ input TRNTEOFN;
+ input TRNTERRFWDN;
+ input TRNTSOFN;
+ input TRNTSRCDSCN;
+ input TRNTSRCRDYN;
+ input TRNTSTRN;
+ input USERCLK;
+ input [15:0] CFGDEVID;
+ input [15:0] CFGSUBSYSID;
+ input [15:0] CFGSUBSYSVENID;
+ input [15:0] CFGVENID;
+ input [15:0] PIPERXDATAA;
+ input [15:0] PIPERXDATAB;
+ input [1:0] PIPERXCHARISKA;
+ input [1:0] PIPERXCHARISKB;
+ input [2:0] PIPERXSTATUSA;
+ input [2:0] PIPERXSTATUSB;
+ input [2:0] TRNFCSEL;
+ input [31:0] TRNTD;
+ input [34:0] MIMRXRDATA;
+ input [35:0] MIMTXRDATA;
+ input [47:0] CFGERRTLPCPLHEADER;
+ input [63:0] CFGDSN;
+ input [7:0] CFGINTERRUPTDI;
+ input [7:0] CFGREVID;
+ input [9:0] CFGDWADDR;
+endmodule
+
+module DSP48A1 (...);
+ parameter integer A0REG = 0;
+ parameter integer A1REG = 1;
+ parameter integer B0REG = 0;
+ parameter integer B1REG = 1;
+ parameter integer CARRYINREG = 1;
+ parameter integer CARRYOUTREG = 1;
+ parameter CARRYINSEL = "OPMODE5";
+ parameter integer CREG = 1;
+ parameter integer DREG = 1;
+ parameter integer MREG = 1;
+ parameter integer OPMODEREG = 1;
+ parameter integer PREG = 1;
+ parameter RSTTYPE = "SYNC";
+ output [17:0] BCOUT;
+ output CARRYOUT;
+ output CARRYOUTF;
+ output [35:0] M;
+ output [47:0] P;
+ output [47:0] PCOUT;
+ input [17:0] A;
+ input [17:0] B;
+ input [47:0] C;
+ input CARRYIN;
+ input CEA;
+ input CEB;
+ input CEC;
+ input CECARRYIN;
+ input CED;
+ input CEM;
+ input CEOPMODE;
+ input CEP;
+ (* clkbuf_sink *)
+ input CLK;
+ input [17:0] D;
+ input [7:0] OPMODE;
+ input [47:0] PCIN;
+ input RSTA;
+ input RSTB;
+ input RSTC;
+ input RSTCARRYIN;
+ input RSTD;
+ input RSTM;
+ input RSTOPMODE;
+ input RSTP;
+endmodule
+
+module BUFGCE (...);
+ parameter CE_TYPE = "SYNC";
+ parameter [0:0] IS_CE_INVERTED = 1'b0;
+ parameter [0:0] IS_I_INVERTED = 1'b0;
+ (* clkbuf_driver *)
+ output O;
+ (* invertible_pin = "IS_CE_INVERTED" *)
+ input CE;
+ (* invertible_pin = "IS_I_INVERTED" *)
+ input I;
+endmodule
+
+module BUFGCE_1 (...);
+ (* clkbuf_driver *)
+ output O;
+ input CE;
+ input I;
+endmodule
+
+module BUFGMUX (...);
+ parameter CLK_SEL_TYPE = "SYNC";
+ (* clkbuf_driver *)
+ output O;
+ input I0;
+ input I1;
+ input S;
+endmodule
+
+module BUFGMUX_1 (...);
+ parameter CLK_SEL_TYPE = "SYNC";
+ (* clkbuf_driver *)
+ output O;
+ input I0;
+ input I1;
+ input S;
+endmodule
+
+module BUFH (...);
+ (* clkbuf_driver *)
+ output O;
+ input I;
+endmodule
+
+module BUFIO2 (...);
+ parameter DIVIDE_BYPASS = "TRUE";
+ parameter integer DIVIDE = 1;
+ parameter I_INVERT = "FALSE";
+ parameter USE_DOUBLER = "FALSE";
+ (* clkbuf_driver *)
+ output DIVCLK;
+ (* clkbuf_driver *)
+ output IOCLK;
+ output SERDESSTROBE;
+ input I;
+endmodule
+
+module BUFIO2_2CLK (...);
+ parameter integer DIVIDE = 2;
+ (* clkbuf_driver *)
+ output DIVCLK;
+ (* clkbuf_driver *)
+ output IOCLK;
+ output SERDESSTROBE;
+ input I;
+ input IB;
+endmodule
+
+module BUFIO2FB (...);
+ parameter DIVIDE_BYPASS = "TRUE";
+ (* clkbuf_driver *)
+ output O;
+ input I;
+endmodule
+
+module BUFPLL_MCB (...);
+ parameter integer DIVIDE = 2;
+ parameter LOCK_SRC = "LOCK_TO_0";
+ (* clkbuf_driver *)
+ output IOCLK0;
+ (* clkbuf_driver *)
+ output IOCLK1;
+ output LOCK;
+ output SERDESSTROBE0;
+ output SERDESSTROBE1;
+ input GCLK;
+ input LOCKED;
+ input PLLIN0;
+ input PLLIN1;
+endmodule
+
+module DCM_CLKGEN (...);
+ parameter SPREAD_SPECTRUM = "NONE";
+ parameter STARTUP_WAIT = "FALSE";
+ parameter integer CLKFXDV_DIVIDE = 2;
+ parameter integer CLKFX_DIVIDE = 1;
+ parameter integer CLKFX_MULTIPLY = 4;
+ parameter real CLKFX_MD_MAX = 0.0;
+ parameter real CLKIN_PERIOD = 0.0;
+ output CLKFX180;
+ output CLKFX;
+ output CLKFXDV;
+ output LOCKED;
+ output PROGDONE;
+ output [2:1] STATUS;
+ input CLKIN;
+ input FREEZEDCM;
+ input PROGCLK;
+ input PROGDATA;
+ input PROGEN;
+ input RST;
+endmodule
+
+module DCM_SP (...);
+ parameter real CLKDV_DIVIDE = 2.0;
+ parameter integer CLKFX_DIVIDE = 1;
+ parameter integer CLKFX_MULTIPLY = 4;
+ parameter CLKIN_DIVIDE_BY_2 = "FALSE";
+ parameter real CLKIN_PERIOD = 10.0;
+ parameter CLKOUT_PHASE_SHIFT = "NONE";
+ parameter CLK_FEEDBACK = "1X";
+ parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+ parameter DFS_FREQUENCY_MODE = "LOW";
+ parameter DLL_FREQUENCY_MODE = "LOW";
+ parameter DSS_MODE = "NONE";
+ parameter DUTY_CYCLE_CORRECTION = "TRUE";
+ parameter FACTORY_JF = 16'hC080;
+ parameter integer PHASE_SHIFT = 0;
+ parameter STARTUP_WAIT = "FALSE";
+ input CLKFB;
+ input CLKIN;
+ input DSSEN;
+ input PSCLK;
+ input PSEN;
+ input PSINCDEC;
+ input RST;
+ output CLK0;
+ output CLK180;
+ output CLK270;
+ output CLK2X;
+ output CLK2X180;
+ output CLK90;
+ output CLKDV;
+ output CLKFX;
+ output CLKFX180;
+ output LOCKED;
+ output PSDONE;
+ output [7:0] STATUS;
+endmodule
+
+module PLL_BASE (...);
+ parameter BANDWIDTH = "OPTIMIZED";
+ parameter integer CLKFBOUT_MULT = 1;
+ parameter real CLKFBOUT_PHASE = 0.0;
+ parameter real CLKIN_PERIOD = 0.000;
+ parameter integer CLKOUT0_DIVIDE = 1;
+ parameter real CLKOUT0_DUTY_CYCLE = 0.5;
+ parameter real CLKOUT0_PHASE = 0.0;
+ parameter integer CLKOUT1_DIVIDE = 1;
+ parameter real CLKOUT1_DUTY_CYCLE = 0.5;
+ parameter real CLKOUT1_PHASE = 0.0;
+ parameter integer CLKOUT2_DIVIDE = 1;
+ parameter real CLKOUT2_DUTY_CYCLE = 0.5;
+ parameter real CLKOUT2_PHASE = 0.0;
+ parameter integer CLKOUT3_DIVIDE = 1;
+ parameter real CLKOUT3_DUTY_CYCLE = 0.5;
+ parameter real CLKOUT3_PHASE = 0.0;
+ parameter integer CLKOUT4_DIVIDE = 1;
+ parameter real CLKOUT4_DUTY_CYCLE = 0.5;
+ parameter real CLKOUT4_PHASE = 0.0;
+ parameter integer CLKOUT5_DIVIDE = 1;
+ parameter real CLKOUT5_DUTY_CYCLE = 0.5;
+ parameter real CLKOUT5_PHASE = 0.0;
+ parameter CLK_FEEDBACK = "CLKFBOUT";
+ parameter COMPENSATION = "SYSTEM_SYNCHRONOUS";
+ parameter integer DIVCLK_DIVIDE = 1;
+ parameter real REF_JITTER = 0.100;
+ parameter RESET_ON_LOSS_OF_LOCK = "FALSE";
+ output CLKFBOUT;
+ output CLKOUT0;
+ output CLKOUT1;
+ output CLKOUT2;
+ output CLKOUT3;
+ output CLKOUT4;
+ output CLKOUT5;
+ output LOCKED;
+ input CLKFBIN;
+ input CLKIN;
+ input RST;
+endmodule
+
+(* keep *)
+module BSCAN_SPARTAN6 (...);
+ parameter integer JTAG_CHAIN = 1;
+ output CAPTURE;
+ output DRCK;
+ output RESET;
+ output RUNTEST;
+ output SEL;
+ output SHIFT;
+ output TCK;
+ output TDI;
+ output TMS;
+ output UPDATE;
+ input TDO;
+endmodule
+
+module DNA_PORT (...);
+ parameter [56:0] SIM_DNA_VALUE = 57'h0;
+ output DOUT;
+ input CLK;
+ input DIN;
+ input READ;
+ input SHIFT;
+endmodule
+
+(* keep *)
+module ICAP_SPARTAN6 (...);
+ parameter DEVICE_ID = 32'h04000093;
+ parameter SIM_CFG_FILE_NAME = "NONE";
+ output BUSY;
+ output [15:0] O;
+ input CLK;
+ input CE;
+ input WRITE;
+ input [15:0] I;
+endmodule
+
+module POST_CRC_INTERNAL (...);
+ output CRCERROR;
+endmodule
+
+(* keep *)
+module STARTUP_SPARTAN6 (...);
+ output CFGCLK;
+ output CFGMCLK;
+ output EOS;
+ input CLK;
+ input GSR;
+ input GTS;
+ input KEYCLEARB;
+endmodule
+
+(* keep *)
+module SUSPEND_SYNC (...);
+ output SREQ;
+ input CLK;
+ input SACK;
+endmodule
+
+module GTPA1_DUAL (...);
+ parameter AC_CAP_DIS_0 = "TRUE";
+ parameter AC_CAP_DIS_1 = "TRUE";
+ parameter integer ALIGN_COMMA_WORD_0 = 1;
+ parameter integer ALIGN_COMMA_WORD_1 = 1;
+ parameter integer CB2_INH_CC_PERIOD_0 = 8;
+ parameter integer CB2_INH_CC_PERIOD_1 = 8;
+ parameter [4:0] CDR_PH_ADJ_TIME_0 = 5'b01010;
+ parameter [4:0] CDR_PH_ADJ_TIME_1 = 5'b01010;
+ parameter integer CHAN_BOND_1_MAX_SKEW_0 = 7;
+ parameter integer CHAN_BOND_1_MAX_SKEW_1 = 7;
+ parameter integer CHAN_BOND_2_MAX_SKEW_0 = 1;
+ parameter integer CHAN_BOND_2_MAX_SKEW_1 = 1;
+ parameter CHAN_BOND_KEEP_ALIGN_0 = "FALSE";
+ parameter CHAN_BOND_KEEP_ALIGN_1 = "FALSE";
+ parameter [9:0] CHAN_BOND_SEQ_1_1_0 = 10'b0101111100;
+ parameter [9:0] CHAN_BOND_SEQ_1_1_1 = 10'b0101111100;
+ parameter [9:0] CHAN_BOND_SEQ_1_2_0 = 10'b0001001010;
+ parameter [9:0] CHAN_BOND_SEQ_1_2_1 = 10'b0001001010;
+ parameter [9:0] CHAN_BOND_SEQ_1_3_0 = 10'b0001001010;
+ parameter [9:0] CHAN_BOND_SEQ_1_3_1 = 10'b0001001010;
+ parameter [9:0] CHAN_BOND_SEQ_1_4_0 = 10'b0110111100;
+ parameter [9:0] CHAN_BOND_SEQ_1_4_1 = 10'b0110111100;
+ parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_0 = 4'b1111;
+ parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_1 = 4'b1111;
+ parameter [9:0] CHAN_BOND_SEQ_2_1_0 = 10'b0110111100;
+ parameter [9:0] CHAN_BOND_SEQ_2_1_1 = 10'b0110111100;
+ parameter [9:0] CHAN_BOND_SEQ_2_2_0 = 10'b0100111100;
+ parameter [9:0] CHAN_BOND_SEQ_2_2_1 = 10'b0100111100;
+ parameter [9:0] CHAN_BOND_SEQ_2_3_0 = 10'b0100111100;
+ parameter [9:0] CHAN_BOND_SEQ_2_3_1 = 10'b0100111100;
+ parameter [9:0] CHAN_BOND_SEQ_2_4_0 = 10'b0100111100;
+ parameter [9:0] CHAN_BOND_SEQ_2_4_1 = 10'b0100111100;
+ parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_0 = 4'b1111;
+ parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_1 = 4'b1111;
+ parameter CHAN_BOND_SEQ_2_USE_0 = "FALSE";
+ parameter CHAN_BOND_SEQ_2_USE_1 = "FALSE";
+ parameter integer CHAN_BOND_SEQ_LEN_0 = 1;
+ parameter integer CHAN_BOND_SEQ_LEN_1 = 1;
+ parameter integer CLK25_DIVIDER_0 = 4;
+ parameter integer CLK25_DIVIDER_1 = 4;
+ parameter CLKINDC_B_0 = "TRUE";
+ parameter CLKINDC_B_1 = "TRUE";
+ parameter CLKRCV_TRST_0 = "TRUE";
+ parameter CLKRCV_TRST_1 = "TRUE";
+ parameter CLK_CORRECT_USE_0 = "TRUE";
+ parameter CLK_CORRECT_USE_1 = "TRUE";
+ parameter integer CLK_COR_ADJ_LEN_0 = 1;
+ parameter integer CLK_COR_ADJ_LEN_1 = 1;
+ parameter integer CLK_COR_DET_LEN_0 = 1;
+ parameter integer CLK_COR_DET_LEN_1 = 1;
+ parameter CLK_COR_INSERT_IDLE_FLAG_0 = "FALSE";
+ parameter CLK_COR_INSERT_IDLE_FLAG_1 = "FALSE";
+ parameter CLK_COR_KEEP_IDLE_0 = "FALSE";
+ parameter CLK_COR_KEEP_IDLE_1 = "FALSE";
+ parameter integer CLK_COR_MAX_LAT_0 = 20;
+ parameter integer CLK_COR_MAX_LAT_1 = 20;
+ parameter integer CLK_COR_MIN_LAT_0 = 18;
+ parameter integer CLK_COR_MIN_LAT_1 = 18;
+ parameter CLK_COR_PRECEDENCE_0 = "TRUE";
+ parameter CLK_COR_PRECEDENCE_1 = "TRUE";
+ parameter integer CLK_COR_REPEAT_WAIT_0 = 0;
+ parameter integer CLK_COR_REPEAT_WAIT_1 = 0;
+ parameter [9:0] CLK_COR_SEQ_1_1_0 = 10'b0100011100;
+ parameter [9:0] CLK_COR_SEQ_1_1_1 = 10'b0100011100;
+ parameter [9:0] CLK_COR_SEQ_1_2_0 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_1_2_1 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_1_3_0 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_1_3_1 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_1_4_0 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_1_4_1 = 10'b0000000000;
+ parameter [3:0] CLK_COR_SEQ_1_ENABLE_0 = 4'b1111;
+ parameter [3:0] CLK_COR_SEQ_1_ENABLE_1 = 4'b1111;
+ parameter [9:0] CLK_COR_SEQ_2_1_0 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_2_1_1 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_2_2_0 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_2_2_1 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_2_3_0 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_2_3_1 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_2_4_0 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_2_4_1 = 10'b0000000000;
+ parameter [3:0] CLK_COR_SEQ_2_ENABLE_0 = 4'b1111;
+ parameter [3:0] CLK_COR_SEQ_2_ENABLE_1 = 4'b1111;
+ parameter CLK_COR_SEQ_2_USE_0 = "FALSE";
+ parameter CLK_COR_SEQ_2_USE_1 = "FALSE";
+ parameter CLK_OUT_GTP_SEL_0 = "REFCLKPLL0";
+ parameter CLK_OUT_GTP_SEL_1 = "REFCLKPLL1";
+ parameter [1:0] CM_TRIM_0 = 2'b00;
+ parameter [1:0] CM_TRIM_1 = 2'b00;
+ parameter [9:0] COMMA_10B_ENABLE_0 = 10'b1111111111;
+ parameter [9:0] COMMA_10B_ENABLE_1 = 10'b1111111111;
+ parameter [3:0] COM_BURST_VAL_0 = 4'b1111;
+ parameter [3:0] COM_BURST_VAL_1 = 4'b1111;
+ parameter DEC_MCOMMA_DETECT_0 = "TRUE";
+ parameter DEC_MCOMMA_DETECT_1 = "TRUE";
+ parameter DEC_PCOMMA_DETECT_0 = "TRUE";
+ parameter DEC_PCOMMA_DETECT_1 = "TRUE";
+ parameter DEC_VALID_COMMA_ONLY_0 = "TRUE";
+ parameter DEC_VALID_COMMA_ONLY_1 = "TRUE";
+ parameter GTP_CFG_PWRUP_0 = "TRUE";
+ parameter GTP_CFG_PWRUP_1 = "TRUE";
+ parameter [9:0] MCOMMA_10B_VALUE_0 = 10'b1010000011;
+ parameter [9:0] MCOMMA_10B_VALUE_1 = 10'b1010000011;
+ parameter MCOMMA_DETECT_0 = "TRUE";
+ parameter MCOMMA_DETECT_1 = "TRUE";
+ parameter [2:0] OOBDETECT_THRESHOLD_0 = 3'b110;
+ parameter [2:0] OOBDETECT_THRESHOLD_1 = 3'b110;
+ parameter integer OOB_CLK_DIVIDER_0 = 4;
+ parameter integer OOB_CLK_DIVIDER_1 = 4;
+ parameter PCI_EXPRESS_MODE_0 = "FALSE";
+ parameter PCI_EXPRESS_MODE_1 = "FALSE";
+ parameter [9:0] PCOMMA_10B_VALUE_0 = 10'b0101111100;
+ parameter [9:0] PCOMMA_10B_VALUE_1 = 10'b0101111100;
+ parameter PCOMMA_DETECT_0 = "TRUE";
+ parameter PCOMMA_DETECT_1 = "TRUE";
+ parameter [2:0] PLLLKDET_CFG_0 = 3'b101;
+ parameter [2:0] PLLLKDET_CFG_1 = 3'b101;
+ parameter [23:0] PLL_COM_CFG_0 = 24'h21680A;
+ parameter [23:0] PLL_COM_CFG_1 = 24'h21680A;
+ parameter [7:0] PLL_CP_CFG_0 = 8'h00;
+ parameter [7:0] PLL_CP_CFG_1 = 8'h00;
+ parameter integer PLL_DIVSEL_FB_0 = 5;
+ parameter integer PLL_DIVSEL_FB_1 = 5;
+ parameter integer PLL_DIVSEL_REF_0 = 2;
+ parameter integer PLL_DIVSEL_REF_1 = 2;
+ parameter integer PLL_RXDIVSEL_OUT_0 = 1;
+ parameter integer PLL_RXDIVSEL_OUT_1 = 1;
+ parameter PLL_SATA_0 = "FALSE";
+ parameter PLL_SATA_1 = "FALSE";
+ parameter PLL_SOURCE_0 = "PLL0";
+ parameter PLL_SOURCE_1 = "PLL0";
+ parameter integer PLL_TXDIVSEL_OUT_0 = 1;
+ parameter integer PLL_TXDIVSEL_OUT_1 = 1;
+ parameter [26:0] PMA_CDR_SCAN_0 = 27'h6404040;
+ parameter [26:0] PMA_CDR_SCAN_1 = 27'h6404040;
+ parameter [35:0] PMA_COM_CFG_EAST = 36'h000008000;
+ parameter [35:0] PMA_COM_CFG_WEST = 36'h00000A000;
+ parameter [6:0] PMA_RXSYNC_CFG_0 = 7'h00;
+ parameter [6:0] PMA_RXSYNC_CFG_1 = 7'h00;
+ parameter [24:0] PMA_RX_CFG_0 = 25'h05CE048;
+ parameter [24:0] PMA_RX_CFG_1 = 25'h05CE048;
+ parameter [19:0] PMA_TX_CFG_0 = 20'h00082;
+ parameter [19:0] PMA_TX_CFG_1 = 20'h00082;
+ parameter RCV_TERM_GND_0 = "FALSE";
+ parameter RCV_TERM_GND_1 = "FALSE";
+ parameter RCV_TERM_VTTRX_0 = "TRUE";
+ parameter RCV_TERM_VTTRX_1 = "TRUE";
+ parameter [7:0] RXEQ_CFG_0 = 8'b01111011;
+ parameter [7:0] RXEQ_CFG_1 = 8'b01111011;
+ parameter [0:0] RXPRBSERR_LOOPBACK_0 = 1'b0;
+ parameter [0:0] RXPRBSERR_LOOPBACK_1 = 1'b0;
+ parameter RX_BUFFER_USE_0 = "TRUE";
+ parameter RX_BUFFER_USE_1 = "TRUE";
+ parameter RX_DECODE_SEQ_MATCH_0 = "TRUE";
+ parameter RX_DECODE_SEQ_MATCH_1 = "TRUE";
+ parameter RX_EN_IDLE_HOLD_CDR_0 = "FALSE";
+ parameter RX_EN_IDLE_HOLD_CDR_1 = "FALSE";
+ parameter RX_EN_IDLE_RESET_BUF_0 = "TRUE";
+ parameter RX_EN_IDLE_RESET_BUF_1 = "TRUE";
+ parameter RX_EN_IDLE_RESET_FR_0 = "TRUE";
+ parameter RX_EN_IDLE_RESET_FR_1 = "TRUE";
+ parameter RX_EN_IDLE_RESET_PH_0 = "TRUE";
+ parameter RX_EN_IDLE_RESET_PH_1 = "TRUE";
+ parameter RX_EN_MODE_RESET_BUF_0 = "TRUE";
+ parameter RX_EN_MODE_RESET_BUF_1 = "TRUE";
+ parameter [3:0] RX_IDLE_HI_CNT_0 = 4'b1000;
+ parameter [3:0] RX_IDLE_HI_CNT_1 = 4'b1000;
+ parameter [3:0] RX_IDLE_LO_CNT_0 = 4'b0000;
+ parameter [3:0] RX_IDLE_LO_CNT_1 = 4'b0000;
+ parameter RX_LOSS_OF_SYNC_FSM_0 = "FALSE";
+ parameter RX_LOSS_OF_SYNC_FSM_1 = "FALSE";
+ parameter integer RX_LOS_INVALID_INCR_0 = 1;
+ parameter integer RX_LOS_INVALID_INCR_1 = 1;
+ parameter integer RX_LOS_THRESHOLD_0 = 4;
+ parameter integer RX_LOS_THRESHOLD_1 = 4;
+ parameter RX_SLIDE_MODE_0 = "PCS";
+ parameter RX_SLIDE_MODE_1 = "PCS";
+ parameter RX_STATUS_FMT_0 = "PCIE";
+ parameter RX_STATUS_FMT_1 = "PCIE";
+ parameter RX_XCLK_SEL_0 = "RXREC";
+ parameter RX_XCLK_SEL_1 = "RXREC";
+ parameter [2:0] SATA_BURST_VAL_0 = 3'b100;
+ parameter [2:0] SATA_BURST_VAL_1 = 3'b100;
+ parameter [2:0] SATA_IDLE_VAL_0 = 3'b011;
+ parameter [2:0] SATA_IDLE_VAL_1 = 3'b011;
+ parameter integer SATA_MAX_BURST_0 = 7;
+ parameter integer SATA_MAX_BURST_1 = 7;
+ parameter integer SATA_MAX_INIT_0 = 22;
+ parameter integer SATA_MAX_INIT_1 = 22;
+ parameter integer SATA_MAX_WAKE_0 = 7;
+ parameter integer SATA_MAX_WAKE_1 = 7;
+ parameter integer SATA_MIN_BURST_0 = 4;
+ parameter integer SATA_MIN_BURST_1 = 4;
+ parameter integer SATA_MIN_INIT_0 = 12;
+ parameter integer SATA_MIN_INIT_1 = 12;
+ parameter integer SATA_MIN_WAKE_0 = 4;
+ parameter integer SATA_MIN_WAKE_1 = 4;
+ parameter integer SIM_GTPRESET_SPEEDUP = 0;
+ parameter SIM_RECEIVER_DETECT_PASS = "FALSE";
+ parameter [2:0] SIM_REFCLK0_SOURCE = 3'b000;
+ parameter [2:0] SIM_REFCLK1_SOURCE = 3'b000;
+ parameter SIM_TX_ELEC_IDLE_LEVEL = "X";
+ parameter SIM_VERSION = "2.0";
+ parameter [4:0] TERMINATION_CTRL_0 = 5'b10100;
+ parameter [4:0] TERMINATION_CTRL_1 = 5'b10100;
+ parameter TERMINATION_OVRD_0 = "FALSE";
+ parameter TERMINATION_OVRD_1 = "FALSE";
+ parameter [11:0] TRANS_TIME_FROM_P2_0 = 12'h03C;
+ parameter [11:0] TRANS_TIME_FROM_P2_1 = 12'h03C;
+ parameter [7:0] TRANS_TIME_NON_P2_0 = 8'h19;
+ parameter [7:0] TRANS_TIME_NON_P2_1 = 8'h19;
+ parameter [9:0] TRANS_TIME_TO_P2_0 = 10'h064;
+ parameter [9:0] TRANS_TIME_TO_P2_1 = 10'h064;
+ parameter [31:0] TST_ATTR_0 = 32'h00000000;
+ parameter [31:0] TST_ATTR_1 = 32'h00000000;
+ parameter [2:0] TXRX_INVERT_0 = 3'b011;
+ parameter [2:0] TXRX_INVERT_1 = 3'b011;
+ parameter TX_BUFFER_USE_0 = "FALSE";
+ parameter TX_BUFFER_USE_1 = "FALSE";
+ parameter [13:0] TX_DETECT_RX_CFG_0 = 14'h1832;
+ parameter [13:0] TX_DETECT_RX_CFG_1 = 14'h1832;
+ parameter [2:0] TX_IDLE_DELAY_0 = 3'b011;
+ parameter [2:0] TX_IDLE_DELAY_1 = 3'b011;
+ parameter [1:0] TX_TDCC_CFG_0 = 2'b00;
+ parameter [1:0] TX_TDCC_CFG_1 = 2'b00;
+ parameter TX_XCLK_SEL_0 = "TXUSR";
+ parameter TX_XCLK_SEL_1 = "TXUSR";
+ output DRDY;
+ output PHYSTATUS0;
+ output PHYSTATUS1;
+ output PLLLKDET0;
+ output PLLLKDET1;
+ output REFCLKOUT0;
+ output REFCLKOUT1;
+ output REFCLKPLL0;
+ output REFCLKPLL1;
+ output RESETDONE0;
+ output RESETDONE1;
+ output RXBYTEISALIGNED0;
+ output RXBYTEISALIGNED1;
+ output RXBYTEREALIGN0;
+ output RXBYTEREALIGN1;
+ output RXCHANBONDSEQ0;
+ output RXCHANBONDSEQ1;
+ output RXCHANISALIGNED0;
+ output RXCHANISALIGNED1;
+ output RXCHANREALIGN0;
+ output RXCHANREALIGN1;
+ output RXCOMMADET0;
+ output RXCOMMADET1;
+ output RXELECIDLE0;
+ output RXELECIDLE1;
+ output RXPRBSERR0;
+ output RXPRBSERR1;
+ output RXRECCLK0;
+ output RXRECCLK1;
+ output RXVALID0;
+ output RXVALID1;
+ output TXN0;
+ output TXN1;
+ output TXOUTCLK0;
+ output TXOUTCLK1;
+ output TXP0;
+ output TXP1;
+ output [15:0] DRPDO;
+ output [1:0] GTPCLKFBEAST;
+ output [1:0] GTPCLKFBWEST;
+ output [1:0] GTPCLKOUT0;
+ output [1:0] GTPCLKOUT1;
+ output [1:0] RXLOSSOFSYNC0;
+ output [1:0] RXLOSSOFSYNC1;
+ output [1:0] TXBUFSTATUS0;
+ output [1:0] TXBUFSTATUS1;
+ output [2:0] RXBUFSTATUS0;
+ output [2:0] RXBUFSTATUS1;
+ output [2:0] RXCHBONDO;
+ output [2:0] RXCLKCORCNT0;
+ output [2:0] RXCLKCORCNT1;
+ output [2:0] RXSTATUS0;
+ output [2:0] RXSTATUS1;
+ output [31:0] RXDATA0;
+ output [31:0] RXDATA1;
+ output [3:0] RXCHARISCOMMA0;
+ output [3:0] RXCHARISCOMMA1;
+ output [3:0] RXCHARISK0;
+ output [3:0] RXCHARISK1;
+ output [3:0] RXDISPERR0;
+ output [3:0] RXDISPERR1;
+ output [3:0] RXNOTINTABLE0;
+ output [3:0] RXNOTINTABLE1;
+ output [3:0] RXRUNDISP0;
+ output [3:0] RXRUNDISP1;
+ output [3:0] TXKERR0;
+ output [3:0] TXKERR1;
+ output [3:0] TXRUNDISP0;
+ output [3:0] TXRUNDISP1;
+ output [4:0] RCALOUTEAST;
+ output [4:0] RCALOUTWEST;
+ output [4:0] TSTOUT0;
+ output [4:0] TSTOUT1;
+ input CLK00;
+ input CLK01;
+ input CLK10;
+ input CLK11;
+ input CLKINEAST0;
+ input CLKINEAST1;
+ input CLKINWEST0;
+ input CLKINWEST1;
+ input DCLK;
+ input DEN;
+ input DWE;
+ input GATERXELECIDLE0;
+ input GATERXELECIDLE1;
+ input GCLK00;
+ input GCLK01;
+ input GCLK10;
+ input GCLK11;
+ input GTPRESET0;
+ input GTPRESET1;
+ input IGNORESIGDET0;
+ input IGNORESIGDET1;
+ input INTDATAWIDTH0;
+ input INTDATAWIDTH1;
+ input PLLCLK00;
+ input PLLCLK01;
+ input PLLCLK10;
+ input PLLCLK11;
+ input PLLLKDETEN0;
+ input PLLLKDETEN1;
+ input PLLPOWERDOWN0;
+ input PLLPOWERDOWN1;
+ input PRBSCNTRESET0;
+ input PRBSCNTRESET1;
+ input REFCLKPWRDNB0;
+ input REFCLKPWRDNB1;
+ input RXBUFRESET0;
+ input RXBUFRESET1;
+ input RXCDRRESET0;
+ input RXCDRRESET1;
+ input RXCHBONDMASTER0;
+ input RXCHBONDMASTER1;
+ input RXCHBONDSLAVE0;
+ input RXCHBONDSLAVE1;
+ input RXCOMMADETUSE0;
+ input RXCOMMADETUSE1;
+ input RXDEC8B10BUSE0;
+ input RXDEC8B10BUSE1;
+ input RXENCHANSYNC0;
+ input RXENCHANSYNC1;
+ input RXENMCOMMAALIGN0;
+ input RXENMCOMMAALIGN1;
+ input RXENPCOMMAALIGN0;
+ input RXENPCOMMAALIGN1;
+ input RXENPMAPHASEALIGN0;
+ input RXENPMAPHASEALIGN1;
+ input RXN0;
+ input RXN1;
+ input RXP0;
+ input RXP1;
+ input RXPMASETPHASE0;
+ input RXPMASETPHASE1;
+ input RXPOLARITY0;
+ input RXPOLARITY1;
+ input RXRESET0;
+ input RXRESET1;
+ input RXSLIDE0;
+ input RXSLIDE1;
+ input RXUSRCLK0;
+ input RXUSRCLK1;
+ input RXUSRCLK20;
+ input RXUSRCLK21;
+ input TSTCLK0;
+ input TSTCLK1;
+ input TXCOMSTART0;
+ input TXCOMSTART1;
+ input TXCOMTYPE0;
+ input TXCOMTYPE1;
+ input TXDETECTRX0;
+ input TXDETECTRX1;
+ input TXELECIDLE0;
+ input TXELECIDLE1;
+ input TXENC8B10BUSE0;
+ input TXENC8B10BUSE1;
+ input TXENPMAPHASEALIGN0;
+ input TXENPMAPHASEALIGN1;
+ input TXINHIBIT0;
+ input TXINHIBIT1;
+ input TXPDOWNASYNCH0;
+ input TXPDOWNASYNCH1;
+ input TXPMASETPHASE0;
+ input TXPMASETPHASE1;
+ input TXPOLARITY0;
+ input TXPOLARITY1;
+ input TXPRBSFORCEERR0;
+ input TXPRBSFORCEERR1;
+ input TXRESET0;
+ input TXRESET1;
+ input TXUSRCLK0;
+ input TXUSRCLK1;
+ input TXUSRCLK20;
+ input TXUSRCLK21;
+ input USRCODEERR0;
+ input USRCODEERR1;
+ input [11:0] TSTIN0;
+ input [11:0] TSTIN1;
+ input [15:0] DI;
+ input [1:0] GTPCLKFBSEL0EAST;
+ input [1:0] GTPCLKFBSEL0WEST;
+ input [1:0] GTPCLKFBSEL1EAST;
+ input [1:0] GTPCLKFBSEL1WEST;
+ input [1:0] RXDATAWIDTH0;
+ input [1:0] RXDATAWIDTH1;
+ input [1:0] RXEQMIX0;
+ input [1:0] RXEQMIX1;
+ input [1:0] RXPOWERDOWN0;
+ input [1:0] RXPOWERDOWN1;
+ input [1:0] TXDATAWIDTH0;
+ input [1:0] TXDATAWIDTH1;
+ input [1:0] TXPOWERDOWN0;
+ input [1:0] TXPOWERDOWN1;
+ input [2:0] LOOPBACK0;
+ input [2:0] LOOPBACK1;
+ input [2:0] REFSELDYPLL0;
+ input [2:0] REFSELDYPLL1;
+ input [2:0] RXCHBONDI;
+ input [2:0] RXENPRBSTST0;
+ input [2:0] RXENPRBSTST1;
+ input [2:0] TXBUFDIFFCTRL0;
+ input [2:0] TXBUFDIFFCTRL1;
+ input [2:0] TXENPRBSTST0;
+ input [2:0] TXENPRBSTST1;
+ input [2:0] TXPREEMPHASIS0;
+ input [2:0] TXPREEMPHASIS1;
+ input [31:0] TXDATA0;
+ input [31:0] TXDATA1;
+ input [3:0] TXBYPASS8B10B0;
+ input [3:0] TXBYPASS8B10B1;
+ input [3:0] TXCHARDISPMODE0;
+ input [3:0] TXCHARDISPMODE1;
+ input [3:0] TXCHARDISPVAL0;
+ input [3:0] TXCHARDISPVAL1;
+ input [3:0] TXCHARISK0;
+ input [3:0] TXCHARISK1;
+ input [3:0] TXDIFFCTRL0;
+ input [3:0] TXDIFFCTRL1;
+ input [4:0] RCALINEAST;
+ input [4:0] RCALINWEST;
+ input [7:0] DADDR;
+ input [7:0] GTPTEST0;
+ input [7:0] GTPTEST1;
+endmodule
+
+module IBUFDS (...);
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_DELAY_VALUE = "0";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IFD_DELAY_VALUE = "AUTO";
+ parameter IOSTANDARD = "DEFAULT";
+ output O;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+endmodule
+
+module IBUFDS_DIFF_OUT (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ output O;
+ output OB;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+endmodule
+
+module IBUFG (...);
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter IBUF_DELAY_VALUE = "0";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ output O;
+ (* iopad_external_pin *)
+ input I;
+endmodule
+
+module IBUFGDS (...);
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter DIFF_TERM = "FALSE";
+ parameter IBUF_DELAY_VALUE = "0";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ output O;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+endmodule
+
+module IBUFGDS_DIFF_OUT (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ output O;
+ output OB;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+endmodule
+
+module IOBUF (...);
+ parameter integer DRIVE = 12;
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SLEW = "SLOW";
+ output O;
+ (* iopad_external_pin *)
+ inout IO;
+ input I;
+ input T;
+endmodule
+
+module IOBUFDS (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SLEW = "SLOW";
+ output O;
+ (* iopad_external_pin *)
+ inout IO;
+ inout IOB;
+ input I;
+ input T;
+endmodule
+
+module IODELAY2 (...);
+ parameter COUNTER_WRAPAROUND = "WRAPAROUND";
+ parameter DATA_RATE = "SDR";
+ parameter DELAY_SRC = "IO";
+ parameter integer IDELAY2_VALUE = 0;
+ parameter IDELAY_MODE = "NORMAL";
+ parameter IDELAY_TYPE = "DEFAULT";
+ parameter integer IDELAY_VALUE = 0;
+ parameter integer ODELAY_VALUE = 0;
+ parameter SERDES_MODE = "NONE";
+ parameter integer SIM_TAPDELAY_VALUE = 75;
+ output BUSY;
+ output DATAOUT2;
+ output DATAOUT;
+ output DOUT;
+ output TOUT;
+ input CAL;
+ input CE;
+ (* clkbuf_sink *)
+ input CLK;
+ input IDATAIN;
+ input INC;
+ (* clkbuf_sink *)
+ input IOCLK0;
+ (* clkbuf_sink *)
+ input IOCLK1;
+ input ODATAIN;
+ input RST;
+ input T;
+endmodule
+
+module IODRP2 (...);
+ parameter DATA_RATE = "SDR";
+ parameter integer SIM_TAPDELAY_VALUE = 75;
+ output DATAOUT2;
+ output DATAOUT;
+ output DOUT;
+ output SDO;
+ output TOUT;
+ input ADD;
+ input BKST;
+ (* clkbuf_sink *)
+ input CLK;
+ input CS;
+ input IDATAIN;
+ (* clkbuf_sink *)
+ input IOCLK0;
+ (* clkbuf_sink *)
+ input IOCLK1;
+ input ODATAIN;
+ input SDI;
+ input T;
+endmodule
+
+module IODRP2_MCB (...);
+ parameter DATA_RATE = "SDR";
+ parameter integer IDELAY_VALUE = 0;
+ parameter integer MCB_ADDRESS = 0;
+ parameter integer ODELAY_VALUE = 0;
+ parameter SERDES_MODE = "NONE";
+ parameter integer SIM_TAPDELAY_VALUE = 75;
+ output AUXSDO;
+ output DATAOUT2;
+ output DATAOUT;
+ output DOUT;
+ output DQSOUTN;
+ output DQSOUTP;
+ output SDO;
+ output TOUT;
+ input ADD;
+ input AUXSDOIN;
+ input BKST;
+ (* clkbuf_sink *)
+ input CLK;
+ input CS;
+ input IDATAIN;
+ (* clkbuf_sink *)
+ input IOCLK0;
+ (* clkbuf_sink *)
+ input IOCLK1;
+ input MEMUPDATE;
+ input ODATAIN;
+ input SDI;
+ input T;
+ input [4:0] AUXADDR;
+endmodule
+
+module ISERDES2 (...);
+ parameter BITSLIP_ENABLE = "FALSE";
+ parameter DATA_RATE = "SDR";
+ parameter integer DATA_WIDTH = 1;
+ parameter INTERFACE_TYPE = "NETWORKING";
+ parameter SERDES_MODE = "NONE";
+ output CFB0;
+ output CFB1;
+ output DFB;
+ output FABRICOUT;
+ output INCDEC;
+ output Q1;
+ output Q2;
+ output Q3;
+ output Q4;
+ output SHIFTOUT;
+ output VALID;
+ input BITSLIP;
+ input CE0;
+ (* clkbuf_sink *)
+ input CLK0;
+ (* clkbuf_sink *)
+ input CLK1;
+ (* clkbuf_sink *)
+ input CLKDIV;
+ input D;
+ input IOCE;
+ input RST;
+ input SHIFTIN;
+endmodule
+
+module KEEPER (...);
+ inout O;
+endmodule
+
+module OBUFDS (...);
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SLEW = "SLOW";
+ (* iopad_external_pin *)
+ output O;
+ (* iopad_external_pin *)
+ output OB;
+ input I;
+endmodule
+
+module OBUFT (...);
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter integer DRIVE = 12;
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SLEW = "SLOW";
+ (* iopad_external_pin *)
+ output O;
+ input I;
+ input T;
+endmodule
+
+module OBUFTDS (...);
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SLEW = "SLOW";
+ (* iopad_external_pin *)
+ output O;
+ (* iopad_external_pin *)
+ output OB;
+ input I;
+ input T;
+endmodule
+
+module OSERDES2 (...);
+ parameter BYPASS_GCLK_FF = "FALSE";
+ parameter DATA_RATE_OQ = "DDR";
+ parameter DATA_RATE_OT = "DDR";
+ parameter integer DATA_WIDTH = 2;
+ parameter OUTPUT_MODE = "SINGLE_ENDED";
+ parameter SERDES_MODE = "NONE";
+ parameter integer TRAIN_PATTERN = 0;
+ output OQ;
+ output SHIFTOUT1;
+ output SHIFTOUT2;
+ output SHIFTOUT3;
+ output SHIFTOUT4;
+ output TQ;
+ (* clkbuf_sink *)
+ input CLK0;
+ (* clkbuf_sink *)
+ input CLK1;
+ (* clkbuf_sink *)
+ input CLKDIV;
+ input D1;
+ input D2;
+ input D3;
+ input D4;
+ input IOCE;
+ input OCE;
+ input RST;
+ input SHIFTIN1;
+ input SHIFTIN2;
+ input SHIFTIN3;
+ input SHIFTIN4;
+ input T1;
+ input T2;
+ input T3;
+ input T4;
+ input TCE;
+ input TRAIN;
+endmodule
+
+module PULLDOWN (...);
+ output O;
+endmodule
+
+module PULLUP (...);
+ output O;
+endmodule
+
+module RAM128X1S (...);
+ parameter [127:0] INIT = 128'h00000000000000000000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input A5;
+ input A6;
+ input D;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM256X1S (...);
+ parameter [255:0] INIT = 256'h0;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O;
+ input [7:0] A;
+ input D;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM32M (...);
+ parameter [63:0] INIT_A = 64'h0000000000000000;
+ parameter [63:0] INIT_B = 64'h0000000000000000;
+ parameter [63:0] INIT_C = 64'h0000000000000000;
+ parameter [63:0] INIT_D = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output [1:0] DOA;
+ output [1:0] DOB;
+ output [1:0] DOC;
+ output [1:0] DOD;
+ input [4:0] ADDRA;
+ input [4:0] ADDRB;
+ input [4:0] ADDRC;
+ input [4:0] ADDRD;
+ input [1:0] DIA;
+ input [1:0] DIB;
+ input [1:0] DIC;
+ input [1:0] DID;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM32X1S (...);
+ parameter [31:0] INIT = 32'h00000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input D;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM32X1S_1 (...);
+ parameter [31:0] INIT = 32'h00000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input D;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM32X2S (...);
+ parameter [31:0] INIT_00 = 32'h00000000;
+ parameter [31:0] INIT_01 = 32'h00000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O0;
+ output O1;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input D0;
+ input D1;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM64M (...);
+ parameter [63:0] INIT_A = 64'h0000000000000000;
+ parameter [63:0] INIT_B = 64'h0000000000000000;
+ parameter [63:0] INIT_C = 64'h0000000000000000;
+ parameter [63:0] INIT_D = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output DOA;
+ output DOB;
+ output DOC;
+ output DOD;
+ input [5:0] ADDRA;
+ input [5:0] ADDRB;
+ input [5:0] ADDRC;
+ input [5:0] ADDRD;
+ input DIA;
+ input DIB;
+ input DIC;
+ input DID;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM64X1S (...);
+ parameter [63:0] INIT = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input A5;
+ input D;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM64X1S_1 (...);
+ parameter [63:0] INIT = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input A5;
+ input D;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM64X2S (...);
+ parameter [63:0] INIT_00 = 64'h0000000000000000;
+ parameter [63:0] INIT_01 = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O0;
+ output O1;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input A5;
+ input D0;
+ input D1;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module ROM128X1 (...);
+ parameter [127:0] INIT = 128'h00000000000000000000000000000000;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input A5;
+ input A6;
+endmodule
+
+module ROM256X1 (...);
+ parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input A5;
+ input A6;
+ input A7;
+endmodule
+
+module ROM32X1 (...);
+ parameter [31:0] INIT = 32'h00000000;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+endmodule
+
+module ROM64X1 (...);
+ parameter [63:0] INIT = 64'h0000000000000000;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input A5;
+endmodule
+
+module IDDR2 (...);
+ parameter DDR_ALIGNMENT = "NONE";
+ parameter [0:0] INIT_Q0 = 1'b0;
+ parameter [0:0] INIT_Q1 = 1'b0;
+ parameter SRTYPE = "SYNC";
+ output Q0;
+ output Q1;
+ (* clkbuf_sink *)
+ input C0;
+ (* clkbuf_sink *)
+ input C1;
+ input CE;
+ input D;
+ input R;
+ input S;
+endmodule
+
+module LDCE (...);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_CLR_INVERTED = 1'b0;
+ parameter [0:0] IS_G_INVERTED = 1'b0;
+ parameter MSGON = "TRUE";
+ parameter XON = "TRUE";
+ output Q;
+ (* invertible_pin = "IS_CLR_INVERTED" *)
+ input CLR;
+ input D;
+ (* invertible_pin = "IS_G_INVERTED" *)
+ input G;
+ input GE;
+endmodule
+
+module LDPE (...);
+ parameter [0:0] INIT = 1'b1;
+ parameter [0:0] IS_G_INVERTED = 1'b0;
+ parameter [0:0] IS_PRE_INVERTED = 1'b0;
+ parameter MSGON = "TRUE";
+ parameter XON = "TRUE";
+ output Q;
+ input D;
+ (* invertible_pin = "IS_G_INVERTED" *)
+ input G;
+ input GE;
+ (* invertible_pin = "IS_PRE_INVERTED" *)
+ input PRE;
+endmodule
+
+module ODDR2 (...);
+ parameter DDR_ALIGNMENT = "NONE";
+ parameter [0:0] INIT = 1'b0;
+ parameter SRTYPE = "SYNC";
+ output Q;
+ (* clkbuf_sink *)
+ input C0;
+ (* clkbuf_sink *)
+ input C1;
+ input CE;
+ input D0;
+ input D1;
+ input R;
+ input S;
+endmodule
+
+module CFGLUT5 (...);
+ parameter [31:0] INIT = 32'h00000000;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ output CDO;
+ output O5;
+ output O6;
+ input I4;
+ input I3;
+ input I2;
+ input I1;
+ input I0;
+ input CDI;
+ input CE;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLK_INVERTED" *)
+ input CLK;
+endmodule
+
diff --git a/techlibs/xilinx/xc6s_ff_map.v b/techlibs/xilinx/xc6s_ff_map.v
new file mode 100644
index 000000000..520a67579
--- /dev/null
+++ b/techlibs/xilinx/xc6s_ff_map.v
@@ -0,0 +1,126 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// ============================================================================
+// FF mapping
+
+`ifndef _NO_FFS
+
+module \$_DFF_N_ (input D, C, output Q);
+ parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+ generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+ FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S(1'b0));
+ else
+ FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
+ endgenerate
+endmodule
+module \$_DFF_P_ (input D, C, output Q);
+ parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+ generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+ FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S(1'b0));
+ else
+ FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
+ endgenerate
+endmodule
+
+module \$_DFFE_NP_ (input D, C, E, output Q);
+ parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+ generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+ FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(1'b0));
+ else
+ FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0));
+ endgenerate
+endmodule
+module \$_DFFE_PP_ (input D, C, E, output Q);
+ parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+ generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+ FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(1'b0));
+ else
+ FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0));
+ endgenerate
+endmodule
+
+module \$_DFF_NN0_ (input D, C, R, output Q);
+ parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+ generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+ $error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
+ else
+ FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
+ endgenerate
+endmodule
+module \$_DFF_NP0_ (input D, C, R, output Q);
+ parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+ generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+ $error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
+ else
+ FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
+ endgenerate
+endmodule
+module \$_DFF_PN0_ (input D, C, R, output Q);
+ parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+ generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+ $error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
+ else
+ FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
+ endgenerate
+endmodule
+module \$_DFF_PP0_ (input D, C, R, output Q);
+ parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+ generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
+ $error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
+ else
+ FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
+ endgenerate
+endmodule
+
+module \$_DFF_NN1_ (input D, C, R, output Q);
+ parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+ generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
+ $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
+ else
+ FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
+ endgenerate
+endmodule
+module \$_DFF_NP1_ (input D, C, R, output Q);
+ parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+ generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
+ $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
+ else
+ FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
+ endgenerate
+endmodule
+module \$_DFF_PN1_ (input D, C, R, output Q);
+ parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+ generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
+ $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
+ else
+ FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
+ endgenerate
+endmodule
+module \$_DFF_PP1_ (input D, C, R, output Q);
+ parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+ generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
+ $error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
+ else
+ FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
+ endgenerate
+endmodule
+
+`endif
+
diff --git a/techlibs/xilinx/xc6v_cells_xtra.v b/techlibs/xilinx/xc6v_cells_xtra.v
new file mode 100644
index 000000000..263bcc69d
--- /dev/null
+++ b/techlibs/xilinx/xc6v_cells_xtra.v
@@ -0,0 +1,2720 @@
+// Created by cells_xtra.py from Xilinx models
+
+module PCIE_2_0 (...);
+ parameter [11:0] AER_BASE_PTR = 12'h128;
+ parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
+ parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
+ parameter [15:0] AER_CAP_ID = 16'h0001;
+ parameter [4:0] AER_CAP_INT_MSG_NUM_MSI = 5'h0A;
+ parameter [4:0] AER_CAP_INT_MSG_NUM_MSIX = 5'h15;
+ parameter [11:0] AER_CAP_NEXTPTR = 12'h160;
+ parameter AER_CAP_ON = "FALSE";
+ parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE";
+ parameter [3:0] AER_CAP_VERSION = 4'h1;
+ parameter ALLOW_X8_GEN2 = "FALSE";
+ parameter [31:0] BAR0 = 32'hFFFFFF00;
+ parameter [31:0] BAR1 = 32'hFFFF0000;
+ parameter [31:0] BAR2 = 32'hFFFF000C;
+ parameter [31:0] BAR3 = 32'hFFFFFFFF;
+ parameter [31:0] BAR4 = 32'h00000000;
+ parameter [31:0] BAR5 = 32'h00000000;
+ parameter [7:0] CAPABILITIES_PTR = 8'h40;
+ parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000;
+ parameter [23:0] CLASS_CODE = 24'h000000;
+ parameter CMD_INTX_IMPLEMENTED = "TRUE";
+ parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE";
+ parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0;
+ parameter [6:0] CRM_MODULE_RSTS = 7'h00;
+ parameter [15:0] DEVICE_ID = 16'h0007;
+ parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE";
+ parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE";
+ parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0;
+ parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0;
+ parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE";
+ parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE";
+ parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2;
+ parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0;
+ parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE";
+ parameter integer DEV_CAP_RSVD_14_12 = 0;
+ parameter integer DEV_CAP_RSVD_17_16 = 0;
+ parameter integer DEV_CAP_RSVD_31_29 = 0;
+ parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE";
+ parameter DISABLE_ASPM_L1_TIMER = "FALSE";
+ parameter DISABLE_BAR_FILTERING = "FALSE";
+ parameter DISABLE_ID_CHECK = "FALSE";
+ parameter DISABLE_LANE_REVERSAL = "FALSE";
+ parameter DISABLE_RX_TC_FILTER = "FALSE";
+ parameter DISABLE_SCRAMBLING = "FALSE";
+ parameter [7:0] DNSTREAM_LINK_NUM = 8'h00;
+ parameter [11:0] DSN_BASE_PTR = 12'h100;
+ parameter [15:0] DSN_CAP_ID = 16'h0003;
+ parameter [11:0] DSN_CAP_NEXTPTR = 12'h000;
+ parameter DSN_CAP_ON = "TRUE";
+ parameter [3:0] DSN_CAP_VERSION = 4'h1;
+ parameter [10:0] ENABLE_MSG_ROUTE = 11'h000;
+ parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE";
+ parameter ENTER_RVRY_EI_L0 = "TRUE";
+ parameter EXIT_LOOPBACK_ON_EI = "TRUE";
+ parameter [31:0] EXPANSION_ROM = 32'hFFFFF001;
+ parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F;
+ parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF;
+ parameter [7:0] HEADER_TYPE = 8'h00;
+ parameter [4:0] INFER_EI = 5'h00;
+ parameter [7:0] INTERRUPT_PIN = 8'h01;
+ parameter IS_SWITCH = "FALSE";
+ parameter [9:0] LAST_CONFIG_DWORD = 10'h042;
+ parameter integer LINK_CAP_ASPM_SUPPORT = 1;
+ parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE";
+ parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE";
+ parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7;
+ parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7;
+ parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7;
+ parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7;
+ parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7;
+ parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7;
+ parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7;
+ parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7;
+ parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE";
+ parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1;
+ parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08;
+ parameter integer LINK_CAP_RSVD_23_22 = 0;
+ parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE";
+ parameter integer LINK_CONTROL_RCB = 0;
+ parameter LINK_CTRL2_DEEMPHASIS = "FALSE";
+ parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE";
+ parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2;
+ parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE";
+ parameter [14:0] LL_ACK_TIMEOUT = 15'h0000;
+ parameter LL_ACK_TIMEOUT_EN = "FALSE";
+ parameter integer LL_ACK_TIMEOUT_FUNC = 0;
+ parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000;
+ parameter LL_REPLAY_TIMEOUT_EN = "FALSE";
+ parameter integer LL_REPLAY_TIMEOUT_FUNC = 0;
+ parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01;
+ parameter [7:0] MSIX_BASE_PTR = 8'h9C;
+ parameter [7:0] MSIX_CAP_ID = 8'h11;
+ parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00;
+ parameter MSIX_CAP_ON = "FALSE";
+ parameter integer MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter [7:0] MSI_BASE_PTR = 8'h48;
+ parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE";
+ parameter [7:0] MSI_CAP_ID = 8'h05;
+ parameter integer MSI_CAP_MULTIMSGCAP = 0;
+ parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0;
+ parameter [7:0] MSI_CAP_NEXTPTR = 8'h60;
+ parameter MSI_CAP_ON = "FALSE";
+ parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE";
+ parameter integer N_FTS_COMCLK_GEN1 = 255;
+ parameter integer N_FTS_COMCLK_GEN2 = 255;
+ parameter integer N_FTS_GEN1 = 255;
+ parameter integer N_FTS_GEN2 = 255;
+ parameter [7:0] PCIE_BASE_PTR = 8'h60;
+ parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10;
+ parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2;
+ parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0;
+ parameter [4:0] PCIE_CAP_INT_MSG_NUM = 5'h00;
+ parameter [7:0] PCIE_CAP_NEXTPTR = 8'h00;
+ parameter PCIE_CAP_ON = "TRUE";
+ parameter integer PCIE_CAP_RSVD_15_14 = 0;
+ parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE";
+ parameter integer PCIE_REVISION = 2;
+ parameter integer PGL0_LANE = 0;
+ parameter integer PGL1_LANE = 1;
+ parameter integer PGL2_LANE = 2;
+ parameter integer PGL3_LANE = 3;
+ parameter integer PGL4_LANE = 4;
+ parameter integer PGL5_LANE = 5;
+ parameter integer PGL6_LANE = 6;
+ parameter integer PGL7_LANE = 7;
+ parameter integer PL_AUTO_CONFIG = 0;
+ parameter PL_FAST_TRAIN = "FALSE";
+ parameter [7:0] PM_BASE_PTR = 8'h40;
+ parameter integer PM_CAP_AUXCURRENT = 0;
+ parameter PM_CAP_D1SUPPORT = "TRUE";
+ parameter PM_CAP_D2SUPPORT = "TRUE";
+ parameter PM_CAP_DSI = "FALSE";
+ parameter [7:0] PM_CAP_ID = 8'h01;
+ parameter [7:0] PM_CAP_NEXTPTR = 8'h48;
+ parameter PM_CAP_ON = "TRUE";
+ parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F;
+ parameter PM_CAP_PME_CLOCK = "FALSE";
+ parameter integer PM_CAP_RSVD_04 = 0;
+ parameter integer PM_CAP_VERSION = 3;
+ parameter PM_CSR_B2B3 = "FALSE";
+ parameter PM_CSR_BPCCEN = "FALSE";
+ parameter PM_CSR_NOSOFTRST = "TRUE";
+ parameter [7:0] PM_DATA0 = 8'h01;
+ parameter [7:0] PM_DATA1 = 8'h01;
+ parameter [7:0] PM_DATA2 = 8'h01;
+ parameter [7:0] PM_DATA3 = 8'h01;
+ parameter [7:0] PM_DATA4 = 8'h01;
+ parameter [7:0] PM_DATA5 = 8'h01;
+ parameter [7:0] PM_DATA6 = 8'h01;
+ parameter [7:0] PM_DATA7 = 8'h01;
+ parameter [1:0] PM_DATA_SCALE0 = 2'h1;
+ parameter [1:0] PM_DATA_SCALE1 = 2'h1;
+ parameter [1:0] PM_DATA_SCALE2 = 2'h1;
+ parameter [1:0] PM_DATA_SCALE3 = 2'h1;
+ parameter [1:0] PM_DATA_SCALE4 = 2'h1;
+ parameter [1:0] PM_DATA_SCALE5 = 2'h1;
+ parameter [1:0] PM_DATA_SCALE6 = 2'h1;
+ parameter [1:0] PM_DATA_SCALE7 = 2'h1;
+ parameter integer RECRC_CHK = 0;
+ parameter RECRC_CHK_TRIM = "FALSE";
+ parameter [7:0] REVISION_ID = 8'h00;
+ parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE";
+ parameter SELECT_DLL_IF = "FALSE";
+ parameter SIM_VERSION = "1.0";
+ parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE";
+ parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE";
+ parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE";
+ parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE";
+ parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE";
+ parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE";
+ parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE";
+ parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000;
+ parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE";
+ parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE";
+ parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0;
+ parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00;
+ parameter integer SPARE_BIT0 = 0;
+ parameter integer SPARE_BIT1 = 0;
+ parameter integer SPARE_BIT2 = 0;
+ parameter integer SPARE_BIT3 = 0;
+ parameter integer SPARE_BIT4 = 0;
+ parameter integer SPARE_BIT5 = 0;
+ parameter integer SPARE_BIT6 = 0;
+ parameter integer SPARE_BIT7 = 0;
+ parameter integer SPARE_BIT8 = 0;
+ parameter [7:0] SPARE_BYTE0 = 8'h00;
+ parameter [7:0] SPARE_BYTE1 = 8'h00;
+ parameter [7:0] SPARE_BYTE2 = 8'h00;
+ parameter [7:0] SPARE_BYTE3 = 8'h00;
+ parameter [31:0] SPARE_WORD0 = 32'h00000000;
+ parameter [31:0] SPARE_WORD1 = 32'h00000000;
+ parameter [31:0] SPARE_WORD2 = 32'h00000000;
+ parameter [31:0] SPARE_WORD3 = 32'h00000000;
+ parameter [15:0] SUBSYSTEM_ID = 16'h0007;
+ parameter [15:0] SUBSYSTEM_VENDOR_ID = 16'h10EE;
+ parameter TL_RBYPASS = "FALSE";
+ parameter integer TL_RX_RAM_RADDR_LATENCY = 0;
+ parameter integer TL_RX_RAM_RDATA_LATENCY = 2;
+ parameter integer TL_RX_RAM_WRITE_LATENCY = 0;
+ parameter TL_TFC_DISABLE = "FALSE";
+ parameter TL_TX_CHECKS_DISABLE = "FALSE";
+ parameter integer TL_TX_RAM_RADDR_LATENCY = 0;
+ parameter integer TL_TX_RAM_RDATA_LATENCY = 2;
+ parameter integer TL_TX_RAM_WRITE_LATENCY = 0;
+ parameter UPCONFIG_CAPABLE = "TRUE";
+ parameter UPSTREAM_FACING = "TRUE";
+ parameter UR_INV_REQ = "TRUE";
+ parameter integer USER_CLK_FREQ = 3;
+ parameter VC0_CPL_INFINITE = "TRUE";
+ parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF;
+ parameter integer VC0_TOTAL_CREDITS_CD = 127;
+ parameter integer VC0_TOTAL_CREDITS_CH = 31;
+ parameter integer VC0_TOTAL_CREDITS_NPH = 12;
+ parameter integer VC0_TOTAL_CREDITS_PD = 288;
+ parameter integer VC0_TOTAL_CREDITS_PH = 32;
+ parameter integer VC0_TX_LASTPACKET = 31;
+ parameter [11:0] VC_BASE_PTR = 12'h10C;
+ parameter [15:0] VC_CAP_ID = 16'h0002;
+ parameter [11:0] VC_CAP_NEXTPTR = 12'h000;
+ parameter VC_CAP_ON = "FALSE";
+ parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE";
+ parameter [3:0] VC_CAP_VERSION = 4'h1;
+ parameter [15:0] VENDOR_ID = 16'h10EE;
+ parameter [11:0] VSEC_BASE_PTR = 12'h160;
+ parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234;
+ parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018;
+ parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1;
+ parameter [15:0] VSEC_CAP_ID = 16'h000B;
+ parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE";
+ parameter [11:0] VSEC_CAP_NEXTPTR = 12'h000;
+ parameter VSEC_CAP_ON = "FALSE";
+ parameter [3:0] VSEC_CAP_VERSION = 4'h1;
+ output CFGAERECRCCHECKEN;
+ output CFGAERECRCGENEN;
+ output CFGCOMMANDBUSMASTERENABLE;
+ output CFGCOMMANDINTERRUPTDISABLE;
+ output CFGCOMMANDIOENABLE;
+ output CFGCOMMANDMEMENABLE;
+ output CFGCOMMANDSERREN;
+ output CFGDEVCONTROL2CPLTIMEOUTDIS;
+ output CFGDEVCONTROLAUXPOWEREN;
+ output CFGDEVCONTROLCORRERRREPORTINGEN;
+ output CFGDEVCONTROLENABLERO;
+ output CFGDEVCONTROLEXTTAGEN;
+ output CFGDEVCONTROLFATALERRREPORTINGEN;
+ output CFGDEVCONTROLNONFATALREPORTINGEN;
+ output CFGDEVCONTROLNOSNOOPEN;
+ output CFGDEVCONTROLPHANTOMEN;
+ output CFGDEVCONTROLURERRREPORTINGEN;
+ output CFGDEVSTATUSCORRERRDETECTED;
+ output CFGDEVSTATUSFATALERRDETECTED;
+ output CFGDEVSTATUSNONFATALERRDETECTED;
+ output CFGDEVSTATUSURDETECTED;
+ output CFGERRAERHEADERLOGSETN;
+ output CFGERRCPLRDYN;
+ output CFGINTERRUPTMSIENABLE;
+ output CFGINTERRUPTMSIXENABLE;
+ output CFGINTERRUPTMSIXFM;
+ output CFGINTERRUPTRDYN;
+ output CFGLINKCONTROLAUTOBANDWIDTHINTEN;
+ output CFGLINKCONTROLBANDWIDTHINTEN;
+ output CFGLINKCONTROLCLOCKPMEN;
+ output CFGLINKCONTROLCOMMONCLOCK;
+ output CFGLINKCONTROLEXTENDEDSYNC;
+ output CFGLINKCONTROLHWAUTOWIDTHDIS;
+ output CFGLINKCONTROLLINKDISABLE;
+ output CFGLINKCONTROLRCB;
+ output CFGLINKCONTROLRETRAINLINK;
+ output CFGLINKSTATUSAUTOBANDWIDTHSTATUS;
+ output CFGLINKSTATUSBANDWITHSTATUS;
+ output CFGLINKSTATUSDLLACTIVE;
+ output CFGLINKSTATUSLINKTRAINING;
+ output CFGMSGRECEIVED;
+ output CFGMSGRECEIVEDASSERTINTA;
+ output CFGMSGRECEIVEDASSERTINTB;
+ output CFGMSGRECEIVEDASSERTINTC;
+ output CFGMSGRECEIVEDASSERTINTD;
+ output CFGMSGRECEIVEDDEASSERTINTA;
+ output CFGMSGRECEIVEDDEASSERTINTB;
+ output CFGMSGRECEIVEDDEASSERTINTC;
+ output CFGMSGRECEIVEDDEASSERTINTD;
+ output CFGMSGRECEIVEDERRCOR;
+ output CFGMSGRECEIVEDERRFATAL;
+ output CFGMSGRECEIVEDERRNONFATAL;
+ output CFGMSGRECEIVEDPMASNAK;
+ output CFGMSGRECEIVEDPMETO;
+ output CFGMSGRECEIVEDPMETOACK;
+ output CFGMSGRECEIVEDPMPME;
+ output CFGMSGRECEIVEDSETSLOTPOWERLIMIT;
+ output CFGMSGRECEIVEDUNLOCK;
+ output CFGPMCSRPMEEN;
+ output CFGPMCSRPMESTATUS;
+ output CFGPMRCVASREQL1N;
+ output CFGPMRCVENTERL1N;
+ output CFGPMRCVENTERL23N;
+ output CFGPMRCVREQACKN;
+ output CFGRDWRDONEN;
+ output CFGSLOTCONTROLELECTROMECHILCTLPULSE;
+ output CFGTRANSACTION;
+ output CFGTRANSACTIONTYPE;
+ output DBGSCLRA;
+ output DBGSCLRB;
+ output DBGSCLRC;
+ output DBGSCLRD;
+ output DBGSCLRE;
+ output DBGSCLRF;
+ output DBGSCLRG;
+ output DBGSCLRH;
+ output DBGSCLRI;
+ output DBGSCLRJ;
+ output DBGSCLRK;
+ output DRPDRDY;
+ output LL2BADDLLPERRN;
+ output LL2BADTLPERRN;
+ output LL2PROTOCOLERRN;
+ output LL2REPLAYROERRN;
+ output LL2REPLAYTOERRN;
+ output LL2SUSPENDOKN;
+ output LL2TFCINIT1SEQN;
+ output LL2TFCINIT2SEQN;
+ output LNKCLKEN;
+ output MIMRXRCE;
+ output MIMRXREN;
+ output MIMRXWEN;
+ output MIMTXRCE;
+ output MIMTXREN;
+ output MIMTXWEN;
+ output PIPERX0POLARITY;
+ output PIPERX1POLARITY;
+ output PIPERX2POLARITY;
+ output PIPERX3POLARITY;
+ output PIPERX4POLARITY;
+ output PIPERX5POLARITY;
+ output PIPERX6POLARITY;
+ output PIPERX7POLARITY;
+ output PIPETX0COMPLIANCE;
+ output PIPETX0ELECIDLE;
+ output PIPETX1COMPLIANCE;
+ output PIPETX1ELECIDLE;
+ output PIPETX2COMPLIANCE;
+ output PIPETX2ELECIDLE;
+ output PIPETX3COMPLIANCE;
+ output PIPETX3ELECIDLE;
+ output PIPETX4COMPLIANCE;
+ output PIPETX4ELECIDLE;
+ output PIPETX5COMPLIANCE;
+ output PIPETX5ELECIDLE;
+ output PIPETX6COMPLIANCE;
+ output PIPETX6ELECIDLE;
+ output PIPETX7COMPLIANCE;
+ output PIPETX7ELECIDLE;
+ output PIPETXDEEMPH;
+ output PIPETXRATE;
+ output PIPETXRCVRDET;
+ output PIPETXRESET;
+ output PL2LINKUPN;
+ output PL2RECEIVERERRN;
+ output PL2RECOVERYN;
+ output PL2RXELECIDLE;
+ output PL2SUSPENDOK;
+ output PLLINKGEN2CAP;
+ output PLLINKPARTNERGEN2SUPPORTED;
+ output PLLINKUPCFGCAP;
+ output PLPHYLNKUPN;
+ output PLRECEIVEDHOTRST;
+ output PLSELLNKRATE;
+ output RECEIVEDFUNCLVLRSTN;
+ output TL2ASPMSUSPENDCREDITCHECKOKN;
+ output TL2ASPMSUSPENDREQN;
+ output TL2PPMSUSPENDOKN;
+ output TRNLNKUPN;
+ output TRNRDLLPSRCRDYN;
+ output TRNRECRCERRN;
+ output TRNREOFN;
+ output TRNRERRFWDN;
+ output TRNRREMN;
+ output TRNRSOFN;
+ output TRNRSRCDSCN;
+ output TRNRSRCRDYN;
+ output TRNTCFGREQN;
+ output TRNTDLLPDSTRDYN;
+ output TRNTDSTRDYN;
+ output TRNTERRDROPN;
+ output USERRSTN;
+ output [11:0] DBGVECC;
+ output [11:0] PLDBGVEC;
+ output [11:0] TRNFCCPLD;
+ output [11:0] TRNFCNPD;
+ output [11:0] TRNFCPD;
+ output [12:0] MIMRXRADDR;
+ output [12:0] MIMRXWADDR;
+ output [12:0] MIMTXRADDR;
+ output [12:0] MIMTXWADDR;
+ output [15:0] CFGMSGDATA;
+ output [15:0] DRPDO;
+ output [15:0] PIPETX0DATA;
+ output [15:0] PIPETX1DATA;
+ output [15:0] PIPETX2DATA;
+ output [15:0] PIPETX3DATA;
+ output [15:0] PIPETX4DATA;
+ output [15:0] PIPETX5DATA;
+ output [15:0] PIPETX6DATA;
+ output [15:0] PIPETX7DATA;
+ output [1:0] CFGLINKCONTROLASPMCONTROL;
+ output [1:0] CFGLINKSTATUSCURRENTSPEED;
+ output [1:0] CFGPMCSRPOWERSTATE;
+ output [1:0] PIPETX0CHARISK;
+ output [1:0] PIPETX0POWERDOWN;
+ output [1:0] PIPETX1CHARISK;
+ output [1:0] PIPETX1POWERDOWN;
+ output [1:0] PIPETX2CHARISK;
+ output [1:0] PIPETX2POWERDOWN;
+ output [1:0] PIPETX3CHARISK;
+ output [1:0] PIPETX3POWERDOWN;
+ output [1:0] PIPETX4CHARISK;
+ output [1:0] PIPETX4POWERDOWN;
+ output [1:0] PIPETX5CHARISK;
+ output [1:0] PIPETX5POWERDOWN;
+ output [1:0] PIPETX6CHARISK;
+ output [1:0] PIPETX6POWERDOWN;
+ output [1:0] PIPETX7CHARISK;
+ output [1:0] PIPETX7POWERDOWN;
+ output [1:0] PLLANEREVERSALMODE;
+ output [1:0] PLRXPMSTATE;
+ output [1:0] PLSELLNKWIDTH;
+ output [2:0] CFGDEVCONTROLMAXPAYLOAD;
+ output [2:0] CFGDEVCONTROLMAXREADREQ;
+ output [2:0] CFGINTERRUPTMMENABLE;
+ output [2:0] CFGPCIELINKSTATE;
+ output [2:0] PIPETXMARGIN;
+ output [2:0] PLINITIALLINKWIDTH;
+ output [2:0] PLTXPMSTATE;
+ output [31:0] CFGDO;
+ output [31:0] TRNRDLLPDATA;
+ output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL;
+ output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH;
+ output [5:0] PLLTSSMSTATE;
+ output [5:0] TRNTBUFAV;
+ output [63:0] DBGVECA;
+ output [63:0] DBGVECB;
+ output [63:0] TRNRD;
+ output [67:0] MIMRXWDATA;
+ output [68:0] MIMTXWDATA;
+ output [6:0] CFGTRANSACTIONADDR;
+ output [6:0] CFGVCTCVCMAP;
+ output [6:0] TRNRBARHITN;
+ output [7:0] CFGINTERRUPTDO;
+ output [7:0] TRNFCCPLH;
+ output [7:0] TRNFCNPH;
+ output [7:0] TRNFCPH;
+ input CFGERRACSN;
+ input CFGERRCORN;
+ input CFGERRCPLABORTN;
+ input CFGERRCPLTIMEOUTN;
+ input CFGERRCPLUNEXPECTN;
+ input CFGERRECRCN;
+ input CFGERRLOCKEDN;
+ input CFGERRPOSTEDN;
+ input CFGERRURN;
+ input CFGINTERRUPTASSERTN;
+ input CFGINTERRUPTN;
+ input CFGPMDIRECTASPML1N;
+ input CFGPMSENDPMACKN;
+ input CFGPMSENDPMETON;
+ input CFGPMSENDPMNAKN;
+ input CFGPMTURNOFFOKN;
+ input CFGPMWAKEN;
+ input CFGRDENN;
+ input CFGTRNPENDINGN;
+ input CFGWRENN;
+ input CFGWRREADONLYN;
+ input CFGWRRW1CASRWN;
+ input CMRSTN;
+ input CMSTICKYRSTN;
+ input DBGSUBMODE;
+ input DLRSTN;
+ input DRPCLK;
+ input DRPDEN;
+ input DRPDWE;
+ input FUNCLVLRSTN;
+ input LL2SENDASREQL1N;
+ input LL2SENDENTERL1N;
+ input LL2SENDENTERL23N;
+ input LL2SUSPENDNOWN;
+ input LL2TLPRCVN;
+ input PIPECLK;
+ input PIPERX0CHANISALIGNED;
+ input PIPERX0ELECIDLE;
+ input PIPERX0PHYSTATUS;
+ input PIPERX0VALID;
+ input PIPERX1CHANISALIGNED;
+ input PIPERX1ELECIDLE;
+ input PIPERX1PHYSTATUS;
+ input PIPERX1VALID;
+ input PIPERX2CHANISALIGNED;
+ input PIPERX2ELECIDLE;
+ input PIPERX2PHYSTATUS;
+ input PIPERX2VALID;
+ input PIPERX3CHANISALIGNED;
+ input PIPERX3ELECIDLE;
+ input PIPERX3PHYSTATUS;
+ input PIPERX3VALID;
+ input PIPERX4CHANISALIGNED;
+ input PIPERX4ELECIDLE;
+ input PIPERX4PHYSTATUS;
+ input PIPERX4VALID;
+ input PIPERX5CHANISALIGNED;
+ input PIPERX5ELECIDLE;
+ input PIPERX5PHYSTATUS;
+ input PIPERX5VALID;
+ input PIPERX6CHANISALIGNED;
+ input PIPERX6ELECIDLE;
+ input PIPERX6PHYSTATUS;
+ input PIPERX6VALID;
+ input PIPERX7CHANISALIGNED;
+ input PIPERX7ELECIDLE;
+ input PIPERX7PHYSTATUS;
+ input PIPERX7VALID;
+ input PLDIRECTEDLINKAUTON;
+ input PLDIRECTEDLINKSPEED;
+ input PLDOWNSTREAMDEEMPHSOURCE;
+ input PLRSTN;
+ input PLTRANSMITHOTRST;
+ input PLUPSTREAMPREFERDEEMPH;
+ input SYSRSTN;
+ input TL2ASPMSUSPENDCREDITCHECKN;
+ input TL2PPMSUSPENDREQN;
+ input TLRSTN;
+ input TRNRDSTRDYN;
+ input TRNRNPOKN;
+ input TRNTCFGGNTN;
+ input TRNTDLLPSRCRDYN;
+ input TRNTECRCGENN;
+ input TRNTEOFN;
+ input TRNTERRFWDN;
+ input TRNTREMN;
+ input TRNTSOFN;
+ input TRNTSRCDSCN;
+ input TRNTSRCRDYN;
+ input TRNTSTRN;
+ input USERCLK;
+ input [127:0] CFGERRAERHEADERLOG;
+ input [15:0] DRPDI;
+ input [15:0] PIPERX0DATA;
+ input [15:0] PIPERX1DATA;
+ input [15:0] PIPERX2DATA;
+ input [15:0] PIPERX3DATA;
+ input [15:0] PIPERX4DATA;
+ input [15:0] PIPERX5DATA;
+ input [15:0] PIPERX6DATA;
+ input [15:0] PIPERX7DATA;
+ input [1:0] DBGMODE;
+ input [1:0] PIPERX0CHARISK;
+ input [1:0] PIPERX1CHARISK;
+ input [1:0] PIPERX2CHARISK;
+ input [1:0] PIPERX3CHARISK;
+ input [1:0] PIPERX4CHARISK;
+ input [1:0] PIPERX5CHARISK;
+ input [1:0] PIPERX6CHARISK;
+ input [1:0] PIPERX7CHARISK;
+ input [1:0] PLDIRECTEDLINKCHANGE;
+ input [1:0] PLDIRECTEDLINKWIDTH;
+ input [2:0] CFGDSFUNCTIONNUMBER;
+ input [2:0] PIPERX0STATUS;
+ input [2:0] PIPERX1STATUS;
+ input [2:0] PIPERX2STATUS;
+ input [2:0] PIPERX3STATUS;
+ input [2:0] PIPERX4STATUS;
+ input [2:0] PIPERX5STATUS;
+ input [2:0] PIPERX6STATUS;
+ input [2:0] PIPERX7STATUS;
+ input [2:0] PLDBGMODE;
+ input [2:0] TRNFCSEL;
+ input [31:0] CFGDI;
+ input [31:0] TRNTDLLPDATA;
+ input [3:0] CFGBYTEENN;
+ input [47:0] CFGERRTLPCPLHEADER;
+ input [4:0] CFGDSDEVICENUMBER;
+ input [4:0] PL2DIRECTEDLSTATE;
+ input [63:0] CFGDSN;
+ input [63:0] TRNTD;
+ input [67:0] MIMRXRDATA;
+ input [68:0] MIMTXRDATA;
+ input [7:0] CFGDSBUSNUMBER;
+ input [7:0] CFGINTERRUPTDI;
+ input [7:0] CFGPORTNUMBER;
+ input [8:0] DRPDADDR;
+ input [9:0] CFGDWADDR;
+endmodule
+
+module SYSMON (...);
+ parameter [15:0] INIT_40 = 16'h0;
+ parameter [15:0] INIT_41 = 16'h0;
+ parameter [15:0] INIT_42 = 16'h0800;
+ parameter [15:0] INIT_43 = 16'h0;
+ parameter [15:0] INIT_44 = 16'h0;
+ parameter [15:0] INIT_45 = 16'h0;
+ parameter [15:0] INIT_46 = 16'h0;
+ parameter [15:0] INIT_47 = 16'h0;
+ parameter [15:0] INIT_48 = 16'h0;
+ parameter [15:0] INIT_49 = 16'h0;
+ parameter [15:0] INIT_4A = 16'h0;
+ parameter [15:0] INIT_4B = 16'h0;
+ parameter [15:0] INIT_4C = 16'h0;
+ parameter [15:0] INIT_4D = 16'h0;
+ parameter [15:0] INIT_4E = 16'h0;
+ parameter [15:0] INIT_4F = 16'h0;
+ parameter [15:0] INIT_50 = 16'h0;
+ parameter [15:0] INIT_51 = 16'h0;
+ parameter [15:0] INIT_52 = 16'h0;
+ parameter [15:0] INIT_53 = 16'h0;
+ parameter [15:0] INIT_54 = 16'h0;
+ parameter [15:0] INIT_55 = 16'h0;
+ parameter [15:0] INIT_56 = 16'h0;
+ parameter [15:0] INIT_57 = 16'h0;
+ parameter SIM_DEVICE = "VIRTEX5";
+ parameter SIM_MONITOR_FILE = "design.txt";
+ output BUSY;
+ output DRDY;
+ output EOC;
+ output EOS;
+ output JTAGBUSY;
+ output JTAGLOCKED;
+ output JTAGMODIFIED;
+ output OT;
+ output [15:0] DO;
+ output [2:0] ALM;
+ output [4:0] CHANNEL;
+ input CONVST;
+ input CONVSTCLK;
+ input DCLK;
+ input DEN;
+ input DWE;
+ input RESET;
+ input VN;
+ input VP;
+ input [15:0] DI;
+ input [15:0] VAUXN;
+ input [15:0] VAUXP;
+ input [6:0] DADDR;
+endmodule
+
+module DSP48E1 (...);
+ parameter integer ACASCREG = 1;
+ parameter integer ADREG = 1;
+ parameter integer ALUMODEREG = 1;
+ parameter integer AREG = 1;
+ parameter AUTORESET_PATDET = "NO_RESET";
+ parameter A_INPUT = "DIRECT";
+ parameter integer BCASCREG = 1;
+ parameter integer BREG = 1;
+ parameter B_INPUT = "DIRECT";
+ parameter integer CARRYINREG = 1;
+ parameter integer CARRYINSELREG = 1;
+ parameter integer CREG = 1;
+ parameter integer DREG = 1;
+ parameter integer INMODEREG = 1;
+ parameter integer MREG = 1;
+ parameter integer OPMODEREG = 1;
+ parameter integer PREG = 1;
+ parameter SEL_MASK = "MASK";
+ parameter SEL_PATTERN = "PATTERN";
+ parameter USE_DPORT = "FALSE";
+ parameter USE_MULT = "MULTIPLY";
+ parameter USE_PATTERN_DETECT = "NO_PATDET";
+ parameter USE_SIMD = "ONE48";
+ parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
+ parameter [47:0] PATTERN = 48'h000000000000;
+ parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
+ parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ parameter [4:0] IS_INMODE_INVERTED = 5'b0;
+ parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
+ output [29:0] ACOUT;
+ output [17:0] BCOUT;
+ output CARRYCASCOUT;
+ output [3:0] CARRYOUT;
+ output MULTSIGNOUT;
+ output OVERFLOW;
+ output [47:0] P;
+ output PATTERNBDETECT;
+ output PATTERNDETECT;
+ output [47:0] PCOUT;
+ output UNDERFLOW;
+ input [29:0] A;
+ input [29:0] ACIN;
+ (* invertible_pin = "IS_ALUMODE_INVERTED" *)
+ input [3:0] ALUMODE;
+ input [17:0] B;
+ input [17:0] BCIN;
+ input [47:0] C;
+ input CARRYCASCIN;
+ (* invertible_pin = "IS_CARRYIN_INVERTED" *)
+ input CARRYIN;
+ input [2:0] CARRYINSEL;
+ input CEA1;
+ input CEA2;
+ input CEAD;
+ input CEALUMODE;
+ input CEB1;
+ input CEB2;
+ input CEC;
+ input CECARRYIN;
+ input CECTRL;
+ input CED;
+ input CEINMODE;
+ input CEM;
+ input CEP;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLK_INVERTED" *)
+ input CLK;
+ input [24:0] D;
+ (* invertible_pin = "IS_INMODE_INVERTED" *)
+ input [4:0] INMODE;
+ input MULTSIGNIN;
+ (* invertible_pin = "IS_OPMODE_INVERTED" *)
+ input [6:0] OPMODE;
+ input [47:0] PCIN;
+ input RSTA;
+ input RSTALLCARRYIN;
+ input RSTALUMODE;
+ input RSTB;
+ input RSTC;
+ input RSTCTRL;
+ input RSTD;
+ input RSTINMODE;
+ input RSTM;
+ input RSTP;
+endmodule
+
+module BUFGCE (...);
+ parameter CE_TYPE = "SYNC";
+ parameter [0:0] IS_CE_INVERTED = 1'b0;
+ parameter [0:0] IS_I_INVERTED = 1'b0;
+ (* clkbuf_driver *)
+ output O;
+ (* invertible_pin = "IS_CE_INVERTED" *)
+ input CE;
+ (* invertible_pin = "IS_I_INVERTED" *)
+ input I;
+endmodule
+
+module BUFGCE_1 (...);
+ (* clkbuf_driver *)
+ output O;
+ input CE;
+ input I;
+endmodule
+
+module BUFGMUX (...);
+ parameter CLK_SEL_TYPE = "SYNC";
+ (* clkbuf_driver *)
+ output O;
+ input I0;
+ input I1;
+ input S;
+endmodule
+
+module BUFGMUX_1 (...);
+ parameter CLK_SEL_TYPE = "SYNC";
+ (* clkbuf_driver *)
+ output O;
+ input I0;
+ input I1;
+ input S;
+endmodule
+
+module BUFGMUX_CTRL (...);
+ (* clkbuf_driver *)
+ output O;
+ input I0;
+ input I1;
+ input S;
+endmodule
+
+module BUFH (...);
+ (* clkbuf_driver *)
+ output O;
+ input I;
+endmodule
+
+module BUFIO (...);
+ (* clkbuf_driver *)
+ output O;
+ input I;
+endmodule
+
+module BUFIODQS (...);
+ parameter DQSMASK_ENABLE = "FALSE";
+ (* clkbuf_driver *)
+ output O;
+ input DQSMASK;
+ input I;
+endmodule
+
+module BUFR (...);
+ parameter BUFR_DIVIDE = "BYPASS";
+ parameter SIM_DEVICE = "7SERIES";
+ (* clkbuf_driver *)
+ output O;
+ input CE;
+ input CLR;
+ input I;
+endmodule
+
+module IBUFDS_GTXE1 (...);
+ parameter CLKCM_CFG = "TRUE";
+ parameter CLKRCV_TRST = "TRUE";
+ parameter [9:0] REFCLKOUT_DLY = 10'b0000000000;
+ output O;
+ output ODIV2;
+ input CEB;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+endmodule
+
+module MMCM_ADV (...);
+ parameter BANDWIDTH = "OPTIMIZED";
+ parameter CLKFBOUT_USE_FINE_PS = "FALSE";
+ parameter CLKOUT0_USE_FINE_PS = "FALSE";
+ parameter CLKOUT1_USE_FINE_PS = "FALSE";
+ parameter CLKOUT2_USE_FINE_PS = "FALSE";
+ parameter CLKOUT3_USE_FINE_PS = "FALSE";
+ parameter CLKOUT4_CASCADE = "FALSE";
+ parameter CLKOUT4_USE_FINE_PS = "FALSE";
+ parameter CLKOUT5_USE_FINE_PS = "FALSE";
+ parameter CLKOUT6_USE_FINE_PS = "FALSE";
+ parameter CLOCK_HOLD = "FALSE";
+ parameter COMPENSATION = "ZHOLD";
+ parameter STARTUP_WAIT = "FALSE";
+ parameter integer CLKOUT1_DIVIDE = 1;
+ parameter integer CLKOUT2_DIVIDE = 1;
+ parameter integer CLKOUT3_DIVIDE = 1;
+ parameter integer CLKOUT4_DIVIDE = 1;
+ parameter integer CLKOUT5_DIVIDE = 1;
+ parameter integer CLKOUT6_DIVIDE = 1;
+ parameter integer DIVCLK_DIVIDE = 1;
+ parameter real CLKFBOUT_MULT_F = 5.000;
+ parameter real CLKFBOUT_PHASE = 0.000;
+ parameter real CLKIN1_PERIOD = 0.000;
+ parameter real CLKIN2_PERIOD = 0.000;
+ parameter real CLKOUT0_DIVIDE_F = 1.000;
+ parameter real CLKOUT0_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT0_PHASE = 0.000;
+ parameter real CLKOUT1_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT1_PHASE = 0.000;
+ parameter real CLKOUT2_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT2_PHASE = 0.000;
+ parameter real CLKOUT3_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT3_PHASE = 0.000;
+ parameter real CLKOUT4_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT4_PHASE = 0.000;
+ parameter real CLKOUT5_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT5_PHASE = 0.000;
+ parameter real CLKOUT6_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT6_PHASE = 0.000;
+ parameter real REF_JITTER1 = 0.010;
+ parameter real REF_JITTER2 = 0.010;
+ parameter real VCOCLK_FREQ_MAX = 1600.0;
+ parameter real VCOCLK_FREQ_MIN = 600.0;
+ parameter real CLKIN_FREQ_MAX = 800.0;
+ parameter real CLKIN_FREQ_MIN = 10.0;
+ parameter real CLKPFD_FREQ_MAX = 550.0;
+ parameter real CLKPFD_FREQ_MIN = 10.0;
+ output CLKFBOUT;
+ output CLKFBOUTB;
+ output CLKFBSTOPPED;
+ output CLKINSTOPPED;
+ output CLKOUT0;
+ output CLKOUT0B;
+ output CLKOUT1;
+ output CLKOUT1B;
+ output CLKOUT2;
+ output CLKOUT2B;
+ output CLKOUT3;
+ output CLKOUT3B;
+ output CLKOUT4;
+ output CLKOUT5;
+ output CLKOUT6;
+ output DRDY;
+ output LOCKED;
+ output PSDONE;
+ output [15:0] DO;
+ input CLKFBIN;
+ input CLKIN1;
+ input CLKIN2;
+ input CLKINSEL;
+ input DCLK;
+ input DEN;
+ input DWE;
+ input PSCLK;
+ input PSEN;
+ input PSINCDEC;
+ input PWRDWN;
+ input RST;
+ input [15:0] DI;
+ input [6:0] DADDR;
+endmodule
+
+module MMCM_BASE (...);
+ parameter BANDWIDTH = "OPTIMIZED";
+ parameter real CLKFBOUT_MULT_F = 5.000;
+ parameter real CLKFBOUT_PHASE = 0.000;
+ parameter real CLKIN1_PERIOD = 0.000;
+ parameter real CLKOUT0_DIVIDE_F = 1.000;
+ parameter real CLKOUT0_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT0_PHASE = 0.000;
+ parameter integer CLKOUT1_DIVIDE = 1;
+ parameter real CLKOUT1_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT1_PHASE = 0.000;
+ parameter integer CLKOUT2_DIVIDE = 1;
+ parameter real CLKOUT2_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT2_PHASE = 0.000;
+ parameter integer CLKOUT3_DIVIDE = 1;
+ parameter real CLKOUT3_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT3_PHASE = 0.000;
+ parameter CLKOUT4_CASCADE = "FALSE";
+ parameter integer CLKOUT4_DIVIDE = 1;
+ parameter real CLKOUT4_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT4_PHASE = 0.000;
+ parameter integer CLKOUT5_DIVIDE = 1;
+ parameter real CLKOUT5_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT5_PHASE = 0.000;
+ parameter integer CLKOUT6_DIVIDE = 1;
+ parameter real CLKOUT6_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT6_PHASE = 0.000;
+ parameter CLOCK_HOLD = "FALSE";
+ parameter integer DIVCLK_DIVIDE = 1;
+ parameter real REF_JITTER1 = 0.010;
+ parameter STARTUP_WAIT = "FALSE";
+ output CLKFBOUT;
+ output CLKFBOUTB;
+ output CLKOUT0;
+ output CLKOUT0B;
+ output CLKOUT1;
+ output CLKOUT1B;
+ output CLKOUT2;
+ output CLKOUT2B;
+ output CLKOUT3;
+ output CLKOUT3B;
+ output CLKOUT4;
+ output CLKOUT5;
+ output CLKOUT6;
+ output LOCKED;
+ input CLKFBIN;
+ input CLKIN1;
+ input PWRDWN;
+ input RST;
+endmodule
+
+(* keep *)
+module BSCAN_VIRTEX6 (...);
+ parameter DISABLE_JTAG = "FALSE";
+ parameter integer JTAG_CHAIN = 1;
+ output CAPTURE;
+ output DRCK;
+ output RESET;
+ output RUNTEST;
+ output SEL;
+ output SHIFT;
+ output TCK;
+ output TDI;
+ output TMS;
+ output UPDATE;
+ input TDO;
+endmodule
+
+(* keep *)
+module CAPTURE_VIRTEX6 (...);
+ parameter ONESHOT = "TRUE";
+ input CAP;
+ input CLK;
+endmodule
+
+module DNA_PORT (...);
+ parameter [56:0] SIM_DNA_VALUE = 57'h0;
+ output DOUT;
+ input CLK;
+ input DIN;
+ input READ;
+ input SHIFT;
+endmodule
+
+module EFUSE_USR (...);
+ parameter [31:0] SIM_EFUSE_VALUE = 32'h00000000;
+ output [31:0] EFUSEUSR;
+endmodule
+
+module FRAME_ECC_VIRTEX6 (...);
+ parameter FARSRC = "EFAR";
+ parameter FRAME_RBT_IN_FILENAME = "NONE";
+ output CRCERROR;
+ output ECCERROR;
+ output ECCERRORSINGLE;
+ output SYNDROMEVALID;
+ output [12:0] SYNDROME;
+ output [23:0] FAR;
+ output [4:0] SYNBIT;
+ output [6:0] SYNWORD;
+endmodule
+
+(* keep *)
+module ICAP_VIRTEX6 (...);
+ parameter [31:0] DEVICE_ID = 32'h04244093;
+ parameter ICAP_WIDTH = "X8";
+ parameter SIM_CFG_FILE_NAME = "NONE";
+ output BUSY;
+ output [31:0] O;
+ input CLK;
+ input CSB;
+ input RDWRB;
+ input [31:0] I;
+endmodule
+
+(* keep *)
+module STARTUP_VIRTEX6 (...);
+ parameter PROG_USR = "FALSE";
+ output CFGCLK;
+ output CFGMCLK;
+ output DINSPI;
+ output EOS;
+ output PREQ;
+ output TCKSPI;
+ input CLK;
+ input GSR;
+ input GTS;
+ input KEYCLEARB;
+ input PACK;
+ input USRCCLKO;
+ input USRCCLKTS;
+ input USRDONEO;
+ input USRDONETS;
+endmodule
+
+module USR_ACCESS_VIRTEX6 (...);
+ output CFGCLK;
+ output [31:0] DATA;
+ output DATAVALID;
+endmodule
+
+(* keep *)
+module DCIRESET (...);
+ output LOCKED;
+ input RST;
+endmodule
+
+module GTHE1_QUAD (...);
+ parameter [15:0] BER_CONST_PTRN0 = 16'h0000;
+ parameter [15:0] BER_CONST_PTRN1 = 16'h0000;
+ parameter [15:0] BUFFER_CONFIG_LANE0 = 16'h4004;
+ parameter [15:0] BUFFER_CONFIG_LANE1 = 16'h4004;
+ parameter [15:0] BUFFER_CONFIG_LANE2 = 16'h4004;
+ parameter [15:0] BUFFER_CONFIG_LANE3 = 16'h4004;
+ parameter [15:0] DFE_TRAIN_CTRL_LANE0 = 16'h0000;
+ parameter [15:0] DFE_TRAIN_CTRL_LANE1 = 16'h0000;
+ parameter [15:0] DFE_TRAIN_CTRL_LANE2 = 16'h0000;
+ parameter [15:0] DFE_TRAIN_CTRL_LANE3 = 16'h0000;
+ parameter [15:0] DLL_CFG0 = 16'h8202;
+ parameter [15:0] DLL_CFG1 = 16'h0000;
+ parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE0 = 16'h0000;
+ parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE1 = 16'h0000;
+ parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE2 = 16'h0000;
+ parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE3 = 16'h0000;
+ parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE0 = 16'h0000;
+ parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE1 = 16'h0000;
+ parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE2 = 16'h0000;
+ parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE3 = 16'h0000;
+ parameter [15:0] E10GBASEKR_PMA_CTRL_LANE0 = 16'h0002;
+ parameter [15:0] E10GBASEKR_PMA_CTRL_LANE1 = 16'h0002;
+ parameter [15:0] E10GBASEKR_PMA_CTRL_LANE2 = 16'h0002;
+ parameter [15:0] E10GBASEKR_PMA_CTRL_LANE3 = 16'h0002;
+ parameter [15:0] E10GBASEKX_CTRL_LANE0 = 16'h0000;
+ parameter [15:0] E10GBASEKX_CTRL_LANE1 = 16'h0000;
+ parameter [15:0] E10GBASEKX_CTRL_LANE2 = 16'h0000;
+ parameter [15:0] E10GBASEKX_CTRL_LANE3 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_CFG_LANE0 = 16'h070C;
+ parameter [15:0] E10GBASER_PCS_CFG_LANE1 = 16'h070C;
+ parameter [15:0] E10GBASER_PCS_CFG_LANE2 = 16'h070C;
+ parameter [15:0] E10GBASER_PCS_CFG_LANE3 = 16'h070C;
+ parameter [15:0] E10GBASER_PCS_SEEDA0_LANE0 = 16'h0001;
+ parameter [15:0] E10GBASER_PCS_SEEDA0_LANE1 = 16'h0001;
+ parameter [15:0] E10GBASER_PCS_SEEDA0_LANE2 = 16'h0001;
+ parameter [15:0] E10GBASER_PCS_SEEDA0_LANE3 = 16'h0001;
+ parameter [15:0] E10GBASER_PCS_SEEDA1_LANE0 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_SEEDA1_LANE1 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_SEEDA1_LANE2 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_SEEDA1_LANE3 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_SEEDA2_LANE0 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_SEEDA2_LANE1 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_SEEDA2_LANE2 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_SEEDA2_LANE3 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_SEEDA3_LANE0 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_SEEDA3_LANE1 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_SEEDA3_LANE2 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_SEEDA3_LANE3 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_SEEDB0_LANE0 = 16'h0001;
+ parameter [15:0] E10GBASER_PCS_SEEDB0_LANE1 = 16'h0001;
+ parameter [15:0] E10GBASER_PCS_SEEDB0_LANE2 = 16'h0001;
+ parameter [15:0] E10GBASER_PCS_SEEDB0_LANE3 = 16'h0001;
+ parameter [15:0] E10GBASER_PCS_SEEDB1_LANE0 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_SEEDB1_LANE1 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_SEEDB1_LANE2 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_SEEDB1_LANE3 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_SEEDB2_LANE0 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_SEEDB2_LANE1 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_SEEDB2_LANE2 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_SEEDB2_LANE3 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_SEEDB3_LANE0 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_SEEDB3_LANE1 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_SEEDB3_LANE2 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_SEEDB3_LANE3 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE0 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE1 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE2 = 16'h0000;
+ parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE3 = 16'h0000;
+ parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE0 = 16'h0000;
+ parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE1 = 16'h0000;
+ parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE2 = 16'h0000;
+ parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE3 = 16'h0000;
+ parameter [15:0] GLBL0_NOISE_CTRL = 16'hF0B8;
+ parameter [15:0] GLBL_AMON_SEL = 16'h0000;
+ parameter [15:0] GLBL_DMON_SEL = 16'h0200;
+ parameter [15:0] GLBL_PWR_CTRL = 16'h0000;
+ parameter [0:0] GTH_CFG_PWRUP_LANE0 = 1'b1;
+ parameter [0:0] GTH_CFG_PWRUP_LANE1 = 1'b1;
+ parameter [0:0] GTH_CFG_PWRUP_LANE2 = 1'b1;
+ parameter [0:0] GTH_CFG_PWRUP_LANE3 = 1'b1;
+ parameter [15:0] LANE_AMON_SEL = 16'h00F0;
+ parameter [15:0] LANE_DMON_SEL = 16'h0000;
+ parameter [15:0] LANE_LNK_CFGOVRD = 16'h0000;
+ parameter [15:0] LANE_PWR_CTRL_LANE0 = 16'h0400;
+ parameter [15:0] LANE_PWR_CTRL_LANE1 = 16'h0400;
+ parameter [15:0] LANE_PWR_CTRL_LANE2 = 16'h0400;
+ parameter [15:0] LANE_PWR_CTRL_LANE3 = 16'h0400;
+ parameter [15:0] LNK_TRN_CFG_LANE0 = 16'h0000;
+ parameter [15:0] LNK_TRN_CFG_LANE1 = 16'h0000;
+ parameter [15:0] LNK_TRN_CFG_LANE2 = 16'h0000;
+ parameter [15:0] LNK_TRN_CFG_LANE3 = 16'h0000;
+ parameter [15:0] LNK_TRN_COEFF_REQ_LANE0 = 16'h0000;
+ parameter [15:0] LNK_TRN_COEFF_REQ_LANE1 = 16'h0000;
+ parameter [15:0] LNK_TRN_COEFF_REQ_LANE2 = 16'h0000;
+ parameter [15:0] LNK_TRN_COEFF_REQ_LANE3 = 16'h0000;
+ parameter [15:0] MISC_CFG = 16'h0008;
+ parameter [15:0] MODE_CFG1 = 16'h0000;
+ parameter [15:0] MODE_CFG2 = 16'h0000;
+ parameter [15:0] MODE_CFG3 = 16'h0000;
+ parameter [15:0] MODE_CFG4 = 16'h0000;
+ parameter [15:0] MODE_CFG5 = 16'h0000;
+ parameter [15:0] MODE_CFG6 = 16'h0000;
+ parameter [15:0] MODE_CFG7 = 16'h0000;
+ parameter [15:0] PCS_ABILITY_LANE0 = 16'h0010;
+ parameter [15:0] PCS_ABILITY_LANE1 = 16'h0010;
+ parameter [15:0] PCS_ABILITY_LANE2 = 16'h0010;
+ parameter [15:0] PCS_ABILITY_LANE3 = 16'h0010;
+ parameter [15:0] PCS_CTRL1_LANE0 = 16'h2040;
+ parameter [15:0] PCS_CTRL1_LANE1 = 16'h2040;
+ parameter [15:0] PCS_CTRL1_LANE2 = 16'h2040;
+ parameter [15:0] PCS_CTRL1_LANE3 = 16'h2040;
+ parameter [15:0] PCS_CTRL2_LANE0 = 16'h0000;
+ parameter [15:0] PCS_CTRL2_LANE1 = 16'h0000;
+ parameter [15:0] PCS_CTRL2_LANE2 = 16'h0000;
+ parameter [15:0] PCS_CTRL2_LANE3 = 16'h0000;
+ parameter [15:0] PCS_MISC_CFG_0_LANE0 = 16'h1116;
+ parameter [15:0] PCS_MISC_CFG_0_LANE1 = 16'h1116;
+ parameter [15:0] PCS_MISC_CFG_0_LANE2 = 16'h1116;
+ parameter [15:0] PCS_MISC_CFG_0_LANE3 = 16'h1116;
+ parameter [15:0] PCS_MISC_CFG_1_LANE0 = 16'h0000;
+ parameter [15:0] PCS_MISC_CFG_1_LANE1 = 16'h0000;
+ parameter [15:0] PCS_MISC_CFG_1_LANE2 = 16'h0000;
+ parameter [15:0] PCS_MISC_CFG_1_LANE3 = 16'h0000;
+ parameter [15:0] PCS_MODE_LANE0 = 16'h0000;
+ parameter [15:0] PCS_MODE_LANE1 = 16'h0000;
+ parameter [15:0] PCS_MODE_LANE2 = 16'h0000;
+ parameter [15:0] PCS_MODE_LANE3 = 16'h0000;
+ parameter [15:0] PCS_RESET_1_LANE0 = 16'h0002;
+ parameter [15:0] PCS_RESET_1_LANE1 = 16'h0002;
+ parameter [15:0] PCS_RESET_1_LANE2 = 16'h0002;
+ parameter [15:0] PCS_RESET_1_LANE3 = 16'h0002;
+ parameter [15:0] PCS_RESET_LANE0 = 16'h0000;
+ parameter [15:0] PCS_RESET_LANE1 = 16'h0000;
+ parameter [15:0] PCS_RESET_LANE2 = 16'h0000;
+ parameter [15:0] PCS_RESET_LANE3 = 16'h0000;
+ parameter [15:0] PCS_TYPE_LANE0 = 16'h002C;
+ parameter [15:0] PCS_TYPE_LANE1 = 16'h002C;
+ parameter [15:0] PCS_TYPE_LANE2 = 16'h002C;
+ parameter [15:0] PCS_TYPE_LANE3 = 16'h002C;
+ parameter [15:0] PLL_CFG0 = 16'h95DF;
+ parameter [15:0] PLL_CFG1 = 16'h81C0;
+ parameter [15:0] PLL_CFG2 = 16'h0424;
+ parameter [15:0] PMA_CTRL1_LANE0 = 16'h0000;
+ parameter [15:0] PMA_CTRL1_LANE1 = 16'h0000;
+ parameter [15:0] PMA_CTRL1_LANE2 = 16'h0000;
+ parameter [15:0] PMA_CTRL1_LANE3 = 16'h0000;
+ parameter [15:0] PMA_CTRL2_LANE0 = 16'h000B;
+ parameter [15:0] PMA_CTRL2_LANE1 = 16'h000B;
+ parameter [15:0] PMA_CTRL2_LANE2 = 16'h000B;
+ parameter [15:0] PMA_CTRL2_LANE3 = 16'h000B;
+ parameter [15:0] PMA_LPBK_CTRL_LANE0 = 16'h0004;
+ parameter [15:0] PMA_LPBK_CTRL_LANE1 = 16'h0004;
+ parameter [15:0] PMA_LPBK_CTRL_LANE2 = 16'h0004;
+ parameter [15:0] PMA_LPBK_CTRL_LANE3 = 16'h0004;
+ parameter [15:0] PRBS_BER_CFG0_LANE0 = 16'h0000;
+ parameter [15:0] PRBS_BER_CFG0_LANE1 = 16'h0000;
+ parameter [15:0] PRBS_BER_CFG0_LANE2 = 16'h0000;
+ parameter [15:0] PRBS_BER_CFG0_LANE3 = 16'h0000;
+ parameter [15:0] PRBS_BER_CFG1_LANE0 = 16'h0000;
+ parameter [15:0] PRBS_BER_CFG1_LANE1 = 16'h0000;
+ parameter [15:0] PRBS_BER_CFG1_LANE2 = 16'h0000;
+ parameter [15:0] PRBS_BER_CFG1_LANE3 = 16'h0000;
+ parameter [15:0] PRBS_CFG_LANE0 = 16'h000A;
+ parameter [15:0] PRBS_CFG_LANE1 = 16'h000A;
+ parameter [15:0] PRBS_CFG_LANE2 = 16'h000A;
+ parameter [15:0] PRBS_CFG_LANE3 = 16'h000A;
+ parameter [15:0] PTRN_CFG0_LSB = 16'h5555;
+ parameter [15:0] PTRN_CFG0_MSB = 16'h5555;
+ parameter [15:0] PTRN_LEN_CFG = 16'h001F;
+ parameter [15:0] PWRUP_DLY = 16'h0000;
+ parameter [15:0] RX_AEQ_VAL0_LANE0 = 16'h03C0;
+ parameter [15:0] RX_AEQ_VAL0_LANE1 = 16'h03C0;
+ parameter [15:0] RX_AEQ_VAL0_LANE2 = 16'h03C0;
+ parameter [15:0] RX_AEQ_VAL0_LANE3 = 16'h03C0;
+ parameter [15:0] RX_AEQ_VAL1_LANE0 = 16'h0000;
+ parameter [15:0] RX_AEQ_VAL1_LANE1 = 16'h0000;
+ parameter [15:0] RX_AEQ_VAL1_LANE2 = 16'h0000;
+ parameter [15:0] RX_AEQ_VAL1_LANE3 = 16'h0000;
+ parameter [15:0] RX_AGC_CTRL_LANE0 = 16'h0000;
+ parameter [15:0] RX_AGC_CTRL_LANE1 = 16'h0000;
+ parameter [15:0] RX_AGC_CTRL_LANE2 = 16'h0000;
+ parameter [15:0] RX_AGC_CTRL_LANE3 = 16'h0000;
+ parameter [15:0] RX_CDR_CTRL0_LANE0 = 16'h0005;
+ parameter [15:0] RX_CDR_CTRL0_LANE1 = 16'h0005;
+ parameter [15:0] RX_CDR_CTRL0_LANE2 = 16'h0005;
+ parameter [15:0] RX_CDR_CTRL0_LANE3 = 16'h0005;
+ parameter [15:0] RX_CDR_CTRL1_LANE0 = 16'h4200;
+ parameter [15:0] RX_CDR_CTRL1_LANE1 = 16'h4200;
+ parameter [15:0] RX_CDR_CTRL1_LANE2 = 16'h4200;
+ parameter [15:0] RX_CDR_CTRL1_LANE3 = 16'h4200;
+ parameter [15:0] RX_CDR_CTRL2_LANE0 = 16'h2000;
+ parameter [15:0] RX_CDR_CTRL2_LANE1 = 16'h2000;
+ parameter [15:0] RX_CDR_CTRL2_LANE2 = 16'h2000;
+ parameter [15:0] RX_CDR_CTRL2_LANE3 = 16'h2000;
+ parameter [15:0] RX_CFG0_LANE0 = 16'h0500;
+ parameter [15:0] RX_CFG0_LANE1 = 16'h0500;
+ parameter [15:0] RX_CFG0_LANE2 = 16'h0500;
+ parameter [15:0] RX_CFG0_LANE3 = 16'h0500;
+ parameter [15:0] RX_CFG1_LANE0 = 16'h821F;
+ parameter [15:0] RX_CFG1_LANE1 = 16'h821F;
+ parameter [15:0] RX_CFG1_LANE2 = 16'h821F;
+ parameter [15:0] RX_CFG1_LANE3 = 16'h821F;
+ parameter [15:0] RX_CFG2_LANE0 = 16'h1001;
+ parameter [15:0] RX_CFG2_LANE1 = 16'h1001;
+ parameter [15:0] RX_CFG2_LANE2 = 16'h1001;
+ parameter [15:0] RX_CFG2_LANE3 = 16'h1001;
+ parameter [15:0] RX_CTLE_CTRL_LANE0 = 16'h008F;
+ parameter [15:0] RX_CTLE_CTRL_LANE1 = 16'h008F;
+ parameter [15:0] RX_CTLE_CTRL_LANE2 = 16'h008F;
+ parameter [15:0] RX_CTLE_CTRL_LANE3 = 16'h008F;
+ parameter [15:0] RX_CTRL_OVRD_LANE0 = 16'h000C;
+ parameter [15:0] RX_CTRL_OVRD_LANE1 = 16'h000C;
+ parameter [15:0] RX_CTRL_OVRD_LANE2 = 16'h000C;
+ parameter [15:0] RX_CTRL_OVRD_LANE3 = 16'h000C;
+ parameter integer RX_FABRIC_WIDTH0 = 6466;
+ parameter integer RX_FABRIC_WIDTH1 = 6466;
+ parameter integer RX_FABRIC_WIDTH2 = 6466;
+ parameter integer RX_FABRIC_WIDTH3 = 6466;
+ parameter [15:0] RX_LOOP_CTRL_LANE0 = 16'h007F;
+ parameter [15:0] RX_LOOP_CTRL_LANE1 = 16'h007F;
+ parameter [15:0] RX_LOOP_CTRL_LANE2 = 16'h007F;
+ parameter [15:0] RX_LOOP_CTRL_LANE3 = 16'h007F;
+ parameter [15:0] RX_MVAL0_LANE0 = 16'h0000;
+ parameter [15:0] RX_MVAL0_LANE1 = 16'h0000;
+ parameter [15:0] RX_MVAL0_LANE2 = 16'h0000;
+ parameter [15:0] RX_MVAL0_LANE3 = 16'h0000;
+ parameter [15:0] RX_MVAL1_LANE0 = 16'h0000;
+ parameter [15:0] RX_MVAL1_LANE1 = 16'h0000;
+ parameter [15:0] RX_MVAL1_LANE2 = 16'h0000;
+ parameter [15:0] RX_MVAL1_LANE3 = 16'h0000;
+ parameter [15:0] RX_P0S_CTRL = 16'h1206;
+ parameter [15:0] RX_P0_CTRL = 16'h11F0;
+ parameter [15:0] RX_P1_CTRL = 16'h120F;
+ parameter [15:0] RX_P2_CTRL = 16'h0E0F;
+ parameter [15:0] RX_PI_CTRL0 = 16'hD2F0;
+ parameter [15:0] RX_PI_CTRL1 = 16'h0080;
+ parameter integer SIM_GTHRESET_SPEEDUP = 1;
+ parameter SIM_VERSION = "1.0";
+ parameter [15:0] SLICE_CFG = 16'h0000;
+ parameter [15:0] SLICE_NOISE_CTRL_0_LANE01 = 16'h0000;
+ parameter [15:0] SLICE_NOISE_CTRL_0_LANE23 = 16'h0000;
+ parameter [15:0] SLICE_NOISE_CTRL_1_LANE01 = 16'h0000;
+ parameter [15:0] SLICE_NOISE_CTRL_1_LANE23 = 16'h0000;
+ parameter [15:0] SLICE_NOISE_CTRL_2_LANE01 = 16'h7FFF;
+ parameter [15:0] SLICE_NOISE_CTRL_2_LANE23 = 16'h7FFF;
+ parameter [15:0] SLICE_TX_RESET_LANE01 = 16'h0000;
+ parameter [15:0] SLICE_TX_RESET_LANE23 = 16'h0000;
+ parameter [15:0] TERM_CTRL_LANE0 = 16'h5007;
+ parameter [15:0] TERM_CTRL_LANE1 = 16'h5007;
+ parameter [15:0] TERM_CTRL_LANE2 = 16'h5007;
+ parameter [15:0] TERM_CTRL_LANE3 = 16'h5007;
+ parameter [15:0] TX_CFG0_LANE0 = 16'h203D;
+ parameter [15:0] TX_CFG0_LANE1 = 16'h203D;
+ parameter [15:0] TX_CFG0_LANE2 = 16'h203D;
+ parameter [15:0] TX_CFG0_LANE3 = 16'h203D;
+ parameter [15:0] TX_CFG1_LANE0 = 16'h0F00;
+ parameter [15:0] TX_CFG1_LANE1 = 16'h0F00;
+ parameter [15:0] TX_CFG1_LANE2 = 16'h0F00;
+ parameter [15:0] TX_CFG1_LANE3 = 16'h0F00;
+ parameter [15:0] TX_CFG2_LANE0 = 16'h0081;
+ parameter [15:0] TX_CFG2_LANE1 = 16'h0081;
+ parameter [15:0] TX_CFG2_LANE2 = 16'h0081;
+ parameter [15:0] TX_CFG2_LANE3 = 16'h0081;
+ parameter [15:0] TX_CLK_SEL0_LANE0 = 16'h2121;
+ parameter [15:0] TX_CLK_SEL0_LANE1 = 16'h2121;
+ parameter [15:0] TX_CLK_SEL0_LANE2 = 16'h2121;
+ parameter [15:0] TX_CLK_SEL0_LANE3 = 16'h2121;
+ parameter [15:0] TX_CLK_SEL1_LANE0 = 16'h2121;
+ parameter [15:0] TX_CLK_SEL1_LANE1 = 16'h2121;
+ parameter [15:0] TX_CLK_SEL1_LANE2 = 16'h2121;
+ parameter [15:0] TX_CLK_SEL1_LANE3 = 16'h2121;
+ parameter [15:0] TX_DISABLE_LANE0 = 16'h0000;
+ parameter [15:0] TX_DISABLE_LANE1 = 16'h0000;
+ parameter [15:0] TX_DISABLE_LANE2 = 16'h0000;
+ parameter [15:0] TX_DISABLE_LANE3 = 16'h0000;
+ parameter integer TX_FABRIC_WIDTH0 = 6466;
+ parameter integer TX_FABRIC_WIDTH1 = 6466;
+ parameter integer TX_FABRIC_WIDTH2 = 6466;
+ parameter integer TX_FABRIC_WIDTH3 = 6466;
+ parameter [15:0] TX_P0P0S_CTRL = 16'h060C;
+ parameter [15:0] TX_P1P2_CTRL = 16'h0C39;
+ parameter [15:0] TX_PREEMPH_LANE0 = 16'h00A1;
+ parameter [15:0] TX_PREEMPH_LANE1 = 16'h00A1;
+ parameter [15:0] TX_PREEMPH_LANE2 = 16'h00A1;
+ parameter [15:0] TX_PREEMPH_LANE3 = 16'h00A1;
+ parameter [15:0] TX_PWR_RATE_OVRD_LANE0 = 16'h0060;
+ parameter [15:0] TX_PWR_RATE_OVRD_LANE1 = 16'h0060;
+ parameter [15:0] TX_PWR_RATE_OVRD_LANE2 = 16'h0060;
+ parameter [15:0] TX_PWR_RATE_OVRD_LANE3 = 16'h0060;
+ output DRDY;
+ output GTHINITDONE;
+ output MGMTPCSRDACK;
+ output RXCTRLACK0;
+ output RXCTRLACK1;
+ output RXCTRLACK2;
+ output RXCTRLACK3;
+ output RXDATATAP0;
+ output RXDATATAP1;
+ output RXDATATAP2;
+ output RXDATATAP3;
+ output RXPCSCLKSMPL0;
+ output RXPCSCLKSMPL1;
+ output RXPCSCLKSMPL2;
+ output RXPCSCLKSMPL3;
+ output RXUSERCLKOUT0;
+ output RXUSERCLKOUT1;
+ output RXUSERCLKOUT2;
+ output RXUSERCLKOUT3;
+ output TSTPATH;
+ output TSTREFCLKFAB;
+ output TSTREFCLKOUT;
+ output TXCTRLACK0;
+ output TXCTRLACK1;
+ output TXCTRLACK2;
+ output TXCTRLACK3;
+ output TXDATATAP10;
+ output TXDATATAP11;
+ output TXDATATAP12;
+ output TXDATATAP13;
+ output TXDATATAP20;
+ output TXDATATAP21;
+ output TXDATATAP22;
+ output TXDATATAP23;
+ output TXN0;
+ output TXN1;
+ output TXN2;
+ output TXN3;
+ output TXP0;
+ output TXP1;
+ output TXP2;
+ output TXP3;
+ output TXPCSCLKSMPL0;
+ output TXPCSCLKSMPL1;
+ output TXPCSCLKSMPL2;
+ output TXPCSCLKSMPL3;
+ output TXUSERCLKOUT0;
+ output TXUSERCLKOUT1;
+ output TXUSERCLKOUT2;
+ output TXUSERCLKOUT3;
+ output [15:0] DRPDO;
+ output [15:0] MGMTPCSRDDATA;
+ output [63:0] RXDATA0;
+ output [63:0] RXDATA1;
+ output [63:0] RXDATA2;
+ output [63:0] RXDATA3;
+ output [7:0] RXCODEERR0;
+ output [7:0] RXCODEERR1;
+ output [7:0] RXCODEERR2;
+ output [7:0] RXCODEERR3;
+ output [7:0] RXCTRL0;
+ output [7:0] RXCTRL1;
+ output [7:0] RXCTRL2;
+ output [7:0] RXCTRL3;
+ output [7:0] RXDISPERR0;
+ output [7:0] RXDISPERR1;
+ output [7:0] RXDISPERR2;
+ output [7:0] RXDISPERR3;
+ output [7:0] RXVALID0;
+ output [7:0] RXVALID1;
+ output [7:0] RXVALID2;
+ output [7:0] RXVALID3;
+ input DCLK;
+ input DEN;
+ input DFETRAINCTRL0;
+ input DFETRAINCTRL1;
+ input DFETRAINCTRL2;
+ input DFETRAINCTRL3;
+ input DISABLEDRP;
+ input DWE;
+ input GTHINIT;
+ input GTHRESET;
+ input GTHX2LANE01;
+ input GTHX2LANE23;
+ input GTHX4LANE;
+ input MGMTPCSREGRD;
+ input MGMTPCSREGWR;
+ input POWERDOWN0;
+ input POWERDOWN1;
+ input POWERDOWN2;
+ input POWERDOWN3;
+ input REFCLK;
+ input RXBUFRESET0;
+ input RXBUFRESET1;
+ input RXBUFRESET2;
+ input RXBUFRESET3;
+ input RXENCOMMADET0;
+ input RXENCOMMADET1;
+ input RXENCOMMADET2;
+ input RXENCOMMADET3;
+ input RXN0;
+ input RXN1;
+ input RXN2;
+ input RXN3;
+ input RXP0;
+ input RXP1;
+ input RXP2;
+ input RXP3;
+ input RXPOLARITY0;
+ input RXPOLARITY1;
+ input RXPOLARITY2;
+ input RXPOLARITY3;
+ input RXSLIP0;
+ input RXSLIP1;
+ input RXSLIP2;
+ input RXSLIP3;
+ input RXUSERCLKIN0;
+ input RXUSERCLKIN1;
+ input RXUSERCLKIN2;
+ input RXUSERCLKIN3;
+ input TXBUFRESET0;
+ input TXBUFRESET1;
+ input TXBUFRESET2;
+ input TXBUFRESET3;
+ input TXDEEMPH0;
+ input TXDEEMPH1;
+ input TXDEEMPH2;
+ input TXDEEMPH3;
+ input TXUSERCLKIN0;
+ input TXUSERCLKIN1;
+ input TXUSERCLKIN2;
+ input TXUSERCLKIN3;
+ input [15:0] DADDR;
+ input [15:0] DI;
+ input [15:0] MGMTPCSREGADDR;
+ input [15:0] MGMTPCSWRDATA;
+ input [1:0] RXPOWERDOWN0;
+ input [1:0] RXPOWERDOWN1;
+ input [1:0] RXPOWERDOWN2;
+ input [1:0] RXPOWERDOWN3;
+ input [1:0] RXRATE0;
+ input [1:0] RXRATE1;
+ input [1:0] RXRATE2;
+ input [1:0] RXRATE3;
+ input [1:0] TXPOWERDOWN0;
+ input [1:0] TXPOWERDOWN1;
+ input [1:0] TXPOWERDOWN2;
+ input [1:0] TXPOWERDOWN3;
+ input [1:0] TXRATE0;
+ input [1:0] TXRATE1;
+ input [1:0] TXRATE2;
+ input [1:0] TXRATE3;
+ input [2:0] PLLREFCLKSEL;
+ input [2:0] SAMPLERATE0;
+ input [2:0] SAMPLERATE1;
+ input [2:0] SAMPLERATE2;
+ input [2:0] SAMPLERATE3;
+ input [2:0] TXMARGIN0;
+ input [2:0] TXMARGIN1;
+ input [2:0] TXMARGIN2;
+ input [2:0] TXMARGIN3;
+ input [3:0] MGMTPCSLANESEL;
+ input [4:0] MGMTPCSMMDADDR;
+ input [5:0] PLLPCSCLKDIV;
+ input [63:0] TXDATA0;
+ input [63:0] TXDATA1;
+ input [63:0] TXDATA2;
+ input [63:0] TXDATA3;
+ input [7:0] TXCTRL0;
+ input [7:0] TXCTRL1;
+ input [7:0] TXCTRL2;
+ input [7:0] TXCTRL3;
+ input [7:0] TXDATAMSB0;
+ input [7:0] TXDATAMSB1;
+ input [7:0] TXDATAMSB2;
+ input [7:0] TXDATAMSB3;
+endmodule
+
+module GTXE1 (...);
+ parameter AC_CAP_DIS = "TRUE";
+ parameter integer ALIGN_COMMA_WORD = 1;
+ parameter [1:0] BGTEST_CFG = 2'b00;
+ parameter [16:0] BIAS_CFG = 17'h00000;
+ parameter [4:0] CDR_PH_ADJ_TIME = 5'b10100;
+ parameter integer CHAN_BOND_1_MAX_SKEW = 7;
+ parameter integer CHAN_BOND_2_MAX_SKEW = 1;
+ parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
+ parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
+ parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0001001010;
+ parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0001001010;
+ parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0110111100;
+ parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
+ parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100111100;
+ parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100111100;
+ parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0110111100;
+ parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100111100;
+ parameter [4:0] CHAN_BOND_SEQ_2_CFG = 5'b00000;
+ parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
+ parameter CHAN_BOND_SEQ_2_USE = "FALSE";
+ parameter integer CHAN_BOND_SEQ_LEN = 1;
+ parameter CLK_CORRECT_USE = "TRUE";
+ parameter integer CLK_COR_ADJ_LEN = 1;
+ parameter integer CLK_COR_DET_LEN = 1;
+ parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
+ parameter CLK_COR_KEEP_IDLE = "FALSE";
+ parameter integer CLK_COR_MAX_LAT = 20;
+ parameter integer CLK_COR_MIN_LAT = 18;
+ parameter CLK_COR_PRECEDENCE = "TRUE";
+ parameter integer CLK_COR_REPEAT_WAIT = 0;
+ parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100;
+ parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000;
+ parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111;
+ parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0000000000;
+ parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
+ parameter CLK_COR_SEQ_2_USE = "FALSE";
+ parameter [1:0] CM_TRIM = 2'b01;
+ parameter [9:0] COMMA_10B_ENABLE = 10'b1111111111;
+ parameter COMMA_DOUBLE = "FALSE";
+ parameter [3:0] COM_BURST_VAL = 4'b1111;
+ parameter DEC_MCOMMA_DETECT = "TRUE";
+ parameter DEC_PCOMMA_DETECT = "TRUE";
+ parameter DEC_VALID_COMMA_ONLY = "TRUE";
+ parameter [4:0] DFE_CAL_TIME = 5'b01100;
+ parameter [7:0] DFE_CFG = 8'b00011011;
+ parameter [2:0] GEARBOX_ENDEC = 3'b000;
+ parameter GEN_RXUSRCLK = "TRUE";
+ parameter GEN_TXUSRCLK = "TRUE";
+ parameter GTX_CFG_PWRUP = "TRUE";
+ parameter [9:0] MCOMMA_10B_VALUE = 10'b1010000011;
+ parameter MCOMMA_DETECT = "TRUE";
+ parameter [2:0] OOBDETECT_THRESHOLD = 3'b011;
+ parameter PCI_EXPRESS_MODE = "FALSE";
+ parameter [9:0] PCOMMA_10B_VALUE = 10'b0101111100;
+ parameter PCOMMA_DETECT = "TRUE";
+ parameter PMA_CAS_CLK_EN = "FALSE";
+ parameter [26:0] PMA_CDR_SCAN = 27'h640404C;
+ parameter [75:0] PMA_CFG = 76'h0040000040000000003;
+ parameter [6:0] PMA_RXSYNC_CFG = 7'h00;
+ parameter [24:0] PMA_RX_CFG = 25'h05CE048;
+ parameter [19:0] PMA_TX_CFG = 20'h00082;
+ parameter [9:0] POWER_SAVE = 10'b0000110100;
+ parameter RCV_TERM_GND = "FALSE";
+ parameter RCV_TERM_VTTRX = "TRUE";
+ parameter RXGEARBOX_USE = "FALSE";
+ parameter [23:0] RXPLL_COM_CFG = 24'h21680A;
+ parameter [7:0] RXPLL_CP_CFG = 8'h00;
+ parameter integer RXPLL_DIVSEL45_FB = 5;
+ parameter integer RXPLL_DIVSEL_FB = 2;
+ parameter integer RXPLL_DIVSEL_OUT = 1;
+ parameter integer RXPLL_DIVSEL_REF = 1;
+ parameter [2:0] RXPLL_LKDET_CFG = 3'b111;
+ parameter [0:0] RXPRBSERR_LOOPBACK = 1'b0;
+ parameter RXRECCLK_CTRL = "RXRECCLKPCS";
+ parameter [9:0] RXRECCLK_DLY = 10'b0000000000;
+ parameter [15:0] RXUSRCLK_DLY = 16'h0000;
+ parameter RX_BUFFER_USE = "TRUE";
+ parameter integer RX_CLK25_DIVIDER = 6;
+ parameter integer RX_DATA_WIDTH = 20;
+ parameter RX_DECODE_SEQ_MATCH = "TRUE";
+ parameter [3:0] RX_DLYALIGN_CTRINC = 4'b0100;
+ parameter [4:0] RX_DLYALIGN_EDGESET = 5'b00110;
+ parameter [3:0] RX_DLYALIGN_LPFINC = 4'b0111;
+ parameter [2:0] RX_DLYALIGN_MONSEL = 3'b000;
+ parameter [7:0] RX_DLYALIGN_OVRDSETTING = 8'b00000000;
+ parameter RX_EN_IDLE_HOLD_CDR = "FALSE";
+ parameter RX_EN_IDLE_HOLD_DFE = "TRUE";
+ parameter RX_EN_IDLE_RESET_BUF = "TRUE";
+ parameter RX_EN_IDLE_RESET_FR = "TRUE";
+ parameter RX_EN_IDLE_RESET_PH = "TRUE";
+ parameter RX_EN_MODE_RESET_BUF = "TRUE";
+ parameter RX_EN_RATE_RESET_BUF = "TRUE";
+ parameter RX_EN_REALIGN_RESET_BUF = "FALSE";
+ parameter RX_EN_REALIGN_RESET_BUF2 = "FALSE";
+ parameter [7:0] RX_EYE_OFFSET = 8'h4C;
+ parameter [1:0] RX_EYE_SCANMODE = 2'b00;
+ parameter RX_FIFO_ADDR_MODE = "FULL";
+ parameter [3:0] RX_IDLE_HI_CNT = 4'b1000;
+ parameter [3:0] RX_IDLE_LO_CNT = 4'b0000;
+ parameter RX_LOSS_OF_SYNC_FSM = "FALSE";
+ parameter integer RX_LOS_INVALID_INCR = 1;
+ parameter integer RX_LOS_THRESHOLD = 4;
+ parameter RX_OVERSAMPLE_MODE = "FALSE";
+ parameter integer RX_SLIDE_AUTO_WAIT = 5;
+ parameter RX_SLIDE_MODE = "OFF";
+ parameter RX_XCLK_SEL = "RXREC";
+ parameter integer SAS_MAX_COMSAS = 52;
+ parameter integer SAS_MIN_COMSAS = 40;
+ parameter [2:0] SATA_BURST_VAL = 3'b100;
+ parameter [2:0] SATA_IDLE_VAL = 3'b100;
+ parameter integer SATA_MAX_BURST = 7;
+ parameter integer SATA_MAX_INIT = 22;
+ parameter integer SATA_MAX_WAKE = 7;
+ parameter integer SATA_MIN_BURST = 4;
+ parameter integer SATA_MIN_INIT = 12;
+ parameter integer SATA_MIN_WAKE = 4;
+ parameter SHOW_REALIGN_COMMA = "TRUE";
+ parameter integer SIM_GTXRESET_SPEEDUP = 1;
+ parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
+ parameter [2:0] SIM_RXREFCLK_SOURCE = 3'b000;
+ parameter [2:0] SIM_TXREFCLK_SOURCE = 3'b000;
+ parameter SIM_TX_ELEC_IDLE_LEVEL = "X";
+ parameter SIM_VERSION = "2.0";
+ parameter [4:0] TERMINATION_CTRL = 5'b10100;
+ parameter TERMINATION_OVRD = "FALSE";
+ parameter [11:0] TRANS_TIME_FROM_P2 = 12'h03C;
+ parameter [7:0] TRANS_TIME_NON_P2 = 8'h19;
+ parameter [7:0] TRANS_TIME_RATE = 8'h0E;
+ parameter [9:0] TRANS_TIME_TO_P2 = 10'h064;
+ parameter [31:0] TST_ATTR = 32'h00000000;
+ parameter TXDRIVE_LOOPBACK_HIZ = "FALSE";
+ parameter TXDRIVE_LOOPBACK_PD = "FALSE";
+ parameter TXGEARBOX_USE = "FALSE";
+ parameter TXOUTCLK_CTRL = "TXOUTCLKPCS";
+ parameter [9:0] TXOUTCLK_DLY = 10'b0000000000;
+ parameter [23:0] TXPLL_COM_CFG = 24'h21680A;
+ parameter [7:0] TXPLL_CP_CFG = 8'h00;
+ parameter integer TXPLL_DIVSEL45_FB = 5;
+ parameter integer TXPLL_DIVSEL_FB = 2;
+ parameter integer TXPLL_DIVSEL_OUT = 1;
+ parameter integer TXPLL_DIVSEL_REF = 1;
+ parameter [2:0] TXPLL_LKDET_CFG = 3'b111;
+ parameter [1:0] TXPLL_SATA = 2'b00;
+ parameter TX_BUFFER_USE = "TRUE";
+ parameter [5:0] TX_BYTECLK_CFG = 6'h00;
+ parameter integer TX_CLK25_DIVIDER = 6;
+ parameter TX_CLK_SOURCE = "RXPLL";
+ parameter integer TX_DATA_WIDTH = 20;
+ parameter [4:0] TX_DEEMPH_0 = 5'b11010;
+ parameter [4:0] TX_DEEMPH_1 = 5'b10000;
+ parameter [13:0] TX_DETECT_RX_CFG = 14'h1832;
+ parameter [3:0] TX_DLYALIGN_CTRINC = 4'b0100;
+ parameter [3:0] TX_DLYALIGN_LPFINC = 4'b0110;
+ parameter [2:0] TX_DLYALIGN_MONSEL = 3'b000;
+ parameter [7:0] TX_DLYALIGN_OVRDSETTING = 8'b10000000;
+ parameter TX_DRIVE_MODE = "DIRECT";
+ parameter TX_EN_RATE_RESET_BUF = "TRUE";
+ parameter [2:0] TX_IDLE_ASSERT_DELAY = 3'b100;
+ parameter [2:0] TX_IDLE_DEASSERT_DELAY = 3'b010;
+ parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110;
+ parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001;
+ parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101;
+ parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010;
+ parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000;
+ parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110;
+ parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100;
+ parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
+ parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
+ parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
+ parameter TX_OVERSAMPLE_MODE = "FALSE";
+ parameter [0:0] TX_PMADATA_OPT = 1'b0;
+ parameter [1:0] TX_TDCC_CFG = 2'b11;
+ parameter [5:0] TX_USRCLK_CFG = 6'h00;
+ parameter TX_XCLK_SEL = "TXUSR";
+ output COMFINISH;
+ output COMINITDET;
+ output COMSASDET;
+ output COMWAKEDET;
+ output DRDY;
+ output PHYSTATUS;
+ output RXBYTEISALIGNED;
+ output RXBYTEREALIGN;
+ output RXCHANBONDSEQ;
+ output RXCHANISALIGNED;
+ output RXCHANREALIGN;
+ output RXCOMMADET;
+ output RXDATAVALID;
+ output RXELECIDLE;
+ output RXHEADERVALID;
+ output RXOVERSAMPLEERR;
+ output RXPLLLKDET;
+ output RXPRBSERR;
+ output RXRATEDONE;
+ output RXRECCLK;
+ output RXRECCLKPCS;
+ output RXRESETDONE;
+ output RXSTARTOFSEQ;
+ output RXVALID;
+ output TXGEARBOXREADY;
+ output TXN;
+ output TXOUTCLK;
+ output TXOUTCLKPCS;
+ output TXP;
+ output TXPLLLKDET;
+ output TXRATEDONE;
+ output TXRESETDONE;
+ output [15:0] DRPDO;
+ output [1:0] MGTREFCLKFAB;
+ output [1:0] RXLOSSOFSYNC;
+ output [1:0] TXBUFSTATUS;
+ output [2:0] DFESENSCAL;
+ output [2:0] RXBUFSTATUS;
+ output [2:0] RXCLKCORCNT;
+ output [2:0] RXHEADER;
+ output [2:0] RXSTATUS;
+ output [31:0] RXDATA;
+ output [3:0] DFETAP3MONITOR;
+ output [3:0] DFETAP4MONITOR;
+ output [3:0] RXCHARISCOMMA;
+ output [3:0] RXCHARISK;
+ output [3:0] RXCHBONDO;
+ output [3:0] RXDISPERR;
+ output [3:0] RXNOTINTABLE;
+ output [3:0] RXRUNDISP;
+ output [3:0] TXKERR;
+ output [3:0] TXRUNDISP;
+ output [4:0] DFEEYEDACMON;
+ output [4:0] DFETAP1MONITOR;
+ output [4:0] DFETAP2MONITOR;
+ output [5:0] DFECLKDLYADJMON;
+ output [7:0] RXDLYALIGNMONITOR;
+ output [7:0] TXDLYALIGNMONITOR;
+ output [9:0] TSTOUT;
+ input DCLK;
+ input DEN;
+ input DFEDLYOVRD;
+ input DFETAPOVRD;
+ input DWE;
+ input GATERXELECIDLE;
+ input GREFCLKRX;
+ input GREFCLKTX;
+ input GTXRXRESET;
+ input GTXTXRESET;
+ input IGNORESIGDET;
+ input PERFCLKRX;
+ input PERFCLKTX;
+ input PLLRXRESET;
+ input PLLTXRESET;
+ input PRBSCNTRESET;
+ input RXBUFRESET;
+ input RXCDRRESET;
+ input RXCHBONDMASTER;
+ input RXCHBONDSLAVE;
+ input RXCOMMADETUSE;
+ input RXDEC8B10BUSE;
+ input RXDLYALIGNDISABLE;
+ input RXDLYALIGNMONENB;
+ input RXDLYALIGNOVERRIDE;
+ input RXDLYALIGNRESET;
+ input RXDLYALIGNSWPPRECURB;
+ input RXDLYALIGNUPDSW;
+ input RXENCHANSYNC;
+ input RXENMCOMMAALIGN;
+ input RXENPCOMMAALIGN;
+ input RXENPMAPHASEALIGN;
+ input RXENSAMPLEALIGN;
+ input RXGEARBOXSLIP;
+ input RXN;
+ input RXP;
+ input RXPLLLKDETEN;
+ input RXPLLPOWERDOWN;
+ input RXPMASETPHASE;
+ input RXPOLARITY;
+ input RXRESET;
+ input RXSLIDE;
+ input RXUSRCLK2;
+ input RXUSRCLK;
+ input TSTCLK0;
+ input TSTCLK1;
+ input TXCOMINIT;
+ input TXCOMSAS;
+ input TXCOMWAKE;
+ input TXDEEMPH;
+ input TXDETECTRX;
+ input TXDLYALIGNDISABLE;
+ input TXDLYALIGNMONENB;
+ input TXDLYALIGNOVERRIDE;
+ input TXDLYALIGNRESET;
+ input TXDLYALIGNUPDSW;
+ input TXELECIDLE;
+ input TXENC8B10BUSE;
+ input TXENPMAPHASEALIGN;
+ input TXINHIBIT;
+ input TXPDOWNASYNCH;
+ input TXPLLLKDETEN;
+ input TXPLLPOWERDOWN;
+ input TXPMASETPHASE;
+ input TXPOLARITY;
+ input TXPRBSFORCEERR;
+ input TXRESET;
+ input TXSTARTSEQ;
+ input TXSWING;
+ input TXUSRCLK2;
+ input TXUSRCLK;
+ input USRCODEERR;
+ input [12:0] GTXTEST;
+ input [15:0] DI;
+ input [19:0] TSTIN;
+ input [1:0] MGTREFCLKRX;
+ input [1:0] MGTREFCLKTX;
+ input [1:0] NORTHREFCLKRX;
+ input [1:0] NORTHREFCLKTX;
+ input [1:0] RXPOWERDOWN;
+ input [1:0] RXRATE;
+ input [1:0] SOUTHREFCLKRX;
+ input [1:0] SOUTHREFCLKTX;
+ input [1:0] TXPOWERDOWN;
+ input [1:0] TXRATE;
+ input [2:0] LOOPBACK;
+ input [2:0] RXCHBONDLEVEL;
+ input [2:0] RXENPRBSTST;
+ input [2:0] RXPLLREFSELDY;
+ input [2:0] TXBUFDIFFCTRL;
+ input [2:0] TXENPRBSTST;
+ input [2:0] TXHEADER;
+ input [2:0] TXMARGIN;
+ input [2:0] TXPLLREFSELDY;
+ input [31:0] TXDATA;
+ input [3:0] DFETAP3;
+ input [3:0] DFETAP4;
+ input [3:0] RXCHBONDI;
+ input [3:0] TXBYPASS8B10B;
+ input [3:0] TXCHARDISPMODE;
+ input [3:0] TXCHARDISPVAL;
+ input [3:0] TXCHARISK;
+ input [3:0] TXDIFFCTRL;
+ input [3:0] TXPREEMPHASIS;
+ input [4:0] DFETAP1;
+ input [4:0] DFETAP2;
+ input [4:0] TXPOSTEMPHASIS;
+ input [5:0] DFECLKDLYADJ;
+ input [6:0] TXSEQUENCE;
+ input [7:0] DADDR;
+ input [9:0] RXEQMIX;
+endmodule
+
+module IBUFDS (...);
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_DELAY_VALUE = "0";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IFD_DELAY_VALUE = "AUTO";
+ parameter IOSTANDARD = "DEFAULT";
+ output O;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+endmodule
+
+module IBUFDS_DIFF_OUT (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ output O;
+ output OB;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+endmodule
+
+module IBUFDS_GTHE1 (...);
+ output O;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+endmodule
+
+module IBUFG (...);
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter IBUF_DELAY_VALUE = "0";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ output O;
+ (* iopad_external_pin *)
+ input I;
+endmodule
+
+module IBUFGDS (...);
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter DIFF_TERM = "FALSE";
+ parameter IBUF_DELAY_VALUE = "0";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ output O;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+endmodule
+
+module IBUFGDS_DIFF_OUT (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ output O;
+ output OB;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+endmodule
+
+(* keep *)
+module IDELAYCTRL (...);
+ parameter SIM_DEVICE = "7SERIES";
+ output RDY;
+ (* clkbuf_sink *)
+ input REFCLK;
+ input RST;
+endmodule
+
+module IOBUF (...);
+ parameter integer DRIVE = 12;
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SLEW = "SLOW";
+ output O;
+ (* iopad_external_pin *)
+ inout IO;
+ input I;
+ input T;
+endmodule
+
+module IOBUFDS (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SLEW = "SLOW";
+ output O;
+ (* iopad_external_pin *)
+ inout IO;
+ inout IOB;
+ input I;
+ input T;
+endmodule
+
+module IODELAYE1 (...);
+ parameter CINVCTRL_SEL = "FALSE";
+ parameter DELAY_SRC = "I";
+ parameter HIGH_PERFORMANCE_MODE = "FALSE";
+ parameter IDELAY_TYPE = "DEFAULT";
+ parameter integer IDELAY_VALUE = 0;
+ parameter ODELAY_TYPE = "FIXED";
+ parameter integer ODELAY_VALUE = 0;
+ parameter real REFCLK_FREQUENCY = 200.0;
+ parameter SIGNAL_PATTERN = "DATA";
+ output [4:0] CNTVALUEOUT;
+ output DATAOUT;
+ (* clkbuf_sink *)
+ input C;
+ input CE;
+ input CINVCTRL;
+ input CLKIN;
+ input [4:0] CNTVALUEIN;
+ input DATAIN;
+ input IDATAIN;
+ input INC;
+ input ODATAIN;
+ input RST;
+ input T;
+endmodule
+
+module ISERDESE1 (...);
+ parameter DATA_RATE = "DDR";
+ parameter integer DATA_WIDTH = 4;
+ parameter DYN_CLKDIV_INV_EN = "FALSE";
+ parameter DYN_CLK_INV_EN = "FALSE";
+ parameter [0:0] INIT_Q1 = 1'b0;
+ parameter [0:0] INIT_Q2 = 1'b0;
+ parameter [0:0] INIT_Q3 = 1'b0;
+ parameter [0:0] INIT_Q4 = 1'b0;
+ parameter INTERFACE_TYPE = "MEMORY";
+ parameter integer NUM_CE = 2;
+ parameter IOBDELAY = "NONE";
+ parameter OFB_USED = "FALSE";
+ parameter SERDES_MODE = "MASTER";
+ parameter [0:0] SRVAL_Q1 = 1'b0;
+ parameter [0:0] SRVAL_Q2 = 1'b0;
+ parameter [0:0] SRVAL_Q3 = 1'b0;
+ parameter [0:0] SRVAL_Q4 = 1'b0;
+ output O;
+ output Q1;
+ output Q2;
+ output Q3;
+ output Q4;
+ output Q5;
+ output Q6;
+ output SHIFTOUT1;
+ output SHIFTOUT2;
+ input BITSLIP;
+ input CE1;
+ input CE2;
+ (* clkbuf_sink *)
+ input CLK;
+ (* clkbuf_sink *)
+ input CLKB;
+ (* clkbuf_sink *)
+ input CLKDIV;
+ input D;
+ input DDLY;
+ input DYNCLKDIVSEL;
+ input DYNCLKSEL;
+ (* clkbuf_sink *)
+ input OCLK;
+ input OFB;
+ input RST;
+ input SHIFTIN1;
+ input SHIFTIN2;
+endmodule
+
+module KEEPER (...);
+ inout O;
+endmodule
+
+module OBUFDS (...);
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SLEW = "SLOW";
+ (* iopad_external_pin *)
+ output O;
+ (* iopad_external_pin *)
+ output OB;
+ input I;
+endmodule
+
+module OBUFT (...);
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter integer DRIVE = 12;
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SLEW = "SLOW";
+ (* iopad_external_pin *)
+ output O;
+ input I;
+ input T;
+endmodule
+
+module OBUFTDS (...);
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SLEW = "SLOW";
+ (* iopad_external_pin *)
+ output O;
+ (* iopad_external_pin *)
+ output OB;
+ input I;
+ input T;
+endmodule
+
+module OSERDESE1 (...);
+ parameter DATA_RATE_OQ = "DDR";
+ parameter DATA_RATE_TQ = "DDR";
+ parameter integer DATA_WIDTH = 4;
+ parameter integer DDR3_DATA = 1;
+ parameter [0:0] INIT_OQ = 1'b0;
+ parameter [0:0] INIT_TQ = 1'b0;
+ parameter INTERFACE_TYPE = "DEFAULT";
+ parameter integer ODELAY_USED = 0;
+ parameter SERDES_MODE = "MASTER";
+ parameter [0:0] SRVAL_OQ = 1'b0;
+ parameter [0:0] SRVAL_TQ = 1'b0;
+ parameter integer TRISTATE_WIDTH = 4;
+ output OCBEXTEND;
+ output OFB;
+ output OQ;
+ output SHIFTOUT1;
+ output SHIFTOUT2;
+ output TFB;
+ output TQ;
+ (* clkbuf_sink *)
+ input CLK;
+ (* clkbuf_sink *)
+ input CLKDIV;
+ input CLKPERF;
+ input CLKPERFDELAY;
+ input D1;
+ input D2;
+ input D3;
+ input D4;
+ input D5;
+ input D6;
+ input OCE;
+ input ODV;
+ input RST;
+ input SHIFTIN1;
+ input SHIFTIN2;
+ input T1;
+ input T2;
+ input T3;
+ input T4;
+ input TCE;
+ input WC;
+endmodule
+
+module PULLDOWN (...);
+ output O;
+endmodule
+
+module PULLUP (...);
+ output O;
+endmodule
+
+module TEMAC_SINGLE (...);
+ parameter EMAC_1000BASEX_ENABLE = "FALSE";
+ parameter EMAC_ADDRFILTER_ENABLE = "FALSE";
+ parameter EMAC_BYTEPHY = "FALSE";
+ parameter EMAC_CTRLLENCHECK_DISABLE = "FALSE";
+ parameter [0:7] EMAC_DCRBASEADDR = 8'h00;
+ parameter EMAC_GTLOOPBACK = "FALSE";
+ parameter EMAC_HOST_ENABLE = "FALSE";
+ parameter [8:0] EMAC_LINKTIMERVAL = 9'h000;
+ parameter EMAC_LTCHECK_DISABLE = "FALSE";
+ parameter EMAC_MDIO_ENABLE = "FALSE";
+ parameter EMAC_MDIO_IGNORE_PHYADZERO = "FALSE";
+ parameter [47:0] EMAC_PAUSEADDR = 48'h000000000000;
+ parameter EMAC_PHYINITAUTONEG_ENABLE = "FALSE";
+ parameter EMAC_PHYISOLATE = "FALSE";
+ parameter EMAC_PHYLOOPBACKMSB = "FALSE";
+ parameter EMAC_PHYPOWERDOWN = "FALSE";
+ parameter EMAC_PHYRESET = "FALSE";
+ parameter EMAC_RGMII_ENABLE = "FALSE";
+ parameter EMAC_RX16BITCLIENT_ENABLE = "FALSE";
+ parameter EMAC_RXFLOWCTRL_ENABLE = "FALSE";
+ parameter EMAC_RXHALFDUPLEX = "FALSE";
+ parameter EMAC_RXINBANDFCS_ENABLE = "FALSE";
+ parameter EMAC_RXJUMBOFRAME_ENABLE = "FALSE";
+ parameter EMAC_RXRESET = "FALSE";
+ parameter EMAC_RXVLAN_ENABLE = "FALSE";
+ parameter EMAC_RX_ENABLE = "TRUE";
+ parameter EMAC_SGMII_ENABLE = "FALSE";
+ parameter EMAC_SPEED_LSB = "FALSE";
+ parameter EMAC_SPEED_MSB = "FALSE";
+ parameter EMAC_TX16BITCLIENT_ENABLE = "FALSE";
+ parameter EMAC_TXFLOWCTRL_ENABLE = "FALSE";
+ parameter EMAC_TXHALFDUPLEX = "FALSE";
+ parameter EMAC_TXIFGADJUST_ENABLE = "FALSE";
+ parameter EMAC_TXINBANDFCS_ENABLE = "FALSE";
+ parameter EMAC_TXJUMBOFRAME_ENABLE = "FALSE";
+ parameter EMAC_TXRESET = "FALSE";
+ parameter EMAC_TXVLAN_ENABLE = "FALSE";
+ parameter EMAC_TX_ENABLE = "TRUE";
+ parameter [47:0] EMAC_UNICASTADDR = 48'h000000000000;
+ parameter EMAC_UNIDIRECTION_ENABLE = "FALSE";
+ parameter EMAC_USECLKEN = "FALSE";
+ parameter SIM_VERSION = "1.0";
+ output DCRHOSTDONEIR;
+ output EMACCLIENTANINTERRUPT;
+ output EMACCLIENTRXBADFRAME;
+ output EMACCLIENTRXCLIENTCLKOUT;
+ output EMACCLIENTRXDVLD;
+ output EMACCLIENTRXDVLDMSW;
+ output EMACCLIENTRXFRAMEDROP;
+ output EMACCLIENTRXGOODFRAME;
+ output EMACCLIENTRXSTATSBYTEVLD;
+ output EMACCLIENTRXSTATSVLD;
+ output EMACCLIENTTXACK;
+ output EMACCLIENTTXCLIENTCLKOUT;
+ output EMACCLIENTTXCOLLISION;
+ output EMACCLIENTTXRETRANSMIT;
+ output EMACCLIENTTXSTATS;
+ output EMACCLIENTTXSTATSBYTEVLD;
+ output EMACCLIENTTXSTATSVLD;
+ output EMACDCRACK;
+ output EMACPHYENCOMMAALIGN;
+ output EMACPHYLOOPBACKMSB;
+ output EMACPHYMCLKOUT;
+ output EMACPHYMDOUT;
+ output EMACPHYMDTRI;
+ output EMACPHYMGTRXRESET;
+ output EMACPHYMGTTXRESET;
+ output EMACPHYPOWERDOWN;
+ output EMACPHYSYNCACQSTATUS;
+ output EMACPHYTXCHARDISPMODE;
+ output EMACPHYTXCHARDISPVAL;
+ output EMACPHYTXCHARISK;
+ output EMACPHYTXCLK;
+ output EMACPHYTXEN;
+ output EMACPHYTXER;
+ output EMACPHYTXGMIIMIICLKOUT;
+ output EMACSPEEDIS10100;
+ output HOSTMIIMRDY;
+ output [0:31] EMACDCRDBUS;
+ output [15:0] EMACCLIENTRXD;
+ output [31:0] HOSTRDDATA;
+ output [6:0] EMACCLIENTRXSTATS;
+ output [7:0] EMACPHYTXD;
+ input CLIENTEMACDCMLOCKED;
+ input CLIENTEMACPAUSEREQ;
+ input CLIENTEMACRXCLIENTCLKIN;
+ input CLIENTEMACTXCLIENTCLKIN;
+ input CLIENTEMACTXDVLD;
+ input CLIENTEMACTXDVLDMSW;
+ input CLIENTEMACTXFIRSTBYTE;
+ input CLIENTEMACTXUNDERRUN;
+ input DCREMACCLK;
+ input DCREMACENABLE;
+ input DCREMACREAD;
+ input DCREMACWRITE;
+ input HOSTCLK;
+ input HOSTMIIMSEL;
+ input HOSTREQ;
+ input PHYEMACCOL;
+ input PHYEMACCRS;
+ input PHYEMACGTXCLK;
+ input PHYEMACMCLKIN;
+ input PHYEMACMDIN;
+ input PHYEMACMIITXCLK;
+ input PHYEMACRXCHARISCOMMA;
+ input PHYEMACRXCHARISK;
+ input PHYEMACRXCLK;
+ input PHYEMACRXDISPERR;
+ input PHYEMACRXDV;
+ input PHYEMACRXER;
+ input PHYEMACRXNOTINTABLE;
+ input PHYEMACRXRUNDISP;
+ input PHYEMACSIGNALDET;
+ input PHYEMACTXBUFERR;
+ input PHYEMACTXGMIIMIICLKIN;
+ input RESET;
+ input [0:31] DCREMACDBUS;
+ input [0:9] DCREMACABUS;
+ input [15:0] CLIENTEMACPAUSEVAL;
+ input [15:0] CLIENTEMACTXD;
+ input [1:0] HOSTOPCODE;
+ input [1:0] PHYEMACRXBUFSTATUS;
+ input [2:0] PHYEMACRXCLKCORCNT;
+ input [31:0] HOSTWRDATA;
+ input [4:0] PHYEMACPHYAD;
+ input [7:0] CLIENTEMACTXIFGDELAY;
+ input [7:0] PHYEMACRXD;
+ input [9:0] HOSTADDR;
+endmodule
+
+module FIFO18E1 (...);
+ parameter ALMOST_EMPTY_OFFSET = 13'h0080;
+ parameter ALMOST_FULL_OFFSET = 13'h0080;
+ parameter integer DATA_WIDTH = 4;
+ parameter integer DO_REG = 1;
+ parameter EN_SYN = "FALSE";
+ parameter FIFO_MODE = "FIFO18";
+ parameter FIRST_WORD_FALL_THROUGH = "FALSE";
+ parameter INIT = 36'h0;
+ parameter SIM_DEVICE = "VIRTEX6";
+ parameter SRVAL = 36'h0;
+ parameter IS_RDCLK_INVERTED = 1'b0;
+ parameter IS_RDEN_INVERTED = 1'b0;
+ parameter IS_RSTREG_INVERTED = 1'b0;
+ parameter IS_RST_INVERTED = 1'b0;
+ parameter IS_WRCLK_INVERTED = 1'b0;
+ parameter IS_WREN_INVERTED = 1'b0;
+ output ALMOSTEMPTY;
+ output ALMOSTFULL;
+ output [31:0] DO;
+ output [3:0] DOP;
+ output EMPTY;
+ output FULL;
+ output [11:0] RDCOUNT;
+ output RDERR;
+ output [11:0] WRCOUNT;
+ output WRERR;
+ input [31:0] DI;
+ input [3:0] DIP;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_RDCLK_INVERTED" *)
+ input RDCLK;
+ (* invertible_pin = "IS_RDEN_INVERTED" *)
+ input RDEN;
+ input REGCE;
+ (* invertible_pin = "IS_RST_INVERTED" *)
+ input RST;
+ (* invertible_pin = "IS_RSTREG_INVERTED" *)
+ input RSTREG;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WRCLK_INVERTED" *)
+ input WRCLK;
+ (* invertible_pin = "IS_WREN_INVERTED" *)
+ input WREN;
+endmodule
+
+module FIFO36E1 (...);
+ parameter ALMOST_EMPTY_OFFSET = 13'h0080;
+ parameter ALMOST_FULL_OFFSET = 13'h0080;
+ parameter integer DATA_WIDTH = 4;
+ parameter integer DO_REG = 1;
+ parameter EN_ECC_READ = "FALSE";
+ parameter EN_ECC_WRITE = "FALSE";
+ parameter EN_SYN = "FALSE";
+ parameter FIFO_MODE = "FIFO36";
+ parameter FIRST_WORD_FALL_THROUGH = "FALSE";
+ parameter INIT = 72'h0;
+ parameter SIM_DEVICE = "VIRTEX6";
+ parameter SRVAL = 72'h0;
+ parameter IS_RDCLK_INVERTED = 1'b0;
+ parameter IS_RDEN_INVERTED = 1'b0;
+ parameter IS_RSTREG_INVERTED = 1'b0;
+ parameter IS_RST_INVERTED = 1'b0;
+ parameter IS_WRCLK_INVERTED = 1'b0;
+ parameter IS_WREN_INVERTED = 1'b0;
+ output ALMOSTEMPTY;
+ output ALMOSTFULL;
+ output DBITERR;
+ output [63:0] DO;
+ output [7:0] DOP;
+ output [7:0] ECCPARITY;
+ output EMPTY;
+ output FULL;
+ output [12:0] RDCOUNT;
+ output RDERR;
+ output SBITERR;
+ output [12:0] WRCOUNT;
+ output WRERR;
+ input [63:0] DI;
+ input [7:0] DIP;
+ input INJECTDBITERR;
+ input INJECTSBITERR;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_RDCLK_INVERTED" *)
+ input RDCLK;
+ (* invertible_pin = "IS_RDEN_INVERTED" *)
+ input RDEN;
+ input REGCE;
+ (* invertible_pin = "IS_RST_INVERTED" *)
+ input RST;
+ (* invertible_pin = "IS_RSTREG_INVERTED" *)
+ input RSTREG;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WRCLK_INVERTED" *)
+ input WRCLK;
+ (* invertible_pin = "IS_WREN_INVERTED" *)
+ input WREN;
+endmodule
+
+module RAM128X1S (...);
+ parameter [127:0] INIT = 128'h00000000000000000000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input A5;
+ input A6;
+ input D;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM256X1S (...);
+ parameter [255:0] INIT = 256'h0;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O;
+ input [7:0] A;
+ input D;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM32M (...);
+ parameter [63:0] INIT_A = 64'h0000000000000000;
+ parameter [63:0] INIT_B = 64'h0000000000000000;
+ parameter [63:0] INIT_C = 64'h0000000000000000;
+ parameter [63:0] INIT_D = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output [1:0] DOA;
+ output [1:0] DOB;
+ output [1:0] DOC;
+ output [1:0] DOD;
+ input [4:0] ADDRA;
+ input [4:0] ADDRB;
+ input [4:0] ADDRC;
+ input [4:0] ADDRD;
+ input [1:0] DIA;
+ input [1:0] DIB;
+ input [1:0] DIC;
+ input [1:0] DID;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM32X1S (...);
+ parameter [31:0] INIT = 32'h00000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input D;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM32X1S_1 (...);
+ parameter [31:0] INIT = 32'h00000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input D;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM32X2S (...);
+ parameter [31:0] INIT_00 = 32'h00000000;
+ parameter [31:0] INIT_01 = 32'h00000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O0;
+ output O1;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input D0;
+ input D1;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM64M (...);
+ parameter [63:0] INIT_A = 64'h0000000000000000;
+ parameter [63:0] INIT_B = 64'h0000000000000000;
+ parameter [63:0] INIT_C = 64'h0000000000000000;
+ parameter [63:0] INIT_D = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output DOA;
+ output DOB;
+ output DOC;
+ output DOD;
+ input [5:0] ADDRA;
+ input [5:0] ADDRB;
+ input [5:0] ADDRC;
+ input [5:0] ADDRD;
+ input DIA;
+ input DIB;
+ input DIC;
+ input DID;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM64X1S (...);
+ parameter [63:0] INIT = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input A5;
+ input D;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM64X1S_1 (...);
+ parameter [63:0] INIT = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input A5;
+ input D;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM64X2S (...);
+ parameter [63:0] INIT_00 = 64'h0000000000000000;
+ parameter [63:0] INIT_01 = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O0;
+ output O1;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input A5;
+ input D0;
+ input D1;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module ROM128X1 (...);
+ parameter [127:0] INIT = 128'h00000000000000000000000000000000;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input A5;
+ input A6;
+endmodule
+
+module ROM256X1 (...);
+ parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input A5;
+ input A6;
+ input A7;
+endmodule
+
+module ROM32X1 (...);
+ parameter [31:0] INIT = 32'h00000000;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+endmodule
+
+module ROM64X1 (...);
+ parameter [63:0] INIT = 64'h0000000000000000;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input A5;
+endmodule
+
+module IDDR (...);
+ parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
+ parameter INIT_Q1 = 1'b0;
+ parameter INIT_Q2 = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter SRTYPE = "SYNC";
+ parameter MSGON = "TRUE";
+ parameter XON = "TRUE";
+ output Q1;
+ output Q2;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C;
+ input CE;
+ (* invertible_pin = "IS_D_INVERTED" *)
+ input D;
+ input R;
+ input S;
+endmodule
+
+module IDDR_2CLK (...);
+ parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
+ parameter INIT_Q1 = 1'b0;
+ parameter INIT_Q2 = 1'b0;
+ parameter [0:0] IS_CB_INVERTED = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter SRTYPE = "SYNC";
+ output Q1;
+ output Q2;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CB_INVERTED" *)
+ input CB;
+ input CE;
+ (* invertible_pin = "IS_D_INVERTED" *)
+ input D;
+ input R;
+ input S;
+endmodule
+
+module LDCE (...);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_CLR_INVERTED = 1'b0;
+ parameter [0:0] IS_G_INVERTED = 1'b0;
+ parameter MSGON = "TRUE";
+ parameter XON = "TRUE";
+ output Q;
+ (* invertible_pin = "IS_CLR_INVERTED" *)
+ input CLR;
+ input D;
+ (* invertible_pin = "IS_G_INVERTED" *)
+ input G;
+ input GE;
+endmodule
+
+module LDPE (...);
+ parameter [0:0] INIT = 1'b1;
+ parameter [0:0] IS_G_INVERTED = 1'b0;
+ parameter [0:0] IS_PRE_INVERTED = 1'b0;
+ parameter MSGON = "TRUE";
+ parameter XON = "TRUE";
+ output Q;
+ input D;
+ (* invertible_pin = "IS_G_INVERTED" *)
+ input G;
+ input GE;
+ (* invertible_pin = "IS_PRE_INVERTED" *)
+ input PRE;
+endmodule
+
+module ODDR (...);
+ parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
+ parameter INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D1_INVERTED = 1'b0;
+ parameter [0:0] IS_D2_INVERTED = 1'b0;
+ parameter SRTYPE = "SYNC";
+ parameter MSGON = "TRUE";
+ parameter XON = "TRUE";
+ output Q;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C;
+ input CE;
+ (* invertible_pin = "IS_D1_INVERTED" *)
+ input D1;
+ (* invertible_pin = "IS_D2_INVERTED" *)
+ input D2;
+ input R;
+ input S;
+endmodule
+
+module CFGLUT5 (...);
+ parameter [31:0] INIT = 32'h00000000;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ output CDO;
+ output O5;
+ output O6;
+ input I4;
+ input I3;
+ input I2;
+ input I1;
+ input I0;
+ input CDI;
+ input CE;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLK_INVERTED" *)
+ input CLK;
+endmodule
+
diff --git a/techlibs/xilinx/xc7_brams_bb.v b/techlibs/xilinx/xc7_brams_bb.v
index 0e8cb406c..a28ba5b14 100644
--- a/techlibs/xilinx/xc7_brams_bb.v
+++ b/techlibs/xilinx/xc7_brams_bb.v
@@ -1,15 +1,25 @@
// Max delays from https://github.com/SymbiFlow/prjxray-db/blob/f8e0364116b2983ac72a3dc8c509ea1cc79e2e3d/artix7/timings/BRAM_L.sdf#L138-L147
module RAMB18E1 (
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
input CLKARDCLK,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
input CLKBWRCLK,
+ (* invertible_pin = "IS_ENARDEN_INVERTED" *)
input ENARDEN,
+ (* invertible_pin = "IS_ENBWREN_INVERTED" *)
input ENBWREN,
input REGCEAREGCE,
input REGCEB,
+ (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
input RSTRAMARSTRAM,
+ (* invertible_pin = "IS_RSTRAMB_INVERTED" *)
input RSTRAMB,
+ (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
input RSTREGARSTREG,
+ (* invertible_pin = "IS_RSTREGB_INVERTED" *)
input RSTREGB,
input [13:0] ADDRARDADDR,
@@ -21,10 +31,14 @@ module RAMB18E1 (
input [1:0] WEA,
input [3:0] WEBWE,
- (* abc_arrival=2454 *) output [15:0] DOADO,
- (* abc_arrival=2454 *) output [15:0] DOBDO,
- (* abc_arrival=2454 *) output [1:0] DOPADOP,
- (* abc_arrival=2454 *) output [1:0] DOPBDOP
+ (* abc_arrival=2454 *)
+ output [15:0] DOADO,
+ (* abc_arrival=2454 *)
+ output [15:0] DOBDO,
+ (* abc_arrival=2454 *)
+ output [1:0] DOPADOP,
+ (* abc_arrival=2454 *)
+ output [1:0] DOPBDOP
);
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@@ -125,15 +139,25 @@ module RAMB18E1 (
endmodule
module RAMB36E1 (
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
input CLKARDCLK,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
input CLKBWRCLK,
+ (* invertible_pin = "IS_ENARDEN_INVERTED" *)
input ENARDEN,
+ (* invertible_pin = "IS_ENBWREN_INVERTED" *)
input ENBWREN,
input REGCEAREGCE,
input REGCEB,
+ (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
input RSTRAMARSTRAM,
+ (* invertible_pin = "IS_RSTRAMB_INVERTED" *)
input RSTRAMB,
+ (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
input RSTREGARSTREG,
+ (* invertible_pin = "IS_RSTREGB_INVERTED" *)
input RSTREGB,
input [15:0] ADDRARDADDR,
@@ -145,10 +169,14 @@ module RAMB36E1 (
input [3:0] WEA,
input [7:0] WEBWE,
- (* abc_arrival=2454 *) output [31:0] DOADO,
- (* abc_arrival=2454 *) output [31:0] DOBDO,
- (* abc_arrival=2454 *) output [3:0] DOPADOP,
- (* abc_arrival=2454 *) output [3:0] DOPBDOP
+ (* abc_arrival=2454 *)
+ output [31:0] DOADO,
+ (* abc_arrival=2454 *)
+ output [31:0] DOBDO,
+ (* abc_arrival=2454 *)
+ output [3:0] DOPADOP,
+ (* abc_arrival=2454 *)
+ output [3:0] DOPBDOP
);
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/xc7_cells_xtra.v
similarity index 60%
rename from techlibs/xilinx/cells_xtra.v
rename to techlibs/xilinx/xc7_cells_xtra.v
index 15fa1b63a..817932e9f 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/xc7_cells_xtra.v
@@ -1,298 +1,4 @@
-// Created by cells_xtra.sh from Xilinx models
-
-module BSCANE2 (...);
- parameter DISABLE_JTAG = "FALSE";
- parameter integer JTAG_CHAIN = 1;
- output CAPTURE;
- output DRCK;
- output RESET;
- output RUNTEST;
- output SEL;
- output SHIFT;
- output TCK;
- output TDI;
- output TMS;
- output UPDATE;
- input TDO;
-endmodule
-
-module BUFGCE (...);
- parameter CE_TYPE = "SYNC";
- parameter [0:0] IS_CE_INVERTED = 1'b0;
- parameter [0:0] IS_I_INVERTED = 1'b0;
- output O;
- input CE;
- input I;
-endmodule
-
-module BUFGCE_1 (...);
- output O;
- input CE, I;
-endmodule
-
-module BUFGMUX (...);
- parameter CLK_SEL_TYPE = "SYNC";
- output O;
- input I0, I1, S;
-endmodule
-
-module BUFGMUX_1 (...);
- parameter CLK_SEL_TYPE = "SYNC";
- output O;
- input I0, I1, S;
-endmodule
-
-module BUFGMUX_CTRL (...);
- output O;
- input I0;
- input I1;
- input S;
-endmodule
-
-module BUFH (...);
- output O;
- input I;
-endmodule
-
-module BUFIO (...);
- output O;
- input I;
-endmodule
-
-module BUFMR (...);
- output O;
- input I;
-endmodule
-
-module BUFMRCE (...);
- parameter CE_TYPE = "SYNC";
- parameter integer INIT_OUT = 0;
- parameter [0:0] IS_CE_INVERTED = 1'b0;
- output O;
- input CE;
- input I;
-endmodule
-
-module BUFR (...);
- output O;
- input CE;
- input CLR;
- input I;
- parameter BUFR_DIVIDE = "BYPASS";
- parameter SIM_DEVICE = "7SERIES";
-endmodule
-
-(* keep *)
-module CAPTUREE2 (...);
- parameter ONESHOT = "TRUE";
- input CAP;
- input CLK;
-endmodule
-
-module CFGLUT5 (...);
- parameter [31:0] INIT = 32'h00000000;
- parameter [0:0] IS_CLK_INVERTED = 1'b0;
- output CDO;
- output O5;
- output O6;
- input I4, I3, I2, I1, I0;
- input CDI, CE, CLK;
-endmodule
-
-(* keep *)
-module DCIRESET (...);
- output LOCKED;
- input RST;
-endmodule
-
-module DNA_PORT (...);
- parameter [56:0] SIM_DNA_VALUE = 57'h0;
- output DOUT;
- input CLK, DIN, READ, SHIFT;
-endmodule
-
-module DSP48E1 (...);
- parameter integer ACASCREG = 1;
- parameter integer ADREG = 1;
- parameter integer ALUMODEREG = 1;
- parameter integer AREG = 1;
- parameter AUTORESET_PATDET = "NO_RESET";
- parameter A_INPUT = "DIRECT";
- parameter integer BCASCREG = 1;
- parameter integer BREG = 1;
- parameter B_INPUT = "DIRECT";
- parameter integer CARRYINREG = 1;
- parameter integer CARRYINSELREG = 1;
- parameter integer CREG = 1;
- parameter integer DREG = 1;
- parameter integer INMODEREG = 1;
- parameter integer MREG = 1;
- parameter integer OPMODEREG = 1;
- parameter integer PREG = 1;
- parameter SEL_MASK = "MASK";
- parameter SEL_PATTERN = "PATTERN";
- parameter USE_DPORT = "FALSE";
- parameter USE_MULT = "MULTIPLY";
- parameter USE_PATTERN_DETECT = "NO_PATDET";
- parameter USE_SIMD = "ONE48";
- parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
- parameter [47:0] PATTERN = 48'h000000000000;
- parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
- parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
- parameter [0:0] IS_CLK_INVERTED = 1'b0;
- parameter [4:0] IS_INMODE_INVERTED = 5'b0;
- parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
- output [29:0] ACOUT;
- output [17:0] BCOUT;
- output CARRYCASCOUT;
- output [3:0] CARRYOUT;
- output MULTSIGNOUT;
- output OVERFLOW;
- output [47:0] P;
- output PATTERNBDETECT;
- output PATTERNDETECT;
- output [47:0] PCOUT;
- output UNDERFLOW;
- input [29:0] A;
- input [29:0] ACIN;
- input [3:0] ALUMODE;
- input [17:0] B;
- input [17:0] BCIN;
- input [47:0] C;
- input CARRYCASCIN;
- input CARRYIN;
- input [2:0] CARRYINSEL;
- input CEA1;
- input CEA2;
- input CEAD;
- input CEALUMODE;
- input CEB1;
- input CEB2;
- input CEC;
- input CECARRYIN;
- input CECTRL;
- input CED;
- input CEINMODE;
- input CEM;
- input CEP;
- input CLK;
- input [24:0] D;
- input [4:0] INMODE;
- input MULTSIGNIN;
- input [6:0] OPMODE;
- input [47:0] PCIN;
- input RSTA;
- input RSTALLCARRYIN;
- input RSTALUMODE;
- input RSTB;
- input RSTC;
- input RSTCTRL;
- input RSTD;
- input RSTINMODE;
- input RSTM;
- input RSTP;
-endmodule
-
-module EFUSE_USR (...);
- parameter [31:0] SIM_EFUSE_VALUE = 32'h00000000;
- output [31:0] EFUSEUSR;
-endmodule
-
-module FIFO18E1 (...);
- parameter ALMOST_EMPTY_OFFSET = 13'h0080;
- parameter ALMOST_FULL_OFFSET = 13'h0080;
- parameter integer DATA_WIDTH = 4;
- parameter integer DO_REG = 1;
- parameter EN_SYN = "FALSE";
- parameter FIFO_MODE = "FIFO18";
- parameter FIRST_WORD_FALL_THROUGH = "FALSE";
- parameter INIT = 36'h0;
- parameter SIM_DEVICE = "VIRTEX6";
- parameter SRVAL = 36'h0;
- parameter IS_RDCLK_INVERTED = 1'b0;
- parameter IS_RDEN_INVERTED = 1'b0;
- parameter IS_RSTREG_INVERTED = 1'b0;
- parameter IS_RST_INVERTED = 1'b0;
- parameter IS_WRCLK_INVERTED = 1'b0;
- parameter IS_WREN_INVERTED = 1'b0;
- output ALMOSTEMPTY;
- output ALMOSTFULL;
- output [31:0] DO;
- output [3:0] DOP;
- output EMPTY;
- output FULL;
- output [11:0] RDCOUNT;
- output RDERR;
- output [11:0] WRCOUNT;
- output WRERR;
- input [31:0] DI;
- input [3:0] DIP;
- input RDCLK;
- input RDEN;
- input REGCE;
- input RST;
- input RSTREG;
- input WRCLK;
- input WREN;
-endmodule
-
-module FIFO36E1 (...);
- parameter ALMOST_EMPTY_OFFSET = 13'h0080;
- parameter ALMOST_FULL_OFFSET = 13'h0080;
- parameter integer DATA_WIDTH = 4;
- parameter integer DO_REG = 1;
- parameter EN_ECC_READ = "FALSE";
- parameter EN_ECC_WRITE = "FALSE";
- parameter EN_SYN = "FALSE";
- parameter FIFO_MODE = "FIFO36";
- parameter FIRST_WORD_FALL_THROUGH = "FALSE";
- parameter INIT = 72'h0;
- parameter SIM_DEVICE = "VIRTEX6";
- parameter SRVAL = 72'h0;
- parameter IS_RDCLK_INVERTED = 1'b0;
- parameter IS_RDEN_INVERTED = 1'b0;
- parameter IS_RSTREG_INVERTED = 1'b0;
- parameter IS_RST_INVERTED = 1'b0;
- parameter IS_WRCLK_INVERTED = 1'b0;
- parameter IS_WREN_INVERTED = 1'b0;
- output ALMOSTEMPTY;
- output ALMOSTFULL;
- output DBITERR;
- output [63:0] DO;
- output [7:0] DOP;
- output [7:0] ECCPARITY;
- output EMPTY;
- output FULL;
- output [12:0] RDCOUNT;
- output RDERR;
- output SBITERR;
- output [12:0] WRCOUNT;
- output WRERR;
- input [63:0] DI;
- input [7:0] DIP;
- input INJECTDBITERR;
- input INJECTSBITERR;
- input RDCLK;
- input RDEN;
- input REGCE;
- input RST;
- input RSTREG;
- input WRCLK;
- input WREN;
-endmodule
-
-module FRAME_ECCE2 (...);
- parameter FARSRC = "EFAR";
- parameter FRAME_RBT_IN_FILENAME = "NONE";
- output CRCERROR;
- output ECCERROR;
- output ECCERRORSINGLE;
- output SYNDROMEVALID;
- output [12:0] SYNDROME;
- output [25:0] FAR;
- output [4:0] SYNBIT;
- output [6:0] SYNWORD;
-endmodule
+// Created by cells_xtra.py from Xilinx models
module GTHE2_CHANNEL (...);
parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0;
@@ -641,20 +347,26 @@ module GTHE2_CHANNEL (...);
output [7:0] RXDISPERR;
output [7:0] RXNOTINTABLE;
input CFGRESET;
+ (* invertible_pin = "IS_CLKRSVD0_INVERTED" *)
input CLKRSVD0;
+ (* invertible_pin = "IS_CLKRSVD1_INVERTED" *)
input CLKRSVD1;
+ (* invertible_pin = "IS_CPLLLOCKDETCLK_INVERTED" *)
input CPLLLOCKDETCLK;
input CPLLLOCKEN;
input CPLLPD;
input CPLLRESET;
input DMONFIFORESET;
+ (* invertible_pin = "IS_DMONITORCLK_INVERTED" *)
input DMONITORCLK;
+ (* invertible_pin = "IS_DRPCLK_INVERTED" *)
input DRPCLK;
input DRPEN;
input DRPWE;
input EYESCANMODE;
input EYESCANRESET;
input EYESCANTRIGGER;
+ (* invertible_pin = "IS_GTGREFCLK_INVERTED" *)
input GTGREFCLK;
input GTHRXN;
input GTHRXP;
@@ -750,9 +462,12 @@ module GTHE2_CHANNEL (...);
input RXSYNCIN;
input RXSYNCMODE;
input RXUSERRDY;
+ (* invertible_pin = "IS_RXUSRCLK2_INVERTED" *)
input RXUSRCLK2;
+ (* invertible_pin = "IS_RXUSRCLK_INVERTED" *)
input RXUSRCLK;
input SETERRSTATUS;
+ (* invertible_pin = "IS_SIGVALIDCLK_INVERTED" *)
input SIGVALIDCLK;
input TX8B10BEN;
input TXCOMINIT;
@@ -775,6 +490,7 @@ module GTHE2_CHANNEL (...);
input TXPHALIGNEN;
input TXPHDLYPD;
input TXPHDLYRESET;
+ (* invertible_pin = "IS_TXPHDLYTSTCLK_INVERTED" *)
input TXPHDLYTSTCLK;
input TXPHINIT;
input TXPHOVRDEN;
@@ -798,7 +514,9 @@ module GTHE2_CHANNEL (...);
input TXSYNCIN;
input TXSYNCMODE;
input TXUSERRDY;
+ (* invertible_pin = "IS_TXUSRCLK2_INVERTED" *)
input TXUSRCLK2;
+ (* invertible_pin = "IS_TXUSRCLK_INVERTED" *)
input TXUSRCLK;
input [13:0] RXADAPTSELTEST;
input [15:0] DRPDI;
@@ -887,9 +605,11 @@ module GTHE2_COMMON (...);
input BGMONITORENB;
input BGPDB;
input BGRCALOVRDENB;
+ (* invertible_pin = "IS_DRPCLK_INVERTED" *)
input DRPCLK;
input DRPEN;
input DRPWE;
+ (* invertible_pin = "IS_GTGREFCLK_INVERTED" *)
input GTGREFCLK;
input GTNORTHREFCLK0;
input GTNORTHREFCLK1;
@@ -897,6 +617,7 @@ module GTHE2_COMMON (...);
input GTREFCLK1;
input GTSOUTHREFCLK0;
input GTSOUTHREFCLK1;
+ (* invertible_pin = "IS_QPLLLOCKDETCLK_INVERTED" *)
input QPLLLOCKDETCLK;
input QPLLLOCKEN;
input QPLLOUTRESET;
@@ -1222,10 +943,14 @@ module GTPE2_CHANNEL (...);
output [4:0] RXPHMONITOR;
output [4:0] RXPHSLIPMONITOR;
input CFGRESET;
+ (* invertible_pin = "IS_CLKRSVD0_INVERTED" *)
input CLKRSVD0;
+ (* invertible_pin = "IS_CLKRSVD1_INVERTED" *)
input CLKRSVD1;
input DMONFIFORESET;
+ (* invertible_pin = "IS_DMONITORCLK_INVERTED" *)
input DMONITORCLK;
+ (* invertible_pin = "IS_DRPCLK_INVERTED" *)
input DRPCLK;
input DRPEN;
input DRPWE;
@@ -1299,9 +1024,12 @@ module GTPE2_CHANNEL (...);
input RXSYNCIN;
input RXSYNCMODE;
input RXUSERRDY;
+ (* invertible_pin = "IS_RXUSRCLK2_INVERTED" *)
input RXUSRCLK2;
+ (* invertible_pin = "IS_RXUSRCLK_INVERTED" *)
input RXUSRCLK;
input SETERRSTATUS;
+ (* invertible_pin = "IS_SIGVALIDCLK_INVERTED" *)
input SIGVALIDCLK;
input TX8B10BEN;
input TXCOMINIT;
@@ -1324,6 +1052,7 @@ module GTPE2_CHANNEL (...);
input TXPHALIGNEN;
input TXPHDLYPD;
input TXPHDLYRESET;
+ (* invertible_pin = "IS_TXPHDLYTSTCLK_INVERTED" *)
input TXPHDLYTSTCLK;
input TXPHINIT;
input TXPHOVRDEN;
@@ -1344,7 +1073,9 @@ module GTPE2_CHANNEL (...);
input TXSYNCIN;
input TXSYNCMODE;
input TXUSERRDY;
+ (* invertible_pin = "IS_TXUSRCLK2_INVERTED" *)
input TXUSRCLK2;
+ (* invertible_pin = "IS_TXUSRCLK_INVERTED" *)
input TXUSRCLK;
input [13:0] RXADAPTSELTEST;
input [15:0] DRPDI;
@@ -1433,21 +1164,26 @@ module GTPE2_COMMON (...);
input BGMONITORENB;
input BGPDB;
input BGRCALOVRDENB;
+ (* invertible_pin = "IS_DRPCLK_INVERTED" *)
input DRPCLK;
input DRPEN;
input DRPWE;
input GTEASTREFCLK0;
input GTEASTREFCLK1;
+ (* invertible_pin = "IS_GTGREFCLK0_INVERTED" *)
input GTGREFCLK0;
+ (* invertible_pin = "IS_GTGREFCLK1_INVERTED" *)
input GTGREFCLK1;
input GTREFCLK0;
input GTREFCLK1;
input GTWESTREFCLK0;
input GTWESTREFCLK1;
+ (* invertible_pin = "IS_PLL0LOCKDETCLK_INVERTED" *)
input PLL0LOCKDETCLK;
input PLL0LOCKEN;
input PLL0PD;
input PLL0RESET;
+ (* invertible_pin = "IS_PLL1LOCKDETCLK_INVERTED" *)
input PLL1LOCKDETCLK;
input PLL1LOCKEN;
input PLL1PD;
@@ -1736,16 +1472,19 @@ module GTXE2_CHANNEL (...);
output [7:0] RXNOTINTABLE;
output [9:0] TSTOUT;
input CFGRESET;
+ (* invertible_pin = "IS_CPLLLOCKDETCLK_INVERTED" *)
input CPLLLOCKDETCLK;
input CPLLLOCKEN;
input CPLLPD;
input CPLLRESET;
+ (* invertible_pin = "IS_DRPCLK_INVERTED" *)
input DRPCLK;
input DRPEN;
input DRPWE;
input EYESCANMODE;
input EYESCANRESET;
input EYESCANTRIGGER;
+ (* invertible_pin = "IS_GTGREFCLK_INVERTED" *)
input GTGREFCLK;
input GTNORTHREFCLK0;
input GTNORTHREFCLK1;
@@ -1822,7 +1561,9 @@ module GTXE2_CHANNEL (...);
input RXQPIEN;
input RXSLIDE;
input RXUSERRDY;
+ (* invertible_pin = "IS_RXUSRCLK2_INVERTED" *)
input RXUSRCLK2;
+ (* invertible_pin = "IS_RXUSRCLK_INVERTED" *)
input RXUSRCLK;
input SETERRSTATUS;
input TX8B10BEN;
@@ -1846,6 +1587,7 @@ module GTXE2_CHANNEL (...);
input TXPHALIGNEN;
input TXPHDLYPD;
input TXPHDLYRESET;
+ (* invertible_pin = "IS_TXPHDLYTSTCLK_INVERTED" *)
input TXPHDLYTSTCLK;
input TXPHINIT;
input TXPHOVRDEN;
@@ -1861,7 +1603,9 @@ module GTXE2_CHANNEL (...);
input TXSTARTSEQ;
input TXSWING;
input TXUSERRDY;
+ (* invertible_pin = "IS_TXUSRCLK2_INVERTED" *)
input TXUSRCLK2;
+ (* invertible_pin = "IS_TXUSRCLK_INVERTED" *)
input TXUSRCLK;
input [15:0] DRPDI;
input [15:0] GTRSVD;
@@ -1938,9 +1682,11 @@ module GTXE2_COMMON (...);
input BGBYPASSB;
input BGMONITORENB;
input BGPDB;
+ (* invertible_pin = "IS_DRPCLK_INVERTED" *)
input DRPCLK;
input DRPEN;
input DRPWE;
+ (* invertible_pin = "IS_GTGREFCLK_INVERTED" *)
input GTGREFCLK;
input GTNORTHREFCLK0;
input GTNORTHREFCLK1;
@@ -1948,6 +1694,7 @@ module GTXE2_COMMON (...);
input GTREFCLK1;
input GTSOUTHREFCLK0;
input GTSOUTHREFCLK1;
+ (* invertible_pin = "IS_QPLLLOCKDETCLK_INVERTED" *)
input QPLLLOCKDETCLK;
input QPLLLOCKEN;
input QPLLOUTRESET;
@@ -1963,429 +1710,1842 @@ module GTXE2_COMMON (...);
input [7:0] PMARSVD;
endmodule
-module IBUF_IBUFDISABLE (...);
- parameter IBUF_LOW_PWR = "TRUE";
- parameter IOSTANDARD = "DEFAULT";
+module PCIE_2_1 (...);
+ parameter [11:0] AER_BASE_PTR = 12'h140;
+ parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
+ parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
+ parameter [15:0] AER_CAP_ID = 16'h0001;
+ parameter AER_CAP_MULTIHEADER = "FALSE";
+ parameter [11:0] AER_CAP_NEXTPTR = 12'h178;
+ parameter AER_CAP_ON = "FALSE";
+ parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000;
+ parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE";
+ parameter [3:0] AER_CAP_VERSION = 4'h2;
+ parameter ALLOW_X8_GEN2 = "FALSE";
+ parameter [31:0] BAR0 = 32'hFFFFFF00;
+ parameter [31:0] BAR1 = 32'hFFFF0000;
+ parameter [31:0] BAR2 = 32'hFFFF000C;
+ parameter [31:0] BAR3 = 32'hFFFFFFFF;
+ parameter [31:0] BAR4 = 32'h00000000;
+ parameter [31:0] BAR5 = 32'h00000000;
+ parameter [7:0] CAPABILITIES_PTR = 8'h40;
+ parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000;
+ parameter integer CFG_ECRC_ERR_CPLSTAT = 0;
+ parameter [23:0] CLASS_CODE = 24'h000000;
+ parameter CMD_INTX_IMPLEMENTED = "TRUE";
+ parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE";
+ parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0;
+ parameter [6:0] CRM_MODULE_RSTS = 7'h00;
+ parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE";
+ parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE";
+ parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE";
+ parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE";
+ parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE";
+ parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE";
+ parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE";
+ parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE";
+ parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0;
+ parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE";
+ parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'h0;
+ parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE";
+ parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE";
+ parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0;
+ parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0;
+ parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE";
+ parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE";
+ parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2;
+ parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0;
+ parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE";
+ parameter integer DEV_CAP_RSVD_14_12 = 0;
+ parameter integer DEV_CAP_RSVD_17_16 = 0;
+ parameter integer DEV_CAP_RSVD_31_29 = 0;
+ parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE";
+ parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE";
+ parameter DISABLE_ASPM_L1_TIMER = "FALSE";
+ parameter DISABLE_BAR_FILTERING = "FALSE";
+ parameter DISABLE_ERR_MSG = "FALSE";
+ parameter DISABLE_ID_CHECK = "FALSE";
+ parameter DISABLE_LANE_REVERSAL = "FALSE";
+ parameter DISABLE_LOCKED_FILTER = "FALSE";
+ parameter DISABLE_PPM_FILTER = "FALSE";
+ parameter DISABLE_RX_POISONED_RESP = "FALSE";
+ parameter DISABLE_RX_TC_FILTER = "FALSE";
+ parameter DISABLE_SCRAMBLING = "FALSE";
+ parameter [7:0] DNSTREAM_LINK_NUM = 8'h00;
+ parameter [11:0] DSN_BASE_PTR = 12'h100;
+ parameter [15:0] DSN_CAP_ID = 16'h0003;
+ parameter [11:0] DSN_CAP_NEXTPTR = 12'h10C;
+ parameter DSN_CAP_ON = "TRUE";
+ parameter [3:0] DSN_CAP_VERSION = 4'h1;
+ parameter [10:0] ENABLE_MSG_ROUTE = 11'h000;
+ parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE";
+ parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE";
+ parameter ENTER_RVRY_EI_L0 = "TRUE";
+ parameter EXIT_LOOPBACK_ON_EI = "TRUE";
+ parameter [31:0] EXPANSION_ROM = 32'hFFFFF001;
+ parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F;
+ parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF;
+ parameter [7:0] HEADER_TYPE = 8'h00;
+ parameter [4:0] INFER_EI = 5'h00;
+ parameter [7:0] INTERRUPT_PIN = 8'h01;
+ parameter INTERRUPT_STAT_AUTO = "TRUE";
+ parameter IS_SWITCH = "FALSE";
+ parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF;
+ parameter LINK_CAP_ASPM_OPTIONALITY = "TRUE";
+ parameter integer LINK_CAP_ASPM_SUPPORT = 1;
+ parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE";
+ parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE";
+ parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7;
+ parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7;
+ parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7;
+ parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7;
+ parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7;
+ parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7;
+ parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7;
+ parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7;
+ parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE";
+ parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1;
+ parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08;
+ parameter integer LINK_CAP_RSVD_23 = 0;
+ parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE";
+ parameter integer LINK_CONTROL_RCB = 0;
+ parameter LINK_CTRL2_DEEMPHASIS = "FALSE";
+ parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE";
+ parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2;
+ parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE";
+ parameter [14:0] LL_ACK_TIMEOUT = 15'h0000;
+ parameter LL_ACK_TIMEOUT_EN = "FALSE";
+ parameter integer LL_ACK_TIMEOUT_FUNC = 0;
+ parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000;
+ parameter LL_REPLAY_TIMEOUT_EN = "FALSE";
+ parameter integer LL_REPLAY_TIMEOUT_FUNC = 0;
+ parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01;
+ parameter MPS_FORCE = "FALSE";
+ parameter [7:0] MSIX_BASE_PTR = 8'h9C;
+ parameter [7:0] MSIX_CAP_ID = 8'h11;
+ parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00;
+ parameter MSIX_CAP_ON = "FALSE";
+ parameter integer MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter [7:0] MSI_BASE_PTR = 8'h48;
+ parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE";
+ parameter [7:0] MSI_CAP_ID = 8'h05;
+ parameter integer MSI_CAP_MULTIMSGCAP = 0;
+ parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0;
+ parameter [7:0] MSI_CAP_NEXTPTR = 8'h60;
+ parameter MSI_CAP_ON = "FALSE";
+ parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE";
+ parameter integer N_FTS_COMCLK_GEN1 = 255;
+ parameter integer N_FTS_COMCLK_GEN2 = 255;
+ parameter integer N_FTS_GEN1 = 255;
+ parameter integer N_FTS_GEN2 = 255;
+ parameter [7:0] PCIE_BASE_PTR = 8'h60;
+ parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10;
+ parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2;
+ parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0;
+ parameter [7:0] PCIE_CAP_NEXTPTR = 8'h9C;
+ parameter PCIE_CAP_ON = "TRUE";
+ parameter integer PCIE_CAP_RSVD_15_14 = 0;
+ parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE";
+ parameter integer PCIE_REVISION = 2;
+ parameter integer PL_AUTO_CONFIG = 0;
+ parameter PL_FAST_TRAIN = "FALSE";
+ parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000;
+ parameter PM_ASPML0S_TIMEOUT_EN = "FALSE";
+ parameter integer PM_ASPML0S_TIMEOUT_FUNC = 0;
+ parameter PM_ASPM_FASTEXIT = "FALSE";
+ parameter [7:0] PM_BASE_PTR = 8'h40;
+ parameter integer PM_CAP_AUXCURRENT = 0;
+ parameter PM_CAP_D1SUPPORT = "TRUE";
+ parameter PM_CAP_D2SUPPORT = "TRUE";
+ parameter PM_CAP_DSI = "FALSE";
+ parameter [7:0] PM_CAP_ID = 8'h01;
+ parameter [7:0] PM_CAP_NEXTPTR = 8'h48;
+ parameter PM_CAP_ON = "TRUE";
+ parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F;
+ parameter PM_CAP_PME_CLOCK = "FALSE";
+ parameter integer PM_CAP_RSVD_04 = 0;
+ parameter integer PM_CAP_VERSION = 3;
+ parameter PM_CSR_B2B3 = "FALSE";
+ parameter PM_CSR_BPCCEN = "FALSE";
+ parameter PM_CSR_NOSOFTRST = "TRUE";
+ parameter [7:0] PM_DATA0 = 8'h01;
+ parameter [7:0] PM_DATA1 = 8'h01;
+ parameter [7:0] PM_DATA2 = 8'h01;
+ parameter [7:0] PM_DATA3 = 8'h01;
+ parameter [7:0] PM_DATA4 = 8'h01;
+ parameter [7:0] PM_DATA5 = 8'h01;
+ parameter [7:0] PM_DATA6 = 8'h01;
+ parameter [7:0] PM_DATA7 = 8'h01;
+ parameter [1:0] PM_DATA_SCALE0 = 2'h1;
+ parameter [1:0] PM_DATA_SCALE1 = 2'h1;
+ parameter [1:0] PM_DATA_SCALE2 = 2'h1;
+ parameter [1:0] PM_DATA_SCALE3 = 2'h1;
+ parameter [1:0] PM_DATA_SCALE4 = 2'h1;
+ parameter [1:0] PM_DATA_SCALE5 = 2'h1;
+ parameter [1:0] PM_DATA_SCALE6 = 2'h1;
+ parameter [1:0] PM_DATA_SCALE7 = 2'h1;
+ parameter PM_MF = "FALSE";
+ parameter [11:0] RBAR_BASE_PTR = 12'h178;
+ parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00;
+ parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00;
+ parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00;
+ parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00;
+ parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00;
+ parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00;
+ parameter [15:0] RBAR_CAP_ID = 16'h0015;
+ parameter [2:0] RBAR_CAP_INDEX0 = 3'h0;
+ parameter [2:0] RBAR_CAP_INDEX1 = 3'h0;
+ parameter [2:0] RBAR_CAP_INDEX2 = 3'h0;
+ parameter [2:0] RBAR_CAP_INDEX3 = 3'h0;
+ parameter [2:0] RBAR_CAP_INDEX4 = 3'h0;
+ parameter [2:0] RBAR_CAP_INDEX5 = 3'h0;
+ parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000;
+ parameter RBAR_CAP_ON = "FALSE";
+ parameter [31:0] RBAR_CAP_SUP0 = 32'h00000000;
+ parameter [31:0] RBAR_CAP_SUP1 = 32'h00000000;
+ parameter [31:0] RBAR_CAP_SUP2 = 32'h00000000;
+ parameter [31:0] RBAR_CAP_SUP3 = 32'h00000000;
+ parameter [31:0] RBAR_CAP_SUP4 = 32'h00000000;
+ parameter [31:0] RBAR_CAP_SUP5 = 32'h00000000;
+ parameter [3:0] RBAR_CAP_VERSION = 4'h1;
+ parameter [2:0] RBAR_NUM = 3'h1;
+ parameter integer RECRC_CHK = 0;
+ parameter RECRC_CHK_TRIM = "FALSE";
+ parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE";
+ parameter [1:0] RP_AUTO_SPD = 2'h1;
+ parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1F;
+ parameter SELECT_DLL_IF = "FALSE";
+ parameter SIM_VERSION = "1.0";
+ parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE";
+ parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE";
+ parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE";
+ parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE";
+ parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE";
+ parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE";
+ parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE";
+ parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000;
+ parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE";
+ parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE";
+ parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0;
+ parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00;
+ parameter integer SPARE_BIT0 = 0;
+ parameter integer SPARE_BIT1 = 0;
+ parameter integer SPARE_BIT2 = 0;
+ parameter integer SPARE_BIT3 = 0;
+ parameter integer SPARE_BIT4 = 0;
+ parameter integer SPARE_BIT5 = 0;
+ parameter integer SPARE_BIT6 = 0;
+ parameter integer SPARE_BIT7 = 0;
+ parameter integer SPARE_BIT8 = 0;
+ parameter [7:0] SPARE_BYTE0 = 8'h00;
+ parameter [7:0] SPARE_BYTE1 = 8'h00;
+ parameter [7:0] SPARE_BYTE2 = 8'h00;
+ parameter [7:0] SPARE_BYTE3 = 8'h00;
+ parameter [31:0] SPARE_WORD0 = 32'h00000000;
+ parameter [31:0] SPARE_WORD1 = 32'h00000000;
+ parameter [31:0] SPARE_WORD2 = 32'h00000000;
+ parameter [31:0] SPARE_WORD3 = 32'h00000000;
+ parameter SSL_MESSAGE_AUTO = "FALSE";
+ parameter TECRC_EP_INV = "FALSE";
+ parameter TL_RBYPASS = "FALSE";
+ parameter integer TL_RX_RAM_RADDR_LATENCY = 0;
+ parameter integer TL_RX_RAM_RDATA_LATENCY = 2;
+ parameter integer TL_RX_RAM_WRITE_LATENCY = 0;
+ parameter TL_TFC_DISABLE = "FALSE";
+ parameter TL_TX_CHECKS_DISABLE = "FALSE";
+ parameter integer TL_TX_RAM_RADDR_LATENCY = 0;
+ parameter integer TL_TX_RAM_RDATA_LATENCY = 2;
+ parameter integer TL_TX_RAM_WRITE_LATENCY = 0;
+ parameter TRN_DW = "FALSE";
+ parameter TRN_NP_FC = "FALSE";
+ parameter UPCONFIG_CAPABLE = "TRUE";
+ parameter UPSTREAM_FACING = "TRUE";
+ parameter UR_ATOMIC = "TRUE";
+ parameter UR_CFG1 = "TRUE";
+ parameter UR_INV_REQ = "TRUE";
+ parameter UR_PRS_RESPONSE = "TRUE";
+ parameter USER_CLK2_DIV2 = "FALSE";
+ parameter integer USER_CLK_FREQ = 3;
+ parameter USE_RID_PINS = "FALSE";
+ parameter VC0_CPL_INFINITE = "TRUE";
+ parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF;
+ parameter integer VC0_TOTAL_CREDITS_CD = 127;
+ parameter integer VC0_TOTAL_CREDITS_CH = 31;
+ parameter integer VC0_TOTAL_CREDITS_NPD = 24;
+ parameter integer VC0_TOTAL_CREDITS_NPH = 12;
+ parameter integer VC0_TOTAL_CREDITS_PD = 288;
+ parameter integer VC0_TOTAL_CREDITS_PH = 32;
+ parameter integer VC0_TX_LASTPACKET = 31;
+ parameter [11:0] VC_BASE_PTR = 12'h10C;
+ parameter [15:0] VC_CAP_ID = 16'h0002;
+ parameter [11:0] VC_CAP_NEXTPTR = 12'h000;
+ parameter VC_CAP_ON = "FALSE";
+ parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE";
+ parameter [3:0] VC_CAP_VERSION = 4'h1;
+ parameter [11:0] VSEC_BASE_PTR = 12'h128;
+ parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234;
+ parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018;
+ parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1;
+ parameter [15:0] VSEC_CAP_ID = 16'h000B;
+ parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE";
+ parameter [11:0] VSEC_CAP_NEXTPTR = 12'h140;
+ parameter VSEC_CAP_ON = "FALSE";
+ parameter [3:0] VSEC_CAP_VERSION = 4'h1;
+ output CFGAERECRCCHECKEN;
+ output CFGAERECRCGENEN;
+ output CFGAERROOTERRCORRERRRECEIVED;
+ output CFGAERROOTERRCORRERRREPORTINGEN;
+ output CFGAERROOTERRFATALERRRECEIVED;
+ output CFGAERROOTERRFATALERRREPORTINGEN;
+ output CFGAERROOTERRNONFATALERRRECEIVED;
+ output CFGAERROOTERRNONFATALERRREPORTINGEN;
+ output CFGBRIDGESERREN;
+ output CFGCOMMANDBUSMASTERENABLE;
+ output CFGCOMMANDINTERRUPTDISABLE;
+ output CFGCOMMANDIOENABLE;
+ output CFGCOMMANDMEMENABLE;
+ output CFGCOMMANDSERREN;
+ output CFGDEVCONTROL2ARIFORWARDEN;
+ output CFGDEVCONTROL2ATOMICEGRESSBLOCK;
+ output CFGDEVCONTROL2ATOMICREQUESTEREN;
+ output CFGDEVCONTROL2CPLTIMEOUTDIS;
+ output CFGDEVCONTROL2IDOCPLEN;
+ output CFGDEVCONTROL2IDOREQEN;
+ output CFGDEVCONTROL2LTREN;
+ output CFGDEVCONTROL2TLPPREFIXBLOCK;
+ output CFGDEVCONTROLAUXPOWEREN;
+ output CFGDEVCONTROLCORRERRREPORTINGEN;
+ output CFGDEVCONTROLENABLERO;
+ output CFGDEVCONTROLEXTTAGEN;
+ output CFGDEVCONTROLFATALERRREPORTINGEN;
+ output CFGDEVCONTROLNONFATALREPORTINGEN;
+ output CFGDEVCONTROLNOSNOOPEN;
+ output CFGDEVCONTROLPHANTOMEN;
+ output CFGDEVCONTROLURERRREPORTINGEN;
+ output CFGDEVSTATUSCORRERRDETECTED;
+ output CFGDEVSTATUSFATALERRDETECTED;
+ output CFGDEVSTATUSNONFATALERRDETECTED;
+ output CFGDEVSTATUSURDETECTED;
+ output CFGERRAERHEADERLOGSETN;
+ output CFGERRCPLRDYN;
+ output CFGINTERRUPTMSIENABLE;
+ output CFGINTERRUPTMSIXENABLE;
+ output CFGINTERRUPTMSIXFM;
+ output CFGINTERRUPTRDYN;
+ output CFGLINKCONTROLAUTOBANDWIDTHINTEN;
+ output CFGLINKCONTROLBANDWIDTHINTEN;
+ output CFGLINKCONTROLCLOCKPMEN;
+ output CFGLINKCONTROLCOMMONCLOCK;
+ output CFGLINKCONTROLEXTENDEDSYNC;
+ output CFGLINKCONTROLHWAUTOWIDTHDIS;
+ output CFGLINKCONTROLLINKDISABLE;
+ output CFGLINKCONTROLRCB;
+ output CFGLINKCONTROLRETRAINLINK;
+ output CFGLINKSTATUSAUTOBANDWIDTHSTATUS;
+ output CFGLINKSTATUSBANDWIDTHSTATUS;
+ output CFGLINKSTATUSDLLACTIVE;
+ output CFGLINKSTATUSLINKTRAINING;
+ output CFGMGMTRDWRDONEN;
+ output CFGMSGRECEIVED;
+ output CFGMSGRECEIVEDASSERTINTA;
+ output CFGMSGRECEIVEDASSERTINTB;
+ output CFGMSGRECEIVEDASSERTINTC;
+ output CFGMSGRECEIVEDASSERTINTD;
+ output CFGMSGRECEIVEDDEASSERTINTA;
+ output CFGMSGRECEIVEDDEASSERTINTB;
+ output CFGMSGRECEIVEDDEASSERTINTC;
+ output CFGMSGRECEIVEDDEASSERTINTD;
+ output CFGMSGRECEIVEDERRCOR;
+ output CFGMSGRECEIVEDERRFATAL;
+ output CFGMSGRECEIVEDERRNONFATAL;
+ output CFGMSGRECEIVEDPMASNAK;
+ output CFGMSGRECEIVEDPMETO;
+ output CFGMSGRECEIVEDPMETOACK;
+ output CFGMSGRECEIVEDPMPME;
+ output CFGMSGRECEIVEDSETSLOTPOWERLIMIT;
+ output CFGMSGRECEIVEDUNLOCK;
+ output CFGPMCSRPMEEN;
+ output CFGPMCSRPMESTATUS;
+ output CFGPMRCVASREQL1N;
+ output CFGPMRCVENTERL1N;
+ output CFGPMRCVENTERL23N;
+ output CFGPMRCVREQACKN;
+ output CFGROOTCONTROLPMEINTEN;
+ output CFGROOTCONTROLSYSERRCORRERREN;
+ output CFGROOTCONTROLSYSERRFATALERREN;
+ output CFGROOTCONTROLSYSERRNONFATALERREN;
+ output CFGSLOTCONTROLELECTROMECHILCTLPULSE;
+ output CFGTRANSACTION;
+ output CFGTRANSACTIONTYPE;
+ output DBGSCLRA;
+ output DBGSCLRB;
+ output DBGSCLRC;
+ output DBGSCLRD;
+ output DBGSCLRE;
+ output DBGSCLRF;
+ output DBGSCLRG;
+ output DBGSCLRH;
+ output DBGSCLRI;
+ output DBGSCLRJ;
+ output DBGSCLRK;
+ output DRPRDY;
+ output LL2BADDLLPERR;
+ output LL2BADTLPERR;
+ output LL2PROTOCOLERR;
+ output LL2RECEIVERERR;
+ output LL2REPLAYROERR;
+ output LL2REPLAYTOERR;
+ output LL2SUSPENDOK;
+ output LL2TFCINIT1SEQ;
+ output LL2TFCINIT2SEQ;
+ output LL2TXIDLE;
+ output LNKCLKEN;
+ output MIMRXREN;
+ output MIMRXWEN;
+ output MIMTXREN;
+ output MIMTXWEN;
+ output PIPERX0POLARITY;
+ output PIPERX1POLARITY;
+ output PIPERX2POLARITY;
+ output PIPERX3POLARITY;
+ output PIPERX4POLARITY;
+ output PIPERX5POLARITY;
+ output PIPERX6POLARITY;
+ output PIPERX7POLARITY;
+ output PIPETX0COMPLIANCE;
+ output PIPETX0ELECIDLE;
+ output PIPETX1COMPLIANCE;
+ output PIPETX1ELECIDLE;
+ output PIPETX2COMPLIANCE;
+ output PIPETX2ELECIDLE;
+ output PIPETX3COMPLIANCE;
+ output PIPETX3ELECIDLE;
+ output PIPETX4COMPLIANCE;
+ output PIPETX4ELECIDLE;
+ output PIPETX5COMPLIANCE;
+ output PIPETX5ELECIDLE;
+ output PIPETX6COMPLIANCE;
+ output PIPETX6ELECIDLE;
+ output PIPETX7COMPLIANCE;
+ output PIPETX7ELECIDLE;
+ output PIPETXDEEMPH;
+ output PIPETXRATE;
+ output PIPETXRCVRDET;
+ output PIPETXRESET;
+ output PL2L0REQ;
+ output PL2LINKUP;
+ output PL2RECEIVERERR;
+ output PL2RECOVERY;
+ output PL2RXELECIDLE;
+ output PL2SUSPENDOK;
+ output PLDIRECTEDCHANGEDONE;
+ output PLLINKGEN2CAP;
+ output PLLINKPARTNERGEN2SUPPORTED;
+ output PLLINKUPCFGCAP;
+ output PLPHYLNKUPN;
+ output PLRECEIVEDHOTRST;
+ output PLSELLNKRATE;
+ output RECEIVEDFUNCLVLRSTN;
+ output TL2ASPMSUSPENDCREDITCHECKOK;
+ output TL2ASPMSUSPENDREQ;
+ output TL2ERRFCPE;
+ output TL2ERRMALFORMED;
+ output TL2ERRRXOVERFLOW;
+ output TL2PPMSUSPENDOK;
+ output TRNLNKUP;
+ output TRNRECRCERR;
+ output TRNREOF;
+ output TRNRERRFWD;
+ output TRNRSOF;
+ output TRNRSRCDSC;
+ output TRNRSRCRDY;
+ output TRNTCFGREQ;
+ output TRNTDLLPDSTRDY;
+ output TRNTERRDROP;
+ output USERRSTN;
+ output [11:0] DBGVECC;
+ output [11:0] PLDBGVEC;
+ output [11:0] TRNFCCPLD;
+ output [11:0] TRNFCNPD;
+ output [11:0] TRNFCPD;
+ output [127:0] TRNRD;
+ output [12:0] MIMRXRADDR;
+ output [12:0] MIMRXWADDR;
+ output [12:0] MIMTXRADDR;
+ output [12:0] MIMTXWADDR;
+ output [15:0] CFGMSGDATA;
+ output [15:0] DRPDO;
+ output [15:0] PIPETX0DATA;
+ output [15:0] PIPETX1DATA;
+ output [15:0] PIPETX2DATA;
+ output [15:0] PIPETX3DATA;
+ output [15:0] PIPETX4DATA;
+ output [15:0] PIPETX5DATA;
+ output [15:0] PIPETX6DATA;
+ output [15:0] PIPETX7DATA;
+ output [1:0] CFGLINKCONTROLASPMCONTROL;
+ output [1:0] CFGLINKSTATUSCURRENTSPEED;
+ output [1:0] CFGPMCSRPOWERSTATE;
+ output [1:0] PIPETX0CHARISK;
+ output [1:0] PIPETX0POWERDOWN;
+ output [1:0] PIPETX1CHARISK;
+ output [1:0] PIPETX1POWERDOWN;
+ output [1:0] PIPETX2CHARISK;
+ output [1:0] PIPETX2POWERDOWN;
+ output [1:0] PIPETX3CHARISK;
+ output [1:0] PIPETX3POWERDOWN;
+ output [1:0] PIPETX4CHARISK;
+ output [1:0] PIPETX4POWERDOWN;
+ output [1:0] PIPETX5CHARISK;
+ output [1:0] PIPETX5POWERDOWN;
+ output [1:0] PIPETX6CHARISK;
+ output [1:0] PIPETX6POWERDOWN;
+ output [1:0] PIPETX7CHARISK;
+ output [1:0] PIPETX7POWERDOWN;
+ output [1:0] PL2RXPMSTATE;
+ output [1:0] PLLANEREVERSALMODE;
+ output [1:0] PLRXPMSTATE;
+ output [1:0] PLSELLNKWIDTH;
+ output [1:0] TRNRDLLPSRCRDY;
+ output [1:0] TRNRREM;
+ output [2:0] CFGDEVCONTROLMAXPAYLOAD;
+ output [2:0] CFGDEVCONTROLMAXREADREQ;
+ output [2:0] CFGINTERRUPTMMENABLE;
+ output [2:0] CFGPCIELINKSTATE;
+ output [2:0] PIPETXMARGIN;
+ output [2:0] PLINITIALLINKWIDTH;
+ output [2:0] PLTXPMSTATE;
+ output [31:0] CFGMGMTDO;
+ output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL;
+ output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH;
+ output [3:0] TRNTDSTRDY;
+ output [4:0] LL2LINKSTATUS;
+ output [5:0] PLLTSSMSTATE;
+ output [5:0] TRNTBUFAV;
+ output [63:0] DBGVECA;
+ output [63:0] DBGVECB;
+ output [63:0] TL2ERRHDR;
+ output [63:0] TRNRDLLPDATA;
+ output [67:0] MIMRXWDATA;
+ output [68:0] MIMTXWDATA;
+ output [6:0] CFGTRANSACTIONADDR;
+ output [6:0] CFGVCTCVCMAP;
+ output [7:0] CFGINTERRUPTDO;
+ output [7:0] TRNFCCPLH;
+ output [7:0] TRNFCNPH;
+ output [7:0] TRNFCPH;
+ output [7:0] TRNRBARHIT;
+ input CFGERRACSN;
+ input CFGERRATOMICEGRESSBLOCKEDN;
+ input CFGERRCORN;
+ input CFGERRCPLABORTN;
+ input CFGERRCPLTIMEOUTN;
+ input CFGERRCPLUNEXPECTN;
+ input CFGERRECRCN;
+ input CFGERRINTERNALCORN;
+ input CFGERRINTERNALUNCORN;
+ input CFGERRLOCKEDN;
+ input CFGERRMALFORMEDN;
+ input CFGERRMCBLOCKEDN;
+ input CFGERRNORECOVERYN;
+ input CFGERRPOISONEDN;
+ input CFGERRPOSTEDN;
+ input CFGERRURN;
+ input CFGFORCECOMMONCLOCKOFF;
+ input CFGFORCEEXTENDEDSYNCON;
+ input CFGINTERRUPTASSERTN;
+ input CFGINTERRUPTN;
+ input CFGINTERRUPTSTATN;
+ input CFGMGMTRDENN;
+ input CFGMGMTWRENN;
+ input CFGMGMTWRREADONLYN;
+ input CFGMGMTWRRW1CASRWN;
+ input CFGPMFORCESTATEENN;
+ input CFGPMHALTASPML0SN;
+ input CFGPMHALTASPML1N;
+ input CFGPMSENDPMETON;
+ input CFGPMTURNOFFOKN;
+ input CFGPMWAKEN;
+ input CFGTRNPENDINGN;
+ input CMRSTN;
+ input CMSTICKYRSTN;
+ input DBGSUBMODE;
+ input DLRSTN;
+ input DRPCLK;
+ input DRPEN;
+ input DRPWE;
+ input FUNCLVLRSTN;
+ input LL2SENDASREQL1;
+ input LL2SENDENTERL1;
+ input LL2SENDENTERL23;
+ input LL2SENDPMACK;
+ input LL2SUSPENDNOW;
+ input LL2TLPRCV;
+ input PIPECLK;
+ input PIPERX0CHANISALIGNED;
+ input PIPERX0ELECIDLE;
+ input PIPERX0PHYSTATUS;
+ input PIPERX0VALID;
+ input PIPERX1CHANISALIGNED;
+ input PIPERX1ELECIDLE;
+ input PIPERX1PHYSTATUS;
+ input PIPERX1VALID;
+ input PIPERX2CHANISALIGNED;
+ input PIPERX2ELECIDLE;
+ input PIPERX2PHYSTATUS;
+ input PIPERX2VALID;
+ input PIPERX3CHANISALIGNED;
+ input PIPERX3ELECIDLE;
+ input PIPERX3PHYSTATUS;
+ input PIPERX3VALID;
+ input PIPERX4CHANISALIGNED;
+ input PIPERX4ELECIDLE;
+ input PIPERX4PHYSTATUS;
+ input PIPERX4VALID;
+ input PIPERX5CHANISALIGNED;
+ input PIPERX5ELECIDLE;
+ input PIPERX5PHYSTATUS;
+ input PIPERX5VALID;
+ input PIPERX6CHANISALIGNED;
+ input PIPERX6ELECIDLE;
+ input PIPERX6PHYSTATUS;
+ input PIPERX6VALID;
+ input PIPERX7CHANISALIGNED;
+ input PIPERX7ELECIDLE;
+ input PIPERX7PHYSTATUS;
+ input PIPERX7VALID;
+ input PLDIRECTEDLINKAUTON;
+ input PLDIRECTEDLINKSPEED;
+ input PLDIRECTEDLTSSMNEWVLD;
+ input PLDIRECTEDLTSSMSTALL;
+ input PLDOWNSTREAMDEEMPHSOURCE;
+ input PLRSTN;
+ input PLTRANSMITHOTRST;
+ input PLUPSTREAMPREFERDEEMPH;
+ input SYSRSTN;
+ input TL2ASPMSUSPENDCREDITCHECK;
+ input TL2PPMSUSPENDREQ;
+ input TLRSTN;
+ input TRNRDSTRDY;
+ input TRNRFCPRET;
+ input TRNRNPOK;
+ input TRNRNPREQ;
+ input TRNTCFGGNT;
+ input TRNTDLLPSRCRDY;
+ input TRNTECRCGEN;
+ input TRNTEOF;
+ input TRNTERRFWD;
+ input TRNTSOF;
+ input TRNTSRCDSC;
+ input TRNTSRCRDY;
+ input TRNTSTR;
+ input USERCLK2;
+ input USERCLK;
+ input [127:0] CFGERRAERHEADERLOG;
+ input [127:0] TRNTD;
+ input [15:0] CFGDEVID;
+ input [15:0] CFGSUBSYSID;
+ input [15:0] CFGSUBSYSVENDID;
+ input [15:0] CFGVENDID;
+ input [15:0] DRPDI;
+ input [15:0] PIPERX0DATA;
+ input [15:0] PIPERX1DATA;
+ input [15:0] PIPERX2DATA;
+ input [15:0] PIPERX3DATA;
+ input [15:0] PIPERX4DATA;
+ input [15:0] PIPERX5DATA;
+ input [15:0] PIPERX6DATA;
+ input [15:0] PIPERX7DATA;
+ input [1:0] CFGPMFORCESTATE;
+ input [1:0] DBGMODE;
+ input [1:0] PIPERX0CHARISK;
+ input [1:0] PIPERX1CHARISK;
+ input [1:0] PIPERX2CHARISK;
+ input [1:0] PIPERX3CHARISK;
+ input [1:0] PIPERX4CHARISK;
+ input [1:0] PIPERX5CHARISK;
+ input [1:0] PIPERX6CHARISK;
+ input [1:0] PIPERX7CHARISK;
+ input [1:0] PLDIRECTEDLINKCHANGE;
+ input [1:0] PLDIRECTEDLINKWIDTH;
+ input [1:0] TRNTREM;
+ input [2:0] CFGDSFUNCTIONNUMBER;
+ input [2:0] CFGFORCEMPS;
+ input [2:0] PIPERX0STATUS;
+ input [2:0] PIPERX1STATUS;
+ input [2:0] PIPERX2STATUS;
+ input [2:0] PIPERX3STATUS;
+ input [2:0] PIPERX4STATUS;
+ input [2:0] PIPERX5STATUS;
+ input [2:0] PIPERX6STATUS;
+ input [2:0] PIPERX7STATUS;
+ input [2:0] PLDBGMODE;
+ input [2:0] TRNFCSEL;
+ input [31:0] CFGMGMTDI;
+ input [31:0] TRNTDLLPDATA;
+ input [3:0] CFGMGMTBYTEENN;
+ input [47:0] CFGERRTLPCPLHEADER;
+ input [4:0] CFGAERINTERRUPTMSGNUM;
+ input [4:0] CFGDSDEVICENUMBER;
+ input [4:0] CFGPCIECAPINTERRUPTMSGNUM;
+ input [4:0] PL2DIRECTEDLSTATE;
+ input [5:0] PLDIRECTEDLTSSMNEW;
+ input [63:0] CFGDSN;
+ input [67:0] MIMRXRDATA;
+ input [68:0] MIMTXRDATA;
+ input [7:0] CFGDSBUSNUMBER;
+ input [7:0] CFGINTERRUPTDI;
+ input [7:0] CFGPORTNUMBER;
+ input [7:0] CFGREVID;
+ input [8:0] DRPADDR;
+ input [9:0] CFGMGMTDWADDR;
+endmodule
+
+module PCIE_3_0 (...);
+ parameter ARI_CAP_ENABLE = "FALSE";
+ parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE";
+ parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE";
+ parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE";
+ parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE";
+ parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000;
+ parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE";
+ parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE";
+ parameter AXISTEN_IF_RC_STRADDLE = "FALSE";
+ parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE";
+ parameter AXISTEN_IF_RQ_PARITY_CHK = "TRUE";
+ parameter [1:0] AXISTEN_IF_WIDTH = 2'h2;
+ parameter CRM_CORE_CLK_FREQ_500 = "TRUE";
+ parameter [1:0] CRM_USER_CLK_FREQ = 2'h2;
+ parameter [7:0] DNSTREAM_LINK_NUM = 8'h00;
+ parameter [1:0] GEN3_PCS_AUTO_REALIGN = 2'h1;
+ parameter GEN3_PCS_RX_ELECIDLE_INTERNAL = "TRUE";
+ parameter [8:0] LL_ACK_TIMEOUT = 9'h000;
+ parameter LL_ACK_TIMEOUT_EN = "FALSE";
+ parameter integer LL_ACK_TIMEOUT_FUNC = 0;
+ parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0000;
+ parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
+ parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0000;
+ parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
+ parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0000;
+ parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
+ parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0000;
+ parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
+ parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000;
+ parameter LL_REPLAY_TIMEOUT_EN = "FALSE";
+ parameter integer LL_REPLAY_TIMEOUT_FUNC = 0;
+ parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0FA;
+ parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE";
+ parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE";
+ parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
+ parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
+ parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000;
+ parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000;
+ parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00;
+ parameter [3:0] PF0_ARI_CAP_VER = 4'h1;
+ parameter [4:0] PF0_BAR0_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF0_BAR0_CONTROL = 3'h4;
+ parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00;
+ parameter [2:0] PF0_BAR1_CONTROL = 3'h0;
+ parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF0_BAR2_CONTROL = 3'h4;
+ parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF0_BAR3_CONTROL = 3'h0;
+ parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF0_BAR4_CONTROL = 3'h4;
+ parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF0_BAR5_CONTROL = 3'h0;
+ parameter [7:0] PF0_BIST_REGISTER = 8'h00;
+ parameter [7:0] PF0_CAPABILITY_POINTER = 8'h50;
+ parameter [23:0] PF0_CLASS_CODE = 24'h000000;
+ parameter [15:0] PF0_DEVICE_ID = 16'h0000;
+ parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE";
+ parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE";
+ parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE";
+ parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE";
+ parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE";
+ parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0;
+ parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE";
+ parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0;
+ parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0;
+ parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE";
+ parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE";
+ parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
+ parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h000;
+ parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h00;
+ parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE";
+ parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00;
+ parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00;
+ parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00;
+ parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00;
+ parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00;
+ parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00;
+ parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00;
+ parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00;
+ parameter [3:0] PF0_DPA_CAP_VER = 4'h1;
+ parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C;
+ parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
+ parameter PF0_EXPANSION_ROM_ENABLE = "FALSE";
+ parameter [7:0] PF0_INTERRUPT_LINE = 8'h00;
+ parameter [2:0] PF0_INTERRUPT_PIN = 3'h1;
+ parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0;
+ parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7;
+ parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7;
+ parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7;
+ parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7;
+ parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7;
+ parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7;
+ parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7;
+ parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7;
+ parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7;
+ parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7;
+ parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7;
+ parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7;
+ parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE";
+ parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000;
+ parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000;
+ parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000;
+ parameter [3:0] PF0_LTR_CAP_VER = 4'h1;
+ parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00;
+ parameter integer PF0_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer PF0_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00;
+ parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h000;
+ parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE";
+ parameter [3:0] PF0_PB_CAP_VER = 4'h1;
+ parameter [7:0] PF0_PM_CAP_ID = 8'h01;
+ parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00;
+ parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE";
+ parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE";
+ parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE";
+ parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE";
+ parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3;
+ parameter PF0_PM_CSR_NOSOFTRESET = "TRUE";
+ parameter PF0_RBAR_CAP_ENABLE = "FALSE";
+ parameter [2:0] PF0_RBAR_CAP_INDEX0 = 3'h0;
+ parameter [2:0] PF0_RBAR_CAP_INDEX1 = 3'h0;
+ parameter [2:0] PF0_RBAR_CAP_INDEX2 = 3'h0;
+ parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h000;
+ parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h00000;
+ parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h00000;
+ parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h00000;
+ parameter [3:0] PF0_RBAR_CAP_VER = 4'h1;
+ parameter [2:0] PF0_RBAR_NUM = 3'h1;
+ parameter [7:0] PF0_REVISION_ID = 8'h00;
+ parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4;
+ parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
+ parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0;
+ parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4;
+ parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0;
+ parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4;
+ parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0;
+ parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000;
+ parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000;
+ parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000;
+ parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1;
+ parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000;
+ parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000;
+ parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
+ parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000;
+ parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0000;
+ parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
+ parameter PF0_TPHR_CAP_ENABLE = "FALSE";
+ parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE";
+ parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0;
+ parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
+ parameter [3:0] PF0_TPHR_CAP_VER = 4'h1;
+ parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000;
+ parameter [3:0] PF0_VC_CAP_VER = 4'h1;
+ parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
+ parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
+ parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000;
+ parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000;
+ parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00;
+ parameter [4:0] PF1_BAR0_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF1_BAR0_CONTROL = 3'h4;
+ parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00;
+ parameter [2:0] PF1_BAR1_CONTROL = 3'h0;
+ parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF1_BAR2_CONTROL = 3'h4;
+ parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF1_BAR3_CONTROL = 3'h0;
+ parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF1_BAR4_CONTROL = 3'h4;
+ parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF1_BAR5_CONTROL = 3'h0;
+ parameter [7:0] PF1_BIST_REGISTER = 8'h00;
+ parameter [7:0] PF1_CAPABILITY_POINTER = 8'h50;
+ parameter [23:0] PF1_CLASS_CODE = 24'h000000;
+ parameter [15:0] PF1_DEVICE_ID = 16'h0000;
+ parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
+ parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h000;
+ parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h00;
+ parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE";
+ parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00;
+ parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00;
+ parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00;
+ parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00;
+ parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00;
+ parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00;
+ parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00;
+ parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00;
+ parameter [3:0] PF1_DPA_CAP_VER = 4'h1;
+ parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C;
+ parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
+ parameter PF1_EXPANSION_ROM_ENABLE = "FALSE";
+ parameter [7:0] PF1_INTERRUPT_LINE = 8'h00;
+ parameter [2:0] PF1_INTERRUPT_PIN = 3'h1;
+ parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00;
+ parameter integer PF1_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer PF1_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00;
+ parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h000;
+ parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE";
+ parameter [3:0] PF1_PB_CAP_VER = 4'h1;
+ parameter [7:0] PF1_PM_CAP_ID = 8'h01;
+ parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00;
+ parameter [2:0] PF1_PM_CAP_VER_ID = 3'h3;
+ parameter PF1_RBAR_CAP_ENABLE = "FALSE";
+ parameter [2:0] PF1_RBAR_CAP_INDEX0 = 3'h0;
+ parameter [2:0] PF1_RBAR_CAP_INDEX1 = 3'h0;
+ parameter [2:0] PF1_RBAR_CAP_INDEX2 = 3'h0;
+ parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h000;
+ parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h00000;
+ parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h00000;
+ parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h00000;
+ parameter [3:0] PF1_RBAR_CAP_VER = 4'h1;
+ parameter [2:0] PF1_RBAR_NUM = 3'h1;
+ parameter [7:0] PF1_REVISION_ID = 8'h00;
+ parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4;
+ parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
+ parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0;
+ parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4;
+ parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0;
+ parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4;
+ parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0;
+ parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000;
+ parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000;
+ parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000;
+ parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1;
+ parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000;
+ parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000;
+ parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
+ parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000;
+ parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0000;
+ parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
+ parameter PF1_TPHR_CAP_ENABLE = "FALSE";
+ parameter PF1_TPHR_CAP_INT_VEC_MODE = "TRUE";
+ parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'h0;
+ parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
+ parameter [3:0] PF1_TPHR_CAP_VER = 4'h1;
+ parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE";
+ parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE";
+ parameter PL_DISABLE_SCRAMBLING = "FALSE";
+ parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE";
+ parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE";
+ parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE";
+ parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02;
+ parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1;
+ parameter PL_EQ_BYPASS_PHASE23 = "FALSE";
+ parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE";
+ parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h3F00;
+ parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h3F00;
+ parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h3F00;
+ parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h3F00;
+ parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h3F00;
+ parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h3F00;
+ parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h3F00;
+ parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h3F00;
+ parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4;
+ parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h8;
+ parameter integer PL_N_FTS_COMCLK_GEN1 = 255;
+ parameter integer PL_N_FTS_COMCLK_GEN2 = 255;
+ parameter integer PL_N_FTS_COMCLK_GEN3 = 255;
+ parameter integer PL_N_FTS_GEN1 = 255;
+ parameter integer PL_N_FTS_GEN2 = 255;
+ parameter integer PL_N_FTS_GEN3 = 255;
+ parameter PL_SIM_FAST_LINK_TRAINING = "FALSE";
+ parameter PL_UPSTREAM_FACING = "TRUE";
+ parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h05DC;
+ parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h00000;
+ parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE";
+ parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000000;
+ parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h186A0;
+ parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0064;
+ parameter SIM_VERSION = "1.0";
+ parameter integer SPARE_BIT0 = 0;
+ parameter integer SPARE_BIT1 = 0;
+ parameter integer SPARE_BIT2 = 0;
+ parameter integer SPARE_BIT3 = 0;
+ parameter integer SPARE_BIT4 = 0;
+ parameter integer SPARE_BIT5 = 0;
+ parameter integer SPARE_BIT6 = 0;
+ parameter integer SPARE_BIT7 = 0;
+ parameter integer SPARE_BIT8 = 0;
+ parameter [7:0] SPARE_BYTE0 = 8'h00;
+ parameter [7:0] SPARE_BYTE1 = 8'h00;
+ parameter [7:0] SPARE_BYTE2 = 8'h00;
+ parameter [7:0] SPARE_BYTE3 = 8'h00;
+ parameter [31:0] SPARE_WORD0 = 32'h00000000;
+ parameter [31:0] SPARE_WORD1 = 32'h00000000;
+ parameter [31:0] SPARE_WORD2 = 32'h00000000;
+ parameter [31:0] SPARE_WORD3 = 32'h00000000;
+ parameter SRIOV_CAP_ENABLE = "FALSE";
+ parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'hBEBC20;
+ parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h0000000;
+ parameter [11:0] TL_CREDITS_CD = 12'h3E0;
+ parameter [7:0] TL_CREDITS_CH = 8'h20;
+ parameter [11:0] TL_CREDITS_NPD = 12'h028;
+ parameter [7:0] TL_CREDITS_NPH = 8'h20;
+ parameter [11:0] TL_CREDITS_PD = 12'h198;
+ parameter [7:0] TL_CREDITS_PH = 8'h20;
+ parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "TRUE";
+ parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE";
+ parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE";
+ parameter TL_LEGACY_MODE_ENABLE = "FALSE";
+ parameter TL_PF_ENABLE_REG = "FALSE";
+ parameter TL_TAG_MGMT_ENABLE = "TRUE";
+ parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h000;
+ parameter [7:0] VF0_CAPABILITY_POINTER = 8'h50;
+ parameter integer VF0_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer VF0_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter integer VF0_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] VF0_PM_CAP_ID = 8'h01;
+ parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h00;
+ parameter [2:0] VF0_PM_CAP_VER_ID = 3'h3;
+ parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
+ parameter VF0_TPHR_CAP_ENABLE = "FALSE";
+ parameter VF0_TPHR_CAP_INT_VEC_MODE = "TRUE";
+ parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 2'h0;
+ parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
+ parameter [3:0] VF0_TPHR_CAP_VER = 4'h1;
+ parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h000;
+ parameter integer VF1_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer VF1_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter integer VF1_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] VF1_PM_CAP_ID = 8'h01;
+ parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h00;
+ parameter [2:0] VF1_PM_CAP_VER_ID = 3'h3;
+ parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
+ parameter VF1_TPHR_CAP_ENABLE = "FALSE";
+ parameter VF1_TPHR_CAP_INT_VEC_MODE = "TRUE";
+ parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 2'h0;
+ parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
+ parameter [3:0] VF1_TPHR_CAP_VER = 4'h1;
+ parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h000;
+ parameter integer VF2_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer VF2_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter integer VF2_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] VF2_PM_CAP_ID = 8'h01;
+ parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h00;
+ parameter [2:0] VF2_PM_CAP_VER_ID = 3'h3;
+ parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
+ parameter VF2_TPHR_CAP_ENABLE = "FALSE";
+ parameter VF2_TPHR_CAP_INT_VEC_MODE = "TRUE";
+ parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 2'h0;
+ parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
+ parameter [3:0] VF2_TPHR_CAP_VER = 4'h1;
+ parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h000;
+ parameter integer VF3_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer VF3_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter integer VF3_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] VF3_PM_CAP_ID = 8'h01;
+ parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h00;
+ parameter [2:0] VF3_PM_CAP_VER_ID = 3'h3;
+ parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
+ parameter VF3_TPHR_CAP_ENABLE = "FALSE";
+ parameter VF3_TPHR_CAP_INT_VEC_MODE = "TRUE";
+ parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 2'h0;
+ parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
+ parameter [3:0] VF3_TPHR_CAP_VER = 4'h1;
+ parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h000;
+ parameter integer VF4_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer VF4_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter integer VF4_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] VF4_PM_CAP_ID = 8'h01;
+ parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h00;
+ parameter [2:0] VF4_PM_CAP_VER_ID = 3'h3;
+ parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
+ parameter VF4_TPHR_CAP_ENABLE = "FALSE";
+ parameter VF4_TPHR_CAP_INT_VEC_MODE = "TRUE";
+ parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 2'h0;
+ parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
+ parameter [3:0] VF4_TPHR_CAP_VER = 4'h1;
+ parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h000;
+ parameter integer VF5_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer VF5_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter integer VF5_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] VF5_PM_CAP_ID = 8'h01;
+ parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h00;
+ parameter [2:0] VF5_PM_CAP_VER_ID = 3'h3;
+ parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
+ parameter VF5_TPHR_CAP_ENABLE = "FALSE";
+ parameter VF5_TPHR_CAP_INT_VEC_MODE = "TRUE";
+ parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 2'h0;
+ parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
+ parameter [3:0] VF5_TPHR_CAP_VER = 4'h1;
+ output CFGERRCOROUT;
+ output CFGERRFATALOUT;
+ output CFGERRNONFATALOUT;
+ output CFGEXTREADRECEIVED;
+ output CFGEXTWRITERECEIVED;
+ output CFGHOTRESETOUT;
+ output CFGINPUTUPDATEDONE;
+ output CFGINTERRUPTAOUTPUT;
+ output CFGINTERRUPTBOUTPUT;
+ output CFGINTERRUPTCOUTPUT;
+ output CFGINTERRUPTDOUTPUT;
+ output CFGINTERRUPTMSIFAIL;
+ output CFGINTERRUPTMSIMASKUPDATE;
+ output CFGINTERRUPTMSISENT;
+ output CFGINTERRUPTMSIXFAIL;
+ output CFGINTERRUPTMSIXSENT;
+ output CFGINTERRUPTSENT;
+ output CFGLOCALERROR;
+ output CFGLTRENABLE;
+ output CFGMCUPDATEDONE;
+ output CFGMGMTREADWRITEDONE;
+ output CFGMSGRECEIVED;
+ output CFGMSGTRANSMITDONE;
+ output CFGPERFUNCTIONUPDATEDONE;
+ output CFGPHYLINKDOWN;
+ output CFGPLSTATUSCHANGE;
+ output CFGPOWERSTATECHANGEINTERRUPT;
+ output CFGTPHSTTREADENABLE;
+ output CFGTPHSTTWRITEENABLE;
+ output DRPRDY;
+ output MAXISCQTLAST;
+ output MAXISCQTVALID;
+ output MAXISRCTLAST;
+ output MAXISRCTVALID;
+ output PCIERQSEQNUMVLD;
+ output PCIERQTAGVLD;
+ output PIPERX0POLARITY;
+ output PIPERX1POLARITY;
+ output PIPERX2POLARITY;
+ output PIPERX3POLARITY;
+ output PIPERX4POLARITY;
+ output PIPERX5POLARITY;
+ output PIPERX6POLARITY;
+ output PIPERX7POLARITY;
+ output PIPETX0COMPLIANCE;
+ output PIPETX0DATAVALID;
+ output PIPETX0ELECIDLE;
+ output PIPETX0STARTBLOCK;
+ output PIPETX1COMPLIANCE;
+ output PIPETX1DATAVALID;
+ output PIPETX1ELECIDLE;
+ output PIPETX1STARTBLOCK;
+ output PIPETX2COMPLIANCE;
+ output PIPETX2DATAVALID;
+ output PIPETX2ELECIDLE;
+ output PIPETX2STARTBLOCK;
+ output PIPETX3COMPLIANCE;
+ output PIPETX3DATAVALID;
+ output PIPETX3ELECIDLE;
+ output PIPETX3STARTBLOCK;
+ output PIPETX4COMPLIANCE;
+ output PIPETX4DATAVALID;
+ output PIPETX4ELECIDLE;
+ output PIPETX4STARTBLOCK;
+ output PIPETX5COMPLIANCE;
+ output PIPETX5DATAVALID;
+ output PIPETX5ELECIDLE;
+ output PIPETX5STARTBLOCK;
+ output PIPETX6COMPLIANCE;
+ output PIPETX6DATAVALID;
+ output PIPETX6ELECIDLE;
+ output PIPETX6STARTBLOCK;
+ output PIPETX7COMPLIANCE;
+ output PIPETX7DATAVALID;
+ output PIPETX7ELECIDLE;
+ output PIPETX7STARTBLOCK;
+ output PIPETXDEEMPH;
+ output PIPETXRCVRDET;
+ output PIPETXRESET;
+ output PIPETXSWING;
+ output PLEQINPROGRESS;
+ output [11:0] CFGFCCPLD;
+ output [11:0] CFGFCNPD;
+ output [11:0] CFGFCPD;
+ output [11:0] CFGVFSTATUS;
+ output [143:0] MIREPLAYRAMWRITEDATA;
+ output [143:0] MIREQUESTRAMWRITEDATA;
+ output [15:0] CFGPERFUNCSTATUSDATA;
+ output [15:0] DBGDATAOUT;
+ output [15:0] DRPDO;
+ output [17:0] CFGVFPOWERSTATE;
+ output [17:0] CFGVFTPHSTMODE;
+ output [1:0] CFGDPASUBSTATECHANGE;
+ output [1:0] CFGFLRINPROCESS;
+ output [1:0] CFGINTERRUPTMSIENABLE;
+ output [1:0] CFGINTERRUPTMSIXENABLE;
+ output [1:0] CFGINTERRUPTMSIXMASK;
+ output [1:0] CFGLINKPOWERSTATE;
+ output [1:0] CFGOBFFENABLE;
+ output [1:0] CFGPHYLINKSTATUS;
+ output [1:0] CFGRCBSTATUS;
+ output [1:0] CFGTPHREQUESTERENABLE;
+ output [1:0] MIREPLAYRAMREADENABLE;
+ output [1:0] MIREPLAYRAMWRITEENABLE;
+ output [1:0] PCIERQTAGAV;
+ output [1:0] PCIETFCNPDAV;
+ output [1:0] PCIETFCNPHAV;
+ output [1:0] PIPERX0EQCONTROL;
+ output [1:0] PIPERX1EQCONTROL;
+ output [1:0] PIPERX2EQCONTROL;
+ output [1:0] PIPERX3EQCONTROL;
+ output [1:0] PIPERX4EQCONTROL;
+ output [1:0] PIPERX5EQCONTROL;
+ output [1:0] PIPERX6EQCONTROL;
+ output [1:0] PIPERX7EQCONTROL;
+ output [1:0] PIPETX0CHARISK;
+ output [1:0] PIPETX0EQCONTROL;
+ output [1:0] PIPETX0POWERDOWN;
+ output [1:0] PIPETX0SYNCHEADER;
+ output [1:0] PIPETX1CHARISK;
+ output [1:0] PIPETX1EQCONTROL;
+ output [1:0] PIPETX1POWERDOWN;
+ output [1:0] PIPETX1SYNCHEADER;
+ output [1:0] PIPETX2CHARISK;
+ output [1:0] PIPETX2EQCONTROL;
+ output [1:0] PIPETX2POWERDOWN;
+ output [1:0] PIPETX2SYNCHEADER;
+ output [1:0] PIPETX3CHARISK;
+ output [1:0] PIPETX3EQCONTROL;
+ output [1:0] PIPETX3POWERDOWN;
+ output [1:0] PIPETX3SYNCHEADER;
+ output [1:0] PIPETX4CHARISK;
+ output [1:0] PIPETX4EQCONTROL;
+ output [1:0] PIPETX4POWERDOWN;
+ output [1:0] PIPETX4SYNCHEADER;
+ output [1:0] PIPETX5CHARISK;
+ output [1:0] PIPETX5EQCONTROL;
+ output [1:0] PIPETX5POWERDOWN;
+ output [1:0] PIPETX5SYNCHEADER;
+ output [1:0] PIPETX6CHARISK;
+ output [1:0] PIPETX6EQCONTROL;
+ output [1:0] PIPETX6POWERDOWN;
+ output [1:0] PIPETX6SYNCHEADER;
+ output [1:0] PIPETX7CHARISK;
+ output [1:0] PIPETX7EQCONTROL;
+ output [1:0] PIPETX7POWERDOWN;
+ output [1:0] PIPETX7SYNCHEADER;
+ output [1:0] PIPETXRATE;
+ output [1:0] PLEQPHASE;
+ output [255:0] MAXISCQTDATA;
+ output [255:0] MAXISRCTDATA;
+ output [2:0] CFGCURRENTSPEED;
+ output [2:0] CFGMAXPAYLOAD;
+ output [2:0] CFGMAXREADREQ;
+ output [2:0] CFGTPHFUNCTIONNUM;
+ output [2:0] PIPERX0EQPRESET;
+ output [2:0] PIPERX1EQPRESET;
+ output [2:0] PIPERX2EQPRESET;
+ output [2:0] PIPERX3EQPRESET;
+ output [2:0] PIPERX4EQPRESET;
+ output [2:0] PIPERX5EQPRESET;
+ output [2:0] PIPERX6EQPRESET;
+ output [2:0] PIPERX7EQPRESET;
+ output [2:0] PIPETXMARGIN;
+ output [31:0] CFGEXTWRITEDATA;
+ output [31:0] CFGINTERRUPTMSIDATA;
+ output [31:0] CFGMGMTREADDATA;
+ output [31:0] CFGTPHSTTWRITEDATA;
+ output [31:0] PIPETX0DATA;
+ output [31:0] PIPETX1DATA;
+ output [31:0] PIPETX2DATA;
+ output [31:0] PIPETX3DATA;
+ output [31:0] PIPETX4DATA;
+ output [31:0] PIPETX5DATA;
+ output [31:0] PIPETX6DATA;
+ output [31:0] PIPETX7DATA;
+ output [3:0] CFGEXTWRITEBYTEENABLE;
+ output [3:0] CFGNEGOTIATEDWIDTH;
+ output [3:0] CFGTPHSTTWRITEBYTEVALID;
+ output [3:0] MICOMPLETIONRAMREADENABLEL;
+ output [3:0] MICOMPLETIONRAMREADENABLEU;
+ output [3:0] MICOMPLETIONRAMWRITEENABLEL;
+ output [3:0] MICOMPLETIONRAMWRITEENABLEU;
+ output [3:0] MIREQUESTRAMREADENABLE;
+ output [3:0] MIREQUESTRAMWRITEENABLE;
+ output [3:0] PCIERQSEQNUM;
+ output [3:0] PIPERX0EQLPTXPRESET;
+ output [3:0] PIPERX1EQLPTXPRESET;
+ output [3:0] PIPERX2EQLPTXPRESET;
+ output [3:0] PIPERX3EQLPTXPRESET;
+ output [3:0] PIPERX4EQLPTXPRESET;
+ output [3:0] PIPERX5EQLPTXPRESET;
+ output [3:0] PIPERX6EQLPTXPRESET;
+ output [3:0] PIPERX7EQLPTXPRESET;
+ output [3:0] PIPETX0EQPRESET;
+ output [3:0] PIPETX1EQPRESET;
+ output [3:0] PIPETX2EQPRESET;
+ output [3:0] PIPETX3EQPRESET;
+ output [3:0] PIPETX4EQPRESET;
+ output [3:0] PIPETX5EQPRESET;
+ output [3:0] PIPETX6EQPRESET;
+ output [3:0] PIPETX7EQPRESET;
+ output [3:0] SAXISCCTREADY;
+ output [3:0] SAXISRQTREADY;
+ output [4:0] CFGMSGRECEIVEDTYPE;
+ output [4:0] CFGTPHSTTADDRESS;
+ output [5:0] CFGFUNCTIONPOWERSTATE;
+ output [5:0] CFGINTERRUPTMSIMMENABLE;
+ output [5:0] CFGINTERRUPTMSIVFENABLE;
+ output [5:0] CFGINTERRUPTMSIXVFENABLE;
+ output [5:0] CFGINTERRUPTMSIXVFMASK;
+ output [5:0] CFGLTSSMSTATE;
+ output [5:0] CFGTPHSTMODE;
+ output [5:0] CFGVFFLRINPROCESS;
+ output [5:0] CFGVFTPHREQUESTERENABLE;
+ output [5:0] PCIECQNPREQCOUNT;
+ output [5:0] PCIERQTAG;
+ output [5:0] PIPERX0EQLPLFFS;
+ output [5:0] PIPERX1EQLPLFFS;
+ output [5:0] PIPERX2EQLPLFFS;
+ output [5:0] PIPERX3EQLPLFFS;
+ output [5:0] PIPERX4EQLPLFFS;
+ output [5:0] PIPERX5EQLPLFFS;
+ output [5:0] PIPERX6EQLPLFFS;
+ output [5:0] PIPERX7EQLPLFFS;
+ output [5:0] PIPETX0EQDEEMPH;
+ output [5:0] PIPETX1EQDEEMPH;
+ output [5:0] PIPETX2EQDEEMPH;
+ output [5:0] PIPETX3EQDEEMPH;
+ output [5:0] PIPETX4EQDEEMPH;
+ output [5:0] PIPETX5EQDEEMPH;
+ output [5:0] PIPETX6EQDEEMPH;
+ output [5:0] PIPETX7EQDEEMPH;
+ output [71:0] MICOMPLETIONRAMWRITEDATAL;
+ output [71:0] MICOMPLETIONRAMWRITEDATAU;
+ output [74:0] MAXISRCTUSER;
+ output [7:0] CFGEXTFUNCTIONNUMBER;
+ output [7:0] CFGFCCPLH;
+ output [7:0] CFGFCNPH;
+ output [7:0] CFGFCPH;
+ output [7:0] CFGFUNCTIONSTATUS;
+ output [7:0] CFGMSGRECEIVEDDATA;
+ output [7:0] MAXISCQTKEEP;
+ output [7:0] MAXISRCTKEEP;
+ output [7:0] PLGEN3PCSRXSLIDE;
+ output [84:0] MAXISCQTUSER;
+ output [8:0] MIREPLAYRAMADDRESS;
+ output [8:0] MIREQUESTRAMREADADDRESSA;
+ output [8:0] MIREQUESTRAMREADADDRESSB;
+ output [8:0] MIREQUESTRAMWRITEADDRESSA;
+ output [8:0] MIREQUESTRAMWRITEADDRESSB;
+ output [9:0] CFGEXTREGISTERNUMBER;
+ output [9:0] MICOMPLETIONRAMREADADDRESSAL;
+ output [9:0] MICOMPLETIONRAMREADADDRESSAU;
+ output [9:0] MICOMPLETIONRAMREADADDRESSBL;
+ output [9:0] MICOMPLETIONRAMREADADDRESSBU;
+ output [9:0] MICOMPLETIONRAMWRITEADDRESSAL;
+ output [9:0] MICOMPLETIONRAMWRITEADDRESSAU;
+ output [9:0] MICOMPLETIONRAMWRITEADDRESSBL;
+ output [9:0] MICOMPLETIONRAMWRITEADDRESSBU;
+ input CFGCONFIGSPACEENABLE;
+ input CFGERRCORIN;
+ input CFGERRUNCORIN;
+ input CFGEXTREADDATAVALID;
+ input CFGHOTRESETIN;
+ input CFGINPUTUPDATEREQUEST;
+ input CFGINTERRUPTMSITPHPRESENT;
+ input CFGINTERRUPTMSIXINT;
+ input CFGLINKTRAININGENABLE;
+ input CFGMCUPDATEREQUEST;
+ input CFGMGMTREAD;
+ input CFGMGMTTYPE1CFGREGACCESS;
+ input CFGMGMTWRITE;
+ input CFGMSGTRANSMIT;
+ input CFGPERFUNCTIONOUTPUTREQUEST;
+ input CFGPOWERSTATECHANGEACK;
+ input CFGREQPMTRANSITIONL23READY;
+ input CFGTPHSTTREADDATAVALID;
+ input CORECLK;
+ input CORECLKMICOMPLETIONRAML;
+ input CORECLKMICOMPLETIONRAMU;
+ input CORECLKMIREPLAYRAM;
+ input CORECLKMIREQUESTRAM;
+ input DRPCLK;
+ input DRPEN;
+ input DRPWE;
+ input MGMTRESETN;
+ input MGMTSTICKYRESETN;
+ input PCIECQNPREQ;
+ input PIPECLK;
+ input PIPERESETN;
+ input PIPERX0DATAVALID;
+ input PIPERX0ELECIDLE;
+ input PIPERX0EQDONE;
+ input PIPERX0EQLPADAPTDONE;
+ input PIPERX0EQLPLFFSSEL;
+ input PIPERX0PHYSTATUS;
+ input PIPERX0STARTBLOCK;
+ input PIPERX0VALID;
+ input PIPERX1DATAVALID;
+ input PIPERX1ELECIDLE;
+ input PIPERX1EQDONE;
+ input PIPERX1EQLPADAPTDONE;
+ input PIPERX1EQLPLFFSSEL;
+ input PIPERX1PHYSTATUS;
+ input PIPERX1STARTBLOCK;
+ input PIPERX1VALID;
+ input PIPERX2DATAVALID;
+ input PIPERX2ELECIDLE;
+ input PIPERX2EQDONE;
+ input PIPERX2EQLPADAPTDONE;
+ input PIPERX2EQLPLFFSSEL;
+ input PIPERX2PHYSTATUS;
+ input PIPERX2STARTBLOCK;
+ input PIPERX2VALID;
+ input PIPERX3DATAVALID;
+ input PIPERX3ELECIDLE;
+ input PIPERX3EQDONE;
+ input PIPERX3EQLPADAPTDONE;
+ input PIPERX3EQLPLFFSSEL;
+ input PIPERX3PHYSTATUS;
+ input PIPERX3STARTBLOCK;
+ input PIPERX3VALID;
+ input PIPERX4DATAVALID;
+ input PIPERX4ELECIDLE;
+ input PIPERX4EQDONE;
+ input PIPERX4EQLPADAPTDONE;
+ input PIPERX4EQLPLFFSSEL;
+ input PIPERX4PHYSTATUS;
+ input PIPERX4STARTBLOCK;
+ input PIPERX4VALID;
+ input PIPERX5DATAVALID;
+ input PIPERX5ELECIDLE;
+ input PIPERX5EQDONE;
+ input PIPERX5EQLPADAPTDONE;
+ input PIPERX5EQLPLFFSSEL;
+ input PIPERX5PHYSTATUS;
+ input PIPERX5STARTBLOCK;
+ input PIPERX5VALID;
+ input PIPERX6DATAVALID;
+ input PIPERX6ELECIDLE;
+ input PIPERX6EQDONE;
+ input PIPERX6EQLPADAPTDONE;
+ input PIPERX6EQLPLFFSSEL;
+ input PIPERX6PHYSTATUS;
+ input PIPERX6STARTBLOCK;
+ input PIPERX6VALID;
+ input PIPERX7DATAVALID;
+ input PIPERX7ELECIDLE;
+ input PIPERX7EQDONE;
+ input PIPERX7EQLPADAPTDONE;
+ input PIPERX7EQLPLFFSSEL;
+ input PIPERX7PHYSTATUS;
+ input PIPERX7STARTBLOCK;
+ input PIPERX7VALID;
+ input PIPETX0EQDONE;
+ input PIPETX1EQDONE;
+ input PIPETX2EQDONE;
+ input PIPETX3EQDONE;
+ input PIPETX4EQDONE;
+ input PIPETX5EQDONE;
+ input PIPETX6EQDONE;
+ input PIPETX7EQDONE;
+ input PLDISABLESCRAMBLER;
+ input PLEQRESETEIEOSCOUNT;
+ input PLGEN3PCSDISABLE;
+ input RECCLK;
+ input RESETN;
+ input SAXISCCTLAST;
+ input SAXISCCTVALID;
+ input SAXISRQTLAST;
+ input SAXISRQTVALID;
+ input USERCLK;
+ input [10:0] DRPADDR;
+ input [143:0] MICOMPLETIONRAMREADDATA;
+ input [143:0] MIREPLAYRAMREADDATA;
+ input [143:0] MIREQUESTRAMREADDATA;
+ input [15:0] CFGDEVID;
+ input [15:0] CFGSUBSYSID;
+ input [15:0] CFGSUBSYSVENDID;
+ input [15:0] CFGVENDID;
+ input [15:0] DRPDI;
+ input [17:0] PIPERX0EQLPNEWTXCOEFFORPRESET;
+ input [17:0] PIPERX1EQLPNEWTXCOEFFORPRESET;
+ input [17:0] PIPERX2EQLPNEWTXCOEFFORPRESET;
+ input [17:0] PIPERX3EQLPNEWTXCOEFFORPRESET;
+ input [17:0] PIPERX4EQLPNEWTXCOEFFORPRESET;
+ input [17:0] PIPERX5EQLPNEWTXCOEFFORPRESET;
+ input [17:0] PIPERX6EQLPNEWTXCOEFFORPRESET;
+ input [17:0] PIPERX7EQLPNEWTXCOEFFORPRESET;
+ input [17:0] PIPETX0EQCOEFF;
+ input [17:0] PIPETX1EQCOEFF;
+ input [17:0] PIPETX2EQCOEFF;
+ input [17:0] PIPETX3EQCOEFF;
+ input [17:0] PIPETX4EQCOEFF;
+ input [17:0] PIPETX5EQCOEFF;
+ input [17:0] PIPETX6EQCOEFF;
+ input [17:0] PIPETX7EQCOEFF;
+ input [18:0] CFGMGMTADDR;
+ input [1:0] CFGFLRDONE;
+ input [1:0] CFGINTERRUPTMSITPHTYPE;
+ input [1:0] CFGINTERRUPTPENDING;
+ input [1:0] PIPERX0CHARISK;
+ input [1:0] PIPERX0SYNCHEADER;
+ input [1:0] PIPERX1CHARISK;
+ input [1:0] PIPERX1SYNCHEADER;
+ input [1:0] PIPERX2CHARISK;
+ input [1:0] PIPERX2SYNCHEADER;
+ input [1:0] PIPERX3CHARISK;
+ input [1:0] PIPERX3SYNCHEADER;
+ input [1:0] PIPERX4CHARISK;
+ input [1:0] PIPERX4SYNCHEADER;
+ input [1:0] PIPERX5CHARISK;
+ input [1:0] PIPERX5SYNCHEADER;
+ input [1:0] PIPERX6CHARISK;
+ input [1:0] PIPERX6SYNCHEADER;
+ input [1:0] PIPERX7CHARISK;
+ input [1:0] PIPERX7SYNCHEADER;
+ input [21:0] MAXISCQTREADY;
+ input [21:0] MAXISRCTREADY;
+ input [255:0] SAXISCCTDATA;
+ input [255:0] SAXISRQTDATA;
+ input [2:0] CFGDSFUNCTIONNUMBER;
+ input [2:0] CFGFCSEL;
+ input [2:0] CFGINTERRUPTMSIATTR;
+ input [2:0] CFGINTERRUPTMSIFUNCTIONNUMBER;
+ input [2:0] CFGMSGTRANSMITTYPE;
+ input [2:0] CFGPERFUNCSTATUSCONTROL;
+ input [2:0] CFGPERFUNCTIONNUMBER;
+ input [2:0] PIPERX0STATUS;
+ input [2:0] PIPERX1STATUS;
+ input [2:0] PIPERX2STATUS;
+ input [2:0] PIPERX3STATUS;
+ input [2:0] PIPERX4STATUS;
+ input [2:0] PIPERX5STATUS;
+ input [2:0] PIPERX6STATUS;
+ input [2:0] PIPERX7STATUS;
+ input [31:0] CFGEXTREADDATA;
+ input [31:0] CFGINTERRUPTMSIINT;
+ input [31:0] CFGINTERRUPTMSIXDATA;
+ input [31:0] CFGMGMTWRITEDATA;
+ input [31:0] CFGMSGTRANSMITDATA;
+ input [31:0] CFGTPHSTTREADDATA;
+ input [31:0] PIPERX0DATA;
+ input [31:0] PIPERX1DATA;
+ input [31:0] PIPERX2DATA;
+ input [31:0] PIPERX3DATA;
+ input [31:0] PIPERX4DATA;
+ input [31:0] PIPERX5DATA;
+ input [31:0] PIPERX6DATA;
+ input [31:0] PIPERX7DATA;
+ input [32:0] SAXISCCTUSER;
+ input [3:0] CFGINTERRUPTINT;
+ input [3:0] CFGINTERRUPTMSISELECT;
+ input [3:0] CFGMGMTBYTEENABLE;
+ input [4:0] CFGDSDEVICENUMBER;
+ input [59:0] SAXISRQTUSER;
+ input [5:0] CFGVFFLRDONE;
+ input [5:0] PIPEEQFS;
+ input [5:0] PIPEEQLF;
+ input [63:0] CFGDSN;
+ input [63:0] CFGINTERRUPTMSIPENDINGSTATUS;
+ input [63:0] CFGINTERRUPTMSIXADDRESS;
+ input [7:0] CFGDSBUSNUMBER;
+ input [7:0] CFGDSPORTNUMBER;
+ input [7:0] CFGREVID;
+ input [7:0] PLGEN3PCSRXSYNCDONE;
+ input [7:0] SAXISCCTKEEP;
+ input [7:0] SAXISRQTKEEP;
+ input [8:0] CFGINTERRUPTMSITPHSTTAG;
+endmodule
+
+module XADC (...);
+ parameter [15:0] INIT_40 = 16'h0;
+ parameter [15:0] INIT_41 = 16'h0;
+ parameter [15:0] INIT_42 = 16'h0800;
+ parameter [15:0] INIT_43 = 16'h0;
+ parameter [15:0] INIT_44 = 16'h0;
+ parameter [15:0] INIT_45 = 16'h0;
+ parameter [15:0] INIT_46 = 16'h0;
+ parameter [15:0] INIT_47 = 16'h0;
+ parameter [15:0] INIT_48 = 16'h0;
+ parameter [15:0] INIT_49 = 16'h0;
+ parameter [15:0] INIT_4A = 16'h0;
+ parameter [15:0] INIT_4B = 16'h0;
+ parameter [15:0] INIT_4C = 16'h0;
+ parameter [15:0] INIT_4D = 16'h0;
+ parameter [15:0] INIT_4E = 16'h0;
+ parameter [15:0] INIT_4F = 16'h0;
+ parameter [15:0] INIT_50 = 16'h0;
+ parameter [15:0] INIT_51 = 16'h0;
+ parameter [15:0] INIT_52 = 16'h0;
+ parameter [15:0] INIT_53 = 16'h0;
+ parameter [15:0] INIT_54 = 16'h0;
+ parameter [15:0] INIT_55 = 16'h0;
+ parameter [15:0] INIT_56 = 16'h0;
+ parameter [15:0] INIT_57 = 16'h0;
+ parameter [15:0] INIT_58 = 16'h0;
+ parameter [15:0] INIT_59 = 16'h0;
+ parameter [15:0] INIT_5A = 16'h0;
+ parameter [15:0] INIT_5B = 16'h0;
+ parameter [15:0] INIT_5C = 16'h0;
+ parameter [15:0] INIT_5D = 16'h0;
+ parameter [15:0] INIT_5E = 16'h0;
+ parameter [15:0] INIT_5F = 16'h0;
+ parameter IS_CONVSTCLK_INVERTED = 1'b0;
+ parameter IS_DCLK_INVERTED = 1'b0;
parameter SIM_DEVICE = "7SERIES";
- parameter USE_IBUFDISABLE = "TRUE";
- output O;
- input I;
- input IBUFDISABLE;
-endmodule
-
-module IBUF_INTERMDISABLE (...);
- parameter IBUF_LOW_PWR = "TRUE";
- parameter IOSTANDARD = "DEFAULT";
- parameter SIM_DEVICE = "7SERIES";
- parameter USE_IBUFDISABLE = "TRUE";
- output O;
- input I;
- input IBUFDISABLE;
- input INTERMDISABLE;
-endmodule
-
-module IBUFDS (...);
- parameter CAPACITANCE = "DONT_CARE";
- parameter DIFF_TERM = "FALSE";
- parameter DQS_BIAS = "FALSE";
- parameter IBUF_DELAY_VALUE = "0";
- parameter IBUF_LOW_PWR = "TRUE";
- parameter IFD_DELAY_VALUE = "AUTO";
- parameter IOSTANDARD = "DEFAULT";
- output O;
- input I, IB;
-endmodule
-
-module IBUFDS_DIFF_OUT (...);
- parameter DIFF_TERM = "FALSE";
- parameter DQS_BIAS = "FALSE";
- parameter IBUF_LOW_PWR = "TRUE";
- parameter IOSTANDARD = "DEFAULT";
- output O, OB;
- input I, IB;
-endmodule
-
-module IBUFDS_DIFF_OUT_IBUFDISABLE (...);
- parameter DIFF_TERM = "FALSE";
- parameter DQS_BIAS = "FALSE";
- parameter IBUF_LOW_PWR = "TRUE";
- parameter IOSTANDARD = "DEFAULT";
- parameter SIM_DEVICE = "7SERIES";
- parameter USE_IBUFDISABLE = "TRUE";
- output O;
- output OB;
- input I;
- input IB;
- input IBUFDISABLE;
-endmodule
-
-module IBUFDS_DIFF_OUT_INTERMDISABLE (...);
- parameter DIFF_TERM = "FALSE";
- parameter DQS_BIAS = "FALSE";
- parameter IBUF_LOW_PWR = "TRUE";
- parameter IOSTANDARD = "DEFAULT";
- parameter SIM_DEVICE = "7SERIES";
- parameter USE_IBUFDISABLE = "TRUE";
- output O;
- output OB;
- input I;
- input IB;
- input IBUFDISABLE;
- input INTERMDISABLE;
-endmodule
-
-module IBUFDS_GTE2 (...);
- parameter CLKCM_CFG = "TRUE";
- parameter CLKRCV_TRST = "TRUE";
- parameter CLKSWING_CFG = "TRUE";
- output O;
- output ODIV2;
- input CEB;
- input I;
- input IB;
-endmodule
-
-module IBUFDS_IBUFDISABLE (...);
- parameter DIFF_TERM = "FALSE";
- parameter DQS_BIAS = "FALSE";
- parameter IBUF_LOW_PWR = "TRUE";
- parameter IOSTANDARD = "DEFAULT";
- parameter SIM_DEVICE = "7SERIES";
- parameter USE_IBUFDISABLE = "TRUE";
- output O;
- input I;
- input IB;
- input IBUFDISABLE;
-endmodule
-
-module IBUFDS_INTERMDISABLE (...);
- parameter DIFF_TERM = "FALSE";
- parameter DQS_BIAS = "FALSE";
- parameter IBUF_LOW_PWR = "TRUE";
- parameter IOSTANDARD = "DEFAULT";
- parameter SIM_DEVICE = "7SERIES";
- parameter USE_IBUFDISABLE = "TRUE";
- output O;
- input I;
- input IB;
- input IBUFDISABLE;
- input INTERMDISABLE;
-endmodule
-
-(* keep *)
-module ICAPE2 (...);
- parameter [31:0] DEVICE_ID = 32'h04244093;
- parameter ICAP_WIDTH = "X32";
- parameter SIM_CFG_FILE_NAME = "NONE";
- output [31:0] O;
- input CLK;
- input CSIB;
- input RDWRB;
- input [31:0] I;
-endmodule
-
-module IDDR (...);
- parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
- parameter INIT_Q1 = 1'b0;
- parameter INIT_Q2 = 1'b0;
- parameter [0:0] IS_C_INVERTED = 1'b0;
- parameter [0:0] IS_D_INVERTED = 1'b0;
- parameter SRTYPE = "SYNC";
- parameter MSGON = "TRUE";
- parameter XON = "TRUE";
- output Q1;
- output Q2;
- input C;
- input CE;
- input D;
- input R;
- input S;
-endmodule
-
-module IDDR_2CLK (...);
- parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
- parameter INIT_Q1 = 1'b0;
- parameter INIT_Q2 = 1'b0;
- parameter [0:0] IS_CB_INVERTED = 1'b0;
- parameter [0:0] IS_C_INVERTED = 1'b0;
- parameter [0:0] IS_D_INVERTED = 1'b0;
- parameter SRTYPE = "SYNC";
- output Q1;
- output Q2;
- input C;
- input CB;
- input CE;
- input D;
- input R;
- input S;
-endmodule
-
-(* keep *)
-module IDELAYCTRL (...);
- parameter SIM_DEVICE = "7SERIES";
- output RDY;
- input REFCLK;
- input RST;
-endmodule
-
-module IDELAYE2 (...);
- parameter CINVCTRL_SEL = "FALSE";
- parameter DELAY_SRC = "IDATAIN";
- parameter HIGH_PERFORMANCE_MODE = "FALSE";
- parameter IDELAY_TYPE = "FIXED";
- parameter integer IDELAY_VALUE = 0;
- parameter [0:0] IS_C_INVERTED = 1'b0;
- parameter [0:0] IS_DATAIN_INVERTED = 1'b0;
- parameter [0:0] IS_IDATAIN_INVERTED = 1'b0;
- parameter PIPE_SEL = "FALSE";
- parameter real REFCLK_FREQUENCY = 200.0;
- parameter SIGNAL_PATTERN = "DATA";
- parameter integer SIM_DELAY_D = 0;
- output [4:0] CNTVALUEOUT;
- output DATAOUT;
- input C;
- input CE;
- input CINVCTRL;
- input [4:0] CNTVALUEIN;
- input DATAIN;
- input IDATAIN;
- input INC;
- input LD;
- input LDPIPEEN;
- input REGRST;
-endmodule
-
-module IN_FIFO (...);
- parameter integer ALMOST_EMPTY_VALUE = 1;
- parameter integer ALMOST_FULL_VALUE = 1;
- parameter ARRAY_MODE = "ARRAY_MODE_4_X_8";
- parameter SYNCHRONOUS_MODE = "FALSE";
- output ALMOSTEMPTY;
- output ALMOSTFULL;
- output EMPTY;
- output FULL;
- output [7:0] Q0;
- output [7:0] Q1;
- output [7:0] Q2;
- output [7:0] Q3;
- output [7:0] Q4;
- output [7:0] Q5;
- output [7:0] Q6;
- output [7:0] Q7;
- output [7:0] Q8;
- output [7:0] Q9;
- input RDCLK;
- input RDEN;
+ parameter SIM_MONITOR_FILE = "design.txt";
+ output BUSY;
+ output DRDY;
+ output EOC;
+ output EOS;
+ output JTAGBUSY;
+ output JTAGLOCKED;
+ output JTAGMODIFIED;
+ output OT;
+ output [15:0] DO;
+ output [7:0] ALM;
+ output [4:0] CHANNEL;
+ output [4:0] MUXADDR;
+ input CONVST;
+ (* invertible_pin = "IS_CONVSTCLK_INVERTED" *)
+ input CONVSTCLK;
+ (* invertible_pin = "IS_DCLK_INVERTED" *)
+ input DCLK;
+ input DEN;
+ input DWE;
input RESET;
- input WRCLK;
- input WREN;
- input [3:0] D0;
- input [3:0] D1;
- input [3:0] D2;
- input [3:0] D3;
- input [3:0] D4;
- input [3:0] D7;
- input [3:0] D8;
- input [3:0] D9;
- input [7:0] D5;
- input [7:0] D6;
+ input VN;
+ input VP;
+ input [15:0] DI;
+ input [15:0] VAUXN;
+ input [15:0] VAUXP;
+ input [6:0] DADDR;
endmodule
-module IOBUF (...);
- parameter integer DRIVE = 12;
- parameter IBUF_LOW_PWR = "TRUE";
- parameter IOSTANDARD = "DEFAULT";
- parameter SLEW = "SLOW";
- output O;
- inout IO;
- input I, T;
-endmodule
-
-module IOBUF_DCIEN (...);
- parameter integer DRIVE = 12;
- parameter IBUF_LOW_PWR = "TRUE";
- parameter IOSTANDARD = "DEFAULT";
- parameter SIM_DEVICE = "7SERIES";
- parameter SLEW = "SLOW";
- parameter USE_IBUFDISABLE = "TRUE";
- output O;
- inout IO;
- input DCITERMDISABLE;
- input I;
- input IBUFDISABLE;
- input T;
-endmodule
-
-module IOBUF_INTERMDISABLE (...);
- parameter integer DRIVE = 12;
- parameter IBUF_LOW_PWR = "TRUE";
- parameter IOSTANDARD = "DEFAULT";
- parameter SIM_DEVICE = "7SERIES";
- parameter SLEW = "SLOW";
- parameter USE_IBUFDISABLE = "TRUE";
- output O;
- inout IO;
- input I;
- input IBUFDISABLE;
- input INTERMDISABLE;
- input T;
-endmodule
-
-module IOBUFDS (...);
- parameter DIFF_TERM = "FALSE";
- parameter DQS_BIAS = "FALSE";
- parameter IBUF_LOW_PWR = "TRUE";
- parameter IOSTANDARD = "DEFAULT";
- parameter SLEW = "SLOW";
- output O;
- inout IO, IOB;
- input I, T;
-endmodule
-
-module IOBUFDS_DCIEN (...);
- parameter DIFF_TERM = "FALSE";
- parameter DQS_BIAS = "FALSE";
- parameter IBUF_LOW_PWR = "TRUE";
- parameter IOSTANDARD = "DEFAULT";
- parameter SIM_DEVICE = "7SERIES";
- parameter SLEW = "SLOW";
- parameter USE_IBUFDISABLE = "TRUE";
- output O;
- inout IO;
- inout IOB;
- input DCITERMDISABLE;
- input I;
- input IBUFDISABLE;
- input T;
-endmodule
-
-module IOBUFDS_DIFF_OUT (...);
- parameter DIFF_TERM = "FALSE";
- parameter DQS_BIAS = "FALSE";
- parameter IBUF_LOW_PWR = "TRUE";
- parameter IOSTANDARD = "DEFAULT";
- output O;
- output OB;
- inout IO;
- inout IOB;
- input I;
- input TM;
- input TS;
-endmodule
-
-module IOBUFDS_DIFF_OUT_DCIEN (...);
- parameter DIFF_TERM = "FALSE";
- parameter DQS_BIAS = "FALSE";
- parameter IBUF_LOW_PWR = "TRUE";
- parameter IOSTANDARD = "DEFAULT";
- parameter SIM_DEVICE = "7SERIES";
- parameter USE_IBUFDISABLE = "TRUE";
- output O;
- output OB;
- inout IO;
- inout IOB;
- input DCITERMDISABLE;
- input I;
- input IBUFDISABLE;
- input TM;
- input TS;
-endmodule
-
-module IOBUFDS_DIFF_OUT_INTERMDISABLE (...);
- parameter DIFF_TERM = "FALSE";
- parameter DQS_BIAS = "FALSE";
- parameter IBUF_LOW_PWR = "TRUE";
- parameter IOSTANDARD = "DEFAULT";
- parameter SIM_DEVICE = "7SERIES";
- parameter USE_IBUFDISABLE = "TRUE";
- output O;
- output OB;
- inout IO;
- inout IOB;
- input I;
- input IBUFDISABLE;
- input INTERMDISABLE;
- input TM;
- input TS;
-endmodule
-
-module ISERDESE2 (...);
- parameter DATA_RATE = "DDR";
- parameter integer DATA_WIDTH = 4;
- parameter DYN_CLKDIV_INV_EN = "FALSE";
- parameter DYN_CLK_INV_EN = "FALSE";
- parameter [0:0] INIT_Q1 = 1'b0;
- parameter [0:0] INIT_Q2 = 1'b0;
- parameter [0:0] INIT_Q3 = 1'b0;
- parameter [0:0] INIT_Q4 = 1'b0;
- parameter INTERFACE_TYPE = "MEMORY";
- parameter IOBDELAY = "NONE";
- parameter [0:0] IS_CLKB_INVERTED = 1'b0;
- parameter [0:0] IS_CLKDIVP_INVERTED = 1'b0;
- parameter [0:0] IS_CLKDIV_INVERTED = 1'b0;
+module DSP48E1 (...);
+ parameter integer ACASCREG = 1;
+ parameter integer ADREG = 1;
+ parameter integer ALUMODEREG = 1;
+ parameter integer AREG = 1;
+ parameter AUTORESET_PATDET = "NO_RESET";
+ parameter A_INPUT = "DIRECT";
+ parameter integer BCASCREG = 1;
+ parameter integer BREG = 1;
+ parameter B_INPUT = "DIRECT";
+ parameter integer CARRYINREG = 1;
+ parameter integer CARRYINSELREG = 1;
+ parameter integer CREG = 1;
+ parameter integer DREG = 1;
+ parameter integer INMODEREG = 1;
+ parameter integer MREG = 1;
+ parameter integer OPMODEREG = 1;
+ parameter integer PREG = 1;
+ parameter SEL_MASK = "MASK";
+ parameter SEL_PATTERN = "PATTERN";
+ parameter USE_DPORT = "FALSE";
+ parameter USE_MULT = "MULTIPLY";
+ parameter USE_PATTERN_DETECT = "NO_PATDET";
+ parameter USE_SIMD = "ONE48";
+ parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
+ parameter [47:0] PATTERN = 48'h000000000000;
+ parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
+ parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
- parameter [0:0] IS_D_INVERTED = 1'b0;
- parameter [0:0] IS_OCLKB_INVERTED = 1'b0;
- parameter [0:0] IS_OCLK_INVERTED = 1'b0;
- parameter integer NUM_CE = 2;
- parameter OFB_USED = "FALSE";
- parameter SERDES_MODE = "MASTER";
- parameter [0:0] SRVAL_Q1 = 1'b0;
- parameter [0:0] SRVAL_Q2 = 1'b0;
- parameter [0:0] SRVAL_Q3 = 1'b0;
- parameter [0:0] SRVAL_Q4 = 1'b0;
- output O;
- output Q1;
- output Q2;
- output Q3;
- output Q4;
- output Q5;
- output Q6;
- output Q7;
- output Q8;
- output SHIFTOUT1;
- output SHIFTOUT2;
- input BITSLIP;
- input CE1;
- input CE2;
+ parameter [4:0] IS_INMODE_INVERTED = 5'b0;
+ parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
+ output [29:0] ACOUT;
+ output [17:0] BCOUT;
+ output CARRYCASCOUT;
+ output [3:0] CARRYOUT;
+ output MULTSIGNOUT;
+ output OVERFLOW;
+ output [47:0] P;
+ output PATTERNBDETECT;
+ output PATTERNDETECT;
+ output [47:0] PCOUT;
+ output UNDERFLOW;
+ input [29:0] A;
+ input [29:0] ACIN;
+ (* invertible_pin = "IS_ALUMODE_INVERTED" *)
+ input [3:0] ALUMODE;
+ input [17:0] B;
+ input [17:0] BCIN;
+ input [47:0] C;
+ input CARRYCASCIN;
+ (* invertible_pin = "IS_CARRYIN_INVERTED" *)
+ input CARRYIN;
+ input [2:0] CARRYINSEL;
+ input CEA1;
+ input CEA2;
+ input CEAD;
+ input CEALUMODE;
+ input CEB1;
+ input CEB2;
+ input CEC;
+ input CECARRYIN;
+ input CECTRL;
+ input CED;
+ input CEINMODE;
+ input CEM;
+ input CEP;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLK_INVERTED" *)
input CLK;
- input CLKB;
- input CLKDIV;
- input CLKDIVP;
- input D;
- input DDLY;
- input DYNCLKDIVSEL;
- input DYNCLKSEL;
- input OCLK;
- input OCLKB;
- input OFB;
- input RST;
- input SHIFTIN1;
- input SHIFTIN2;
+ input [24:0] D;
+ (* invertible_pin = "IS_INMODE_INVERTED" *)
+ input [4:0] INMODE;
+ input MULTSIGNIN;
+ (* invertible_pin = "IS_OPMODE_INVERTED" *)
+ input [6:0] OPMODE;
+ input [47:0] PCIN;
+ input RSTA;
+ input RSTALLCARRYIN;
+ input RSTALUMODE;
+ input RSTB;
+ input RSTC;
+ input RSTCTRL;
+ input RSTD;
+ input RSTINMODE;
+ input RSTM;
+ input RSTP;
endmodule
-module KEEPER (...);
- inout O;
+module BUFGCE (...);
+ parameter CE_TYPE = "SYNC";
+ parameter [0:0] IS_CE_INVERTED = 1'b0;
+ parameter [0:0] IS_I_INVERTED = 1'b0;
+ (* clkbuf_driver *)
+ output O;
+ (* invertible_pin = "IS_CE_INVERTED" *)
+ input CE;
+ (* invertible_pin = "IS_I_INVERTED" *)
+ input I;
endmodule
-module LDCE (...);
- parameter [0:0] INIT = 1'b0;
- parameter [0:0] IS_CLR_INVERTED = 1'b0;
- parameter [0:0] IS_G_INVERTED = 1'b0;
- parameter MSGON = "TRUE";
- parameter XON = "TRUE";
- output Q;
- input CLR, D, G, GE;
+module BUFGCE_1 (...);
+ (* clkbuf_driver *)
+ output O;
+ input CE;
+ input I;
endmodule
-module LDPE (...);
- parameter [0:0] INIT = 1'b1;
- parameter [0:0] IS_G_INVERTED = 1'b0;
- parameter [0:0] IS_PRE_INVERTED = 1'b0;
- parameter MSGON = "TRUE";
- parameter XON = "TRUE";
- output Q;
- input D, G, GE, PRE;
+module BUFGMUX (...);
+ parameter CLK_SEL_TYPE = "SYNC";
+ (* clkbuf_driver *)
+ output O;
+ input I0;
+ input I1;
+ input S;
+endmodule
+
+module BUFGMUX_1 (...);
+ parameter CLK_SEL_TYPE = "SYNC";
+ (* clkbuf_driver *)
+ output O;
+ input I0;
+ input I1;
+ input S;
+endmodule
+
+module BUFGMUX_CTRL (...);
+ (* clkbuf_driver *)
+ output O;
+ input I0;
+ input I1;
+ input S;
+endmodule
+
+module BUFH (...);
+ (* clkbuf_driver *)
+ output O;
+ input I;
+endmodule
+
+module BUFIO (...);
+ (* clkbuf_driver *)
+ output O;
+ input I;
+endmodule
+
+module BUFMR (...);
+ (* clkbuf_driver *)
+ output O;
+ input I;
+endmodule
+
+module BUFMRCE (...);
+ parameter CE_TYPE = "SYNC";
+ parameter integer INIT_OUT = 0;
+ parameter [0:0] IS_CE_INVERTED = 1'b0;
+ (* clkbuf_driver *)
+ output O;
+ (* invertible_pin = "IS_CE_INVERTED" *)
+ input CE;
+ input I;
+endmodule
+
+module BUFR (...);
+ parameter BUFR_DIVIDE = "BYPASS";
+ parameter SIM_DEVICE = "7SERIES";
+ (* clkbuf_driver *)
+ output O;
+ input CE;
+ input CLR;
+ input I;
endmodule
module MMCME2_ADV (...);
@@ -2466,6 +3626,7 @@ module MMCME2_ADV (...);
input CLKFBIN;
input CLKIN1;
input CLKIN2;
+ (* invertible_pin = "IS_CLKINSEL_INVERTED" *)
input CLKINSEL;
input [6:0] DADDR;
input DCLK;
@@ -2473,9 +3634,13 @@ module MMCME2_ADV (...);
input [15:0] DI;
input DWE;
input PSCLK;
+ (* invertible_pin = "IS_PSEN_INVERTED" *)
input PSEN;
+ (* invertible_pin = "IS_PSINCDEC_INVERTED" *)
input PSINCDEC;
+ (* invertible_pin = "IS_PWRDWN_INVERTED" *)
input PWRDWN;
+ (* invertible_pin = "IS_RST_INVERTED" *)
input RST;
endmodule
@@ -2529,11 +3694,678 @@ module MMCME2_BASE (...);
input RST;
endmodule
+module PLLE2_ADV (...);
+ parameter BANDWIDTH = "OPTIMIZED";
+ parameter COMPENSATION = "ZHOLD";
+ parameter STARTUP_WAIT = "FALSE";
+ parameter integer CLKOUT0_DIVIDE = 1;
+ parameter integer CLKOUT1_DIVIDE = 1;
+ parameter integer CLKOUT2_DIVIDE = 1;
+ parameter integer CLKOUT3_DIVIDE = 1;
+ parameter integer CLKOUT4_DIVIDE = 1;
+ parameter integer CLKOUT5_DIVIDE = 1;
+ parameter integer DIVCLK_DIVIDE = 1;
+ parameter integer CLKFBOUT_MULT = 5;
+ parameter real CLKFBOUT_PHASE = 0.000;
+ parameter real CLKIN1_PERIOD = 0.000;
+ parameter real CLKIN2_PERIOD = 0.000;
+ parameter real CLKOUT0_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT0_PHASE = 0.000;
+ parameter real CLKOUT1_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT1_PHASE = 0.000;
+ parameter real CLKOUT2_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT2_PHASE = 0.000;
+ parameter real CLKOUT3_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT3_PHASE = 0.000;
+ parameter real CLKOUT4_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT4_PHASE = 0.000;
+ parameter real CLKOUT5_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT5_PHASE = 0.000;
+ parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0;
+ parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_INVERTED = 1'b0;
+ parameter real REF_JITTER1 = 0.010;
+ parameter real REF_JITTER2 = 0.010;
+ parameter real VCOCLK_FREQ_MAX = 2133.000;
+ parameter real VCOCLK_FREQ_MIN = 800.000;
+ parameter real CLKIN_FREQ_MAX = 1066.000;
+ parameter real CLKIN_FREQ_MIN = 19.000;
+ parameter real CLKPFD_FREQ_MAX = 550.0;
+ parameter real CLKPFD_FREQ_MIN = 19.0;
+ output CLKFBOUT;
+ output CLKOUT0;
+ output CLKOUT1;
+ output CLKOUT2;
+ output CLKOUT3;
+ output CLKOUT4;
+ output CLKOUT5;
+ output DRDY;
+ output LOCKED;
+ output [15:0] DO;
+ input CLKFBIN;
+ input CLKIN1;
+ input CLKIN2;
+ (* invertible_pin = "IS_CLKINSEL_INVERTED" *)
+ input CLKINSEL;
+ input DCLK;
+ input DEN;
+ input DWE;
+ (* invertible_pin = "IS_PWRDWN_INVERTED" *)
+ input PWRDWN;
+ (* invertible_pin = "IS_RST_INVERTED" *)
+ input RST;
+ input [15:0] DI;
+ input [6:0] DADDR;
+endmodule
+
+module PLLE2_BASE (...);
+ parameter BANDWIDTH = "OPTIMIZED";
+ parameter integer CLKFBOUT_MULT = 5;
+ parameter real CLKFBOUT_PHASE = 0.000;
+ parameter real CLKIN1_PERIOD = 0.000;
+ parameter integer CLKOUT0_DIVIDE = 1;
+ parameter real CLKOUT0_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT0_PHASE = 0.000;
+ parameter integer CLKOUT1_DIVIDE = 1;
+ parameter real CLKOUT1_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT1_PHASE = 0.000;
+ parameter integer CLKOUT2_DIVIDE = 1;
+ parameter real CLKOUT2_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT2_PHASE = 0.000;
+ parameter integer CLKOUT3_DIVIDE = 1;
+ parameter real CLKOUT3_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT3_PHASE = 0.000;
+ parameter integer CLKOUT4_DIVIDE = 1;
+ parameter real CLKOUT4_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT4_PHASE = 0.000;
+ parameter integer CLKOUT5_DIVIDE = 1;
+ parameter real CLKOUT5_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT5_PHASE = 0.000;
+ parameter integer DIVCLK_DIVIDE = 1;
+ parameter real REF_JITTER1 = 0.010;
+ parameter STARTUP_WAIT = "FALSE";
+ output CLKFBOUT;
+ output CLKOUT0;
+ output CLKOUT1;
+ output CLKOUT2;
+ output CLKOUT3;
+ output CLKOUT4;
+ output CLKOUT5;
+ output LOCKED;
+ input CLKFBIN;
+ input CLKIN1;
+ input PWRDWN;
+ input RST;
+endmodule
+
+(* keep *)
+module BSCANE2 (...);
+ parameter DISABLE_JTAG = "FALSE";
+ parameter integer JTAG_CHAIN = 1;
+ output CAPTURE;
+ output DRCK;
+ output RESET;
+ output RUNTEST;
+ output SEL;
+ output SHIFT;
+ output TCK;
+ output TDI;
+ output TMS;
+ output UPDATE;
+ input TDO;
+endmodule
+
+(* keep *)
+module CAPTUREE2 (...);
+ parameter ONESHOT = "TRUE";
+ input CAP;
+ input CLK;
+endmodule
+
+module DNA_PORT (...);
+ parameter [56:0] SIM_DNA_VALUE = 57'h0;
+ output DOUT;
+ input CLK;
+ input DIN;
+ input READ;
+ input SHIFT;
+endmodule
+
+module EFUSE_USR (...);
+ parameter [31:0] SIM_EFUSE_VALUE = 32'h00000000;
+ output [31:0] EFUSEUSR;
+endmodule
+
+module FRAME_ECCE2 (...);
+ parameter FARSRC = "EFAR";
+ parameter FRAME_RBT_IN_FILENAME = "NONE";
+ output CRCERROR;
+ output ECCERROR;
+ output ECCERRORSINGLE;
+ output SYNDROMEVALID;
+ output [12:0] SYNDROME;
+ output [25:0] FAR;
+ output [4:0] SYNBIT;
+ output [6:0] SYNWORD;
+endmodule
+
+(* keep *)
+module ICAPE2 (...);
+ parameter [31:0] DEVICE_ID = 32'h04244093;
+ parameter ICAP_WIDTH = "X32";
+ parameter SIM_CFG_FILE_NAME = "NONE";
+ output [31:0] O;
+ input CLK;
+ input CSIB;
+ input RDWRB;
+ input [31:0] I;
+endmodule
+
+(* keep *)
+module STARTUPE2 (...);
+ parameter PROG_USR = "FALSE";
+ parameter real SIM_CCLK_FREQ = 0.0;
+ output CFGCLK;
+ output CFGMCLK;
+ output EOS;
+ output PREQ;
+ input CLK;
+ input GSR;
+ input GTS;
+ input KEYCLEARB;
+ input PACK;
+ input USRCCLKO;
+ input USRCCLKTS;
+ input USRDONEO;
+ input USRDONETS;
+endmodule
+
+module USR_ACCESSE2 (...);
+ output CFGCLK;
+ output DATAVALID;
+ output [31:0] DATA;
+endmodule
+
+(* keep *)
+module DCIRESET (...);
+ output LOCKED;
+ input RST;
+endmodule
+
+module IBUF_IBUFDISABLE (...);
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ (* iopad_external_pin *)
+ input I;
+ input IBUFDISABLE;
+endmodule
+
+module IBUF_INTERMDISABLE (...);
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ (* iopad_external_pin *)
+ input I;
+ input IBUFDISABLE;
+ input INTERMDISABLE;
+endmodule
+
+module IBUFDS (...);
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_DELAY_VALUE = "0";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IFD_DELAY_VALUE = "AUTO";
+ parameter IOSTANDARD = "DEFAULT";
+ output O;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+endmodule
+
+module IBUFDS_DIFF_OUT (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ output O;
+ output OB;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+endmodule
+
+module IBUFDS_DIFF_OUT_IBUFDISABLE (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ output OB;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+ input IBUFDISABLE;
+endmodule
+
+module IBUFDS_DIFF_OUT_INTERMDISABLE (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ output OB;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+ input IBUFDISABLE;
+ input INTERMDISABLE;
+endmodule
+
+module IBUFDS_GTE2 (...);
+ parameter CLKCM_CFG = "TRUE";
+ parameter CLKRCV_TRST = "TRUE";
+ parameter CLKSWING_CFG = "TRUE";
+ output O;
+ output ODIV2;
+ input CEB;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+endmodule
+
+module IBUFDS_IBUFDISABLE (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+ input IBUFDISABLE;
+endmodule
+
+module IBUFDS_INTERMDISABLE (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+ input IBUFDISABLE;
+ input INTERMDISABLE;
+endmodule
+
+module IBUFG (...);
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter IBUF_DELAY_VALUE = "0";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ output O;
+ (* iopad_external_pin *)
+ input I;
+endmodule
+
+module IBUFGDS (...);
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter DIFF_TERM = "FALSE";
+ parameter IBUF_DELAY_VALUE = "0";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ output O;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+endmodule
+
+module IBUFGDS_DIFF_OUT (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ output O;
+ output OB;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+endmodule
+
+(* keep *)
+module IDELAYCTRL (...);
+ parameter SIM_DEVICE = "7SERIES";
+ output RDY;
+ (* clkbuf_sink *)
+ input REFCLK;
+ input RST;
+endmodule
+
+module IDELAYE2 (...);
+ parameter CINVCTRL_SEL = "FALSE";
+ parameter DELAY_SRC = "IDATAIN";
+ parameter HIGH_PERFORMANCE_MODE = "FALSE";
+ parameter IDELAY_TYPE = "FIXED";
+ parameter integer IDELAY_VALUE = 0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_DATAIN_INVERTED = 1'b0;
+ parameter [0:0] IS_IDATAIN_INVERTED = 1'b0;
+ parameter PIPE_SEL = "FALSE";
+ parameter real REFCLK_FREQUENCY = 200.0;
+ parameter SIGNAL_PATTERN = "DATA";
+ parameter integer SIM_DELAY_D = 0;
+ output [4:0] CNTVALUEOUT;
+ output DATAOUT;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C;
+ input CE;
+ input CINVCTRL;
+ input [4:0] CNTVALUEIN;
+ (* invertible_pin = "IS_DATAIN_INVERTED" *)
+ input DATAIN;
+ (* invertible_pin = "IS_IDATAIN_INVERTED" *)
+ input IDATAIN;
+ input INC;
+ input LD;
+ input LDPIPEEN;
+ input REGRST;
+endmodule
+
+module IN_FIFO (...);
+ parameter integer ALMOST_EMPTY_VALUE = 1;
+ parameter integer ALMOST_FULL_VALUE = 1;
+ parameter ARRAY_MODE = "ARRAY_MODE_4_X_8";
+ parameter SYNCHRONOUS_MODE = "FALSE";
+ output ALMOSTEMPTY;
+ output ALMOSTFULL;
+ output EMPTY;
+ output FULL;
+ output [7:0] Q0;
+ output [7:0] Q1;
+ output [7:0] Q2;
+ output [7:0] Q3;
+ output [7:0] Q4;
+ output [7:0] Q5;
+ output [7:0] Q6;
+ output [7:0] Q7;
+ output [7:0] Q8;
+ output [7:0] Q9;
+ (* clkbuf_sink *)
+ input RDCLK;
+ input RDEN;
+ input RESET;
+ (* clkbuf_sink *)
+ input WRCLK;
+ input WREN;
+ input [3:0] D0;
+ input [3:0] D1;
+ input [3:0] D2;
+ input [3:0] D3;
+ input [3:0] D4;
+ input [3:0] D7;
+ input [3:0] D8;
+ input [3:0] D9;
+ input [7:0] D5;
+ input [7:0] D6;
+endmodule
+
+module IOBUF (...);
+ parameter integer DRIVE = 12;
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SLEW = "SLOW";
+ output O;
+ (* iopad_external_pin *)
+ inout IO;
+ input I;
+ input T;
+endmodule
+
+module IOBUF_DCIEN (...);
+ parameter integer DRIVE = 12;
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter SLEW = "SLOW";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ (* iopad_external_pin *)
+ inout IO;
+ input DCITERMDISABLE;
+ input I;
+ input IBUFDISABLE;
+ input T;
+endmodule
+
+module IOBUF_INTERMDISABLE (...);
+ parameter integer DRIVE = 12;
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter SLEW = "SLOW";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ (* iopad_external_pin *)
+ inout IO;
+ input I;
+ input IBUFDISABLE;
+ input INTERMDISABLE;
+ input T;
+endmodule
+
+module IOBUFDS (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SLEW = "SLOW";
+ output O;
+ (* iopad_external_pin *)
+ inout IO;
+ inout IOB;
+ input I;
+ input T;
+endmodule
+
+module IOBUFDS_DCIEN (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter SLEW = "SLOW";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ (* iopad_external_pin *)
+ inout IO;
+ (* iopad_external_pin *)
+ inout IOB;
+ input DCITERMDISABLE;
+ input I;
+ input IBUFDISABLE;
+ input T;
+endmodule
+
+module IOBUFDS_DIFF_OUT (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ output O;
+ output OB;
+ (* iopad_external_pin *)
+ inout IO;
+ (* iopad_external_pin *)
+ inout IOB;
+ input I;
+ input TM;
+ input TS;
+endmodule
+
+module IOBUFDS_DIFF_OUT_DCIEN (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ output OB;
+ (* iopad_external_pin *)
+ inout IO;
+ (* iopad_external_pin *)
+ inout IOB;
+ input DCITERMDISABLE;
+ input I;
+ input IBUFDISABLE;
+ input TM;
+ input TS;
+endmodule
+
+module IOBUFDS_DIFF_OUT_INTERMDISABLE (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ output OB;
+ (* iopad_external_pin *)
+ inout IO;
+ (* iopad_external_pin *)
+ inout IOB;
+ input I;
+ input IBUFDISABLE;
+ input INTERMDISABLE;
+ input TM;
+ input TS;
+endmodule
+
+module IOBUFDS_INTERMDISABLE (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter SLEW = "SLOW";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ (* iopad_external_pin *)
+ inout IO;
+ (* iopad_external_pin *)
+ inout IOB;
+ input I;
+ input IBUFDISABLE;
+ input INTERMDISABLE;
+ input T;
+endmodule
+
+module ISERDESE2 (...);
+ parameter DATA_RATE = "DDR";
+ parameter integer DATA_WIDTH = 4;
+ parameter DYN_CLKDIV_INV_EN = "FALSE";
+ parameter DYN_CLK_INV_EN = "FALSE";
+ parameter [0:0] INIT_Q1 = 1'b0;
+ parameter [0:0] INIT_Q2 = 1'b0;
+ parameter [0:0] INIT_Q3 = 1'b0;
+ parameter [0:0] INIT_Q4 = 1'b0;
+ parameter INTERFACE_TYPE = "MEMORY";
+ parameter IOBDELAY = "NONE";
+ parameter [0:0] IS_CLKB_INVERTED = 1'b0;
+ parameter [0:0] IS_CLKDIVP_INVERTED = 1'b0;
+ parameter [0:0] IS_CLKDIV_INVERTED = 1'b0;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_OCLKB_INVERTED = 1'b0;
+ parameter [0:0] IS_OCLK_INVERTED = 1'b0;
+ parameter integer NUM_CE = 2;
+ parameter OFB_USED = "FALSE";
+ parameter SERDES_MODE = "MASTER";
+ parameter [0:0] SRVAL_Q1 = 1'b0;
+ parameter [0:0] SRVAL_Q2 = 1'b0;
+ parameter [0:0] SRVAL_Q3 = 1'b0;
+ parameter [0:0] SRVAL_Q4 = 1'b0;
+ output O;
+ output Q1;
+ output Q2;
+ output Q3;
+ output Q4;
+ output Q5;
+ output Q6;
+ output Q7;
+ output Q8;
+ output SHIFTOUT1;
+ output SHIFTOUT2;
+ input BITSLIP;
+ input CE1;
+ input CE2;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLK_INVERTED" *)
+ input CLK;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLKB_INVERTED" *)
+ input CLKB;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLKDIV_INVERTED" *)
+ input CLKDIV;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLKDIVP_INVERTED" *)
+ input CLKDIVP;
+ (* invertible_pin = "IS_D_INVERTED" *)
+ input D;
+ input DDLY;
+ input DYNCLKDIVSEL;
+ input DYNCLKSEL;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_OCLK_INVERTED" *)
+ input OCLK;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_OCLKB_INVERTED" *)
+ input OCLKB;
+ input OFB;
+ input RST;
+ input SHIFTIN1;
+ input SHIFTIN2;
+endmodule
+
+module KEEPER (...);
+ inout O;
+endmodule
+
module OBUFDS (...);
parameter CAPACITANCE = "DONT_CARE";
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
- output O, OB;
+ (* iopad_external_pin *)
+ output O;
+ (* iopad_external_pin *)
+ output OB;
input I;
endmodule
@@ -2542,34 +4374,22 @@ module OBUFT (...);
parameter integer DRIVE = 12;
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
+ (* iopad_external_pin *)
output O;
- input I, T;
+ input I;
+ input T;
endmodule
module OBUFTDS (...);
parameter CAPACITANCE = "DONT_CARE";
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
- output O, OB;
- input I, T;
-endmodule
-
-module ODDR (...);
- output Q;
- input C;
- input CE;
- input D1;
- input D2;
- input R;
- input S;
- parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
- parameter INIT = 1'b0;
- parameter [0:0] IS_C_INVERTED = 1'b0;
- parameter [0:0] IS_D1_INVERTED = 1'b0;
- parameter [0:0] IS_D2_INVERTED = 1'b0;
- parameter SRTYPE = "SYNC";
- parameter MSGON = "TRUE";
- parameter XON = "TRUE";
+ (* iopad_external_pin *)
+ output O;
+ (* iopad_external_pin *)
+ output OB;
+ input I;
+ input T;
endmodule
module ODELAYE2 (...);
@@ -2586,6 +4406,8 @@ module ODELAYE2 (...);
parameter integer SIM_DELAY_D = 0;
output [4:0] CNTVALUEOUT;
output DATAOUT;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
input C;
input CE;
input CINVCTRL;
@@ -2594,6 +4416,7 @@ module ODELAYE2 (...);
input INC;
input LD;
input LDPIPEEN;
+ (* invertible_pin = "IS_ODATAIN_INVERTED" *)
input ODATAIN;
input REGRST;
endmodule
@@ -2631,23 +4454,39 @@ module OSERDESE2 (...);
output TBYTEOUT;
output TFB;
output TQ;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLK_INVERTED" *)
input CLK;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLKDIV_INVERTED" *)
input CLKDIV;
+ (* invertible_pin = "IS_D1_INVERTED" *)
input D1;
+ (* invertible_pin = "IS_D2_INVERTED" *)
input D2;
+ (* invertible_pin = "IS_D3_INVERTED" *)
input D3;
+ (* invertible_pin = "IS_D4_INVERTED" *)
input D4;
+ (* invertible_pin = "IS_D5_INVERTED" *)
input D5;
+ (* invertible_pin = "IS_D6_INVERTED" *)
input D6;
+ (* invertible_pin = "IS_D7_INVERTED" *)
input D7;
+ (* invertible_pin = "IS_D8_INVERTED" *)
input D8;
input OCE;
input RST;
input SHIFTIN1;
input SHIFTIN2;
+ (* invertible_pin = "IS_T1_INVERTED" *)
input T1;
+ (* invertible_pin = "IS_T2_INVERTED" *)
input T2;
+ (* invertible_pin = "IS_T3_INVERTED" *)
input T3;
+ (* invertible_pin = "IS_T4_INVERTED" *)
input T4;
input TBYTEIN;
input TCE;
@@ -2673,9 +4512,11 @@ module OUT_FIFO (...);
output [3:0] Q9;
output [7:0] Q5;
output [7:0] Q6;
+ (* clkbuf_sink *)
input RDCLK;
input RDEN;
input RESET;
+ (* clkbuf_sink *)
input WRCLK;
input WREN;
input [7:0] D0;
@@ -2718,6 +4559,7 @@ module PHASER_IN (...);
input FREQREFCLK;
input MEMREFCLK;
input PHASEREFCLK;
+ (* invertible_pin = "IS_RST_INVERTED" *)
input RST;
input SYNCIN;
input SYSCLK;
@@ -2759,6 +4601,7 @@ module PHASER_IN_PHY (...);
input FREQREFCLK;
input MEMREFCLK;
input PHASEREFCLK;
+ (* invertible_pin = "IS_RST_INVERTED" *)
input RST;
input RSTDQSFIND;
input SYNCIN;
@@ -2801,6 +4644,7 @@ module PHASER_OUT (...);
input FREQREFCLK;
input MEMREFCLK;
input PHASEREFCLK;
+ (* invertible_pin = "IS_RST_INVERTED" *)
input RST;
input SELFINEOCLKDELAY;
input SYNCIN;
@@ -2845,6 +4689,7 @@ module PHASER_OUT_PHY (...);
input FREQREFCLK;
input MEMREFCLK;
input PHASEREFCLK;
+ (* invertible_pin = "IS_RST_INVERTED" *)
input RST;
input SELFINEOCLKDELAY;
input SYNCIN;
@@ -2858,7 +4703,9 @@ module PHASER_REF (...);
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
output LOCKED;
input CLKIN;
+ (* invertible_pin = "IS_PWRDWN_INVERTED" *)
input PWRDWN;
+ (* invertible_pin = "IS_RST_INVERTED" *)
input RST;
endmodule
@@ -2922,105 +4769,454 @@ module PHY_CONTROL (...);
input [31:0] PHYCTLWD;
endmodule
-module PLLE2_ADV (...);
- parameter BANDWIDTH = "OPTIMIZED";
- parameter COMPENSATION = "ZHOLD";
- parameter STARTUP_WAIT = "FALSE";
- parameter integer CLKOUT0_DIVIDE = 1;
- parameter integer CLKOUT1_DIVIDE = 1;
- parameter integer CLKOUT2_DIVIDE = 1;
- parameter integer CLKOUT3_DIVIDE = 1;
- parameter integer CLKOUT4_DIVIDE = 1;
- parameter integer CLKOUT5_DIVIDE = 1;
- parameter integer DIVCLK_DIVIDE = 1;
- parameter integer CLKFBOUT_MULT = 5;
- parameter real CLKFBOUT_PHASE = 0.000;
- parameter real CLKIN1_PERIOD = 0.000;
- parameter real CLKIN2_PERIOD = 0.000;
- parameter real CLKOUT0_DUTY_CYCLE = 0.500;
- parameter real CLKOUT0_PHASE = 0.000;
- parameter real CLKOUT1_DUTY_CYCLE = 0.500;
- parameter real CLKOUT1_PHASE = 0.000;
- parameter real CLKOUT2_DUTY_CYCLE = 0.500;
- parameter real CLKOUT2_PHASE = 0.000;
- parameter real CLKOUT3_DUTY_CYCLE = 0.500;
- parameter real CLKOUT3_PHASE = 0.000;
- parameter real CLKOUT4_DUTY_CYCLE = 0.500;
- parameter real CLKOUT4_PHASE = 0.000;
- parameter real CLKOUT5_DUTY_CYCLE = 0.500;
- parameter real CLKOUT5_PHASE = 0.000;
- parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0;
- parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
- parameter [0:0] IS_RST_INVERTED = 1'b0;
- parameter real REF_JITTER1 = 0.010;
- parameter real REF_JITTER2 = 0.010;
- parameter real VCOCLK_FREQ_MAX = 2133.000;
- parameter real VCOCLK_FREQ_MIN = 800.000;
- parameter real CLKIN_FREQ_MAX = 1066.000;
- parameter real CLKIN_FREQ_MIN = 19.000;
- parameter real CLKPFD_FREQ_MAX = 550.0;
- parameter real CLKPFD_FREQ_MIN = 19.0;
- output CLKFBOUT;
- output CLKOUT0;
- output CLKOUT1;
- output CLKOUT2;
- output CLKOUT3;
- output CLKOUT4;
- output CLKOUT5;
- output DRDY;
- output LOCKED;
- output [15:0] DO;
- input CLKFBIN;
- input CLKIN1;
- input CLKIN2;
- input CLKINSEL;
- input DCLK;
- input DEN;
- input DWE;
- input PWRDWN;
- input RST;
- input [15:0] DI;
- input [6:0] DADDR;
+module PULLDOWN (...);
+ output O;
endmodule
-module PLLE2_BASE (...);
- parameter BANDWIDTH = "OPTIMIZED";
- parameter integer CLKFBOUT_MULT = 5;
- parameter real CLKFBOUT_PHASE = 0.000;
- parameter real CLKIN1_PERIOD = 0.000;
- parameter integer CLKOUT0_DIVIDE = 1;
- parameter real CLKOUT0_DUTY_CYCLE = 0.500;
- parameter real CLKOUT0_PHASE = 0.000;
- parameter integer CLKOUT1_DIVIDE = 1;
- parameter real CLKOUT1_DUTY_CYCLE = 0.500;
- parameter real CLKOUT1_PHASE = 0.000;
- parameter integer CLKOUT2_DIVIDE = 1;
- parameter real CLKOUT2_DUTY_CYCLE = 0.500;
- parameter real CLKOUT2_PHASE = 0.000;
- parameter integer CLKOUT3_DIVIDE = 1;
- parameter real CLKOUT3_DUTY_CYCLE = 0.500;
- parameter real CLKOUT3_PHASE = 0.000;
- parameter integer CLKOUT4_DIVIDE = 1;
- parameter real CLKOUT4_DUTY_CYCLE = 0.500;
- parameter real CLKOUT4_PHASE = 0.000;
- parameter integer CLKOUT5_DIVIDE = 1;
- parameter real CLKOUT5_DUTY_CYCLE = 0.500;
- parameter real CLKOUT5_PHASE = 0.000;
- parameter integer DIVCLK_DIVIDE = 1;
- parameter real REF_JITTER1 = 0.010;
- parameter STARTUP_WAIT = "FALSE";
- output CLKFBOUT;
- output CLKOUT0;
- output CLKOUT1;
- output CLKOUT2;
- output CLKOUT3;
- output CLKOUT4;
- output CLKOUT5;
- output LOCKED;
- input CLKFBIN;
- input CLKIN1;
- input PWRDWN;
+module PULLUP (...);
+ output O;
+endmodule
+
+module FIFO18E1 (...);
+ parameter ALMOST_EMPTY_OFFSET = 13'h0080;
+ parameter ALMOST_FULL_OFFSET = 13'h0080;
+ parameter integer DATA_WIDTH = 4;
+ parameter integer DO_REG = 1;
+ parameter EN_SYN = "FALSE";
+ parameter FIFO_MODE = "FIFO18";
+ parameter FIRST_WORD_FALL_THROUGH = "FALSE";
+ parameter INIT = 36'h0;
+ parameter SIM_DEVICE = "VIRTEX6";
+ parameter SRVAL = 36'h0;
+ parameter IS_RDCLK_INVERTED = 1'b0;
+ parameter IS_RDEN_INVERTED = 1'b0;
+ parameter IS_RSTREG_INVERTED = 1'b0;
+ parameter IS_RST_INVERTED = 1'b0;
+ parameter IS_WRCLK_INVERTED = 1'b0;
+ parameter IS_WREN_INVERTED = 1'b0;
+ output ALMOSTEMPTY;
+ output ALMOSTFULL;
+ output [31:0] DO;
+ output [3:0] DOP;
+ output EMPTY;
+ output FULL;
+ output [11:0] RDCOUNT;
+ output RDERR;
+ output [11:0] WRCOUNT;
+ output WRERR;
+ input [31:0] DI;
+ input [3:0] DIP;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_RDCLK_INVERTED" *)
+ input RDCLK;
+ (* invertible_pin = "IS_RDEN_INVERTED" *)
+ input RDEN;
+ input REGCE;
+ (* invertible_pin = "IS_RST_INVERTED" *)
input RST;
+ (* invertible_pin = "IS_RSTREG_INVERTED" *)
+ input RSTREG;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WRCLK_INVERTED" *)
+ input WRCLK;
+ (* invertible_pin = "IS_WREN_INVERTED" *)
+ input WREN;
+endmodule
+
+module FIFO36E1 (...);
+ parameter ALMOST_EMPTY_OFFSET = 13'h0080;
+ parameter ALMOST_FULL_OFFSET = 13'h0080;
+ parameter integer DATA_WIDTH = 4;
+ parameter integer DO_REG = 1;
+ parameter EN_ECC_READ = "FALSE";
+ parameter EN_ECC_WRITE = "FALSE";
+ parameter EN_SYN = "FALSE";
+ parameter FIFO_MODE = "FIFO36";
+ parameter FIRST_WORD_FALL_THROUGH = "FALSE";
+ parameter INIT = 72'h0;
+ parameter SIM_DEVICE = "VIRTEX6";
+ parameter SRVAL = 72'h0;
+ parameter IS_RDCLK_INVERTED = 1'b0;
+ parameter IS_RDEN_INVERTED = 1'b0;
+ parameter IS_RSTREG_INVERTED = 1'b0;
+ parameter IS_RST_INVERTED = 1'b0;
+ parameter IS_WRCLK_INVERTED = 1'b0;
+ parameter IS_WREN_INVERTED = 1'b0;
+ output ALMOSTEMPTY;
+ output ALMOSTFULL;
+ output DBITERR;
+ output [63:0] DO;
+ output [7:0] DOP;
+ output [7:0] ECCPARITY;
+ output EMPTY;
+ output FULL;
+ output [12:0] RDCOUNT;
+ output RDERR;
+ output SBITERR;
+ output [12:0] WRCOUNT;
+ output WRERR;
+ input [63:0] DI;
+ input [7:0] DIP;
+ input INJECTDBITERR;
+ input INJECTSBITERR;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_RDCLK_INVERTED" *)
+ input RDCLK;
+ (* invertible_pin = "IS_RDEN_INVERTED" *)
+ input RDEN;
+ input REGCE;
+ (* invertible_pin = "IS_RST_INVERTED" *)
+ input RST;
+ (* invertible_pin = "IS_RSTREG_INVERTED" *)
+ input RSTREG;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WRCLK_INVERTED" *)
+ input WRCLK;
+ (* invertible_pin = "IS_WREN_INVERTED" *)
+ input WREN;
+endmodule
+
+module RAM128X1S (...);
+ parameter [127:0] INIT = 128'h00000000000000000000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input A5;
+ input A6;
+ input D;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM256X1S (...);
+ parameter [255:0] INIT = 256'h0;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O;
+ input [7:0] A;
+ input D;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM32M (...);
+ parameter [63:0] INIT_A = 64'h0000000000000000;
+ parameter [63:0] INIT_B = 64'h0000000000000000;
+ parameter [63:0] INIT_C = 64'h0000000000000000;
+ parameter [63:0] INIT_D = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output [1:0] DOA;
+ output [1:0] DOB;
+ output [1:0] DOC;
+ output [1:0] DOD;
+ input [4:0] ADDRA;
+ input [4:0] ADDRB;
+ input [4:0] ADDRC;
+ input [4:0] ADDRD;
+ input [1:0] DIA;
+ input [1:0] DIB;
+ input [1:0] DIC;
+ input [1:0] DID;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM32X1S (...);
+ parameter [31:0] INIT = 32'h00000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input D;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM32X1S_1 (...);
+ parameter [31:0] INIT = 32'h00000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input D;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM32X2S (...);
+ parameter [31:0] INIT_00 = 32'h00000000;
+ parameter [31:0] INIT_01 = 32'h00000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O0;
+ output O1;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input D0;
+ input D1;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM64M (...);
+ parameter [63:0] INIT_A = 64'h0000000000000000;
+ parameter [63:0] INIT_B = 64'h0000000000000000;
+ parameter [63:0] INIT_C = 64'h0000000000000000;
+ parameter [63:0] INIT_D = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output DOA;
+ output DOB;
+ output DOC;
+ output DOD;
+ input [5:0] ADDRA;
+ input [5:0] ADDRB;
+ input [5:0] ADDRC;
+ input [5:0] ADDRD;
+ input DIA;
+ input DIB;
+ input DIC;
+ input DID;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM64X1S (...);
+ parameter [63:0] INIT = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input A5;
+ input D;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM64X1S_1 (...);
+ parameter [63:0] INIT = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input A5;
+ input D;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM64X2S (...);
+ parameter [63:0] INIT_00 = 64'h0000000000000000;
+ parameter [63:0] INIT_01 = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O0;
+ output O1;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input A5;
+ input D0;
+ input D1;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module ROM128X1 (...);
+ parameter [127:0] INIT = 128'h00000000000000000000000000000000;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input A5;
+ input A6;
+endmodule
+
+module ROM256X1 (...);
+ parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input A5;
+ input A6;
+ input A7;
+endmodule
+
+module ROM32X1 (...);
+ parameter [31:0] INIT = 32'h00000000;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+endmodule
+
+module ROM64X1 (...);
+ parameter [63:0] INIT = 64'h0000000000000000;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input A5;
+endmodule
+
+module IDDR (...);
+ parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
+ parameter INIT_Q1 = 1'b0;
+ parameter INIT_Q2 = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter SRTYPE = "SYNC";
+ parameter MSGON = "TRUE";
+ parameter XON = "TRUE";
+ output Q1;
+ output Q2;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C;
+ input CE;
+ (* invertible_pin = "IS_D_INVERTED" *)
+ input D;
+ input R;
+ input S;
+endmodule
+
+module IDDR_2CLK (...);
+ parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
+ parameter INIT_Q1 = 1'b0;
+ parameter INIT_Q2 = 1'b0;
+ parameter [0:0] IS_CB_INVERTED = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter SRTYPE = "SYNC";
+ output Q1;
+ output Q2;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CB_INVERTED" *)
+ input CB;
+ input CE;
+ (* invertible_pin = "IS_D_INVERTED" *)
+ input D;
+ input R;
+ input S;
+endmodule
+
+module LDCE (...);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_CLR_INVERTED = 1'b0;
+ parameter [0:0] IS_G_INVERTED = 1'b0;
+ parameter MSGON = "TRUE";
+ parameter XON = "TRUE";
+ output Q;
+ (* invertible_pin = "IS_CLR_INVERTED" *)
+ input CLR;
+ input D;
+ (* invertible_pin = "IS_G_INVERTED" *)
+ input G;
+ input GE;
+endmodule
+
+module LDPE (...);
+ parameter [0:0] INIT = 1'b1;
+ parameter [0:0] IS_G_INVERTED = 1'b0;
+ parameter [0:0] IS_PRE_INVERTED = 1'b0;
+ parameter MSGON = "TRUE";
+ parameter XON = "TRUE";
+ output Q;
+ input D;
+ (* invertible_pin = "IS_G_INVERTED" *)
+ input G;
+ input GE;
+ (* invertible_pin = "IS_PRE_INVERTED" *)
+ input PRE;
+endmodule
+
+module ODDR (...);
+ parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
+ parameter INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D1_INVERTED = 1'b0;
+ parameter [0:0] IS_D2_INVERTED = 1'b0;
+ parameter SRTYPE = "SYNC";
+ parameter MSGON = "TRUE";
+ parameter XON = "TRUE";
+ output Q;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C;
+ input CE;
+ (* invertible_pin = "IS_D1_INVERTED" *)
+ input D1;
+ (* invertible_pin = "IS_D2_INVERTED" *)
+ input D2;
+ input R;
+ input S;
+endmodule
+
+module CFGLUT5 (...);
+ parameter [31:0] INIT = 32'h00000000;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ output CDO;
+ output O5;
+ output O6;
+ input I4;
+ input I3;
+ input I2;
+ input I1;
+ input I0;
+ input CDI;
+ input CE;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLK_INVERTED" *)
+ input CLK;
endmodule
(* keep *)
@@ -3647,228 +5843,3 @@ module PS7 (...);
input [7:0] SAXIHP3WSTRB;
endmodule
-module PULLDOWN (...);
- output O;
-endmodule
-
-module PULLUP (...);
- output O;
-endmodule
-
-module RAM128X1S (...);
- parameter [127:0] INIT = 128'h00000000000000000000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE;
-endmodule
-
-module RAM256X1S (...);
- parameter [255:0] INIT = 256'h0;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input [7:0] A;
- input D;
- input WCLK;
- input WE;
-endmodule
-
-module RAM32M (...);
- parameter [63:0] INIT_A = 64'h0000000000000000;
- parameter [63:0] INIT_B = 64'h0000000000000000;
- parameter [63:0] INIT_C = 64'h0000000000000000;
- parameter [63:0] INIT_D = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output [1:0] DOA;
- output [1:0] DOB;
- output [1:0] DOC;
- output [1:0] DOD;
- input [4:0] ADDRA;
- input [4:0] ADDRB;
- input [4:0] ADDRC;
- input [4:0] ADDRD;
- input [1:0] DIA;
- input [1:0] DIB;
- input [1:0] DIC;
- input [1:0] DID;
- input WCLK;
- input WE;
-endmodule
-
-module RAM32X1S (...);
- parameter [31:0] INIT = 32'h00000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0, A1, A2, A3, A4, D, WCLK, WE;
-endmodule
-
-module RAM32X1S_1 (...);
- parameter [31:0] INIT = 32'h00000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0, A1, A2, A3, A4, D, WCLK, WE;
-endmodule
-
-module RAM32X2S (...);
- parameter [31:0] INIT_00 = 32'h00000000;
- parameter [31:0] INIT_01 = 32'h00000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O0, O1;
- input A0, A1, A2, A3, A4, D0, D1, WCLK, WE;
-endmodule
-
-module RAM64M (...);
- parameter [63:0] INIT_A = 64'h0000000000000000;
- parameter [63:0] INIT_B = 64'h0000000000000000;
- parameter [63:0] INIT_C = 64'h0000000000000000;
- parameter [63:0] INIT_D = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output DOA;
- output DOB;
- output DOC;
- output DOD;
- input [5:0] ADDRA;
- input [5:0] ADDRB;
- input [5:0] ADDRC;
- input [5:0] ADDRD;
- input DIA;
- input DIB;
- input DIC;
- input DID;
- input WCLK;
- input WE;
-endmodule
-
-module RAM64X1S (...);
- parameter [63:0] INIT = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0, A1, A2, A3, A4, A5, D, WCLK, WE;
-endmodule
-
-module RAM64X1S_1 (...);
- parameter [63:0] INIT = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0, A1, A2, A3, A4, A5, D, WCLK, WE;
-endmodule
-
-module RAM64X2S (...);
- parameter [63:0] INIT_00 = 64'h0000000000000000;
- parameter [63:0] INIT_01 = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O0, O1;
- input A0, A1, A2, A3, A4, A5, D0, D1, WCLK, WE;
-endmodule
-
-module ROM128X1 (...);
- parameter [127:0] INIT = 128'h00000000000000000000000000000000;
- output O;
- input A0, A1, A2, A3, A4, A5, A6;
-endmodule
-
-module ROM256X1 (...);
- parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- output O;
- input A0, A1, A2, A3, A4, A5, A6, A7;
-endmodule
-
-module ROM32X1 (...);
- parameter [31:0] INIT = 32'h00000000;
- output O;
- input A0, A1, A2, A3, A4;
-endmodule
-
-module ROM64X1 (...);
- parameter [63:0] INIT = 64'h0000000000000000;
- output O;
- input A0, A1, A2, A3, A4, A5;
-endmodule
-
-(* keep *)
-module STARTUPE2 (...);
- parameter PROG_USR = "FALSE";
- parameter real SIM_CCLK_FREQ = 0.0;
- output CFGCLK;
- output CFGMCLK;
- output EOS;
- output PREQ;
- input CLK;
- input GSR;
- input GTS;
- input KEYCLEARB;
- input PACK;
- input USRCCLKO;
- input USRCCLKTS;
- input USRDONEO;
- input USRDONETS;
-endmodule
-
-module USR_ACCESSE2 (...);
- output CFGCLK;
- output DATAVALID;
- output [31:0] DATA;
-endmodule
-
-module XADC (...);
- output BUSY;
- output DRDY;
- output EOC;
- output EOS;
- output JTAGBUSY;
- output JTAGLOCKED;
- output JTAGMODIFIED;
- output OT;
- output [15:0] DO;
- output [7:0] ALM;
- output [4:0] CHANNEL;
- output [4:0] MUXADDR;
- input CONVST;
- input CONVSTCLK;
- input DCLK;
- input DEN;
- input DWE;
- input RESET;
- input VN;
- input VP;
- input [15:0] DI;
- input [15:0] VAUXN;
- input [15:0] VAUXP;
- input [6:0] DADDR;
- parameter [15:0] INIT_40 = 16'h0;
- parameter [15:0] INIT_41 = 16'h0;
- parameter [15:0] INIT_42 = 16'h0800;
- parameter [15:0] INIT_43 = 16'h0;
- parameter [15:0] INIT_44 = 16'h0;
- parameter [15:0] INIT_45 = 16'h0;
- parameter [15:0] INIT_46 = 16'h0;
- parameter [15:0] INIT_47 = 16'h0;
- parameter [15:0] INIT_48 = 16'h0;
- parameter [15:0] INIT_49 = 16'h0;
- parameter [15:0] INIT_4A = 16'h0;
- parameter [15:0] INIT_4B = 16'h0;
- parameter [15:0] INIT_4C = 16'h0;
- parameter [15:0] INIT_4D = 16'h0;
- parameter [15:0] INIT_4E = 16'h0;
- parameter [15:0] INIT_4F = 16'h0;
- parameter [15:0] INIT_50 = 16'h0;
- parameter [15:0] INIT_51 = 16'h0;
- parameter [15:0] INIT_52 = 16'h0;
- parameter [15:0] INIT_53 = 16'h0;
- parameter [15:0] INIT_54 = 16'h0;
- parameter [15:0] INIT_55 = 16'h0;
- parameter [15:0] INIT_56 = 16'h0;
- parameter [15:0] INIT_57 = 16'h0;
- parameter [15:0] INIT_58 = 16'h0;
- parameter [15:0] INIT_59 = 16'h0;
- parameter [15:0] INIT_5A = 16'h0;
- parameter [15:0] INIT_5B = 16'h0;
- parameter [15:0] INIT_5C = 16'h0;
- parameter [15:0] INIT_5D = 16'h0;
- parameter [15:0] INIT_5E = 16'h0;
- parameter [15:0] INIT_5F = 16'h0;
- parameter IS_CONVSTCLK_INVERTED = 1'b0;
- parameter IS_DCLK_INVERTED = 1'b0;
- parameter SIM_DEVICE = "7SERIES";
- parameter SIM_MONITOR_FILE = "design.txt";
-endmodule
-
diff --git a/techlibs/xilinx/xc7_ff_map.v b/techlibs/xilinx/xc7_ff_map.v
new file mode 100644
index 000000000..f6197b78b
--- /dev/null
+++ b/techlibs/xilinx/xc7_ff_map.v
@@ -0,0 +1,78 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// ============================================================================
+// FF mapping
+
+`ifndef _NO_FFS
+
+module \$_DFF_N_ (input D, C, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
+endmodule
+module \$_DFF_P_ (input D, C, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
+endmodule
+
+module \$_DFFE_NP_ (input D, C, E, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0));
+endmodule
+module \$_DFFE_PP_ (input D, C, E, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0));
+endmodule
+
+module \$_DFF_NN0_ (input D, C, R, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
+endmodule
+module \$_DFF_NP0_ (input D, C, R, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
+endmodule
+module \$_DFF_PN0_ (input D, C, R, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
+endmodule
+module \$_DFF_PP0_ (input D, C, R, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
+endmodule
+
+module \$_DFF_NN1_ (input D, C, R, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
+endmodule
+module \$_DFF_NP1_ (input D, C, R, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
+endmodule
+module \$_DFF_PN1_ (input D, C, R, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
+endmodule
+module \$_DFF_PP1_ (input D, C, R, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
+endmodule
+
+`endif
+
diff --git a/techlibs/xilinx/xcu_cells_xtra.v b/techlibs/xilinx/xcu_cells_xtra.v
new file mode 100644
index 000000000..2d331a221
--- /dev/null
+++ b/techlibs/xilinx/xcu_cells_xtra.v
@@ -0,0 +1,11798 @@
+// Created by cells_xtra.py from Xilinx models
+
+module CMAC (...);
+ parameter CTL_PTP_TRANSPCLK_MODE = "FALSE";
+ parameter CTL_RX_CHECK_ACK = "TRUE";
+ parameter CTL_RX_CHECK_PREAMBLE = "FALSE";
+ parameter CTL_RX_CHECK_SFD = "FALSE";
+ parameter CTL_RX_DELETE_FCS = "TRUE";
+ parameter [15:0] CTL_RX_ETYPE_GCP = 16'h8808;
+ parameter [15:0] CTL_RX_ETYPE_GPP = 16'h8808;
+ parameter [15:0] CTL_RX_ETYPE_PCP = 16'h8808;
+ parameter [15:0] CTL_RX_ETYPE_PPP = 16'h8808;
+ parameter CTL_RX_FORWARD_CONTROL = "FALSE";
+ parameter CTL_RX_IGNORE_FCS = "FALSE";
+ parameter [14:0] CTL_RX_MAX_PACKET_LEN = 15'h2580;
+ parameter [7:0] CTL_RX_MIN_PACKET_LEN = 8'h40;
+ parameter [15:0] CTL_RX_OPCODE_GPP = 16'h0001;
+ parameter [15:0] CTL_RX_OPCODE_MAX_GCP = 16'hFFFF;
+ parameter [15:0] CTL_RX_OPCODE_MAX_PCP = 16'hFFFF;
+ parameter [15:0] CTL_RX_OPCODE_MIN_GCP = 16'h0000;
+ parameter [15:0] CTL_RX_OPCODE_MIN_PCP = 16'h0000;
+ parameter [15:0] CTL_RX_OPCODE_PPP = 16'h0001;
+ parameter [47:0] CTL_RX_PAUSE_DA_MCAST = 48'h0180C2000001;
+ parameter [47:0] CTL_RX_PAUSE_DA_UCAST = 48'h000000000000;
+ parameter [47:0] CTL_RX_PAUSE_SA = 48'h000000000000;
+ parameter CTL_RX_PROCESS_LFI = "FALSE";
+ parameter [15:0] CTL_RX_VL_LENGTH_MINUS1 = 16'h3FFF;
+ parameter [63:0] CTL_RX_VL_MARKER_ID0 = 64'hC16821003E97DE00;
+ parameter [63:0] CTL_RX_VL_MARKER_ID1 = 64'h9D718E00628E7100;
+ parameter [63:0] CTL_RX_VL_MARKER_ID10 = 64'hFD6C990002936600;
+ parameter [63:0] CTL_RX_VL_MARKER_ID11 = 64'hB9915500466EAA00;
+ parameter [63:0] CTL_RX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00;
+ parameter [63:0] CTL_RX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200;
+ parameter [63:0] CTL_RX_VL_MARKER_ID14 = 64'h83C7CA007C383500;
+ parameter [63:0] CTL_RX_VL_MARKER_ID15 = 64'h3536CD00CAC93200;
+ parameter [63:0] CTL_RX_VL_MARKER_ID16 = 64'hC4314C003BCEB300;
+ parameter [63:0] CTL_RX_VL_MARKER_ID17 = 64'hADD6B70052294800;
+ parameter [63:0] CTL_RX_VL_MARKER_ID18 = 64'h5F662A00A099D500;
+ parameter [63:0] CTL_RX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00;
+ parameter [63:0] CTL_RX_VL_MARKER_ID2 = 64'h594BE800A6B41700;
+ parameter [63:0] CTL_RX_VL_MARKER_ID3 = 64'h4D957B00B26A8400;
+ parameter [63:0] CTL_RX_VL_MARKER_ID4 = 64'hF50709000AF8F600;
+ parameter [63:0] CTL_RX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00;
+ parameter [63:0] CTL_RX_VL_MARKER_ID6 = 64'h9A4A260065B5D900;
+ parameter [63:0] CTL_RX_VL_MARKER_ID7 = 64'h7B45660084BA9900;
+ parameter [63:0] CTL_RX_VL_MARKER_ID8 = 64'hA02476005FDB8900;
+ parameter [63:0] CTL_RX_VL_MARKER_ID9 = 64'h68C9FB0097360400;
+ parameter CTL_TEST_MODE_PIN_CHAR = "FALSE";
+ parameter [47:0] CTL_TX_DA_GPP = 48'h0180C2000001;
+ parameter [47:0] CTL_TX_DA_PPP = 48'h0180C2000001;
+ parameter [15:0] CTL_TX_ETHERTYPE_GPP = 16'h8808;
+ parameter [15:0] CTL_TX_ETHERTYPE_PPP = 16'h8808;
+ parameter CTL_TX_FCS_INS_ENABLE = "TRUE";
+ parameter CTL_TX_IGNORE_FCS = "FALSE";
+ parameter [15:0] CTL_TX_OPCODE_GPP = 16'h0001;
+ parameter [15:0] CTL_TX_OPCODE_PPP = 16'h0001;
+ parameter CTL_TX_PTP_1STEP_ENABLE = "FALSE";
+ parameter [10:0] CTL_TX_PTP_LATENCY_ADJUST = 11'h2C1;
+ parameter [47:0] CTL_TX_SA_GPP = 48'h000000000000;
+ parameter [47:0] CTL_TX_SA_PPP = 48'h000000000000;
+ parameter [15:0] CTL_TX_VL_LENGTH_MINUS1 = 16'h3FFF;
+ parameter [63:0] CTL_TX_VL_MARKER_ID0 = 64'hC16821003E97DE00;
+ parameter [63:0] CTL_TX_VL_MARKER_ID1 = 64'h9D718E00628E7100;
+ parameter [63:0] CTL_TX_VL_MARKER_ID10 = 64'hFD6C990002936600;
+ parameter [63:0] CTL_TX_VL_MARKER_ID11 = 64'hB9915500466EAA00;
+ parameter [63:0] CTL_TX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00;
+ parameter [63:0] CTL_TX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200;
+ parameter [63:0] CTL_TX_VL_MARKER_ID14 = 64'h83C7CA007C383500;
+ parameter [63:0] CTL_TX_VL_MARKER_ID15 = 64'h3536CD00CAC93200;
+ parameter [63:0] CTL_TX_VL_MARKER_ID16 = 64'hC4314C003BCEB300;
+ parameter [63:0] CTL_TX_VL_MARKER_ID17 = 64'hADD6B70052294800;
+ parameter [63:0] CTL_TX_VL_MARKER_ID18 = 64'h5F662A00A099D500;
+ parameter [63:0] CTL_TX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00;
+ parameter [63:0] CTL_TX_VL_MARKER_ID2 = 64'h594BE800A6B41700;
+ parameter [63:0] CTL_TX_VL_MARKER_ID3 = 64'h4D957B00B26A8400;
+ parameter [63:0] CTL_TX_VL_MARKER_ID4 = 64'hF50709000AF8F600;
+ parameter [63:0] CTL_TX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00;
+ parameter [63:0] CTL_TX_VL_MARKER_ID6 = 64'h9A4A260065B5D900;
+ parameter [63:0] CTL_TX_VL_MARKER_ID7 = 64'h7B45660084BA9900;
+ parameter [63:0] CTL_TX_VL_MARKER_ID8 = 64'hA02476005FDB8900;
+ parameter [63:0] CTL_TX_VL_MARKER_ID9 = 64'h68C9FB0097360400;
+ parameter SIM_VERSION = "2.0";
+ parameter TEST_MODE_PIN_CHAR = "FALSE";
+ output [15:0] DRP_DO;
+ output DRP_RDY;
+ output [127:0] RX_DATAOUT0;
+ output [127:0] RX_DATAOUT1;
+ output [127:0] RX_DATAOUT2;
+ output [127:0] RX_DATAOUT3;
+ output RX_ENAOUT0;
+ output RX_ENAOUT1;
+ output RX_ENAOUT2;
+ output RX_ENAOUT3;
+ output RX_EOPOUT0;
+ output RX_EOPOUT1;
+ output RX_EOPOUT2;
+ output RX_EOPOUT3;
+ output RX_ERROUT0;
+ output RX_ERROUT1;
+ output RX_ERROUT2;
+ output RX_ERROUT3;
+ output [6:0] RX_LANE_ALIGNER_FILL_0;
+ output [6:0] RX_LANE_ALIGNER_FILL_1;
+ output [6:0] RX_LANE_ALIGNER_FILL_10;
+ output [6:0] RX_LANE_ALIGNER_FILL_11;
+ output [6:0] RX_LANE_ALIGNER_FILL_12;
+ output [6:0] RX_LANE_ALIGNER_FILL_13;
+ output [6:0] RX_LANE_ALIGNER_FILL_14;
+ output [6:0] RX_LANE_ALIGNER_FILL_15;
+ output [6:0] RX_LANE_ALIGNER_FILL_16;
+ output [6:0] RX_LANE_ALIGNER_FILL_17;
+ output [6:0] RX_LANE_ALIGNER_FILL_18;
+ output [6:0] RX_LANE_ALIGNER_FILL_19;
+ output [6:0] RX_LANE_ALIGNER_FILL_2;
+ output [6:0] RX_LANE_ALIGNER_FILL_3;
+ output [6:0] RX_LANE_ALIGNER_FILL_4;
+ output [6:0] RX_LANE_ALIGNER_FILL_5;
+ output [6:0] RX_LANE_ALIGNER_FILL_6;
+ output [6:0] RX_LANE_ALIGNER_FILL_7;
+ output [6:0] RX_LANE_ALIGNER_FILL_8;
+ output [6:0] RX_LANE_ALIGNER_FILL_9;
+ output [3:0] RX_MTYOUT0;
+ output [3:0] RX_MTYOUT1;
+ output [3:0] RX_MTYOUT2;
+ output [3:0] RX_MTYOUT3;
+ output [4:0] RX_PTP_PCSLANE_OUT;
+ output [79:0] RX_PTP_TSTAMP_OUT;
+ output RX_SOPOUT0;
+ output RX_SOPOUT1;
+ output RX_SOPOUT2;
+ output RX_SOPOUT3;
+ output STAT_RX_ALIGNED;
+ output STAT_RX_ALIGNED_ERR;
+ output [6:0] STAT_RX_BAD_CODE;
+ output [3:0] STAT_RX_BAD_FCS;
+ output STAT_RX_BAD_PREAMBLE;
+ output STAT_RX_BAD_SFD;
+ output STAT_RX_BIP_ERR_0;
+ output STAT_RX_BIP_ERR_1;
+ output STAT_RX_BIP_ERR_10;
+ output STAT_RX_BIP_ERR_11;
+ output STAT_RX_BIP_ERR_12;
+ output STAT_RX_BIP_ERR_13;
+ output STAT_RX_BIP_ERR_14;
+ output STAT_RX_BIP_ERR_15;
+ output STAT_RX_BIP_ERR_16;
+ output STAT_RX_BIP_ERR_17;
+ output STAT_RX_BIP_ERR_18;
+ output STAT_RX_BIP_ERR_19;
+ output STAT_RX_BIP_ERR_2;
+ output STAT_RX_BIP_ERR_3;
+ output STAT_RX_BIP_ERR_4;
+ output STAT_RX_BIP_ERR_5;
+ output STAT_RX_BIP_ERR_6;
+ output STAT_RX_BIP_ERR_7;
+ output STAT_RX_BIP_ERR_8;
+ output STAT_RX_BIP_ERR_9;
+ output [19:0] STAT_RX_BLOCK_LOCK;
+ output STAT_RX_BROADCAST;
+ output [3:0] STAT_RX_FRAGMENT;
+ output [3:0] STAT_RX_FRAMING_ERR_0;
+ output [3:0] STAT_RX_FRAMING_ERR_1;
+ output [3:0] STAT_RX_FRAMING_ERR_10;
+ output [3:0] STAT_RX_FRAMING_ERR_11;
+ output [3:0] STAT_RX_FRAMING_ERR_12;
+ output [3:0] STAT_RX_FRAMING_ERR_13;
+ output [3:0] STAT_RX_FRAMING_ERR_14;
+ output [3:0] STAT_RX_FRAMING_ERR_15;
+ output [3:0] STAT_RX_FRAMING_ERR_16;
+ output [3:0] STAT_RX_FRAMING_ERR_17;
+ output [3:0] STAT_RX_FRAMING_ERR_18;
+ output [3:0] STAT_RX_FRAMING_ERR_19;
+ output [3:0] STAT_RX_FRAMING_ERR_2;
+ output [3:0] STAT_RX_FRAMING_ERR_3;
+ output [3:0] STAT_RX_FRAMING_ERR_4;
+ output [3:0] STAT_RX_FRAMING_ERR_5;
+ output [3:0] STAT_RX_FRAMING_ERR_6;
+ output [3:0] STAT_RX_FRAMING_ERR_7;
+ output [3:0] STAT_RX_FRAMING_ERR_8;
+ output [3:0] STAT_RX_FRAMING_ERR_9;
+ output STAT_RX_FRAMING_ERR_VALID_0;
+ output STAT_RX_FRAMING_ERR_VALID_1;
+ output STAT_RX_FRAMING_ERR_VALID_10;
+ output STAT_RX_FRAMING_ERR_VALID_11;
+ output STAT_RX_FRAMING_ERR_VALID_12;
+ output STAT_RX_FRAMING_ERR_VALID_13;
+ output STAT_RX_FRAMING_ERR_VALID_14;
+ output STAT_RX_FRAMING_ERR_VALID_15;
+ output STAT_RX_FRAMING_ERR_VALID_16;
+ output STAT_RX_FRAMING_ERR_VALID_17;
+ output STAT_RX_FRAMING_ERR_VALID_18;
+ output STAT_RX_FRAMING_ERR_VALID_19;
+ output STAT_RX_FRAMING_ERR_VALID_2;
+ output STAT_RX_FRAMING_ERR_VALID_3;
+ output STAT_RX_FRAMING_ERR_VALID_4;
+ output STAT_RX_FRAMING_ERR_VALID_5;
+ output STAT_RX_FRAMING_ERR_VALID_6;
+ output STAT_RX_FRAMING_ERR_VALID_7;
+ output STAT_RX_FRAMING_ERR_VALID_8;
+ output STAT_RX_FRAMING_ERR_VALID_9;
+ output STAT_RX_GOT_SIGNAL_OS;
+ output STAT_RX_HI_BER;
+ output STAT_RX_INRANGEERR;
+ output STAT_RX_INTERNAL_LOCAL_FAULT;
+ output STAT_RX_JABBER;
+ output [7:0] STAT_RX_LANE0_VLM_BIP7;
+ output STAT_RX_LANE0_VLM_BIP7_VALID;
+ output STAT_RX_LOCAL_FAULT;
+ output [19:0] STAT_RX_MF_ERR;
+ output [19:0] STAT_RX_MF_LEN_ERR;
+ output [19:0] STAT_RX_MF_REPEAT_ERR;
+ output STAT_RX_MISALIGNED;
+ output STAT_RX_MULTICAST;
+ output STAT_RX_OVERSIZE;
+ output STAT_RX_PACKET_1024_1518_BYTES;
+ output STAT_RX_PACKET_128_255_BYTES;
+ output STAT_RX_PACKET_1519_1522_BYTES;
+ output STAT_RX_PACKET_1523_1548_BYTES;
+ output STAT_RX_PACKET_1549_2047_BYTES;
+ output STAT_RX_PACKET_2048_4095_BYTES;
+ output STAT_RX_PACKET_256_511_BYTES;
+ output STAT_RX_PACKET_4096_8191_BYTES;
+ output STAT_RX_PACKET_512_1023_BYTES;
+ output STAT_RX_PACKET_64_BYTES;
+ output STAT_RX_PACKET_65_127_BYTES;
+ output STAT_RX_PACKET_8192_9215_BYTES;
+ output STAT_RX_PACKET_BAD_FCS;
+ output STAT_RX_PACKET_LARGE;
+ output [3:0] STAT_RX_PACKET_SMALL;
+ output STAT_RX_PAUSE;
+ output [15:0] STAT_RX_PAUSE_QUANTA0;
+ output [15:0] STAT_RX_PAUSE_QUANTA1;
+ output [15:0] STAT_RX_PAUSE_QUANTA2;
+ output [15:0] STAT_RX_PAUSE_QUANTA3;
+ output [15:0] STAT_RX_PAUSE_QUANTA4;
+ output [15:0] STAT_RX_PAUSE_QUANTA5;
+ output [15:0] STAT_RX_PAUSE_QUANTA6;
+ output [15:0] STAT_RX_PAUSE_QUANTA7;
+ output [15:0] STAT_RX_PAUSE_QUANTA8;
+ output [8:0] STAT_RX_PAUSE_REQ;
+ output [8:0] STAT_RX_PAUSE_VALID;
+ output STAT_RX_RECEIVED_LOCAL_FAULT;
+ output STAT_RX_REMOTE_FAULT;
+ output STAT_RX_STATUS;
+ output [3:0] STAT_RX_STOMPED_FCS;
+ output [19:0] STAT_RX_SYNCED;
+ output [19:0] STAT_RX_SYNCED_ERR;
+ output [2:0] STAT_RX_TEST_PATTERN_MISMATCH;
+ output STAT_RX_TOOLONG;
+ output [7:0] STAT_RX_TOTAL_BYTES;
+ output [13:0] STAT_RX_TOTAL_GOOD_BYTES;
+ output STAT_RX_TOTAL_GOOD_PACKETS;
+ output [3:0] STAT_RX_TOTAL_PACKETS;
+ output STAT_RX_TRUNCATED;
+ output [3:0] STAT_RX_UNDERSIZE;
+ output STAT_RX_UNICAST;
+ output STAT_RX_USER_PAUSE;
+ output STAT_RX_VLAN;
+ output [19:0] STAT_RX_VL_DEMUXED;
+ output [4:0] STAT_RX_VL_NUMBER_0;
+ output [4:0] STAT_RX_VL_NUMBER_1;
+ output [4:0] STAT_RX_VL_NUMBER_10;
+ output [4:0] STAT_RX_VL_NUMBER_11;
+ output [4:0] STAT_RX_VL_NUMBER_12;
+ output [4:0] STAT_RX_VL_NUMBER_13;
+ output [4:0] STAT_RX_VL_NUMBER_14;
+ output [4:0] STAT_RX_VL_NUMBER_15;
+ output [4:0] STAT_RX_VL_NUMBER_16;
+ output [4:0] STAT_RX_VL_NUMBER_17;
+ output [4:0] STAT_RX_VL_NUMBER_18;
+ output [4:0] STAT_RX_VL_NUMBER_19;
+ output [4:0] STAT_RX_VL_NUMBER_2;
+ output [4:0] STAT_RX_VL_NUMBER_3;
+ output [4:0] STAT_RX_VL_NUMBER_4;
+ output [4:0] STAT_RX_VL_NUMBER_5;
+ output [4:0] STAT_RX_VL_NUMBER_6;
+ output [4:0] STAT_RX_VL_NUMBER_7;
+ output [4:0] STAT_RX_VL_NUMBER_8;
+ output [4:0] STAT_RX_VL_NUMBER_9;
+ output STAT_TX_BAD_FCS;
+ output STAT_TX_BROADCAST;
+ output STAT_TX_FRAME_ERROR;
+ output STAT_TX_LOCAL_FAULT;
+ output STAT_TX_MULTICAST;
+ output STAT_TX_PACKET_1024_1518_BYTES;
+ output STAT_TX_PACKET_128_255_BYTES;
+ output STAT_TX_PACKET_1519_1522_BYTES;
+ output STAT_TX_PACKET_1523_1548_BYTES;
+ output STAT_TX_PACKET_1549_2047_BYTES;
+ output STAT_TX_PACKET_2048_4095_BYTES;
+ output STAT_TX_PACKET_256_511_BYTES;
+ output STAT_TX_PACKET_4096_8191_BYTES;
+ output STAT_TX_PACKET_512_1023_BYTES;
+ output STAT_TX_PACKET_64_BYTES;
+ output STAT_TX_PACKET_65_127_BYTES;
+ output STAT_TX_PACKET_8192_9215_BYTES;
+ output STAT_TX_PACKET_LARGE;
+ output STAT_TX_PACKET_SMALL;
+ output STAT_TX_PAUSE;
+ output [8:0] STAT_TX_PAUSE_VALID;
+ output STAT_TX_PTP_FIFO_READ_ERROR;
+ output STAT_TX_PTP_FIFO_WRITE_ERROR;
+ output [6:0] STAT_TX_TOTAL_BYTES;
+ output [13:0] STAT_TX_TOTAL_GOOD_BYTES;
+ output STAT_TX_TOTAL_GOOD_PACKETS;
+ output STAT_TX_TOTAL_PACKETS;
+ output STAT_TX_UNICAST;
+ output STAT_TX_USER_PAUSE;
+ output STAT_TX_VLAN;
+ output TX_OVFOUT;
+ output [4:0] TX_PTP_PCSLANE_OUT;
+ output [79:0] TX_PTP_TSTAMP_OUT;
+ output [15:0] TX_PTP_TSTAMP_TAG_OUT;
+ output TX_PTP_TSTAMP_VALID_OUT;
+ output TX_RDYOUT;
+ output [15:0] TX_SERDES_ALT_DATA0;
+ output [15:0] TX_SERDES_ALT_DATA1;
+ output [15:0] TX_SERDES_ALT_DATA2;
+ output [15:0] TX_SERDES_ALT_DATA3;
+ output [63:0] TX_SERDES_DATA0;
+ output [63:0] TX_SERDES_DATA1;
+ output [63:0] TX_SERDES_DATA2;
+ output [63:0] TX_SERDES_DATA3;
+ output [31:0] TX_SERDES_DATA4;
+ output [31:0] TX_SERDES_DATA5;
+ output [31:0] TX_SERDES_DATA6;
+ output [31:0] TX_SERDES_DATA7;
+ output [31:0] TX_SERDES_DATA8;
+ output [31:0] TX_SERDES_DATA9;
+ output TX_UNFOUT;
+ input CTL_CAUI4_MODE;
+ input CTL_RX_CHECK_ETYPE_GCP;
+ input CTL_RX_CHECK_ETYPE_GPP;
+ input CTL_RX_CHECK_ETYPE_PCP;
+ input CTL_RX_CHECK_ETYPE_PPP;
+ input CTL_RX_CHECK_MCAST_GCP;
+ input CTL_RX_CHECK_MCAST_GPP;
+ input CTL_RX_CHECK_MCAST_PCP;
+ input CTL_RX_CHECK_MCAST_PPP;
+ input CTL_RX_CHECK_OPCODE_GCP;
+ input CTL_RX_CHECK_OPCODE_GPP;
+ input CTL_RX_CHECK_OPCODE_PCP;
+ input CTL_RX_CHECK_OPCODE_PPP;
+ input CTL_RX_CHECK_SA_GCP;
+ input CTL_RX_CHECK_SA_GPP;
+ input CTL_RX_CHECK_SA_PCP;
+ input CTL_RX_CHECK_SA_PPP;
+ input CTL_RX_CHECK_UCAST_GCP;
+ input CTL_RX_CHECK_UCAST_GPP;
+ input CTL_RX_CHECK_UCAST_PCP;
+ input CTL_RX_CHECK_UCAST_PPP;
+ input CTL_RX_ENABLE;
+ input CTL_RX_ENABLE_GCP;
+ input CTL_RX_ENABLE_GPP;
+ input CTL_RX_ENABLE_PCP;
+ input CTL_RX_ENABLE_PPP;
+ input CTL_RX_FORCE_RESYNC;
+ input [8:0] CTL_RX_PAUSE_ACK;
+ input [8:0] CTL_RX_PAUSE_ENABLE;
+ input [79:0] CTL_RX_SYSTEMTIMERIN;
+ input CTL_RX_TEST_PATTERN;
+ input CTL_TX_ENABLE;
+ input CTL_TX_LANE0_VLM_BIP7_OVERRIDE;
+ input [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE;
+ input [8:0] CTL_TX_PAUSE_ENABLE;
+ input [15:0] CTL_TX_PAUSE_QUANTA0;
+ input [15:0] CTL_TX_PAUSE_QUANTA1;
+ input [15:0] CTL_TX_PAUSE_QUANTA2;
+ input [15:0] CTL_TX_PAUSE_QUANTA3;
+ input [15:0] CTL_TX_PAUSE_QUANTA4;
+ input [15:0] CTL_TX_PAUSE_QUANTA5;
+ input [15:0] CTL_TX_PAUSE_QUANTA6;
+ input [15:0] CTL_TX_PAUSE_QUANTA7;
+ input [15:0] CTL_TX_PAUSE_QUANTA8;
+ input [15:0] CTL_TX_PAUSE_REFRESH_TIMER0;
+ input [15:0] CTL_TX_PAUSE_REFRESH_TIMER1;
+ input [15:0] CTL_TX_PAUSE_REFRESH_TIMER2;
+ input [15:0] CTL_TX_PAUSE_REFRESH_TIMER3;
+ input [15:0] CTL_TX_PAUSE_REFRESH_TIMER4;
+ input [15:0] CTL_TX_PAUSE_REFRESH_TIMER5;
+ input [15:0] CTL_TX_PAUSE_REFRESH_TIMER6;
+ input [15:0] CTL_TX_PAUSE_REFRESH_TIMER7;
+ input [15:0] CTL_TX_PAUSE_REFRESH_TIMER8;
+ input [8:0] CTL_TX_PAUSE_REQ;
+ input CTL_TX_PTP_VLANE_ADJUST_MODE;
+ input CTL_TX_RESEND_PAUSE;
+ input CTL_TX_SEND_IDLE;
+ input CTL_TX_SEND_RFI;
+ input [79:0] CTL_TX_SYSTEMTIMERIN;
+ input CTL_TX_TEST_PATTERN;
+ input [9:0] DRP_ADDR;
+ input DRP_CLK;
+ input [15:0] DRP_DI;
+ input DRP_EN;
+ input DRP_WE;
+ input RX_CLK;
+ input RX_RESET;
+ input [15:0] RX_SERDES_ALT_DATA0;
+ input [15:0] RX_SERDES_ALT_DATA1;
+ input [15:0] RX_SERDES_ALT_DATA2;
+ input [15:0] RX_SERDES_ALT_DATA3;
+ input [9:0] RX_SERDES_CLK;
+ input [63:0] RX_SERDES_DATA0;
+ input [63:0] RX_SERDES_DATA1;
+ input [63:0] RX_SERDES_DATA2;
+ input [63:0] RX_SERDES_DATA3;
+ input [31:0] RX_SERDES_DATA4;
+ input [31:0] RX_SERDES_DATA5;
+ input [31:0] RX_SERDES_DATA6;
+ input [31:0] RX_SERDES_DATA7;
+ input [31:0] RX_SERDES_DATA8;
+ input [31:0] RX_SERDES_DATA9;
+ input [9:0] RX_SERDES_RESET;
+ input TX_CLK;
+ input [127:0] TX_DATAIN0;
+ input [127:0] TX_DATAIN1;
+ input [127:0] TX_DATAIN2;
+ input [127:0] TX_DATAIN3;
+ input TX_ENAIN0;
+ input TX_ENAIN1;
+ input TX_ENAIN2;
+ input TX_ENAIN3;
+ input TX_EOPIN0;
+ input TX_EOPIN1;
+ input TX_EOPIN2;
+ input TX_EOPIN3;
+ input TX_ERRIN0;
+ input TX_ERRIN1;
+ input TX_ERRIN2;
+ input TX_ERRIN3;
+ input [3:0] TX_MTYIN0;
+ input [3:0] TX_MTYIN1;
+ input [3:0] TX_MTYIN2;
+ input [3:0] TX_MTYIN3;
+ input [1:0] TX_PTP_1588OP_IN;
+ input [15:0] TX_PTP_CHKSUM_OFFSET_IN;
+ input [63:0] TX_PTP_RXTSTAMP_IN;
+ input [15:0] TX_PTP_TAG_FIELD_IN;
+ input [15:0] TX_PTP_TSTAMP_OFFSET_IN;
+ input TX_PTP_UPD_CHKSUM_IN;
+ input TX_RESET;
+ input TX_SOPIN0;
+ input TX_SOPIN1;
+ input TX_SOPIN2;
+ input TX_SOPIN3;
+endmodule
+
+module CMACE4 (...);
+ parameter CTL_PTP_TRANSPCLK_MODE = "FALSE";
+ parameter CTL_RX_CHECK_ACK = "TRUE";
+ parameter CTL_RX_CHECK_PREAMBLE = "FALSE";
+ parameter CTL_RX_CHECK_SFD = "FALSE";
+ parameter CTL_RX_DELETE_FCS = "TRUE";
+ parameter [15:0] CTL_RX_ETYPE_GCP = 16'h8808;
+ parameter [15:0] CTL_RX_ETYPE_GPP = 16'h8808;
+ parameter [15:0] CTL_RX_ETYPE_PCP = 16'h8808;
+ parameter [15:0] CTL_RX_ETYPE_PPP = 16'h8808;
+ parameter CTL_RX_FORWARD_CONTROL = "FALSE";
+ parameter CTL_RX_IGNORE_FCS = "FALSE";
+ parameter [14:0] CTL_RX_MAX_PACKET_LEN = 15'h2580;
+ parameter [7:0] CTL_RX_MIN_PACKET_LEN = 8'h40;
+ parameter [15:0] CTL_RX_OPCODE_GPP = 16'h0001;
+ parameter [15:0] CTL_RX_OPCODE_MAX_GCP = 16'hFFFF;
+ parameter [15:0] CTL_RX_OPCODE_MAX_PCP = 16'hFFFF;
+ parameter [15:0] CTL_RX_OPCODE_MIN_GCP = 16'h0000;
+ parameter [15:0] CTL_RX_OPCODE_MIN_PCP = 16'h0000;
+ parameter [15:0] CTL_RX_OPCODE_PPP = 16'h0001;
+ parameter [47:0] CTL_RX_PAUSE_DA_MCAST = 48'h0180C2000001;
+ parameter [47:0] CTL_RX_PAUSE_DA_UCAST = 48'h000000000000;
+ parameter [47:0] CTL_RX_PAUSE_SA = 48'h000000000000;
+ parameter CTL_RX_PROCESS_LFI = "FALSE";
+ parameter [8:0] CTL_RX_RSFEC_AM_THRESHOLD = 9'h046;
+ parameter [1:0] CTL_RX_RSFEC_FILL_ADJUST = 2'h0;
+ parameter [15:0] CTL_RX_VL_LENGTH_MINUS1 = 16'h3FFF;
+ parameter [63:0] CTL_RX_VL_MARKER_ID0 = 64'hC16821003E97DE00;
+ parameter [63:0] CTL_RX_VL_MARKER_ID1 = 64'h9D718E00628E7100;
+ parameter [63:0] CTL_RX_VL_MARKER_ID10 = 64'hFD6C990002936600;
+ parameter [63:0] CTL_RX_VL_MARKER_ID11 = 64'hB9915500466EAA00;
+ parameter [63:0] CTL_RX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00;
+ parameter [63:0] CTL_RX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200;
+ parameter [63:0] CTL_RX_VL_MARKER_ID14 = 64'h83C7CA007C383500;
+ parameter [63:0] CTL_RX_VL_MARKER_ID15 = 64'h3536CD00CAC93200;
+ parameter [63:0] CTL_RX_VL_MARKER_ID16 = 64'hC4314C003BCEB300;
+ parameter [63:0] CTL_RX_VL_MARKER_ID17 = 64'hADD6B70052294800;
+ parameter [63:0] CTL_RX_VL_MARKER_ID18 = 64'h5F662A00A099D500;
+ parameter [63:0] CTL_RX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00;
+ parameter [63:0] CTL_RX_VL_MARKER_ID2 = 64'h594BE800A6B41700;
+ parameter [63:0] CTL_RX_VL_MARKER_ID3 = 64'h4D957B00B26A8400;
+ parameter [63:0] CTL_RX_VL_MARKER_ID4 = 64'hF50709000AF8F600;
+ parameter [63:0] CTL_RX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00;
+ parameter [63:0] CTL_RX_VL_MARKER_ID6 = 64'h9A4A260065B5D900;
+ parameter [63:0] CTL_RX_VL_MARKER_ID7 = 64'h7B45660084BA9900;
+ parameter [63:0] CTL_RX_VL_MARKER_ID8 = 64'hA02476005FDB8900;
+ parameter [63:0] CTL_RX_VL_MARKER_ID9 = 64'h68C9FB0097360400;
+ parameter CTL_TEST_MODE_PIN_CHAR = "FALSE";
+ parameter CTL_TX_CUSTOM_PREAMBLE_ENABLE = "FALSE";
+ parameter [47:0] CTL_TX_DA_GPP = 48'h0180C2000001;
+ parameter [47:0] CTL_TX_DA_PPP = 48'h0180C2000001;
+ parameter [15:0] CTL_TX_ETHERTYPE_GPP = 16'h8808;
+ parameter [15:0] CTL_TX_ETHERTYPE_PPP = 16'h8808;
+ parameter CTL_TX_FCS_INS_ENABLE = "TRUE";
+ parameter CTL_TX_IGNORE_FCS = "FALSE";
+ parameter [3:0] CTL_TX_IPG_VALUE = 4'hC;
+ parameter [15:0] CTL_TX_OPCODE_GPP = 16'h0001;
+ parameter [15:0] CTL_TX_OPCODE_PPP = 16'h0001;
+ parameter CTL_TX_PTP_1STEP_ENABLE = "FALSE";
+ parameter [10:0] CTL_TX_PTP_LATENCY_ADJUST = 11'h2C1;
+ parameter [47:0] CTL_TX_SA_GPP = 48'h000000000000;
+ parameter [47:0] CTL_TX_SA_PPP = 48'h000000000000;
+ parameter [15:0] CTL_TX_VL_LENGTH_MINUS1 = 16'h3FFF;
+ parameter [63:0] CTL_TX_VL_MARKER_ID0 = 64'hC16821003E97DE00;
+ parameter [63:0] CTL_TX_VL_MARKER_ID1 = 64'h9D718E00628E7100;
+ parameter [63:0] CTL_TX_VL_MARKER_ID10 = 64'hFD6C990002936600;
+ parameter [63:0] CTL_TX_VL_MARKER_ID11 = 64'hB9915500466EAA00;
+ parameter [63:0] CTL_TX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00;
+ parameter [63:0] CTL_TX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200;
+ parameter [63:0] CTL_TX_VL_MARKER_ID14 = 64'h83C7CA007C383500;
+ parameter [63:0] CTL_TX_VL_MARKER_ID15 = 64'h3536CD00CAC93200;
+ parameter [63:0] CTL_TX_VL_MARKER_ID16 = 64'hC4314C003BCEB300;
+ parameter [63:0] CTL_TX_VL_MARKER_ID17 = 64'hADD6B70052294800;
+ parameter [63:0] CTL_TX_VL_MARKER_ID18 = 64'h5F662A00A099D500;
+ parameter [63:0] CTL_TX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00;
+ parameter [63:0] CTL_TX_VL_MARKER_ID2 = 64'h594BE800A6B41700;
+ parameter [63:0] CTL_TX_VL_MARKER_ID3 = 64'h4D957B00B26A8400;
+ parameter [63:0] CTL_TX_VL_MARKER_ID4 = 64'hF50709000AF8F600;
+ parameter [63:0] CTL_TX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00;
+ parameter [63:0] CTL_TX_VL_MARKER_ID6 = 64'h9A4A260065B5D900;
+ parameter [63:0] CTL_TX_VL_MARKER_ID7 = 64'h7B45660084BA9900;
+ parameter [63:0] CTL_TX_VL_MARKER_ID8 = 64'hA02476005FDB8900;
+ parameter [63:0] CTL_TX_VL_MARKER_ID9 = 64'h68C9FB0097360400;
+ parameter SIM_DEVICE = "ULTRASCALE_PLUS";
+ parameter TEST_MODE_PIN_CHAR = "FALSE";
+ output [15:0] DRP_DO;
+ output DRP_RDY;
+ output [329:0] RSFEC_BYPASS_RX_DOUT;
+ output RSFEC_BYPASS_RX_DOUT_CW_START;
+ output RSFEC_BYPASS_RX_DOUT_VALID;
+ output [329:0] RSFEC_BYPASS_TX_DOUT;
+ output RSFEC_BYPASS_TX_DOUT_CW_START;
+ output RSFEC_BYPASS_TX_DOUT_VALID;
+ output [127:0] RX_DATAOUT0;
+ output [127:0] RX_DATAOUT1;
+ output [127:0] RX_DATAOUT2;
+ output [127:0] RX_DATAOUT3;
+ output RX_ENAOUT0;
+ output RX_ENAOUT1;
+ output RX_ENAOUT2;
+ output RX_ENAOUT3;
+ output RX_EOPOUT0;
+ output RX_EOPOUT1;
+ output RX_EOPOUT2;
+ output RX_EOPOUT3;
+ output RX_ERROUT0;
+ output RX_ERROUT1;
+ output RX_ERROUT2;
+ output RX_ERROUT3;
+ output [6:0] RX_LANE_ALIGNER_FILL_0;
+ output [6:0] RX_LANE_ALIGNER_FILL_1;
+ output [6:0] RX_LANE_ALIGNER_FILL_10;
+ output [6:0] RX_LANE_ALIGNER_FILL_11;
+ output [6:0] RX_LANE_ALIGNER_FILL_12;
+ output [6:0] RX_LANE_ALIGNER_FILL_13;
+ output [6:0] RX_LANE_ALIGNER_FILL_14;
+ output [6:0] RX_LANE_ALIGNER_FILL_15;
+ output [6:0] RX_LANE_ALIGNER_FILL_16;
+ output [6:0] RX_LANE_ALIGNER_FILL_17;
+ output [6:0] RX_LANE_ALIGNER_FILL_18;
+ output [6:0] RX_LANE_ALIGNER_FILL_19;
+ output [6:0] RX_LANE_ALIGNER_FILL_2;
+ output [6:0] RX_LANE_ALIGNER_FILL_3;
+ output [6:0] RX_LANE_ALIGNER_FILL_4;
+ output [6:0] RX_LANE_ALIGNER_FILL_5;
+ output [6:0] RX_LANE_ALIGNER_FILL_6;
+ output [6:0] RX_LANE_ALIGNER_FILL_7;
+ output [6:0] RX_LANE_ALIGNER_FILL_8;
+ output [6:0] RX_LANE_ALIGNER_FILL_9;
+ output [3:0] RX_MTYOUT0;
+ output [3:0] RX_MTYOUT1;
+ output [3:0] RX_MTYOUT2;
+ output [3:0] RX_MTYOUT3;
+ output [7:0] RX_OTN_BIP8_0;
+ output [7:0] RX_OTN_BIP8_1;
+ output [7:0] RX_OTN_BIP8_2;
+ output [7:0] RX_OTN_BIP8_3;
+ output [7:0] RX_OTN_BIP8_4;
+ output [65:0] RX_OTN_DATA_0;
+ output [65:0] RX_OTN_DATA_1;
+ output [65:0] RX_OTN_DATA_2;
+ output [65:0] RX_OTN_DATA_3;
+ output [65:0] RX_OTN_DATA_4;
+ output RX_OTN_ENA;
+ output RX_OTN_LANE0;
+ output RX_OTN_VLMARKER;
+ output [55:0] RX_PREOUT;
+ output [4:0] RX_PTP_PCSLANE_OUT;
+ output [79:0] RX_PTP_TSTAMP_OUT;
+ output RX_SOPOUT0;
+ output RX_SOPOUT1;
+ output RX_SOPOUT2;
+ output RX_SOPOUT3;
+ output STAT_RX_ALIGNED;
+ output STAT_RX_ALIGNED_ERR;
+ output [2:0] STAT_RX_BAD_CODE;
+ output [2:0] STAT_RX_BAD_FCS;
+ output STAT_RX_BAD_PREAMBLE;
+ output STAT_RX_BAD_SFD;
+ output STAT_RX_BIP_ERR_0;
+ output STAT_RX_BIP_ERR_1;
+ output STAT_RX_BIP_ERR_10;
+ output STAT_RX_BIP_ERR_11;
+ output STAT_RX_BIP_ERR_12;
+ output STAT_RX_BIP_ERR_13;
+ output STAT_RX_BIP_ERR_14;
+ output STAT_RX_BIP_ERR_15;
+ output STAT_RX_BIP_ERR_16;
+ output STAT_RX_BIP_ERR_17;
+ output STAT_RX_BIP_ERR_18;
+ output STAT_RX_BIP_ERR_19;
+ output STAT_RX_BIP_ERR_2;
+ output STAT_RX_BIP_ERR_3;
+ output STAT_RX_BIP_ERR_4;
+ output STAT_RX_BIP_ERR_5;
+ output STAT_RX_BIP_ERR_6;
+ output STAT_RX_BIP_ERR_7;
+ output STAT_RX_BIP_ERR_8;
+ output STAT_RX_BIP_ERR_9;
+ output [19:0] STAT_RX_BLOCK_LOCK;
+ output STAT_RX_BROADCAST;
+ output [2:0] STAT_RX_FRAGMENT;
+ output [1:0] STAT_RX_FRAMING_ERR_0;
+ output [1:0] STAT_RX_FRAMING_ERR_1;
+ output [1:0] STAT_RX_FRAMING_ERR_10;
+ output [1:0] STAT_RX_FRAMING_ERR_11;
+ output [1:0] STAT_RX_FRAMING_ERR_12;
+ output [1:0] STAT_RX_FRAMING_ERR_13;
+ output [1:0] STAT_RX_FRAMING_ERR_14;
+ output [1:0] STAT_RX_FRAMING_ERR_15;
+ output [1:0] STAT_RX_FRAMING_ERR_16;
+ output [1:0] STAT_RX_FRAMING_ERR_17;
+ output [1:0] STAT_RX_FRAMING_ERR_18;
+ output [1:0] STAT_RX_FRAMING_ERR_19;
+ output [1:0] STAT_RX_FRAMING_ERR_2;
+ output [1:0] STAT_RX_FRAMING_ERR_3;
+ output [1:0] STAT_RX_FRAMING_ERR_4;
+ output [1:0] STAT_RX_FRAMING_ERR_5;
+ output [1:0] STAT_RX_FRAMING_ERR_6;
+ output [1:0] STAT_RX_FRAMING_ERR_7;
+ output [1:0] STAT_RX_FRAMING_ERR_8;
+ output [1:0] STAT_RX_FRAMING_ERR_9;
+ output STAT_RX_FRAMING_ERR_VALID_0;
+ output STAT_RX_FRAMING_ERR_VALID_1;
+ output STAT_RX_FRAMING_ERR_VALID_10;
+ output STAT_RX_FRAMING_ERR_VALID_11;
+ output STAT_RX_FRAMING_ERR_VALID_12;
+ output STAT_RX_FRAMING_ERR_VALID_13;
+ output STAT_RX_FRAMING_ERR_VALID_14;
+ output STAT_RX_FRAMING_ERR_VALID_15;
+ output STAT_RX_FRAMING_ERR_VALID_16;
+ output STAT_RX_FRAMING_ERR_VALID_17;
+ output STAT_RX_FRAMING_ERR_VALID_18;
+ output STAT_RX_FRAMING_ERR_VALID_19;
+ output STAT_RX_FRAMING_ERR_VALID_2;
+ output STAT_RX_FRAMING_ERR_VALID_3;
+ output STAT_RX_FRAMING_ERR_VALID_4;
+ output STAT_RX_FRAMING_ERR_VALID_5;
+ output STAT_RX_FRAMING_ERR_VALID_6;
+ output STAT_RX_FRAMING_ERR_VALID_7;
+ output STAT_RX_FRAMING_ERR_VALID_8;
+ output STAT_RX_FRAMING_ERR_VALID_9;
+ output STAT_RX_GOT_SIGNAL_OS;
+ output STAT_RX_HI_BER;
+ output STAT_RX_INRANGEERR;
+ output STAT_RX_INTERNAL_LOCAL_FAULT;
+ output STAT_RX_JABBER;
+ output [7:0] STAT_RX_LANE0_VLM_BIP7;
+ output STAT_RX_LANE0_VLM_BIP7_VALID;
+ output STAT_RX_LOCAL_FAULT;
+ output [19:0] STAT_RX_MF_ERR;
+ output [19:0] STAT_RX_MF_LEN_ERR;
+ output [19:0] STAT_RX_MF_REPEAT_ERR;
+ output STAT_RX_MISALIGNED;
+ output STAT_RX_MULTICAST;
+ output STAT_RX_OVERSIZE;
+ output STAT_RX_PACKET_1024_1518_BYTES;
+ output STAT_RX_PACKET_128_255_BYTES;
+ output STAT_RX_PACKET_1519_1522_BYTES;
+ output STAT_RX_PACKET_1523_1548_BYTES;
+ output STAT_RX_PACKET_1549_2047_BYTES;
+ output STAT_RX_PACKET_2048_4095_BYTES;
+ output STAT_RX_PACKET_256_511_BYTES;
+ output STAT_RX_PACKET_4096_8191_BYTES;
+ output STAT_RX_PACKET_512_1023_BYTES;
+ output STAT_RX_PACKET_64_BYTES;
+ output STAT_RX_PACKET_65_127_BYTES;
+ output STAT_RX_PACKET_8192_9215_BYTES;
+ output STAT_RX_PACKET_BAD_FCS;
+ output STAT_RX_PACKET_LARGE;
+ output [2:0] STAT_RX_PACKET_SMALL;
+ output STAT_RX_PAUSE;
+ output [15:0] STAT_RX_PAUSE_QUANTA0;
+ output [15:0] STAT_RX_PAUSE_QUANTA1;
+ output [15:0] STAT_RX_PAUSE_QUANTA2;
+ output [15:0] STAT_RX_PAUSE_QUANTA3;
+ output [15:0] STAT_RX_PAUSE_QUANTA4;
+ output [15:0] STAT_RX_PAUSE_QUANTA5;
+ output [15:0] STAT_RX_PAUSE_QUANTA6;
+ output [15:0] STAT_RX_PAUSE_QUANTA7;
+ output [15:0] STAT_RX_PAUSE_QUANTA8;
+ output [8:0] STAT_RX_PAUSE_REQ;
+ output [8:0] STAT_RX_PAUSE_VALID;
+ output STAT_RX_RECEIVED_LOCAL_FAULT;
+ output STAT_RX_REMOTE_FAULT;
+ output STAT_RX_RSFEC_AM_LOCK0;
+ output STAT_RX_RSFEC_AM_LOCK1;
+ output STAT_RX_RSFEC_AM_LOCK2;
+ output STAT_RX_RSFEC_AM_LOCK3;
+ output STAT_RX_RSFEC_CORRECTED_CW_INC;
+ output STAT_RX_RSFEC_CW_INC;
+ output [2:0] STAT_RX_RSFEC_ERR_COUNT0_INC;
+ output [2:0] STAT_RX_RSFEC_ERR_COUNT1_INC;
+ output [2:0] STAT_RX_RSFEC_ERR_COUNT2_INC;
+ output [2:0] STAT_RX_RSFEC_ERR_COUNT3_INC;
+ output STAT_RX_RSFEC_HI_SER;
+ output STAT_RX_RSFEC_LANE_ALIGNMENT_STATUS;
+ output [13:0] STAT_RX_RSFEC_LANE_FILL_0;
+ output [13:0] STAT_RX_RSFEC_LANE_FILL_1;
+ output [13:0] STAT_RX_RSFEC_LANE_FILL_2;
+ output [13:0] STAT_RX_RSFEC_LANE_FILL_3;
+ output [7:0] STAT_RX_RSFEC_LANE_MAPPING;
+ output [31:0] STAT_RX_RSFEC_RSVD;
+ output STAT_RX_RSFEC_UNCORRECTED_CW_INC;
+ output STAT_RX_STATUS;
+ output [2:0] STAT_RX_STOMPED_FCS;
+ output [19:0] STAT_RX_SYNCED;
+ output [19:0] STAT_RX_SYNCED_ERR;
+ output [2:0] STAT_RX_TEST_PATTERN_MISMATCH;
+ output STAT_RX_TOOLONG;
+ output [6:0] STAT_RX_TOTAL_BYTES;
+ output [13:0] STAT_RX_TOTAL_GOOD_BYTES;
+ output STAT_RX_TOTAL_GOOD_PACKETS;
+ output [2:0] STAT_RX_TOTAL_PACKETS;
+ output STAT_RX_TRUNCATED;
+ output [2:0] STAT_RX_UNDERSIZE;
+ output STAT_RX_UNICAST;
+ output STAT_RX_USER_PAUSE;
+ output STAT_RX_VLAN;
+ output [19:0] STAT_RX_VL_DEMUXED;
+ output [4:0] STAT_RX_VL_NUMBER_0;
+ output [4:0] STAT_RX_VL_NUMBER_1;
+ output [4:0] STAT_RX_VL_NUMBER_10;
+ output [4:0] STAT_RX_VL_NUMBER_11;
+ output [4:0] STAT_RX_VL_NUMBER_12;
+ output [4:0] STAT_RX_VL_NUMBER_13;
+ output [4:0] STAT_RX_VL_NUMBER_14;
+ output [4:0] STAT_RX_VL_NUMBER_15;
+ output [4:0] STAT_RX_VL_NUMBER_16;
+ output [4:0] STAT_RX_VL_NUMBER_17;
+ output [4:0] STAT_RX_VL_NUMBER_18;
+ output [4:0] STAT_RX_VL_NUMBER_19;
+ output [4:0] STAT_RX_VL_NUMBER_2;
+ output [4:0] STAT_RX_VL_NUMBER_3;
+ output [4:0] STAT_RX_VL_NUMBER_4;
+ output [4:0] STAT_RX_VL_NUMBER_5;
+ output [4:0] STAT_RX_VL_NUMBER_6;
+ output [4:0] STAT_RX_VL_NUMBER_7;
+ output [4:0] STAT_RX_VL_NUMBER_8;
+ output [4:0] STAT_RX_VL_NUMBER_9;
+ output STAT_TX_BAD_FCS;
+ output STAT_TX_BROADCAST;
+ output STAT_TX_FRAME_ERROR;
+ output STAT_TX_LOCAL_FAULT;
+ output STAT_TX_MULTICAST;
+ output STAT_TX_PACKET_1024_1518_BYTES;
+ output STAT_TX_PACKET_128_255_BYTES;
+ output STAT_TX_PACKET_1519_1522_BYTES;
+ output STAT_TX_PACKET_1523_1548_BYTES;
+ output STAT_TX_PACKET_1549_2047_BYTES;
+ output STAT_TX_PACKET_2048_4095_BYTES;
+ output STAT_TX_PACKET_256_511_BYTES;
+ output STAT_TX_PACKET_4096_8191_BYTES;
+ output STAT_TX_PACKET_512_1023_BYTES;
+ output STAT_TX_PACKET_64_BYTES;
+ output STAT_TX_PACKET_65_127_BYTES;
+ output STAT_TX_PACKET_8192_9215_BYTES;
+ output STAT_TX_PACKET_LARGE;
+ output STAT_TX_PACKET_SMALL;
+ output STAT_TX_PAUSE;
+ output [8:0] STAT_TX_PAUSE_VALID;
+ output STAT_TX_PTP_FIFO_READ_ERROR;
+ output STAT_TX_PTP_FIFO_WRITE_ERROR;
+ output [5:0] STAT_TX_TOTAL_BYTES;
+ output [13:0] STAT_TX_TOTAL_GOOD_BYTES;
+ output STAT_TX_TOTAL_GOOD_PACKETS;
+ output STAT_TX_TOTAL_PACKETS;
+ output STAT_TX_UNICAST;
+ output STAT_TX_USER_PAUSE;
+ output STAT_TX_VLAN;
+ output TX_OVFOUT;
+ output [4:0] TX_PTP_PCSLANE_OUT;
+ output [79:0] TX_PTP_TSTAMP_OUT;
+ output [15:0] TX_PTP_TSTAMP_TAG_OUT;
+ output TX_PTP_TSTAMP_VALID_OUT;
+ output TX_RDYOUT;
+ output [15:0] TX_SERDES_ALT_DATA0;
+ output [15:0] TX_SERDES_ALT_DATA1;
+ output [15:0] TX_SERDES_ALT_DATA2;
+ output [15:0] TX_SERDES_ALT_DATA3;
+ output [63:0] TX_SERDES_DATA0;
+ output [63:0] TX_SERDES_DATA1;
+ output [63:0] TX_SERDES_DATA2;
+ output [63:0] TX_SERDES_DATA3;
+ output [31:0] TX_SERDES_DATA4;
+ output [31:0] TX_SERDES_DATA5;
+ output [31:0] TX_SERDES_DATA6;
+ output [31:0] TX_SERDES_DATA7;
+ output [31:0] TX_SERDES_DATA8;
+ output [31:0] TX_SERDES_DATA9;
+ output TX_UNFOUT;
+ input CTL_CAUI4_MODE;
+ input CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE;
+ input CTL_RSFEC_IEEE_ERROR_INDICATION_MODE;
+ input CTL_RX_CHECK_ETYPE_GCP;
+ input CTL_RX_CHECK_ETYPE_GPP;
+ input CTL_RX_CHECK_ETYPE_PCP;
+ input CTL_RX_CHECK_ETYPE_PPP;
+ input CTL_RX_CHECK_MCAST_GCP;
+ input CTL_RX_CHECK_MCAST_GPP;
+ input CTL_RX_CHECK_MCAST_PCP;
+ input CTL_RX_CHECK_MCAST_PPP;
+ input CTL_RX_CHECK_OPCODE_GCP;
+ input CTL_RX_CHECK_OPCODE_GPP;
+ input CTL_RX_CHECK_OPCODE_PCP;
+ input CTL_RX_CHECK_OPCODE_PPP;
+ input CTL_RX_CHECK_SA_GCP;
+ input CTL_RX_CHECK_SA_GPP;
+ input CTL_RX_CHECK_SA_PCP;
+ input CTL_RX_CHECK_SA_PPP;
+ input CTL_RX_CHECK_UCAST_GCP;
+ input CTL_RX_CHECK_UCAST_GPP;
+ input CTL_RX_CHECK_UCAST_PCP;
+ input CTL_RX_CHECK_UCAST_PPP;
+ input CTL_RX_ENABLE;
+ input CTL_RX_ENABLE_GCP;
+ input CTL_RX_ENABLE_GPP;
+ input CTL_RX_ENABLE_PCP;
+ input CTL_RX_ENABLE_PPP;
+ input CTL_RX_FORCE_RESYNC;
+ input [8:0] CTL_RX_PAUSE_ACK;
+ input [8:0] CTL_RX_PAUSE_ENABLE;
+ input CTL_RX_RSFEC_ENABLE;
+ input CTL_RX_RSFEC_ENABLE_CORRECTION;
+ input CTL_RX_RSFEC_ENABLE_INDICATION;
+ input [79:0] CTL_RX_SYSTEMTIMERIN;
+ input CTL_RX_TEST_PATTERN;
+ input CTL_TX_ENABLE;
+ input CTL_TX_LANE0_VLM_BIP7_OVERRIDE;
+ input [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE;
+ input [8:0] CTL_TX_PAUSE_ENABLE;
+ input [15:0] CTL_TX_PAUSE_QUANTA0;
+ input [15:0] CTL_TX_PAUSE_QUANTA1;
+ input [15:0] CTL_TX_PAUSE_QUANTA2;
+ input [15:0] CTL_TX_PAUSE_QUANTA3;
+ input [15:0] CTL_TX_PAUSE_QUANTA4;
+ input [15:0] CTL_TX_PAUSE_QUANTA5;
+ input [15:0] CTL_TX_PAUSE_QUANTA6;
+ input [15:0] CTL_TX_PAUSE_QUANTA7;
+ input [15:0] CTL_TX_PAUSE_QUANTA8;
+ input [15:0] CTL_TX_PAUSE_REFRESH_TIMER0;
+ input [15:0] CTL_TX_PAUSE_REFRESH_TIMER1;
+ input [15:0] CTL_TX_PAUSE_REFRESH_TIMER2;
+ input [15:0] CTL_TX_PAUSE_REFRESH_TIMER3;
+ input [15:0] CTL_TX_PAUSE_REFRESH_TIMER4;
+ input [15:0] CTL_TX_PAUSE_REFRESH_TIMER5;
+ input [15:0] CTL_TX_PAUSE_REFRESH_TIMER6;
+ input [15:0] CTL_TX_PAUSE_REFRESH_TIMER7;
+ input [15:0] CTL_TX_PAUSE_REFRESH_TIMER8;
+ input [8:0] CTL_TX_PAUSE_REQ;
+ input CTL_TX_PTP_VLANE_ADJUST_MODE;
+ input CTL_TX_RESEND_PAUSE;
+ input CTL_TX_RSFEC_ENABLE;
+ input CTL_TX_SEND_IDLE;
+ input CTL_TX_SEND_LFI;
+ input CTL_TX_SEND_RFI;
+ input [79:0] CTL_TX_SYSTEMTIMERIN;
+ input CTL_TX_TEST_PATTERN;
+ input [9:0] DRP_ADDR;
+ input DRP_CLK;
+ input [15:0] DRP_DI;
+ input DRP_EN;
+ input DRP_WE;
+ input [329:0] RSFEC_BYPASS_RX_DIN;
+ input RSFEC_BYPASS_RX_DIN_CW_START;
+ input [329:0] RSFEC_BYPASS_TX_DIN;
+ input RSFEC_BYPASS_TX_DIN_CW_START;
+ input RX_CLK;
+ input RX_RESET;
+ input [15:0] RX_SERDES_ALT_DATA0;
+ input [15:0] RX_SERDES_ALT_DATA1;
+ input [15:0] RX_SERDES_ALT_DATA2;
+ input [15:0] RX_SERDES_ALT_DATA3;
+ input [9:0] RX_SERDES_CLK;
+ input [63:0] RX_SERDES_DATA0;
+ input [63:0] RX_SERDES_DATA1;
+ input [63:0] RX_SERDES_DATA2;
+ input [63:0] RX_SERDES_DATA3;
+ input [31:0] RX_SERDES_DATA4;
+ input [31:0] RX_SERDES_DATA5;
+ input [31:0] RX_SERDES_DATA6;
+ input [31:0] RX_SERDES_DATA7;
+ input [31:0] RX_SERDES_DATA8;
+ input [31:0] RX_SERDES_DATA9;
+ input [9:0] RX_SERDES_RESET;
+ input TX_CLK;
+ input [127:0] TX_DATAIN0;
+ input [127:0] TX_DATAIN1;
+ input [127:0] TX_DATAIN2;
+ input [127:0] TX_DATAIN3;
+ input TX_ENAIN0;
+ input TX_ENAIN1;
+ input TX_ENAIN2;
+ input TX_ENAIN3;
+ input TX_EOPIN0;
+ input TX_EOPIN1;
+ input TX_EOPIN2;
+ input TX_EOPIN3;
+ input TX_ERRIN0;
+ input TX_ERRIN1;
+ input TX_ERRIN2;
+ input TX_ERRIN3;
+ input [3:0] TX_MTYIN0;
+ input [3:0] TX_MTYIN1;
+ input [3:0] TX_MTYIN2;
+ input [3:0] TX_MTYIN3;
+ input [55:0] TX_PREIN;
+ input [1:0] TX_PTP_1588OP_IN;
+ input [15:0] TX_PTP_CHKSUM_OFFSET_IN;
+ input [63:0] TX_PTP_RXTSTAMP_IN;
+ input [15:0] TX_PTP_TAG_FIELD_IN;
+ input [15:0] TX_PTP_TSTAMP_OFFSET_IN;
+ input TX_PTP_UPD_CHKSUM_IN;
+ input TX_RESET;
+ input TX_SOPIN0;
+ input TX_SOPIN1;
+ input TX_SOPIN2;
+ input TX_SOPIN3;
+endmodule
+
+module GTHE3_CHANNEL (...);
+ parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0;
+ parameter [0:0] ACJTAG_MODE = 1'b0;
+ parameter [0:0] ACJTAG_RESET = 1'b0;
+ parameter [15:0] ADAPT_CFG0 = 16'hF800;
+ parameter [15:0] ADAPT_CFG1 = 16'h0000;
+ parameter ALIGN_COMMA_DOUBLE = "FALSE";
+ parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111;
+ parameter integer ALIGN_COMMA_WORD = 1;
+ parameter ALIGN_MCOMMA_DET = "TRUE";
+ parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
+ parameter ALIGN_PCOMMA_DET = "TRUE";
+ parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
+ parameter [0:0] A_RXOSCALRESET = 1'b0;
+ parameter [0:0] A_RXPROGDIVRESET = 1'b0;
+ parameter [0:0] A_TXPROGDIVRESET = 1'b0;
+ parameter CBCC_DATA_SOURCE_SEL = "DECODED";
+ parameter [0:0] CDR_SWAP_MODE_EN = 1'b0;
+ parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
+ parameter integer CHAN_BOND_MAX_SKEW = 7;
+ parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
+ parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000;
+ parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000;
+ parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000;
+ parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
+ parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000;
+ parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000;
+ parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000;
+ parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000;
+ parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
+ parameter CHAN_BOND_SEQ_2_USE = "FALSE";
+ parameter integer CHAN_BOND_SEQ_LEN = 2;
+ parameter CLK_CORRECT_USE = "TRUE";
+ parameter CLK_COR_KEEP_IDLE = "FALSE";
+ parameter integer CLK_COR_MAX_LAT = 20;
+ parameter integer CLK_COR_MIN_LAT = 18;
+ parameter CLK_COR_PRECEDENCE = "TRUE";
+ parameter integer CLK_COR_REPEAT_WAIT = 0;
+ parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100;
+ parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000;
+ parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111;
+ parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000;
+ parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000;
+ parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000;
+ parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000;
+ parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
+ parameter CLK_COR_SEQ_2_USE = "FALSE";
+ parameter integer CLK_COR_SEQ_LEN = 2;
+ parameter [15:0] CPLL_CFG0 = 16'h20F8;
+ parameter [15:0] CPLL_CFG1 = 16'hA494;
+ parameter [15:0] CPLL_CFG2 = 16'hF001;
+ parameter [5:0] CPLL_CFG3 = 6'h00;
+ parameter integer CPLL_FBDIV = 4;
+ parameter integer CPLL_FBDIV_45 = 4;
+ parameter [15:0] CPLL_INIT_CFG0 = 16'h001E;
+ parameter [7:0] CPLL_INIT_CFG1 = 8'h00;
+ parameter [15:0] CPLL_LOCK_CFG = 16'h01E8;
+ parameter integer CPLL_REFCLK_DIV = 1;
+ parameter [1:0] DDI_CTRL = 2'b00;
+ parameter integer DDI_REALIGN_WAIT = 15;
+ parameter DEC_MCOMMA_DETECT = "TRUE";
+ parameter DEC_PCOMMA_DETECT = "TRUE";
+ parameter DEC_VALID_COMMA_ONLY = "TRUE";
+ parameter [0:0] DFE_D_X_REL_POS = 1'b0;
+ parameter [0:0] DFE_VCM_COMP_EN = 1'b0;
+ parameter [9:0] DMONITOR_CFG0 = 10'h000;
+ parameter [7:0] DMONITOR_CFG1 = 8'h00;
+ parameter [0:0] ES_CLK_PHASE_SEL = 1'b0;
+ parameter [5:0] ES_CONTROL = 6'b000000;
+ parameter ES_ERRDET_EN = "FALSE";
+ parameter ES_EYE_SCAN_EN = "FALSE";
+ parameter [11:0] ES_HORZ_OFFSET = 12'h000;
+ parameter [9:0] ES_PMA_CFG = 10'b0000000000;
+ parameter [4:0] ES_PRESCALE = 5'b00000;
+ parameter [15:0] ES_QUALIFIER0 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER1 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER2 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER3 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER4 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK0 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK1 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK2 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK3 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK4 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK0 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK1 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK2 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK3 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK4 = 16'h0000;
+ parameter [10:0] EVODD_PHI_CFG = 11'b00000000000;
+ parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0;
+ parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111;
+ parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111;
+ parameter FTS_LANE_DESKEW_EN = "FALSE";
+ parameter [4:0] GEARBOX_MODE = 5'b00000;
+ parameter [0:0] GM_BIAS_SELECT = 1'b0;
+ parameter [0:0] LOCAL_MASTER = 1'b0;
+ parameter [1:0] OOBDIVCTL = 2'b00;
+ parameter [0:0] OOB_PWRUP = 1'b0;
+ parameter PCI3_AUTO_REALIGN = "FRST_SMPL";
+ parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1;
+ parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00;
+ parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0;
+ parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000;
+ parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000;
+ parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000;
+ parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0;
+ parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0;
+ parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000;
+ parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000;
+ parameter [15:0] PCIE_RXPMA_CFG = 16'h0000;
+ parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000;
+ parameter [15:0] PCIE_TXPMA_CFG = 16'h0000;
+ parameter PCS_PCIE_EN = "FALSE";
+ parameter [15:0] PCS_RSVD0 = 16'b0000000000000000;
+ parameter [2:0] PCS_RSVD1 = 3'b000;
+ parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C;
+ parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19;
+ parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64;
+ parameter [1:0] PLL_SEL_MODE_GEN12 = 2'h0;
+ parameter [1:0] PLL_SEL_MODE_GEN3 = 2'h0;
+ parameter [15:0] PMA_RSV1 = 16'h0000;
+ parameter [2:0] PROCESS_PAR = 3'b010;
+ parameter [0:0] RATE_SW_USE_DRP = 1'b0;
+ parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0;
+ parameter [4:0] RXBUFRESET_TIME = 5'b00001;
+ parameter RXBUF_ADDR_MODE = "FULL";
+ parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000;
+ parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000;
+ parameter RXBUF_EN = "TRUE";
+ parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
+ parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
+ parameter RXBUF_RESET_ON_EIDLE = "FALSE";
+ parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
+ parameter integer RXBUF_THRESH_OVFLW = 0;
+ parameter RXBUF_THRESH_OVRD = "FALSE";
+ parameter integer RXBUF_THRESH_UNDFLW = 4;
+ parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001;
+ parameter [4:0] RXCDRPHRESET_TIME = 5'b00001;
+ parameter [15:0] RXCDR_CFG0 = 16'h0000;
+ parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0000;
+ parameter [15:0] RXCDR_CFG1 = 16'h0080;
+ parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000;
+ parameter [15:0] RXCDR_CFG2 = 16'h07E6;
+ parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0000;
+ parameter [15:0] RXCDR_CFG3 = 16'h0000;
+ parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0000;
+ parameter [15:0] RXCDR_CFG4 = 16'h0000;
+ parameter [15:0] RXCDR_CFG4_GEN3 = 16'h0000;
+ parameter [15:0] RXCDR_CFG5 = 16'h0000;
+ parameter [15:0] RXCDR_CFG5_GEN3 = 16'h0000;
+ parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0;
+ parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0;
+ parameter [15:0] RXCDR_LOCK_CFG0 = 16'h5080;
+ parameter [15:0] RXCDR_LOCK_CFG1 = 16'h07E0;
+ parameter [15:0] RXCDR_LOCK_CFG2 = 16'h7C42;
+ parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0;
+ parameter [15:0] RXCFOK_CFG0 = 16'h4000;
+ parameter [15:0] RXCFOK_CFG1 = 16'h0060;
+ parameter [15:0] RXCFOK_CFG2 = 16'h000E;
+ parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111;
+ parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000;
+ parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0032;
+ parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0000;
+ parameter [15:0] RXDFE_CFG0 = 16'h0A00;
+ parameter [15:0] RXDFE_CFG1 = 16'h0000;
+ parameter [15:0] RXDFE_GC_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_GC_CFG1 = 16'h7840;
+ parameter [15:0] RXDFE_GC_CFG2 = 16'h0000;
+ parameter [15:0] RXDFE_H2_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H2_CFG1 = 16'h0000;
+ parameter [15:0] RXDFE_H3_CFG0 = 16'h4000;
+ parameter [15:0] RXDFE_H3_CFG1 = 16'h0000;
+ parameter [15:0] RXDFE_H4_CFG0 = 16'h2000;
+ parameter [15:0] RXDFE_H4_CFG1 = 16'h0003;
+ parameter [15:0] RXDFE_H5_CFG0 = 16'h2000;
+ parameter [15:0] RXDFE_H5_CFG1 = 16'h0003;
+ parameter [15:0] RXDFE_H6_CFG0 = 16'h2000;
+ parameter [15:0] RXDFE_H6_CFG1 = 16'h0000;
+ parameter [15:0] RXDFE_H7_CFG0 = 16'h2000;
+ parameter [15:0] RXDFE_H7_CFG1 = 16'h0000;
+ parameter [15:0] RXDFE_H8_CFG0 = 16'h2000;
+ parameter [15:0] RXDFE_H8_CFG1 = 16'h0000;
+ parameter [15:0] RXDFE_H9_CFG0 = 16'h2000;
+ parameter [15:0] RXDFE_H9_CFG1 = 16'h0000;
+ parameter [15:0] RXDFE_HA_CFG0 = 16'h2000;
+ parameter [15:0] RXDFE_HA_CFG1 = 16'h0000;
+ parameter [15:0] RXDFE_HB_CFG0 = 16'h2000;
+ parameter [15:0] RXDFE_HB_CFG1 = 16'h0000;
+ parameter [15:0] RXDFE_HC_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_HC_CFG1 = 16'h0000;
+ parameter [15:0] RXDFE_HD_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_HD_CFG1 = 16'h0000;
+ parameter [15:0] RXDFE_HE_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_HE_CFG1 = 16'h0000;
+ parameter [15:0] RXDFE_HF_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_HF_CFG1 = 16'h0000;
+ parameter [15:0] RXDFE_OS_CFG0 = 16'h8000;
+ parameter [15:0] RXDFE_OS_CFG1 = 16'h0000;
+ parameter [15:0] RXDFE_UT_CFG0 = 16'h8000;
+ parameter [15:0] RXDFE_UT_CFG1 = 16'h0003;
+ parameter [15:0] RXDFE_VP_CFG0 = 16'hAA00;
+ parameter [15:0] RXDFE_VP_CFG1 = 16'h0033;
+ parameter [15:0] RXDLY_CFG = 16'h001F;
+ parameter [15:0] RXDLY_LCFG = 16'h0030;
+ parameter RXELECIDLE_CFG = "Sigcfg_4";
+ parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4;
+ parameter RXGEARBOX_EN = "FALSE";
+ parameter [4:0] RXISCANRESET_TIME = 5'b00001;
+ parameter [15:0] RXLPM_CFG = 16'h0000;
+ parameter [15:0] RXLPM_GC_CFG = 16'h0000;
+ parameter [15:0] RXLPM_KH_CFG0 = 16'h0000;
+ parameter [15:0] RXLPM_KH_CFG1 = 16'h0002;
+ parameter [15:0] RXLPM_OS_CFG0 = 16'h8000;
+ parameter [15:0] RXLPM_OS_CFG1 = 16'h0002;
+ parameter [8:0] RXOOB_CFG = 9'b000000110;
+ parameter RXOOB_CLK_CFG = "PMA";
+ parameter [4:0] RXOSCALRESET_TIME = 5'b00011;
+ parameter integer RXOUT_DIV = 4;
+ parameter [4:0] RXPCSRESET_TIME = 5'b00001;
+ parameter [15:0] RXPHBEACON_CFG = 16'h0000;
+ parameter [15:0] RXPHDLY_CFG = 16'h2020;
+ parameter [15:0] RXPHSAMP_CFG = 16'h2100;
+ parameter [15:0] RXPHSLIP_CFG = 16'h6622;
+ parameter [4:0] RXPH_MONITOR_SEL = 5'b00000;
+ parameter [1:0] RXPI_CFG0 = 2'b00;
+ parameter [1:0] RXPI_CFG1 = 2'b00;
+ parameter [1:0] RXPI_CFG2 = 2'b00;
+ parameter [1:0] RXPI_CFG3 = 2'b00;
+ parameter [0:0] RXPI_CFG4 = 1'b0;
+ parameter [0:0] RXPI_CFG5 = 1'b1;
+ parameter [2:0] RXPI_CFG6 = 3'b000;
+ parameter [0:0] RXPI_LPM = 1'b0;
+ parameter [0:0] RXPI_VREFSEL = 1'b0;
+ parameter RXPMACLK_SEL = "DATA";
+ parameter [4:0] RXPMARESET_TIME = 5'b00001;
+ parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0;
+ parameter integer RXPRBS_LINKACQ_CNT = 15;
+ parameter integer RXSLIDE_AUTO_WAIT = 7;
+ parameter RXSLIDE_MODE = "OFF";
+ parameter [0:0] RXSYNC_MULTILANE = 1'b0;
+ parameter [0:0] RXSYNC_OVRD = 1'b0;
+ parameter [0:0] RXSYNC_SKIP_DA = 1'b0;
+ parameter [0:0] RX_AFE_CM_EN = 1'b0;
+ parameter [15:0] RX_BIAS_CFG0 = 16'h0AD4;
+ parameter [5:0] RX_BUFFER_CFG = 6'b000000;
+ parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0;
+ parameter integer RX_CLK25_DIV = 8;
+ parameter [0:0] RX_CLKMUX_EN = 1'b1;
+ parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000;
+ parameter [3:0] RX_CM_BUF_CFG = 4'b1010;
+ parameter [0:0] RX_CM_BUF_PD = 1'b0;
+ parameter [1:0] RX_CM_SEL = 2'b11;
+ parameter [3:0] RX_CM_TRIM = 4'b0100;
+ parameter [7:0] RX_CTLE3_LPF = 8'b00000000;
+ parameter integer RX_DATA_WIDTH = 20;
+ parameter [5:0] RX_DDI_SEL = 6'b000000;
+ parameter RX_DEFER_RESET_BUF_EN = "TRUE";
+ parameter [3:0] RX_DFELPM_CFG0 = 4'b0110;
+ parameter [0:0] RX_DFELPM_CFG1 = 1'b0;
+ parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1;
+ parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00;
+ parameter [2:0] RX_DFE_AGC_CFG1 = 3'b100;
+ parameter [1:0] RX_DFE_KL_LPM_KH_CFG0 = 2'b01;
+ parameter [2:0] RX_DFE_KL_LPM_KH_CFG1 = 3'b010;
+ parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01;
+ parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010;
+ parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0;
+ parameter RX_DISPERR_SEQ_MATCH = "TRUE";
+ parameter [4:0] RX_DIVRESET_TIME = 5'b00001;
+ parameter [0:0] RX_EN_HI_LR = 1'b0;
+ parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000;
+ parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0;
+ parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00;
+ parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0;
+ parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0;
+ parameter integer RX_INT_DATAWIDTH = 1;
+ parameter [0:0] RX_PMA_POWER_SAVE = 1'b0;
+ parameter real RX_PROGDIV_CFG = 4.0;
+ parameter [2:0] RX_SAMPLE_PERIOD = 3'b101;
+ parameter integer RX_SIG_VALID_DLY = 11;
+ parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0;
+ parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000;
+ parameter [1:0] RX_SUM_RES_CTRL = 2'b00;
+ parameter [3:0] RX_SUM_VCMTUNE = 4'b0000;
+ parameter [0:0] RX_SUM_VCM_OVWR = 1'b0;
+ parameter [2:0] RX_SUM_VREF_TUNE = 3'b000;
+ parameter [1:0] RX_TUNE_AFE_OS = 2'b00;
+ parameter [0:0] RX_WIDEMODE_CDR = 1'b0;
+ parameter RX_XCLK_SEL = "RXDES";
+ parameter integer SAS_MAX_COM = 64;
+ parameter integer SAS_MIN_COM = 36;
+ parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
+ parameter [2:0] SATA_BURST_VAL = 3'b100;
+ parameter SATA_CPLL_CFG = "VCO_3000MHZ";
+ parameter [2:0] SATA_EIDLE_VAL = 3'b100;
+ parameter integer SATA_MAX_BURST = 8;
+ parameter integer SATA_MAX_INIT = 21;
+ parameter integer SATA_MAX_WAKE = 7;
+ parameter integer SATA_MIN_BURST = 4;
+ parameter integer SATA_MIN_INIT = 12;
+ parameter integer SATA_MIN_WAKE = 4;
+ parameter SHOW_REALIGN_COMMA = "TRUE";
+ parameter SIM_MODE = "FAST";
+ parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
+ parameter SIM_RESET_SPEEDUP = "TRUE";
+ parameter [0:0] SIM_TX_EIDLE_DRIVE_LEVEL = 1'b0;
+ parameter integer SIM_VERSION = 2;
+ parameter [1:0] TAPDLY_SET_TX = 2'h0;
+ parameter [3:0] TEMPERATUR_PAR = 4'b0010;
+ parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000;
+ parameter [2:0] TERM_RCAL_OVRD = 3'b000;
+ parameter [7:0] TRANS_TIME_RATE = 8'h0E;
+ parameter [7:0] TST_RSV0 = 8'h00;
+ parameter [7:0] TST_RSV1 = 8'h00;
+ parameter TXBUF_EN = "TRUE";
+ parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE";
+ parameter [15:0] TXDLY_CFG = 16'h001F;
+ parameter [15:0] TXDLY_LCFG = 16'h0030;
+ parameter [3:0] TXDRVBIAS_N = 4'b1010;
+ parameter [3:0] TXDRVBIAS_P = 4'b1100;
+ parameter TXFIFO_ADDR_CFG = "LOW";
+ parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4;
+ parameter TXGEARBOX_EN = "FALSE";
+ parameter integer TXOUT_DIV = 4;
+ parameter [4:0] TXPCSRESET_TIME = 5'b00001;
+ parameter [15:0] TXPHDLY_CFG0 = 16'h2020;
+ parameter [15:0] TXPHDLY_CFG1 = 16'h0001;
+ parameter [15:0] TXPH_CFG = 16'h0980;
+ parameter [4:0] TXPH_MONITOR_SEL = 5'b00000;
+ parameter [1:0] TXPI_CFG0 = 2'b00;
+ parameter [1:0] TXPI_CFG1 = 2'b00;
+ parameter [1:0] TXPI_CFG2 = 2'b00;
+ parameter [0:0] TXPI_CFG3 = 1'b0;
+ parameter [0:0] TXPI_CFG4 = 1'b1;
+ parameter [2:0] TXPI_CFG5 = 3'b000;
+ parameter [0:0] TXPI_GRAY_SEL = 1'b0;
+ parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0;
+ parameter [0:0] TXPI_LPM = 1'b0;
+ parameter TXPI_PPMCLK_SEL = "TXUSRCLK2";
+ parameter [7:0] TXPI_PPM_CFG = 8'b00000000;
+ parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000;
+ parameter [0:0] TXPI_VREFSEL = 1'b0;
+ parameter [4:0] TXPMARESET_TIME = 5'b00001;
+ parameter [0:0] TXSYNC_MULTILANE = 1'b0;
+ parameter [0:0] TXSYNC_OVRD = 1'b0;
+ parameter [0:0] TXSYNC_SKIP_DA = 1'b0;
+ parameter integer TX_CLK25_DIV = 8;
+ parameter [0:0] TX_CLKMUX_EN = 1'b1;
+ parameter integer TX_DATA_WIDTH = 20;
+ parameter [5:0] TX_DCD_CFG = 6'b000010;
+ parameter [0:0] TX_DCD_EN = 1'b0;
+ parameter [5:0] TX_DEEMPH0 = 6'b000000;
+ parameter [5:0] TX_DEEMPH1 = 6'b000000;
+ parameter [4:0] TX_DIVRESET_TIME = 5'b00001;
+ parameter TX_DRIVE_MODE = "DIRECT";
+ parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110;
+ parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100;
+ parameter [0:0] TX_EML_PHI_TUNE = 1'b0;
+ parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0;
+ parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0;
+ parameter integer TX_INT_DATAWIDTH = 1;
+ parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
+ parameter [0:0] TX_MAINCURSOR_SEL = 1'b0;
+ parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110;
+ parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001;
+ parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101;
+ parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010;
+ parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000;
+ parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110;
+ parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100;
+ parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
+ parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
+ parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
+ parameter [2:0] TX_MODE_SEL = 3'b000;
+ parameter [0:0] TX_PMADATA_OPT = 1'b0;
+ parameter [0:0] TX_PMA_POWER_SAVE = 1'b0;
+ parameter TX_PROGCLK_SEL = "POSTPI";
+ parameter real TX_PROGDIV_CFG = 4.0;
+ parameter [0:0] TX_QPI_STATUS_EN = 1'b0;
+ parameter [13:0] TX_RXDETECT_CFG = 14'h0032;
+ parameter [2:0] TX_RXDETECT_REF = 3'b100;
+ parameter [2:0] TX_SAMPLE_PERIOD = 3'b101;
+ parameter [0:0] TX_SARC_LPBK_ENB = 1'b0;
+ parameter TX_XCLK_SEL = "TXOUT";
+ parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0;
+ parameter [1:0] WB_MODE = 2'b00;
+ output [2:0] BUFGTCE;
+ output [2:0] BUFGTCEMASK;
+ output [8:0] BUFGTDIV;
+ output [2:0] BUFGTRESET;
+ output [2:0] BUFGTRSTMASK;
+ output CPLLFBCLKLOST;
+ output CPLLLOCK;
+ output CPLLREFCLKLOST;
+ output [16:0] DMONITOROUT;
+ output [15:0] DRPDO;
+ output DRPRDY;
+ output EYESCANDATAERROR;
+ output GTHTXN;
+ output GTHTXP;
+ output GTPOWERGOOD;
+ output GTREFCLKMONITOR;
+ output PCIERATEGEN3;
+ output PCIERATEIDLE;
+ output [1:0] PCIERATEQPLLPD;
+ output [1:0] PCIERATEQPLLRESET;
+ output PCIESYNCTXSYNCDONE;
+ output PCIEUSERGEN3RDY;
+ output PCIEUSERPHYSTATUSRST;
+ output PCIEUSERRATESTART;
+ output [11:0] PCSRSVDOUT;
+ output PHYSTATUS;
+ output [7:0] PINRSRVDAS;
+ output RESETEXCEPTION;
+ output [2:0] RXBUFSTATUS;
+ output RXBYTEISALIGNED;
+ output RXBYTEREALIGN;
+ output RXCDRLOCK;
+ output RXCDRPHDONE;
+ output RXCHANBONDSEQ;
+ output RXCHANISALIGNED;
+ output RXCHANREALIGN;
+ output [4:0] RXCHBONDO;
+ output [1:0] RXCLKCORCNT;
+ output RXCOMINITDET;
+ output RXCOMMADET;
+ output RXCOMSASDET;
+ output RXCOMWAKEDET;
+ output [15:0] RXCTRL0;
+ output [15:0] RXCTRL1;
+ output [7:0] RXCTRL2;
+ output [7:0] RXCTRL3;
+ output [127:0] RXDATA;
+ output [7:0] RXDATAEXTENDRSVD;
+ output [1:0] RXDATAVALID;
+ output RXDLYSRESETDONE;
+ output RXELECIDLE;
+ output [5:0] RXHEADER;
+ output [1:0] RXHEADERVALID;
+ output [6:0] RXMONITOROUT;
+ output RXOSINTDONE;
+ output RXOSINTSTARTED;
+ output RXOSINTSTROBEDONE;
+ output RXOSINTSTROBESTARTED;
+ output RXOUTCLK;
+ output RXOUTCLKFABRIC;
+ output RXOUTCLKPCS;
+ output RXPHALIGNDONE;
+ output RXPHALIGNERR;
+ output RXPMARESETDONE;
+ output RXPRBSERR;
+ output RXPRBSLOCKED;
+ output RXPRGDIVRESETDONE;
+ output RXQPISENN;
+ output RXQPISENP;
+ output RXRATEDONE;
+ output RXRECCLKOUT;
+ output RXRESETDONE;
+ output RXSLIDERDY;
+ output RXSLIPDONE;
+ output RXSLIPOUTCLKRDY;
+ output RXSLIPPMARDY;
+ output [1:0] RXSTARTOFSEQ;
+ output [2:0] RXSTATUS;
+ output RXSYNCDONE;
+ output RXSYNCOUT;
+ output RXVALID;
+ output [1:0] TXBUFSTATUS;
+ output TXCOMFINISH;
+ output TXDLYSRESETDONE;
+ output TXOUTCLK;
+ output TXOUTCLKFABRIC;
+ output TXOUTCLKPCS;
+ output TXPHALIGNDONE;
+ output TXPHINITDONE;
+ output TXPMARESETDONE;
+ output TXPRGDIVRESETDONE;
+ output TXQPISENN;
+ output TXQPISENP;
+ output TXRATEDONE;
+ output TXRESETDONE;
+ output TXSYNCDONE;
+ output TXSYNCOUT;
+ input CFGRESET;
+ input CLKRSVD0;
+ input CLKRSVD1;
+ input CPLLLOCKDETCLK;
+ input CPLLLOCKEN;
+ input CPLLPD;
+ input [2:0] CPLLREFCLKSEL;
+ input CPLLRESET;
+ input DMONFIFORESET;
+ input DMONITORCLK;
+ input [8:0] DRPADDR;
+ input DRPCLK;
+ input [15:0] DRPDI;
+ input DRPEN;
+ input DRPWE;
+ input EVODDPHICALDONE;
+ input EVODDPHICALSTART;
+ input EVODDPHIDRDEN;
+ input EVODDPHIDWREN;
+ input EVODDPHIXRDEN;
+ input EVODDPHIXWREN;
+ input EYESCANMODE;
+ input EYESCANRESET;
+ input EYESCANTRIGGER;
+ input GTGREFCLK;
+ input GTHRXN;
+ input GTHRXP;
+ input GTNORTHREFCLK0;
+ input GTNORTHREFCLK1;
+ input GTREFCLK0;
+ input GTREFCLK1;
+ input GTRESETSEL;
+ input [15:0] GTRSVD;
+ input GTRXRESET;
+ input GTSOUTHREFCLK0;
+ input GTSOUTHREFCLK1;
+ input GTTXRESET;
+ input [2:0] LOOPBACK;
+ input LPBKRXTXSEREN;
+ input LPBKTXRXSEREN;
+ input PCIEEQRXEQADAPTDONE;
+ input PCIERSTIDLE;
+ input PCIERSTTXSYNCSTART;
+ input PCIEUSERRATEDONE;
+ input [15:0] PCSRSVDIN;
+ input [4:0] PCSRSVDIN2;
+ input [4:0] PMARSVDIN;
+ input QPLL0CLK;
+ input QPLL0REFCLK;
+ input QPLL1CLK;
+ input QPLL1REFCLK;
+ input RESETOVRD;
+ input RSTCLKENTX;
+ input RX8B10BEN;
+ input RXBUFRESET;
+ input RXCDRFREQRESET;
+ input RXCDRHOLD;
+ input RXCDROVRDEN;
+ input RXCDRRESET;
+ input RXCDRRESETRSV;
+ input RXCHBONDEN;
+ input [4:0] RXCHBONDI;
+ input [2:0] RXCHBONDLEVEL;
+ input RXCHBONDMASTER;
+ input RXCHBONDSLAVE;
+ input RXCOMMADETEN;
+ input [1:0] RXDFEAGCCTRL;
+ input RXDFEAGCHOLD;
+ input RXDFEAGCOVRDEN;
+ input RXDFELFHOLD;
+ input RXDFELFOVRDEN;
+ input RXDFELPMRESET;
+ input RXDFETAP10HOLD;
+ input RXDFETAP10OVRDEN;
+ input RXDFETAP11HOLD;
+ input RXDFETAP11OVRDEN;
+ input RXDFETAP12HOLD;
+ input RXDFETAP12OVRDEN;
+ input RXDFETAP13HOLD;
+ input RXDFETAP13OVRDEN;
+ input RXDFETAP14HOLD;
+ input RXDFETAP14OVRDEN;
+ input RXDFETAP15HOLD;
+ input RXDFETAP15OVRDEN;
+ input RXDFETAP2HOLD;
+ input RXDFETAP2OVRDEN;
+ input RXDFETAP3HOLD;
+ input RXDFETAP3OVRDEN;
+ input RXDFETAP4HOLD;
+ input RXDFETAP4OVRDEN;
+ input RXDFETAP5HOLD;
+ input RXDFETAP5OVRDEN;
+ input RXDFETAP6HOLD;
+ input RXDFETAP6OVRDEN;
+ input RXDFETAP7HOLD;
+ input RXDFETAP7OVRDEN;
+ input RXDFETAP8HOLD;
+ input RXDFETAP8OVRDEN;
+ input RXDFETAP9HOLD;
+ input RXDFETAP9OVRDEN;
+ input RXDFEUTHOLD;
+ input RXDFEUTOVRDEN;
+ input RXDFEVPHOLD;
+ input RXDFEVPOVRDEN;
+ input RXDFEVSEN;
+ input RXDFEXYDEN;
+ input RXDLYBYPASS;
+ input RXDLYEN;
+ input RXDLYOVRDEN;
+ input RXDLYSRESET;
+ input [1:0] RXELECIDLEMODE;
+ input RXGEARBOXSLIP;
+ input RXLATCLK;
+ input RXLPMEN;
+ input RXLPMGCHOLD;
+ input RXLPMGCOVRDEN;
+ input RXLPMHFHOLD;
+ input RXLPMHFOVRDEN;
+ input RXLPMLFHOLD;
+ input RXLPMLFKLOVRDEN;
+ input RXLPMOSHOLD;
+ input RXLPMOSOVRDEN;
+ input RXMCOMMAALIGNEN;
+ input [1:0] RXMONITORSEL;
+ input RXOOBRESET;
+ input RXOSCALRESET;
+ input RXOSHOLD;
+ input [3:0] RXOSINTCFG;
+ input RXOSINTEN;
+ input RXOSINTHOLD;
+ input RXOSINTOVRDEN;
+ input RXOSINTSTROBE;
+ input RXOSINTTESTOVRDEN;
+ input RXOSOVRDEN;
+ input [2:0] RXOUTCLKSEL;
+ input RXPCOMMAALIGNEN;
+ input RXPCSRESET;
+ input [1:0] RXPD;
+ input RXPHALIGN;
+ input RXPHALIGNEN;
+ input RXPHDLYPD;
+ input RXPHDLYRESET;
+ input RXPHOVRDEN;
+ input [1:0] RXPLLCLKSEL;
+ input RXPMARESET;
+ input RXPOLARITY;
+ input RXPRBSCNTRESET;
+ input [3:0] RXPRBSSEL;
+ input RXPROGDIVRESET;
+ input RXQPIEN;
+ input [2:0] RXRATE;
+ input RXRATEMODE;
+ input RXSLIDE;
+ input RXSLIPOUTCLK;
+ input RXSLIPPMA;
+ input RXSYNCALLIN;
+ input RXSYNCIN;
+ input RXSYNCMODE;
+ input [1:0] RXSYSCLKSEL;
+ input RXUSERRDY;
+ input RXUSRCLK;
+ input RXUSRCLK2;
+ input SIGVALIDCLK;
+ input [19:0] TSTIN;
+ input [7:0] TX8B10BBYPASS;
+ input TX8B10BEN;
+ input [2:0] TXBUFDIFFCTRL;
+ input TXCOMINIT;
+ input TXCOMSAS;
+ input TXCOMWAKE;
+ input [15:0] TXCTRL0;
+ input [15:0] TXCTRL1;
+ input [7:0] TXCTRL2;
+ input [127:0] TXDATA;
+ input [7:0] TXDATAEXTENDRSVD;
+ input TXDEEMPH;
+ input TXDETECTRX;
+ input [3:0] TXDIFFCTRL;
+ input TXDIFFPD;
+ input TXDLYBYPASS;
+ input TXDLYEN;
+ input TXDLYHOLD;
+ input TXDLYOVRDEN;
+ input TXDLYSRESET;
+ input TXDLYUPDOWN;
+ input TXELECIDLE;
+ input [5:0] TXHEADER;
+ input TXINHIBIT;
+ input TXLATCLK;
+ input [6:0] TXMAINCURSOR;
+ input [2:0] TXMARGIN;
+ input [2:0] TXOUTCLKSEL;
+ input TXPCSRESET;
+ input [1:0] TXPD;
+ input TXPDELECIDLEMODE;
+ input TXPHALIGN;
+ input TXPHALIGNEN;
+ input TXPHDLYPD;
+ input TXPHDLYRESET;
+ input TXPHDLYTSTCLK;
+ input TXPHINIT;
+ input TXPHOVRDEN;
+ input TXPIPPMEN;
+ input TXPIPPMOVRDEN;
+ input TXPIPPMPD;
+ input TXPIPPMSEL;
+ input [4:0] TXPIPPMSTEPSIZE;
+ input TXPISOPD;
+ input [1:0] TXPLLCLKSEL;
+ input TXPMARESET;
+ input TXPOLARITY;
+ input [4:0] TXPOSTCURSOR;
+ input TXPOSTCURSORINV;
+ input TXPRBSFORCEERR;
+ input [3:0] TXPRBSSEL;
+ input [4:0] TXPRECURSOR;
+ input TXPRECURSORINV;
+ input TXPROGDIVRESET;
+ input TXQPIBIASEN;
+ input TXQPISTRONGPDOWN;
+ input TXQPIWEAKPUP;
+ input [2:0] TXRATE;
+ input TXRATEMODE;
+ input [6:0] TXSEQUENCE;
+ input TXSWING;
+ input TXSYNCALLIN;
+ input TXSYNCIN;
+ input TXSYNCMODE;
+ input [1:0] TXSYSCLKSEL;
+ input TXUSERRDY;
+ input TXUSRCLK;
+ input TXUSRCLK2;
+endmodule
+
+module GTHE3_COMMON (...);
+ parameter [15:0] BIAS_CFG0 = 16'h0000;
+ parameter [15:0] BIAS_CFG1 = 16'h0000;
+ parameter [15:0] BIAS_CFG2 = 16'h0000;
+ parameter [15:0] BIAS_CFG3 = 16'h0000;
+ parameter [15:0] BIAS_CFG4 = 16'h0000;
+ parameter [9:0] BIAS_CFG_RSVD = 10'b0000000000;
+ parameter [15:0] COMMON_CFG0 = 16'h0000;
+ parameter [15:0] COMMON_CFG1 = 16'h0000;
+ parameter [15:0] POR_CFG = 16'h0004;
+ parameter [15:0] QPLL0_CFG0 = 16'h3018;
+ parameter [15:0] QPLL0_CFG1 = 16'h0000;
+ parameter [15:0] QPLL0_CFG1_G3 = 16'h0020;
+ parameter [15:0] QPLL0_CFG2 = 16'h0000;
+ parameter [15:0] QPLL0_CFG2_G3 = 16'h0000;
+ parameter [15:0] QPLL0_CFG3 = 16'h0120;
+ parameter [15:0] QPLL0_CFG4 = 16'h0009;
+ parameter [9:0] QPLL0_CP = 10'b0000011111;
+ parameter [9:0] QPLL0_CP_G3 = 10'b0000011111;
+ parameter integer QPLL0_FBDIV = 66;
+ parameter integer QPLL0_FBDIV_G3 = 80;
+ parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000;
+ parameter [7:0] QPLL0_INIT_CFG1 = 8'h00;
+ parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8;
+ parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h01E8;
+ parameter [9:0] QPLL0_LPF = 10'b1111111111;
+ parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111;
+ parameter integer QPLL0_REFCLK_DIV = 2;
+ parameter [15:0] QPLL0_SDM_CFG0 = 16'b0000000000000000;
+ parameter [15:0] QPLL0_SDM_CFG1 = 16'b0000000000000000;
+ parameter [15:0] QPLL0_SDM_CFG2 = 16'b0000000000000000;
+ parameter [15:0] QPLL1_CFG0 = 16'h3018;
+ parameter [15:0] QPLL1_CFG1 = 16'h0000;
+ parameter [15:0] QPLL1_CFG1_G3 = 16'h0020;
+ parameter [15:0] QPLL1_CFG2 = 16'h0000;
+ parameter [15:0] QPLL1_CFG2_G3 = 16'h0000;
+ parameter [15:0] QPLL1_CFG3 = 16'h0120;
+ parameter [15:0] QPLL1_CFG4 = 16'h0009;
+ parameter [9:0] QPLL1_CP = 10'b0000011111;
+ parameter [9:0] QPLL1_CP_G3 = 10'b0000011111;
+ parameter integer QPLL1_FBDIV = 66;
+ parameter integer QPLL1_FBDIV_G3 = 80;
+ parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000;
+ parameter [7:0] QPLL1_INIT_CFG1 = 8'h00;
+ parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8;
+ parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8;
+ parameter [9:0] QPLL1_LPF = 10'b1111111111;
+ parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111;
+ parameter integer QPLL1_REFCLK_DIV = 2;
+ parameter [15:0] QPLL1_SDM_CFG0 = 16'b0000000000000000;
+ parameter [15:0] QPLL1_SDM_CFG1 = 16'b0000000000000000;
+ parameter [15:0] QPLL1_SDM_CFG2 = 16'b0000000000000000;
+ parameter [15:0] RSVD_ATTR0 = 16'h0000;
+ parameter [15:0] RSVD_ATTR1 = 16'h0000;
+ parameter [15:0] RSVD_ATTR2 = 16'h0000;
+ parameter [15:0] RSVD_ATTR3 = 16'h0000;
+ parameter [1:0] RXRECCLKOUT0_SEL = 2'b00;
+ parameter [1:0] RXRECCLKOUT1_SEL = 2'b00;
+ parameter [0:0] SARC_EN = 1'b1;
+ parameter [0:0] SARC_SEL = 1'b0;
+ parameter [15:0] SDM0DATA1_0 = 16'b0000000000000000;
+ parameter [8:0] SDM0DATA1_1 = 9'b000000000;
+ parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000;
+ parameter [8:0] SDM0INITSEED0_1 = 9'b000000000;
+ parameter [0:0] SDM0_DATA_PIN_SEL = 1'b0;
+ parameter [0:0] SDM0_WIDTH_PIN_SEL = 1'b0;
+ parameter [15:0] SDM1DATA1_0 = 16'b0000000000000000;
+ parameter [8:0] SDM1DATA1_1 = 9'b000000000;
+ parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000;
+ parameter [8:0] SDM1INITSEED0_1 = 9'b000000000;
+ parameter [0:0] SDM1_DATA_PIN_SEL = 1'b0;
+ parameter [0:0] SDM1_WIDTH_PIN_SEL = 1'b0;
+ parameter SIM_MODE = "FAST";
+ parameter SIM_RESET_SPEEDUP = "TRUE";
+ parameter integer SIM_VERSION = 2;
+ output [15:0] DRPDO;
+ output DRPRDY;
+ output [7:0] PMARSVDOUT0;
+ output [7:0] PMARSVDOUT1;
+ output QPLL0FBCLKLOST;
+ output QPLL0LOCK;
+ output QPLL0OUTCLK;
+ output QPLL0OUTREFCLK;
+ output QPLL0REFCLKLOST;
+ output QPLL1FBCLKLOST;
+ output QPLL1LOCK;
+ output QPLL1OUTCLK;
+ output QPLL1OUTREFCLK;
+ output QPLL1REFCLKLOST;
+ output [7:0] QPLLDMONITOR0;
+ output [7:0] QPLLDMONITOR1;
+ output REFCLKOUTMONITOR0;
+ output REFCLKOUTMONITOR1;
+ output [1:0] RXRECCLK0_SEL;
+ output [1:0] RXRECCLK1_SEL;
+ input BGBYPASSB;
+ input BGMONITORENB;
+ input BGPDB;
+ input [4:0] BGRCALOVRD;
+ input BGRCALOVRDENB;
+ input [8:0] DRPADDR;
+ input DRPCLK;
+ input [15:0] DRPDI;
+ input DRPEN;
+ input DRPWE;
+ input GTGREFCLK0;
+ input GTGREFCLK1;
+ input GTNORTHREFCLK00;
+ input GTNORTHREFCLK01;
+ input GTNORTHREFCLK10;
+ input GTNORTHREFCLK11;
+ input GTREFCLK00;
+ input GTREFCLK01;
+ input GTREFCLK10;
+ input GTREFCLK11;
+ input GTSOUTHREFCLK00;
+ input GTSOUTHREFCLK01;
+ input GTSOUTHREFCLK10;
+ input GTSOUTHREFCLK11;
+ input [7:0] PMARSVD0;
+ input [7:0] PMARSVD1;
+ input QPLL0CLKRSVD0;
+ input QPLL0CLKRSVD1;
+ input QPLL0LOCKDETCLK;
+ input QPLL0LOCKEN;
+ input QPLL0PD;
+ input [2:0] QPLL0REFCLKSEL;
+ input QPLL0RESET;
+ input QPLL1CLKRSVD0;
+ input QPLL1CLKRSVD1;
+ input QPLL1LOCKDETCLK;
+ input QPLL1LOCKEN;
+ input QPLL1PD;
+ input [2:0] QPLL1REFCLKSEL;
+ input QPLL1RESET;
+ input [7:0] QPLLRSVD1;
+ input [4:0] QPLLRSVD2;
+ input [4:0] QPLLRSVD3;
+ input [7:0] QPLLRSVD4;
+ input RCALENB;
+endmodule
+
+module GTHE4_CHANNEL (...);
+ parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0;
+ parameter [0:0] ACJTAG_MODE = 1'b0;
+ parameter [0:0] ACJTAG_RESET = 1'b0;
+ parameter [15:0] ADAPT_CFG0 = 16'h9200;
+ parameter [15:0] ADAPT_CFG1 = 16'h801C;
+ parameter [15:0] ADAPT_CFG2 = 16'h0000;
+ parameter ALIGN_COMMA_DOUBLE = "FALSE";
+ parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111;
+ parameter integer ALIGN_COMMA_WORD = 1;
+ parameter ALIGN_MCOMMA_DET = "TRUE";
+ parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
+ parameter ALIGN_PCOMMA_DET = "TRUE";
+ parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
+ parameter [0:0] A_RXOSCALRESET = 1'b0;
+ parameter [0:0] A_RXPROGDIVRESET = 1'b0;
+ parameter [0:0] A_RXTERMINATION = 1'b1;
+ parameter [4:0] A_TXDIFFCTRL = 5'b01100;
+ parameter [0:0] A_TXPROGDIVRESET = 1'b0;
+ parameter [0:0] CAPBYPASS_FORCE = 1'b0;
+ parameter CBCC_DATA_SOURCE_SEL = "DECODED";
+ parameter [0:0] CDR_SWAP_MODE_EN = 1'b0;
+ parameter [0:0] CFOK_PWRSVE_EN = 1'b1;
+ parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
+ parameter integer CHAN_BOND_MAX_SKEW = 7;
+ parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
+ parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000;
+ parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000;
+ parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000;
+ parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
+ parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000;
+ parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000;
+ parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000;
+ parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000;
+ parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
+ parameter CHAN_BOND_SEQ_2_USE = "FALSE";
+ parameter integer CHAN_BOND_SEQ_LEN = 2;
+ parameter [15:0] CH_HSPMUX = 16'h2424;
+ parameter [15:0] CKCAL1_CFG_0 = 16'b0000000000000000;
+ parameter [15:0] CKCAL1_CFG_1 = 16'b0000000000000000;
+ parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000;
+ parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000;
+ parameter [15:0] CKCAL2_CFG_0 = 16'b0000000000000000;
+ parameter [15:0] CKCAL2_CFG_1 = 16'b0000000000000000;
+ parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000;
+ parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000;
+ parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000;
+ parameter [15:0] CKCAL_RSVD0 = 16'h4000;
+ parameter [15:0] CKCAL_RSVD1 = 16'h0000;
+ parameter CLK_CORRECT_USE = "TRUE";
+ parameter CLK_COR_KEEP_IDLE = "FALSE";
+ parameter integer CLK_COR_MAX_LAT = 20;
+ parameter integer CLK_COR_MIN_LAT = 18;
+ parameter CLK_COR_PRECEDENCE = "TRUE";
+ parameter integer CLK_COR_REPEAT_WAIT = 0;
+ parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100;
+ parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000;
+ parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111;
+ parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000;
+ parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000;
+ parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000;
+ parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000;
+ parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
+ parameter CLK_COR_SEQ_2_USE = "FALSE";
+ parameter integer CLK_COR_SEQ_LEN = 2;
+ parameter [15:0] CPLL_CFG0 = 16'h01FA;
+ parameter [15:0] CPLL_CFG1 = 16'h24A9;
+ parameter [15:0] CPLL_CFG2 = 16'h6807;
+ parameter [15:0] CPLL_CFG3 = 16'h0000;
+ parameter integer CPLL_FBDIV = 4;
+ parameter integer CPLL_FBDIV_45 = 4;
+ parameter [15:0] CPLL_INIT_CFG0 = 16'h001E;
+ parameter [15:0] CPLL_LOCK_CFG = 16'h01E8;
+ parameter integer CPLL_REFCLK_DIV = 1;
+ parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000;
+ parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0;
+ parameter [1:0] DDI_CTRL = 2'b00;
+ parameter integer DDI_REALIGN_WAIT = 15;
+ parameter DEC_MCOMMA_DETECT = "TRUE";
+ parameter DEC_PCOMMA_DETECT = "TRUE";
+ parameter DEC_VALID_COMMA_ONLY = "TRUE";
+ parameter [0:0] DELAY_ELEC = 1'b0;
+ parameter [9:0] DMONITOR_CFG0 = 10'h000;
+ parameter [7:0] DMONITOR_CFG1 = 8'h00;
+ parameter [0:0] ES_CLK_PHASE_SEL = 1'b0;
+ parameter [5:0] ES_CONTROL = 6'b000000;
+ parameter ES_ERRDET_EN = "FALSE";
+ parameter ES_EYE_SCAN_EN = "FALSE";
+ parameter [11:0] ES_HORZ_OFFSET = 12'h800;
+ parameter [4:0] ES_PRESCALE = 5'b00000;
+ parameter [15:0] ES_QUALIFIER0 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER1 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER2 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER3 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER4 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER5 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER6 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER7 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER8 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER9 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK0 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK1 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK2 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK3 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK4 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK5 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK6 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK7 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK8 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK9 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK0 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK1 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK2 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK3 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK4 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK5 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK6 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK7 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK8 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK9 = 16'h0000;
+ parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0;
+ parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111;
+ parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111;
+ parameter FTS_LANE_DESKEW_EN = "FALSE";
+ parameter [4:0] GEARBOX_MODE = 5'b00000;
+ parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0;
+ parameter [0:0] LOCAL_MASTER = 1'b0;
+ parameter [2:0] LPBK_BIAS_CTRL = 3'b000;
+ parameter [0:0] LPBK_EN_RCAL_B = 1'b0;
+ parameter [3:0] LPBK_EXT_RCAL = 4'b0000;
+ parameter [2:0] LPBK_IND_CTRL0 = 3'b000;
+ parameter [2:0] LPBK_IND_CTRL1 = 3'b000;
+ parameter [2:0] LPBK_IND_CTRL2 = 3'b000;
+ parameter [3:0] LPBK_RG_CTRL = 4'b0000;
+ parameter [1:0] OOBDIVCTL = 2'b00;
+ parameter [0:0] OOB_PWRUP = 1'b0;
+ parameter PCI3_AUTO_REALIGN = "FRST_SMPL";
+ parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1;
+ parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00;
+ parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0;
+ parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000;
+ parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000;
+ parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000;
+ parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0;
+ parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0;
+ parameter [4:0] PCIE3_CLK_COR_EMPTY_THRSH = 5'b00000;
+ parameter [5:0] PCIE3_CLK_COR_FULL_THRSH = 6'b010000;
+ parameter [4:0] PCIE3_CLK_COR_MAX_LAT = 5'b01000;
+ parameter [4:0] PCIE3_CLK_COR_MIN_LAT = 5'b00100;
+ parameter [5:0] PCIE3_CLK_COR_THRSH_TIMER = 6'b001000;
+ parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000;
+ parameter [1:0] PCIE_PLL_SEL_MODE_GEN12 = 2'h0;
+ parameter [1:0] PCIE_PLL_SEL_MODE_GEN3 = 2'h0;
+ parameter [1:0] PCIE_PLL_SEL_MODE_GEN4 = 2'h0;
+ parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000;
+ parameter [15:0] PCIE_RXPMA_CFG = 16'h0000;
+ parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000;
+ parameter [15:0] PCIE_TXPMA_CFG = 16'h0000;
+ parameter PCS_PCIE_EN = "FALSE";
+ parameter [15:0] PCS_RSVD0 = 16'b0000000000000000;
+ parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C;
+ parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19;
+ parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64;
+ parameter integer PREIQ_FREQ_BST = 0;
+ parameter [2:0] PROCESS_PAR = 3'b010;
+ parameter [0:0] RATE_SW_USE_DRP = 1'b0;
+ parameter [0:0] RCLK_SIPO_DLY_ENB = 1'b0;
+ parameter [0:0] RCLK_SIPO_INV_EN = 1'b0;
+ parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0;
+ parameter [2:0] RTX_BUF_CML_CTRL = 3'b010;
+ parameter [1:0] RTX_BUF_TERM_CTRL = 2'b00;
+ parameter [4:0] RXBUFRESET_TIME = 5'b00001;
+ parameter RXBUF_ADDR_MODE = "FULL";
+ parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000;
+ parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000;
+ parameter RXBUF_EN = "TRUE";
+ parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
+ parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
+ parameter RXBUF_RESET_ON_EIDLE = "FALSE";
+ parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
+ parameter integer RXBUF_THRESH_OVFLW = 0;
+ parameter RXBUF_THRESH_OVRD = "FALSE";
+ parameter integer RXBUF_THRESH_UNDFLW = 4;
+ parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001;
+ parameter [4:0] RXCDRPHRESET_TIME = 5'b00001;
+ parameter [15:0] RXCDR_CFG0 = 16'h0003;
+ parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0003;
+ parameter [15:0] RXCDR_CFG1 = 16'h0000;
+ parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000;
+ parameter [15:0] RXCDR_CFG2 = 16'h0164;
+ parameter [9:0] RXCDR_CFG2_GEN2 = 10'h164;
+ parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0034;
+ parameter [15:0] RXCDR_CFG2_GEN4 = 16'h0034;
+ parameter [15:0] RXCDR_CFG3 = 16'h0024;
+ parameter [5:0] RXCDR_CFG3_GEN2 = 6'h24;
+ parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0024;
+ parameter [15:0] RXCDR_CFG3_GEN4 = 16'h0024;
+ parameter [15:0] RXCDR_CFG4 = 16'h5CF6;
+ parameter [15:0] RXCDR_CFG4_GEN3 = 16'h5CF6;
+ parameter [15:0] RXCDR_CFG5 = 16'hB46B;
+ parameter [15:0] RXCDR_CFG5_GEN3 = 16'h146B;
+ parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0;
+ parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0;
+ parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0040;
+ parameter [15:0] RXCDR_LOCK_CFG1 = 16'h8000;
+ parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000;
+ parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000;
+ parameter [15:0] RXCDR_LOCK_CFG4 = 16'h0000;
+ parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0;
+ parameter [15:0] RXCFOK_CFG0 = 16'h0000;
+ parameter [15:0] RXCFOK_CFG1 = 16'h0002;
+ parameter [15:0] RXCFOK_CFG2 = 16'h002D;
+ parameter [15:0] RXCKCAL1_IQ_LOOP_RST_CFG = 16'h0000;
+ parameter [15:0] RXCKCAL1_I_LOOP_RST_CFG = 16'h0000;
+ parameter [15:0] RXCKCAL1_Q_LOOP_RST_CFG = 16'h0000;
+ parameter [15:0] RXCKCAL2_DX_LOOP_RST_CFG = 16'h0000;
+ parameter [15:0] RXCKCAL2_D_LOOP_RST_CFG = 16'h0000;
+ parameter [15:0] RXCKCAL2_S_LOOP_RST_CFG = 16'h0000;
+ parameter [15:0] RXCKCAL2_X_LOOP_RST_CFG = 16'h0000;
+ parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111;
+ parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000;
+ parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022;
+ parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100;
+ parameter [15:0] RXDFE_CFG0 = 16'h4000;
+ parameter [15:0] RXDFE_CFG1 = 16'h0000;
+ parameter [15:0] RXDFE_GC_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_GC_CFG1 = 16'h0000;
+ parameter [15:0] RXDFE_GC_CFG2 = 16'h0000;
+ parameter [15:0] RXDFE_H2_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H2_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_H3_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H3_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_H4_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H4_CFG1 = 16'h0003;
+ parameter [15:0] RXDFE_H5_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H5_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_H6_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H6_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_H7_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H7_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_H8_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H8_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_H9_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H9_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_HA_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_HA_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_HB_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_HB_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_HC_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_HC_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_HD_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_HD_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_HE_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_HE_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_HF_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_HF_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_KH_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_KH_CFG1 = 16'h0000;
+ parameter [15:0] RXDFE_KH_CFG2 = 16'h0000;
+ parameter [15:0] RXDFE_KH_CFG3 = 16'h0000;
+ parameter [15:0] RXDFE_OS_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_OS_CFG1 = 16'h0002;
+ parameter [0:0] RXDFE_PWR_SAVING = 1'b0;
+ parameter [15:0] RXDFE_UT_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_UT_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_UT_CFG2 = 16'h0000;
+ parameter [15:0] RXDFE_VP_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_VP_CFG1 = 16'h0022;
+ parameter [15:0] RXDLY_CFG = 16'h0010;
+ parameter [15:0] RXDLY_LCFG = 16'h0030;
+ parameter RXELECIDLE_CFG = "SIGCFG_4";
+ parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4;
+ parameter RXGEARBOX_EN = "FALSE";
+ parameter [4:0] RXISCANRESET_TIME = 5'b00001;
+ parameter [15:0] RXLPM_CFG = 16'h0000;
+ parameter [15:0] RXLPM_GC_CFG = 16'h1000;
+ parameter [15:0] RXLPM_KH_CFG0 = 16'h0000;
+ parameter [15:0] RXLPM_KH_CFG1 = 16'h0002;
+ parameter [15:0] RXLPM_OS_CFG0 = 16'h0000;
+ parameter [15:0] RXLPM_OS_CFG1 = 16'h0000;
+ parameter [8:0] RXOOB_CFG = 9'b000110000;
+ parameter RXOOB_CLK_CFG = "PMA";
+ parameter [4:0] RXOSCALRESET_TIME = 5'b00011;
+ parameter integer RXOUT_DIV = 4;
+ parameter [4:0] RXPCSRESET_TIME = 5'b00001;
+ parameter [15:0] RXPHBEACON_CFG = 16'h0000;
+ parameter [15:0] RXPHDLY_CFG = 16'h2020;
+ parameter [15:0] RXPHSAMP_CFG = 16'h2100;
+ parameter [15:0] RXPHSLIP_CFG = 16'h9933;
+ parameter [4:0] RXPH_MONITOR_SEL = 5'b00000;
+ parameter [0:0] RXPI_AUTO_BW_SEL_BYPASS = 1'b0;
+ parameter [15:0] RXPI_CFG0 = 16'h0002;
+ parameter [15:0] RXPI_CFG1 = 16'b0000000000000000;
+ parameter [0:0] RXPI_LPM = 1'b0;
+ parameter [1:0] RXPI_SEL_LC = 2'b00;
+ parameter [1:0] RXPI_STARTCODE = 2'b00;
+ parameter [0:0] RXPI_VREFSEL = 1'b0;
+ parameter RXPMACLK_SEL = "DATA";
+ parameter [4:0] RXPMARESET_TIME = 5'b00001;
+ parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0;
+ parameter integer RXPRBS_LINKACQ_CNT = 15;
+ parameter [0:0] RXREFCLKDIV2_SEL = 1'b0;
+ parameter integer RXSLIDE_AUTO_WAIT = 7;
+ parameter RXSLIDE_MODE = "OFF";
+ parameter [0:0] RXSYNC_MULTILANE = 1'b0;
+ parameter [0:0] RXSYNC_OVRD = 1'b0;
+ parameter [0:0] RXSYNC_SKIP_DA = 1'b0;
+ parameter [0:0] RX_AFE_CM_EN = 1'b0;
+ parameter [15:0] RX_BIAS_CFG0 = 16'h12B0;
+ parameter [5:0] RX_BUFFER_CFG = 6'b000000;
+ parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0;
+ parameter integer RX_CLK25_DIV = 8;
+ parameter [0:0] RX_CLKMUX_EN = 1'b1;
+ parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000;
+ parameter [3:0] RX_CM_BUF_CFG = 4'b1010;
+ parameter [0:0] RX_CM_BUF_PD = 1'b0;
+ parameter integer RX_CM_SEL = 3;
+ parameter integer RX_CM_TRIM = 12;
+ parameter [7:0] RX_CTLE3_LPF = 8'b00000000;
+ parameter integer RX_DATA_WIDTH = 20;
+ parameter [5:0] RX_DDI_SEL = 6'b000000;
+ parameter RX_DEFER_RESET_BUF_EN = "TRUE";
+ parameter [2:0] RX_DEGEN_CTRL = 3'b011;
+ parameter integer RX_DFELPM_CFG0 = 0;
+ parameter [0:0] RX_DFELPM_CFG1 = 1'b1;
+ parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1;
+ parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00;
+ parameter integer RX_DFE_AGC_CFG1 = 4;
+ parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1;
+ parameter integer RX_DFE_KL_LPM_KH_CFG1 = 4;
+ parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01;
+ parameter integer RX_DFE_KL_LPM_KL_CFG1 = 4;
+ parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0;
+ parameter RX_DISPERR_SEQ_MATCH = "TRUE";
+ parameter [0:0] RX_DIV2_MODE_B = 1'b0;
+ parameter [4:0] RX_DIVRESET_TIME = 5'b00001;
+ parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0;
+ parameter [0:0] RX_EN_HI_LR = 1'b1;
+ parameter [8:0] RX_EXT_RL_CTRL = 9'b000000000;
+ parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000;
+ parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0;
+ parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00;
+ parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0;
+ parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0;
+ parameter integer RX_INT_DATAWIDTH = 1;
+ parameter [0:0] RX_PMA_POWER_SAVE = 1'b0;
+ parameter [15:0] RX_PMA_RSV0 = 16'h0000;
+ parameter real RX_PROGDIV_CFG = 0.0;
+ parameter [15:0] RX_PROGDIV_RATE = 16'h0001;
+ parameter [3:0] RX_RESLOAD_CTRL = 4'b0000;
+ parameter [0:0] RX_RESLOAD_OVRD = 1'b0;
+ parameter [2:0] RX_SAMPLE_PERIOD = 3'b101;
+ parameter integer RX_SIG_VALID_DLY = 11;
+ parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0;
+ parameter [3:0] RX_SUM_IREF_TUNE = 4'b1001;
+ parameter [3:0] RX_SUM_RESLOAD_CTRL = 4'b0000;
+ parameter [3:0] RX_SUM_VCMTUNE = 4'b1010;
+ parameter [0:0] RX_SUM_VCM_OVWR = 1'b0;
+ parameter [2:0] RX_SUM_VREF_TUNE = 3'b100;
+ parameter [1:0] RX_TUNE_AFE_OS = 2'b00;
+ parameter [2:0] RX_VREG_CTRL = 3'b101;
+ parameter [0:0] RX_VREG_PDB = 1'b1;
+ parameter [1:0] RX_WIDEMODE_CDR = 2'b01;
+ parameter [1:0] RX_WIDEMODE_CDR_GEN3 = 2'b01;
+ parameter [1:0] RX_WIDEMODE_CDR_GEN4 = 2'b01;
+ parameter RX_XCLK_SEL = "RXDES";
+ parameter [0:0] RX_XMODE_SEL = 1'b0;
+ parameter [0:0] SAMPLE_CLK_PHASE = 1'b0;
+ parameter [0:0] SAS_12G_MODE = 1'b0;
+ parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
+ parameter [2:0] SATA_BURST_VAL = 3'b100;
+ parameter SATA_CPLL_CFG = "VCO_3000MHZ";
+ parameter [2:0] SATA_EIDLE_VAL = 3'b100;
+ parameter SHOW_REALIGN_COMMA = "TRUE";
+ parameter SIM_DEVICE = "ULTRASCALE_PLUS";
+ parameter SIM_MODE = "FAST";
+ parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
+ parameter SIM_RESET_SPEEDUP = "TRUE";
+ parameter SIM_TX_EIDLE_DRIVE_LEVEL = "Z";
+ parameter [0:0] SRSTMODE = 1'b0;
+ parameter [1:0] TAPDLY_SET_TX = 2'h0;
+ parameter [3:0] TEMPERATURE_PAR = 4'b0010;
+ parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000;
+ parameter [2:0] TERM_RCAL_OVRD = 3'b000;
+ parameter [7:0] TRANS_TIME_RATE = 8'h0E;
+ parameter [7:0] TST_RSV0 = 8'h00;
+ parameter [7:0] TST_RSV1 = 8'h00;
+ parameter TXBUF_EN = "TRUE";
+ parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE";
+ parameter [15:0] TXDLY_CFG = 16'h0010;
+ parameter [15:0] TXDLY_LCFG = 16'h0030;
+ parameter [3:0] TXDRVBIAS_N = 4'b1010;
+ parameter TXFIFO_ADDR_CFG = "LOW";
+ parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4;
+ parameter TXGEARBOX_EN = "FALSE";
+ parameter integer TXOUT_DIV = 4;
+ parameter [4:0] TXPCSRESET_TIME = 5'b00001;
+ parameter [15:0] TXPHDLY_CFG0 = 16'h6020;
+ parameter [15:0] TXPHDLY_CFG1 = 16'h0002;
+ parameter [15:0] TXPH_CFG = 16'h0123;
+ parameter [15:0] TXPH_CFG2 = 16'h0000;
+ parameter [4:0] TXPH_MONITOR_SEL = 5'b00000;
+ parameter [15:0] TXPI_CFG = 16'h0000;
+ parameter [1:0] TXPI_CFG0 = 2'b00;
+ parameter [1:0] TXPI_CFG1 = 2'b00;
+ parameter [1:0] TXPI_CFG2 = 2'b00;
+ parameter [0:0] TXPI_CFG3 = 1'b0;
+ parameter [0:0] TXPI_CFG4 = 1'b1;
+ parameter [2:0] TXPI_CFG5 = 3'b000;
+ parameter [0:0] TXPI_GRAY_SEL = 1'b0;
+ parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0;
+ parameter [0:0] TXPI_LPM = 1'b0;
+ parameter [0:0] TXPI_PPM = 1'b0;
+ parameter TXPI_PPMCLK_SEL = "TXUSRCLK2";
+ parameter [7:0] TXPI_PPM_CFG = 8'b00000000;
+ parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000;
+ parameter [0:0] TXPI_VREFSEL = 1'b0;
+ parameter [4:0] TXPMARESET_TIME = 5'b00001;
+ parameter [0:0] TXREFCLKDIV2_SEL = 1'b0;
+ parameter [0:0] TXSYNC_MULTILANE = 1'b0;
+ parameter [0:0] TXSYNC_OVRD = 1'b0;
+ parameter [0:0] TXSYNC_SKIP_DA = 1'b0;
+ parameter integer TX_CLK25_DIV = 8;
+ parameter [0:0] TX_CLKMUX_EN = 1'b1;
+ parameter integer TX_DATA_WIDTH = 20;
+ parameter [15:0] TX_DCC_LOOP_RST_CFG = 16'h0000;
+ parameter [5:0] TX_DEEMPH0 = 6'b000000;
+ parameter [5:0] TX_DEEMPH1 = 6'b000000;
+ parameter [5:0] TX_DEEMPH2 = 6'b000000;
+ parameter [5:0] TX_DEEMPH3 = 6'b000000;
+ parameter [4:0] TX_DIVRESET_TIME = 5'b00001;
+ parameter TX_DRIVE_MODE = "DIRECT";
+ parameter integer TX_DRVMUX_CTRL = 2;
+ parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110;
+ parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100;
+ parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0;
+ parameter [0:0] TX_FIFO_BYP_EN = 1'b0;
+ parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0;
+ parameter integer TX_INT_DATAWIDTH = 1;
+ parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
+ parameter [0:0] TX_MAINCURSOR_SEL = 1'b0;
+ parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110;
+ parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001;
+ parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101;
+ parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010;
+ parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000;
+ parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110;
+ parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100;
+ parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
+ parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
+ parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
+ parameter [15:0] TX_PHICAL_CFG0 = 16'h0000;
+ parameter [15:0] TX_PHICAL_CFG1 = 16'h003F;
+ parameter [15:0] TX_PHICAL_CFG2 = 16'h0000;
+ parameter integer TX_PI_BIASSET = 0;
+ parameter [1:0] TX_PI_IBIAS_MID = 2'b00;
+ parameter [0:0] TX_PMADATA_OPT = 1'b0;
+ parameter [0:0] TX_PMA_POWER_SAVE = 1'b0;
+ parameter [15:0] TX_PMA_RSV0 = 16'h0008;
+ parameter integer TX_PREDRV_CTRL = 2;
+ parameter TX_PROGCLK_SEL = "POSTPI";
+ parameter real TX_PROGDIV_CFG = 0.0;
+ parameter [15:0] TX_PROGDIV_RATE = 16'h0001;
+ parameter [0:0] TX_QPI_STATUS_EN = 1'b0;
+ parameter [13:0] TX_RXDETECT_CFG = 14'h0032;
+ parameter integer TX_RXDETECT_REF = 3;
+ parameter [2:0] TX_SAMPLE_PERIOD = 3'b101;
+ parameter [0:0] TX_SARC_LPBK_ENB = 1'b0;
+ parameter [1:0] TX_SW_MEAS = 2'b00;
+ parameter [2:0] TX_VREG_CTRL = 3'b000;
+ parameter [0:0] TX_VREG_PDB = 1'b0;
+ parameter [1:0] TX_VREG_VREFSEL = 2'b00;
+ parameter TX_XCLK_SEL = "TXOUT";
+ parameter [0:0] USB_BOTH_BURST_IDLE = 1'b0;
+ parameter [6:0] USB_BURSTMAX_U3WAKE = 7'b1111111;
+ parameter [6:0] USB_BURSTMIN_U3WAKE = 7'b1100011;
+ parameter [0:0] USB_CLK_COR_EQ_EN = 1'b0;
+ parameter [0:0] USB_EXT_CNTL = 1'b1;
+ parameter [9:0] USB_IDLEMAX_POLLING = 10'b1010111011;
+ parameter [9:0] USB_IDLEMIN_POLLING = 10'b0100101011;
+ parameter [8:0] USB_LFPSPING_BURST = 9'b000000101;
+ parameter [8:0] USB_LFPSPOLLING_BURST = 9'b000110001;
+ parameter [8:0] USB_LFPSPOLLING_IDLE_MS = 9'b000000100;
+ parameter [8:0] USB_LFPSU1EXIT_BURST = 9'b000011101;
+ parameter [8:0] USB_LFPSU2LPEXIT_BURST_MS = 9'b001100011;
+ parameter [8:0] USB_LFPSU3WAKE_BURST_MS = 9'b111110011;
+ parameter [3:0] USB_LFPS_TPERIOD = 4'b0011;
+ parameter [0:0] USB_LFPS_TPERIOD_ACCURATE = 1'b1;
+ parameter [0:0] USB_MODE = 1'b0;
+ parameter [0:0] USB_PCIE_ERR_REP_DIS = 1'b0;
+ parameter integer USB_PING_SATA_MAX_INIT = 21;
+ parameter integer USB_PING_SATA_MIN_INIT = 12;
+ parameter integer USB_POLL_SATA_MAX_BURST = 8;
+ parameter integer USB_POLL_SATA_MIN_BURST = 4;
+ parameter [0:0] USB_RAW_ELEC = 1'b0;
+ parameter [0:0] USB_RXIDLE_P0_CTRL = 1'b1;
+ parameter [0:0] USB_TXIDLE_TUNE_ENABLE = 1'b1;
+ parameter integer USB_U1_SATA_MAX_WAKE = 7;
+ parameter integer USB_U1_SATA_MIN_WAKE = 4;
+ parameter integer USB_U2_SAS_MAX_COM = 64;
+ parameter integer USB_U2_SAS_MIN_COM = 36;
+ parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0;
+ parameter [0:0] Y_ALL_MODE = 1'b0;
+ output BUFGTCE;
+ output [2:0] BUFGTCEMASK;
+ output [8:0] BUFGTDIV;
+ output BUFGTRESET;
+ output [2:0] BUFGTRSTMASK;
+ output CPLLFBCLKLOST;
+ output CPLLLOCK;
+ output CPLLREFCLKLOST;
+ output [15:0] DMONITOROUT;
+ output DMONITOROUTCLK;
+ output [15:0] DRPDO;
+ output DRPRDY;
+ output EYESCANDATAERROR;
+ output GTHTXN;
+ output GTHTXP;
+ output GTPOWERGOOD;
+ output GTREFCLKMONITOR;
+ output PCIERATEGEN3;
+ output PCIERATEIDLE;
+ output [1:0] PCIERATEQPLLPD;
+ output [1:0] PCIERATEQPLLRESET;
+ output PCIESYNCTXSYNCDONE;
+ output PCIEUSERGEN3RDY;
+ output PCIEUSERPHYSTATUSRST;
+ output PCIEUSERRATESTART;
+ output [15:0] PCSRSVDOUT;
+ output PHYSTATUS;
+ output [15:0] PINRSRVDAS;
+ output POWERPRESENT;
+ output RESETEXCEPTION;
+ output [2:0] RXBUFSTATUS;
+ output RXBYTEISALIGNED;
+ output RXBYTEREALIGN;
+ output RXCDRLOCK;
+ output RXCDRPHDONE;
+ output RXCHANBONDSEQ;
+ output RXCHANISALIGNED;
+ output RXCHANREALIGN;
+ output [4:0] RXCHBONDO;
+ output RXCKCALDONE;
+ output [1:0] RXCLKCORCNT;
+ output RXCOMINITDET;
+ output RXCOMMADET;
+ output RXCOMSASDET;
+ output RXCOMWAKEDET;
+ output [15:0] RXCTRL0;
+ output [15:0] RXCTRL1;
+ output [7:0] RXCTRL2;
+ output [7:0] RXCTRL3;
+ output [127:0] RXDATA;
+ output [7:0] RXDATAEXTENDRSVD;
+ output [1:0] RXDATAVALID;
+ output RXDLYSRESETDONE;
+ output RXELECIDLE;
+ output [5:0] RXHEADER;
+ output [1:0] RXHEADERVALID;
+ output RXLFPSTRESETDET;
+ output RXLFPSU2LPEXITDET;
+ output RXLFPSU3WAKEDET;
+ output [7:0] RXMONITOROUT;
+ output RXOSINTDONE;
+ output RXOSINTSTARTED;
+ output RXOSINTSTROBEDONE;
+ output RXOSINTSTROBESTARTED;
+ output RXOUTCLK;
+ output RXOUTCLKFABRIC;
+ output RXOUTCLKPCS;
+ output RXPHALIGNDONE;
+ output RXPHALIGNERR;
+ output RXPMARESETDONE;
+ output RXPRBSERR;
+ output RXPRBSLOCKED;
+ output RXPRGDIVRESETDONE;
+ output RXQPISENN;
+ output RXQPISENP;
+ output RXRATEDONE;
+ output RXRECCLKOUT;
+ output RXRESETDONE;
+ output RXSLIDERDY;
+ output RXSLIPDONE;
+ output RXSLIPOUTCLKRDY;
+ output RXSLIPPMARDY;
+ output [1:0] RXSTARTOFSEQ;
+ output [2:0] RXSTATUS;
+ output RXSYNCDONE;
+ output RXSYNCOUT;
+ output RXVALID;
+ output [1:0] TXBUFSTATUS;
+ output TXCOMFINISH;
+ output TXDCCDONE;
+ output TXDLYSRESETDONE;
+ output TXOUTCLK;
+ output TXOUTCLKFABRIC;
+ output TXOUTCLKPCS;
+ output TXPHALIGNDONE;
+ output TXPHINITDONE;
+ output TXPMARESETDONE;
+ output TXPRGDIVRESETDONE;
+ output TXQPISENN;
+ output TXQPISENP;
+ output TXRATEDONE;
+ output TXRESETDONE;
+ output TXSYNCDONE;
+ output TXSYNCOUT;
+ input CDRSTEPDIR;
+ input CDRSTEPSQ;
+ input CDRSTEPSX;
+ input CFGRESET;
+ input CLKRSVD0;
+ input CLKRSVD1;
+ input CPLLFREQLOCK;
+ input CPLLLOCKDETCLK;
+ input CPLLLOCKEN;
+ input CPLLPD;
+ input [2:0] CPLLREFCLKSEL;
+ input CPLLRESET;
+ input DMONFIFORESET;
+ input DMONITORCLK;
+ input [9:0] DRPADDR;
+ input DRPCLK;
+ input [15:0] DRPDI;
+ input DRPEN;
+ input DRPRST;
+ input DRPWE;
+ input EYESCANRESET;
+ input EYESCANTRIGGER;
+ input FREQOS;
+ input GTGREFCLK;
+ input GTHRXN;
+ input GTHRXP;
+ input GTNORTHREFCLK0;
+ input GTNORTHREFCLK1;
+ input GTREFCLK0;
+ input GTREFCLK1;
+ input [15:0] GTRSVD;
+ input GTRXRESET;
+ input GTRXRESETSEL;
+ input GTSOUTHREFCLK0;
+ input GTSOUTHREFCLK1;
+ input GTTXRESET;
+ input GTTXRESETSEL;
+ input INCPCTRL;
+ input [2:0] LOOPBACK;
+ input PCIEEQRXEQADAPTDONE;
+ input PCIERSTIDLE;
+ input PCIERSTTXSYNCSTART;
+ input PCIEUSERRATEDONE;
+ input [15:0] PCSRSVDIN;
+ input QPLL0CLK;
+ input QPLL0FREQLOCK;
+ input QPLL0REFCLK;
+ input QPLL1CLK;
+ input QPLL1FREQLOCK;
+ input QPLL1REFCLK;
+ input RESETOVRD;
+ input RX8B10BEN;
+ input RXAFECFOKEN;
+ input RXBUFRESET;
+ input RXCDRFREQRESET;
+ input RXCDRHOLD;
+ input RXCDROVRDEN;
+ input RXCDRRESET;
+ input RXCHBONDEN;
+ input [4:0] RXCHBONDI;
+ input [2:0] RXCHBONDLEVEL;
+ input RXCHBONDMASTER;
+ input RXCHBONDSLAVE;
+ input RXCKCALRESET;
+ input [6:0] RXCKCALSTART;
+ input RXCOMMADETEN;
+ input [1:0] RXDFEAGCCTRL;
+ input RXDFEAGCHOLD;
+ input RXDFEAGCOVRDEN;
+ input [3:0] RXDFECFOKFCNUM;
+ input RXDFECFOKFEN;
+ input RXDFECFOKFPULSE;
+ input RXDFECFOKHOLD;
+ input RXDFECFOKOVREN;
+ input RXDFEKHHOLD;
+ input RXDFEKHOVRDEN;
+ input RXDFELFHOLD;
+ input RXDFELFOVRDEN;
+ input RXDFELPMRESET;
+ input RXDFETAP10HOLD;
+ input RXDFETAP10OVRDEN;
+ input RXDFETAP11HOLD;
+ input RXDFETAP11OVRDEN;
+ input RXDFETAP12HOLD;
+ input RXDFETAP12OVRDEN;
+ input RXDFETAP13HOLD;
+ input RXDFETAP13OVRDEN;
+ input RXDFETAP14HOLD;
+ input RXDFETAP14OVRDEN;
+ input RXDFETAP15HOLD;
+ input RXDFETAP15OVRDEN;
+ input RXDFETAP2HOLD;
+ input RXDFETAP2OVRDEN;
+ input RXDFETAP3HOLD;
+ input RXDFETAP3OVRDEN;
+ input RXDFETAP4HOLD;
+ input RXDFETAP4OVRDEN;
+ input RXDFETAP5HOLD;
+ input RXDFETAP5OVRDEN;
+ input RXDFETAP6HOLD;
+ input RXDFETAP6OVRDEN;
+ input RXDFETAP7HOLD;
+ input RXDFETAP7OVRDEN;
+ input RXDFETAP8HOLD;
+ input RXDFETAP8OVRDEN;
+ input RXDFETAP9HOLD;
+ input RXDFETAP9OVRDEN;
+ input RXDFEUTHOLD;
+ input RXDFEUTOVRDEN;
+ input RXDFEVPHOLD;
+ input RXDFEVPOVRDEN;
+ input RXDFEXYDEN;
+ input RXDLYBYPASS;
+ input RXDLYEN;
+ input RXDLYOVRDEN;
+ input RXDLYSRESET;
+ input [1:0] RXELECIDLEMODE;
+ input RXEQTRAINING;
+ input RXGEARBOXSLIP;
+ input RXLATCLK;
+ input RXLPMEN;
+ input RXLPMGCHOLD;
+ input RXLPMGCOVRDEN;
+ input RXLPMHFHOLD;
+ input RXLPMHFOVRDEN;
+ input RXLPMLFHOLD;
+ input RXLPMLFKLOVRDEN;
+ input RXLPMOSHOLD;
+ input RXLPMOSOVRDEN;
+ input RXMCOMMAALIGNEN;
+ input [1:0] RXMONITORSEL;
+ input RXOOBRESET;
+ input RXOSCALRESET;
+ input RXOSHOLD;
+ input RXOSOVRDEN;
+ input [2:0] RXOUTCLKSEL;
+ input RXPCOMMAALIGNEN;
+ input RXPCSRESET;
+ input [1:0] RXPD;
+ input RXPHALIGN;
+ input RXPHALIGNEN;
+ input RXPHDLYPD;
+ input RXPHDLYRESET;
+ input RXPHOVRDEN;
+ input [1:0] RXPLLCLKSEL;
+ input RXPMARESET;
+ input RXPOLARITY;
+ input RXPRBSCNTRESET;
+ input [3:0] RXPRBSSEL;
+ input RXPROGDIVRESET;
+ input RXQPIEN;
+ input [2:0] RXRATE;
+ input RXRATEMODE;
+ input RXSLIDE;
+ input RXSLIPOUTCLK;
+ input RXSLIPPMA;
+ input RXSYNCALLIN;
+ input RXSYNCIN;
+ input RXSYNCMODE;
+ input [1:0] RXSYSCLKSEL;
+ input RXTERMINATION;
+ input RXUSERRDY;
+ input RXUSRCLK;
+ input RXUSRCLK2;
+ input SIGVALIDCLK;
+ input [19:0] TSTIN;
+ input [7:0] TX8B10BBYPASS;
+ input TX8B10BEN;
+ input TXCOMINIT;
+ input TXCOMSAS;
+ input TXCOMWAKE;
+ input [15:0] TXCTRL0;
+ input [15:0] TXCTRL1;
+ input [7:0] TXCTRL2;
+ input [127:0] TXDATA;
+ input [7:0] TXDATAEXTENDRSVD;
+ input TXDCCFORCESTART;
+ input TXDCCRESET;
+ input [1:0] TXDEEMPH;
+ input TXDETECTRX;
+ input [4:0] TXDIFFCTRL;
+ input TXDLYBYPASS;
+ input TXDLYEN;
+ input TXDLYHOLD;
+ input TXDLYOVRDEN;
+ input TXDLYSRESET;
+ input TXDLYUPDOWN;
+ input TXELECIDLE;
+ input [5:0] TXHEADER;
+ input TXINHIBIT;
+ input TXLATCLK;
+ input TXLFPSTRESET;
+ input TXLFPSU2LPEXIT;
+ input TXLFPSU3WAKE;
+ input [6:0] TXMAINCURSOR;
+ input [2:0] TXMARGIN;
+ input TXMUXDCDEXHOLD;
+ input TXMUXDCDORWREN;
+ input TXONESZEROS;
+ input [2:0] TXOUTCLKSEL;
+ input TXPCSRESET;
+ input [1:0] TXPD;
+ input TXPDELECIDLEMODE;
+ input TXPHALIGN;
+ input TXPHALIGNEN;
+ input TXPHDLYPD;
+ input TXPHDLYRESET;
+ input TXPHDLYTSTCLK;
+ input TXPHINIT;
+ input TXPHOVRDEN;
+ input TXPIPPMEN;
+ input TXPIPPMOVRDEN;
+ input TXPIPPMPD;
+ input TXPIPPMSEL;
+ input [4:0] TXPIPPMSTEPSIZE;
+ input TXPISOPD;
+ input [1:0] TXPLLCLKSEL;
+ input TXPMARESET;
+ input TXPOLARITY;
+ input [4:0] TXPOSTCURSOR;
+ input TXPRBSFORCEERR;
+ input [3:0] TXPRBSSEL;
+ input [4:0] TXPRECURSOR;
+ input TXPROGDIVRESET;
+ input TXQPIBIASEN;
+ input TXQPIWEAKPUP;
+ input [2:0] TXRATE;
+ input TXRATEMODE;
+ input [6:0] TXSEQUENCE;
+ input TXSWING;
+ input TXSYNCALLIN;
+ input TXSYNCIN;
+ input TXSYNCMODE;
+ input [1:0] TXSYSCLKSEL;
+ input TXUSERRDY;
+ input TXUSRCLK;
+ input TXUSRCLK2;
+endmodule
+
+module GTHE4_COMMON (...);
+ parameter [0:0] AEN_QPLL0_FBDIV = 1'b1;
+ parameter [0:0] AEN_QPLL1_FBDIV = 1'b1;
+ parameter [0:0] AEN_SDM0TOGGLE = 1'b0;
+ parameter [0:0] AEN_SDM1TOGGLE = 1'b0;
+ parameter [0:0] A_SDM0TOGGLE = 1'b0;
+ parameter [8:0] A_SDM1DATA_HIGH = 9'b000000000;
+ parameter [15:0] A_SDM1DATA_LOW = 16'b0000000000000000;
+ parameter [0:0] A_SDM1TOGGLE = 1'b0;
+ parameter [15:0] BIAS_CFG0 = 16'h0000;
+ parameter [15:0] BIAS_CFG1 = 16'h0000;
+ parameter [15:0] BIAS_CFG2 = 16'h0000;
+ parameter [15:0] BIAS_CFG3 = 16'h0000;
+ parameter [15:0] BIAS_CFG4 = 16'h0000;
+ parameter [15:0] BIAS_CFG_RSVD = 16'h0000;
+ parameter [15:0] COMMON_CFG0 = 16'h0000;
+ parameter [15:0] COMMON_CFG1 = 16'h0000;
+ parameter [15:0] POR_CFG = 16'h0000;
+ parameter [15:0] PPF0_CFG = 16'h0F00;
+ parameter [15:0] PPF1_CFG = 16'h0F00;
+ parameter QPLL0CLKOUT_RATE = "FULL";
+ parameter [15:0] QPLL0_CFG0 = 16'h391C;
+ parameter [15:0] QPLL0_CFG1 = 16'h0000;
+ parameter [15:0] QPLL0_CFG1_G3 = 16'h0020;
+ parameter [15:0] QPLL0_CFG2 = 16'h0F80;
+ parameter [15:0] QPLL0_CFG2_G3 = 16'h0F80;
+ parameter [15:0] QPLL0_CFG3 = 16'h0120;
+ parameter [15:0] QPLL0_CFG4 = 16'h0002;
+ parameter [9:0] QPLL0_CP = 10'b0000011111;
+ parameter [9:0] QPLL0_CP_G3 = 10'b0000011111;
+ parameter integer QPLL0_FBDIV = 66;
+ parameter integer QPLL0_FBDIV_G3 = 80;
+ parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000;
+ parameter [7:0] QPLL0_INIT_CFG1 = 8'h00;
+ parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8;
+ parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8;
+ parameter [9:0] QPLL0_LPF = 10'b1011111111;
+ parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111;
+ parameter [0:0] QPLL0_PCI_EN = 1'b0;
+ parameter [0:0] QPLL0_RATE_SW_USE_DRP = 1'b0;
+ parameter integer QPLL0_REFCLK_DIV = 1;
+ parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040;
+ parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000;
+ parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000;
+ parameter QPLL1CLKOUT_RATE = "FULL";
+ parameter [15:0] QPLL1_CFG0 = 16'h691C;
+ parameter [15:0] QPLL1_CFG1 = 16'h0020;
+ parameter [15:0] QPLL1_CFG1_G3 = 16'h0020;
+ parameter [15:0] QPLL1_CFG2 = 16'h0F80;
+ parameter [15:0] QPLL1_CFG2_G3 = 16'h0F80;
+ parameter [15:0] QPLL1_CFG3 = 16'h0120;
+ parameter [15:0] QPLL1_CFG4 = 16'h0002;
+ parameter [9:0] QPLL1_CP = 10'b0000011111;
+ parameter [9:0] QPLL1_CP_G3 = 10'b0000011111;
+ parameter integer QPLL1_FBDIV = 66;
+ parameter integer QPLL1_FBDIV_G3 = 80;
+ parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000;
+ parameter [7:0] QPLL1_INIT_CFG1 = 8'h00;
+ parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8;
+ parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8;
+ parameter [9:0] QPLL1_LPF = 10'b1011111111;
+ parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111;
+ parameter [0:0] QPLL1_PCI_EN = 1'b0;
+ parameter [0:0] QPLL1_RATE_SW_USE_DRP = 1'b0;
+ parameter integer QPLL1_REFCLK_DIV = 1;
+ parameter [15:0] QPLL1_SDM_CFG0 = 16'h0000;
+ parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000;
+ parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000;
+ parameter [15:0] RSVD_ATTR0 = 16'h0000;
+ parameter [15:0] RSVD_ATTR1 = 16'h0000;
+ parameter [15:0] RSVD_ATTR2 = 16'h0000;
+ parameter [15:0] RSVD_ATTR3 = 16'h0000;
+ parameter [1:0] RXRECCLKOUT0_SEL = 2'b00;
+ parameter [1:0] RXRECCLKOUT1_SEL = 2'b00;
+ parameter [0:0] SARC_ENB = 1'b0;
+ parameter [0:0] SARC_SEL = 1'b0;
+ parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000;
+ parameter [8:0] SDM0INITSEED0_1 = 9'b000000000;
+ parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000;
+ parameter [8:0] SDM1INITSEED0_1 = 9'b000000000;
+ parameter SIM_DEVICE = "ULTRASCALE_PLUS";
+ parameter SIM_MODE = "FAST";
+ parameter SIM_RESET_SPEEDUP = "TRUE";
+ output [15:0] DRPDO;
+ output DRPRDY;
+ output [7:0] PMARSVDOUT0;
+ output [7:0] PMARSVDOUT1;
+ output QPLL0FBCLKLOST;
+ output QPLL0LOCK;
+ output QPLL0OUTCLK;
+ output QPLL0OUTREFCLK;
+ output QPLL0REFCLKLOST;
+ output QPLL1FBCLKLOST;
+ output QPLL1LOCK;
+ output QPLL1OUTCLK;
+ output QPLL1OUTREFCLK;
+ output QPLL1REFCLKLOST;
+ output [7:0] QPLLDMONITOR0;
+ output [7:0] QPLLDMONITOR1;
+ output REFCLKOUTMONITOR0;
+ output REFCLKOUTMONITOR1;
+ output [1:0] RXRECCLK0SEL;
+ output [1:0] RXRECCLK1SEL;
+ output [3:0] SDM0FINALOUT;
+ output [14:0] SDM0TESTDATA;
+ output [3:0] SDM1FINALOUT;
+ output [14:0] SDM1TESTDATA;
+ output [9:0] TCONGPO;
+ output TCONRSVDOUT0;
+ input BGBYPASSB;
+ input BGMONITORENB;
+ input BGPDB;
+ input [4:0] BGRCALOVRD;
+ input BGRCALOVRDENB;
+ input [15:0] DRPADDR;
+ input DRPCLK;
+ input [15:0] DRPDI;
+ input DRPEN;
+ input DRPWE;
+ input GTGREFCLK0;
+ input GTGREFCLK1;
+ input GTNORTHREFCLK00;
+ input GTNORTHREFCLK01;
+ input GTNORTHREFCLK10;
+ input GTNORTHREFCLK11;
+ input GTREFCLK00;
+ input GTREFCLK01;
+ input GTREFCLK10;
+ input GTREFCLK11;
+ input GTSOUTHREFCLK00;
+ input GTSOUTHREFCLK01;
+ input GTSOUTHREFCLK10;
+ input GTSOUTHREFCLK11;
+ input [2:0] PCIERATEQPLL0;
+ input [2:0] PCIERATEQPLL1;
+ input [7:0] PMARSVD0;
+ input [7:0] PMARSVD1;
+ input QPLL0CLKRSVD0;
+ input QPLL0CLKRSVD1;
+ input [7:0] QPLL0FBDIV;
+ input QPLL0LOCKDETCLK;
+ input QPLL0LOCKEN;
+ input QPLL0PD;
+ input [2:0] QPLL0REFCLKSEL;
+ input QPLL0RESET;
+ input QPLL1CLKRSVD0;
+ input QPLL1CLKRSVD1;
+ input [7:0] QPLL1FBDIV;
+ input QPLL1LOCKDETCLK;
+ input QPLL1LOCKEN;
+ input QPLL1PD;
+ input [2:0] QPLL1REFCLKSEL;
+ input QPLL1RESET;
+ input [7:0] QPLLRSVD1;
+ input [4:0] QPLLRSVD2;
+ input [4:0] QPLLRSVD3;
+ input [7:0] QPLLRSVD4;
+ input RCALENB;
+ input [24:0] SDM0DATA;
+ input SDM0RESET;
+ input SDM0TOGGLE;
+ input [1:0] SDM0WIDTH;
+ input [24:0] SDM1DATA;
+ input SDM1RESET;
+ input SDM1TOGGLE;
+ input [1:0] SDM1WIDTH;
+ input [9:0] TCONGPI;
+ input TCONPOWERUP;
+ input [1:0] TCONRESET;
+ input [1:0] TCONRSVDIN1;
+endmodule
+
+module GTYE3_CHANNEL (...);
+ parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0;
+ parameter [0:0] ACJTAG_MODE = 1'b0;
+ parameter [0:0] ACJTAG_RESET = 1'b0;
+ parameter [15:0] ADAPT_CFG0 = 16'h9200;
+ parameter [15:0] ADAPT_CFG1 = 16'h801C;
+ parameter [15:0] ADAPT_CFG2 = 16'b0000000000000000;
+ parameter ALIGN_COMMA_DOUBLE = "FALSE";
+ parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111;
+ parameter integer ALIGN_COMMA_WORD = 1;
+ parameter ALIGN_MCOMMA_DET = "TRUE";
+ parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
+ parameter ALIGN_PCOMMA_DET = "TRUE";
+ parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
+ parameter [0:0] AUTO_BW_SEL_BYPASS = 1'b0;
+ parameter [0:0] A_RXOSCALRESET = 1'b0;
+ parameter [0:0] A_RXPROGDIVRESET = 1'b0;
+ parameter [4:0] A_TXDIFFCTRL = 5'b01100;
+ parameter [0:0] A_TXPROGDIVRESET = 1'b0;
+ parameter [0:0] CAPBYPASS_FORCE = 1'b0;
+ parameter CBCC_DATA_SOURCE_SEL = "DECODED";
+ parameter [0:0] CDR_SWAP_MODE_EN = 1'b0;
+ parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
+ parameter integer CHAN_BOND_MAX_SKEW = 7;
+ parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
+ parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000;
+ parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000;
+ parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000;
+ parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
+ parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000;
+ parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000;
+ parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000;
+ parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000;
+ parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
+ parameter CHAN_BOND_SEQ_2_USE = "FALSE";
+ parameter integer CHAN_BOND_SEQ_LEN = 2;
+ parameter [15:0] CH_HSPMUX = 16'h0000;
+ parameter [15:0] CKCAL1_CFG_0 = 16'b0000000000000000;
+ parameter [15:0] CKCAL1_CFG_1 = 16'b0000000000000000;
+ parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000;
+ parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000;
+ parameter [15:0] CKCAL2_CFG_0 = 16'b0000000000000000;
+ parameter [15:0] CKCAL2_CFG_1 = 16'b0000000000000000;
+ parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000;
+ parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000;
+ parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000;
+ parameter [15:0] CKCAL_RSVD0 = 16'h0000;
+ parameter [15:0] CKCAL_RSVD1 = 16'h0000;
+ parameter CLK_CORRECT_USE = "TRUE";
+ parameter CLK_COR_KEEP_IDLE = "FALSE";
+ parameter integer CLK_COR_MAX_LAT = 20;
+ parameter integer CLK_COR_MIN_LAT = 18;
+ parameter CLK_COR_PRECEDENCE = "TRUE";
+ parameter integer CLK_COR_REPEAT_WAIT = 0;
+ parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100;
+ parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000;
+ parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111;
+ parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000;
+ parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000;
+ parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000;
+ parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000;
+ parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
+ parameter CLK_COR_SEQ_2_USE = "FALSE";
+ parameter integer CLK_COR_SEQ_LEN = 2;
+ parameter [15:0] CPLL_CFG0 = 16'h20F8;
+ parameter [15:0] CPLL_CFG1 = 16'hA494;
+ parameter [15:0] CPLL_CFG2 = 16'hF001;
+ parameter [5:0] CPLL_CFG3 = 6'h00;
+ parameter integer CPLL_FBDIV = 4;
+ parameter integer CPLL_FBDIV_45 = 4;
+ parameter [15:0] CPLL_INIT_CFG0 = 16'h001E;
+ parameter [7:0] CPLL_INIT_CFG1 = 8'h00;
+ parameter [15:0] CPLL_LOCK_CFG = 16'h01E8;
+ parameter integer CPLL_REFCLK_DIV = 1;
+ parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000;
+ parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0;
+ parameter [1:0] DDI_CTRL = 2'b00;
+ parameter integer DDI_REALIGN_WAIT = 15;
+ parameter DEC_MCOMMA_DETECT = "TRUE";
+ parameter DEC_PCOMMA_DETECT = "TRUE";
+ parameter DEC_VALID_COMMA_ONLY = "TRUE";
+ parameter [0:0] DFE_D_X_REL_POS = 1'b0;
+ parameter [0:0] DFE_VCM_COMP_EN = 1'b0;
+ parameter [9:0] DMONITOR_CFG0 = 10'h000;
+ parameter [7:0] DMONITOR_CFG1 = 8'h00;
+ parameter [0:0] ES_CLK_PHASE_SEL = 1'b0;
+ parameter [5:0] ES_CONTROL = 6'b000000;
+ parameter ES_ERRDET_EN = "FALSE";
+ parameter ES_EYE_SCAN_EN = "FALSE";
+ parameter [11:0] ES_HORZ_OFFSET = 12'h000;
+ parameter [9:0] ES_PMA_CFG = 10'b0000000000;
+ parameter [4:0] ES_PRESCALE = 5'b00000;
+ parameter [15:0] ES_QUALIFIER0 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER1 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER2 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER3 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER4 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER5 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER6 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER7 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER8 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER9 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK0 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK1 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK2 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK3 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK4 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK5 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK6 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK7 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK8 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK9 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK0 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK1 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK2 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK3 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK4 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK5 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK6 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK7 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK8 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK9 = 16'h0000;
+ parameter [10:0] EVODD_PHI_CFG = 11'b00000000000;
+ parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0;
+ parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111;
+ parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111;
+ parameter FTS_LANE_DESKEW_EN = "FALSE";
+ parameter [4:0] GEARBOX_MODE = 5'b00000;
+ parameter [0:0] GM_BIAS_SELECT = 1'b0;
+ parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0;
+ parameter [0:0] LOCAL_MASTER = 1'b0;
+ parameter [15:0] LOOP0_CFG = 16'h0000;
+ parameter [15:0] LOOP10_CFG = 16'h0000;
+ parameter [15:0] LOOP11_CFG = 16'h0000;
+ parameter [15:0] LOOP12_CFG = 16'h0000;
+ parameter [15:0] LOOP13_CFG = 16'h0000;
+ parameter [15:0] LOOP1_CFG = 16'h0000;
+ parameter [15:0] LOOP2_CFG = 16'h0000;
+ parameter [15:0] LOOP3_CFG = 16'h0000;
+ parameter [15:0] LOOP4_CFG = 16'h0000;
+ parameter [15:0] LOOP5_CFG = 16'h0000;
+ parameter [15:0] LOOP6_CFG = 16'h0000;
+ parameter [15:0] LOOP7_CFG = 16'h0000;
+ parameter [15:0] LOOP8_CFG = 16'h0000;
+ parameter [15:0] LOOP9_CFG = 16'h0000;
+ parameter [2:0] LPBK_BIAS_CTRL = 3'b000;
+ parameter [0:0] LPBK_EN_RCAL_B = 1'b0;
+ parameter [3:0] LPBK_EXT_RCAL = 4'b0000;
+ parameter [3:0] LPBK_RG_CTRL = 4'b0000;
+ parameter [1:0] OOBDIVCTL = 2'b00;
+ parameter [0:0] OOB_PWRUP = 1'b0;
+ parameter PCI3_AUTO_REALIGN = "FRST_SMPL";
+ parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1;
+ parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00;
+ parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0;
+ parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000;
+ parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000;
+ parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000;
+ parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0;
+ parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0;
+ parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000;
+ parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000;
+ parameter [15:0] PCIE_RXPMA_CFG = 16'h0000;
+ parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000;
+ parameter [15:0] PCIE_TXPMA_CFG = 16'h0000;
+ parameter PCS_PCIE_EN = "FALSE";
+ parameter [15:0] PCS_RSVD0 = 16'b0000000000000000;
+ parameter [2:0] PCS_RSVD1 = 3'b000;
+ parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C;
+ parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19;
+ parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64;
+ parameter [1:0] PLL_SEL_MODE_GEN12 = 2'h0;
+ parameter [1:0] PLL_SEL_MODE_GEN3 = 2'h0;
+ parameter [15:0] PMA_RSV0 = 16'h0000;
+ parameter [15:0] PMA_RSV1 = 16'h0000;
+ parameter integer PREIQ_FREQ_BST = 0;
+ parameter [2:0] PROCESS_PAR = 3'b010;
+ parameter [0:0] RATE_SW_USE_DRP = 1'b0;
+ parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0;
+ parameter [4:0] RXBUFRESET_TIME = 5'b00001;
+ parameter RXBUF_ADDR_MODE = "FULL";
+ parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000;
+ parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000;
+ parameter RXBUF_EN = "TRUE";
+ parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
+ parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
+ parameter RXBUF_RESET_ON_EIDLE = "FALSE";
+ parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
+ parameter integer RXBUF_THRESH_OVFLW = 0;
+ parameter RXBUF_THRESH_OVRD = "FALSE";
+ parameter integer RXBUF_THRESH_UNDFLW = 4;
+ parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001;
+ parameter [4:0] RXCDRPHRESET_TIME = 5'b00001;
+ parameter [15:0] RXCDR_CFG0 = 16'h0000;
+ parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0000;
+ parameter [15:0] RXCDR_CFG1 = 16'h0300;
+ parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0300;
+ parameter [15:0] RXCDR_CFG2 = 16'h0060;
+ parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0060;
+ parameter [15:0] RXCDR_CFG3 = 16'h0000;
+ parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0000;
+ parameter [15:0] RXCDR_CFG4 = 16'h0002;
+ parameter [15:0] RXCDR_CFG4_GEN3 = 16'h0002;
+ parameter [15:0] RXCDR_CFG5 = 16'h0000;
+ parameter [15:0] RXCDR_CFG5_GEN3 = 16'h0000;
+ parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0;
+ parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0;
+ parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0001;
+ parameter [15:0] RXCDR_LOCK_CFG1 = 16'h0000;
+ parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000;
+ parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000;
+ parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0;
+ parameter [1:0] RXCFOKDONE_SRC = 2'b00;
+ parameter [15:0] RXCFOK_CFG0 = 16'h3E00;
+ parameter [15:0] RXCFOK_CFG1 = 16'h0042;
+ parameter [15:0] RXCFOK_CFG2 = 16'h002D;
+ parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111;
+ parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000;
+ parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022;
+ parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100;
+ parameter [15:0] RXDFE_CFG0 = 16'h4C00;
+ parameter [15:0] RXDFE_CFG1 = 16'h0000;
+ parameter [15:0] RXDFE_GC_CFG0 = 16'h1E00;
+ parameter [15:0] RXDFE_GC_CFG1 = 16'h1900;
+ parameter [15:0] RXDFE_GC_CFG2 = 16'h0000;
+ parameter [15:0] RXDFE_H2_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H2_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_H3_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H3_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_H4_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H4_CFG1 = 16'h0003;
+ parameter [15:0] RXDFE_H5_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H5_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_H6_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H6_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_H7_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H7_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_H8_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H8_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_H9_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H9_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_HA_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_HA_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_HB_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_HB_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_HC_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_HC_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_HD_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_HD_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_HE_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_HE_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_HF_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_HF_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_OS_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_OS_CFG1 = 16'h0200;
+ parameter [0:0] RXDFE_PWR_SAVING = 1'b0;
+ parameter [15:0] RXDFE_UT_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_UT_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_VP_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_VP_CFG1 = 16'h0022;
+ parameter [15:0] RXDLY_CFG = 16'h001F;
+ parameter [15:0] RXDLY_LCFG = 16'h0030;
+ parameter RXELECIDLE_CFG = "SIGCFG_4";
+ parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4;
+ parameter RXGEARBOX_EN = "FALSE";
+ parameter [4:0] RXISCANRESET_TIME = 5'b00001;
+ parameter [15:0] RXLPM_CFG = 16'h0000;
+ parameter [15:0] RXLPM_GC_CFG = 16'h0200;
+ parameter [15:0] RXLPM_KH_CFG0 = 16'h0000;
+ parameter [15:0] RXLPM_KH_CFG1 = 16'h0002;
+ parameter [15:0] RXLPM_OS_CFG0 = 16'h0400;
+ parameter [15:0] RXLPM_OS_CFG1 = 16'h0000;
+ parameter [8:0] RXOOB_CFG = 9'b000000110;
+ parameter RXOOB_CLK_CFG = "PMA";
+ parameter [4:0] RXOSCALRESET_TIME = 5'b00011;
+ parameter integer RXOUT_DIV = 4;
+ parameter [4:0] RXPCSRESET_TIME = 5'b00001;
+ parameter [15:0] RXPHBEACON_CFG = 16'h0000;
+ parameter [15:0] RXPHDLY_CFG = 16'h2020;
+ parameter [15:0] RXPHSAMP_CFG = 16'h2100;
+ parameter [15:0] RXPHSLIP_CFG = 16'h9933;
+ parameter [4:0] RXPH_MONITOR_SEL = 5'b00000;
+ parameter [0:0] RXPI_AUTO_BW_SEL_BYPASS = 1'b0;
+ parameter [15:0] RXPI_CFG = 16'h0100;
+ parameter [0:0] RXPI_LPM = 1'b0;
+ parameter [15:0] RXPI_RSV0 = 16'h0000;
+ parameter [1:0] RXPI_SEL_LC = 2'b00;
+ parameter [1:0] RXPI_STARTCODE = 2'b00;
+ parameter [0:0] RXPI_VREFSEL = 1'b0;
+ parameter RXPMACLK_SEL = "DATA";
+ parameter [4:0] RXPMARESET_TIME = 5'b00001;
+ parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0;
+ parameter integer RXPRBS_LINKACQ_CNT = 15;
+ parameter integer RXSLIDE_AUTO_WAIT = 7;
+ parameter RXSLIDE_MODE = "OFF";
+ parameter [0:0] RXSYNC_MULTILANE = 1'b0;
+ parameter [0:0] RXSYNC_OVRD = 1'b0;
+ parameter [0:0] RXSYNC_SKIP_DA = 1'b0;
+ parameter [0:0] RX_AFE_CM_EN = 1'b0;
+ parameter [15:0] RX_BIAS_CFG0 = 16'h1534;
+ parameter [5:0] RX_BUFFER_CFG = 6'b000000;
+ parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0;
+ parameter integer RX_CLK25_DIV = 8;
+ parameter [0:0] RX_CLKMUX_EN = 1'b1;
+ parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000;
+ parameter [3:0] RX_CM_BUF_CFG = 4'b1010;
+ parameter [0:0] RX_CM_BUF_PD = 1'b0;
+ parameter integer RX_CM_SEL = 3;
+ parameter integer RX_CM_TRIM = 10;
+ parameter [0:0] RX_CTLE1_KHKL = 1'b0;
+ parameter [0:0] RX_CTLE2_KHKL = 1'b0;
+ parameter [0:0] RX_CTLE3_AGC = 1'b0;
+ parameter integer RX_DATA_WIDTH = 20;
+ parameter [5:0] RX_DDI_SEL = 6'b000000;
+ parameter RX_DEFER_RESET_BUF_EN = "TRUE";
+ parameter [2:0] RX_DEGEN_CTRL = 3'b010;
+ parameter integer RX_DFELPM_CFG0 = 6;
+ parameter [0:0] RX_DFELPM_CFG1 = 1'b0;
+ parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1;
+ parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00;
+ parameter integer RX_DFE_AGC_CFG1 = 4;
+ parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1;
+ parameter integer RX_DFE_KL_LPM_KH_CFG1 = 2;
+ parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01;
+ parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010;
+ parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0;
+ parameter RX_DISPERR_SEQ_MATCH = "TRUE";
+ parameter [0:0] RX_DIV2_MODE_B = 1'b0;
+ parameter [4:0] RX_DIVRESET_TIME = 5'b00001;
+ parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0;
+ parameter [0:0] RX_EN_HI_LR = 1'b0;
+ parameter [8:0] RX_EXT_RL_CTRL = 9'b000000000;
+ parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000;
+ parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0;
+ parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00;
+ parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0;
+ parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0;
+ parameter integer RX_INT_DATAWIDTH = 1;
+ parameter [0:0] RX_PMA_POWER_SAVE = 1'b0;
+ parameter real RX_PROGDIV_CFG = 0.0;
+ parameter [15:0] RX_PROGDIV_RATE = 16'h0001;
+ parameter [3:0] RX_RESLOAD_CTRL = 4'b0000;
+ parameter [0:0] RX_RESLOAD_OVRD = 1'b0;
+ parameter [2:0] RX_SAMPLE_PERIOD = 3'b101;
+ parameter integer RX_SIG_VALID_DLY = 11;
+ parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0;
+ parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000;
+ parameter [3:0] RX_SUM_VCMTUNE = 4'b1000;
+ parameter [0:0] RX_SUM_VCM_OVWR = 1'b0;
+ parameter [2:0] RX_SUM_VREF_TUNE = 3'b100;
+ parameter [1:0] RX_TUNE_AFE_OS = 2'b00;
+ parameter [2:0] RX_VREG_CTRL = 3'b101;
+ parameter [0:0] RX_VREG_PDB = 1'b1;
+ parameter [1:0] RX_WIDEMODE_CDR = 2'b01;
+ parameter RX_XCLK_SEL = "RXDES";
+ parameter [0:0] RX_XMODE_SEL = 1'b0;
+ parameter integer SAS_MAX_COM = 64;
+ parameter integer SAS_MIN_COM = 36;
+ parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
+ parameter [2:0] SATA_BURST_VAL = 3'b100;
+ parameter SATA_CPLL_CFG = "VCO_3000MHZ";
+ parameter [2:0] SATA_EIDLE_VAL = 3'b100;
+ parameter integer SATA_MAX_BURST = 8;
+ parameter integer SATA_MAX_INIT = 21;
+ parameter integer SATA_MAX_WAKE = 7;
+ parameter integer SATA_MIN_BURST = 4;
+ parameter integer SATA_MIN_INIT = 12;
+ parameter integer SATA_MIN_WAKE = 4;
+ parameter SHOW_REALIGN_COMMA = "TRUE";
+ parameter SIM_MODE = "FAST";
+ parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
+ parameter SIM_RESET_SPEEDUP = "TRUE";
+ parameter [0:0] SIM_TX_EIDLE_DRIVE_LEVEL = 1'b0;
+ parameter integer SIM_VERSION = 2;
+ parameter [1:0] TAPDLY_SET_TX = 2'h0;
+ parameter [3:0] TEMPERATURE_PAR = 4'b0010;
+ parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000;
+ parameter [2:0] TERM_RCAL_OVRD = 3'b000;
+ parameter [7:0] TRANS_TIME_RATE = 8'h0E;
+ parameter [7:0] TST_RSV0 = 8'h00;
+ parameter [7:0] TST_RSV1 = 8'h00;
+ parameter TXBUF_EN = "TRUE";
+ parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE";
+ parameter [15:0] TXDLY_CFG = 16'h001F;
+ parameter [15:0] TXDLY_LCFG = 16'h0030;
+ parameter TXFIFO_ADDR_CFG = "LOW";
+ parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4;
+ parameter TXGEARBOX_EN = "FALSE";
+ parameter integer TXOUT_DIV = 4;
+ parameter [4:0] TXPCSRESET_TIME = 5'b00001;
+ parameter [15:0] TXPHDLY_CFG0 = 16'h2020;
+ parameter [15:0] TXPHDLY_CFG1 = 16'h0001;
+ parameter [15:0] TXPH_CFG = 16'h0123;
+ parameter [15:0] TXPH_CFG2 = 16'h0000;
+ parameter [4:0] TXPH_MONITOR_SEL = 5'b00000;
+ parameter [1:0] TXPI_CFG0 = 2'b00;
+ parameter [1:0] TXPI_CFG1 = 2'b00;
+ parameter [1:0] TXPI_CFG2 = 2'b00;
+ parameter [0:0] TXPI_CFG3 = 1'b0;
+ parameter [0:0] TXPI_CFG4 = 1'b1;
+ parameter [2:0] TXPI_CFG5 = 3'b000;
+ parameter [0:0] TXPI_GRAY_SEL = 1'b0;
+ parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0;
+ parameter [0:0] TXPI_LPM = 1'b0;
+ parameter TXPI_PPMCLK_SEL = "TXUSRCLK2";
+ parameter [7:0] TXPI_PPM_CFG = 8'b00000000;
+ parameter [15:0] TXPI_RSV0 = 16'h0000;
+ parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000;
+ parameter [0:0] TXPI_VREFSEL = 1'b0;
+ parameter [4:0] TXPMARESET_TIME = 5'b00001;
+ parameter [0:0] TXSYNC_MULTILANE = 1'b0;
+ parameter [0:0] TXSYNC_OVRD = 1'b0;
+ parameter [0:0] TXSYNC_SKIP_DA = 1'b0;
+ parameter integer TX_CLK25_DIV = 8;
+ parameter [0:0] TX_CLKMUX_EN = 1'b1;
+ parameter [0:0] TX_CLKREG_PDB = 1'b0;
+ parameter [2:0] TX_CLKREG_SET = 3'b000;
+ parameter integer TX_DATA_WIDTH = 20;
+ parameter [5:0] TX_DCD_CFG = 6'b000010;
+ parameter [0:0] TX_DCD_EN = 1'b0;
+ parameter [5:0] TX_DEEMPH0 = 6'b000000;
+ parameter [5:0] TX_DEEMPH1 = 6'b000000;
+ parameter [4:0] TX_DIVRESET_TIME = 5'b00001;
+ parameter TX_DRIVE_MODE = "DIRECT";
+ parameter integer TX_DRVMUX_CTRL = 2;
+ parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110;
+ parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100;
+ parameter [0:0] TX_EML_PHI_TUNE = 1'b0;
+ parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0;
+ parameter [0:0] TX_FIFO_BYP_EN = 1'b0;
+ parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0;
+ parameter integer TX_INT_DATAWIDTH = 1;
+ parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
+ parameter [0:0] TX_MAINCURSOR_SEL = 1'b0;
+ parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110;
+ parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001;
+ parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101;
+ parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010;
+ parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000;
+ parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110;
+ parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100;
+ parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
+ parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
+ parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
+ parameter [2:0] TX_MODE_SEL = 3'b000;
+ parameter [15:0] TX_PHICAL_CFG0 = 16'h0000;
+ parameter [15:0] TX_PHICAL_CFG1 = 16'h7E00;
+ parameter [15:0] TX_PHICAL_CFG2 = 16'h0000;
+ parameter integer TX_PI_BIASSET = 0;
+ parameter [15:0] TX_PI_CFG0 = 16'h0000;
+ parameter [15:0] TX_PI_CFG1 = 16'h0000;
+ parameter [0:0] TX_PI_DIV2_MODE_B = 1'b0;
+ parameter [0:0] TX_PI_SEL_QPLL0 = 1'b0;
+ parameter [0:0] TX_PI_SEL_QPLL1 = 1'b0;
+ parameter [0:0] TX_PMADATA_OPT = 1'b0;
+ parameter [0:0] TX_PMA_POWER_SAVE = 1'b0;
+ parameter integer TX_PREDRV_CTRL = 2;
+ parameter TX_PROGCLK_SEL = "POSTPI";
+ parameter real TX_PROGDIV_CFG = 0.0;
+ parameter [15:0] TX_PROGDIV_RATE = 16'h0001;
+ parameter [13:0] TX_RXDETECT_CFG = 14'h0032;
+ parameter integer TX_RXDETECT_REF = 4;
+ parameter [2:0] TX_SAMPLE_PERIOD = 3'b101;
+ parameter [0:0] TX_SARC_LPBK_ENB = 1'b0;
+ parameter TX_XCLK_SEL = "TXOUT";
+ parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0;
+ output [2:0] BUFGTCE;
+ output [2:0] BUFGTCEMASK;
+ output [8:0] BUFGTDIV;
+ output [2:0] BUFGTRESET;
+ output [2:0] BUFGTRSTMASK;
+ output CPLLFBCLKLOST;
+ output CPLLLOCK;
+ output CPLLREFCLKLOST;
+ output [16:0] DMONITOROUT;
+ output [15:0] DRPDO;
+ output DRPRDY;
+ output EYESCANDATAERROR;
+ output GTPOWERGOOD;
+ output GTREFCLKMONITOR;
+ output GTYTXN;
+ output GTYTXP;
+ output PCIERATEGEN3;
+ output PCIERATEIDLE;
+ output [1:0] PCIERATEQPLLPD;
+ output [1:0] PCIERATEQPLLRESET;
+ output PCIESYNCTXSYNCDONE;
+ output PCIEUSERGEN3RDY;
+ output PCIEUSERPHYSTATUSRST;
+ output PCIEUSERRATESTART;
+ output [15:0] PCSRSVDOUT;
+ output PHYSTATUS;
+ output [7:0] PINRSRVDAS;
+ output RESETEXCEPTION;
+ output [2:0] RXBUFSTATUS;
+ output RXBYTEISALIGNED;
+ output RXBYTEREALIGN;
+ output RXCDRLOCK;
+ output RXCDRPHDONE;
+ output RXCHANBONDSEQ;
+ output RXCHANISALIGNED;
+ output RXCHANREALIGN;
+ output [4:0] RXCHBONDO;
+ output RXCKCALDONE;
+ output [1:0] RXCLKCORCNT;
+ output RXCOMINITDET;
+ output RXCOMMADET;
+ output RXCOMSASDET;
+ output RXCOMWAKEDET;
+ output [15:0] RXCTRL0;
+ output [15:0] RXCTRL1;
+ output [7:0] RXCTRL2;
+ output [7:0] RXCTRL3;
+ output [127:0] RXDATA;
+ output [7:0] RXDATAEXTENDRSVD;
+ output [1:0] RXDATAVALID;
+ output RXDLYSRESETDONE;
+ output RXELECIDLE;
+ output [5:0] RXHEADER;
+ output [1:0] RXHEADERVALID;
+ output [6:0] RXMONITOROUT;
+ output RXOSINTDONE;
+ output RXOSINTSTARTED;
+ output RXOSINTSTROBEDONE;
+ output RXOSINTSTROBESTARTED;
+ output RXOUTCLK;
+ output RXOUTCLKFABRIC;
+ output RXOUTCLKPCS;
+ output RXPHALIGNDONE;
+ output RXPHALIGNERR;
+ output RXPMARESETDONE;
+ output RXPRBSERR;
+ output RXPRBSLOCKED;
+ output RXPRGDIVRESETDONE;
+ output RXRATEDONE;
+ output RXRECCLKOUT;
+ output RXRESETDONE;
+ output RXSLIDERDY;
+ output RXSLIPDONE;
+ output RXSLIPOUTCLKRDY;
+ output RXSLIPPMARDY;
+ output [1:0] RXSTARTOFSEQ;
+ output [2:0] RXSTATUS;
+ output RXSYNCDONE;
+ output RXSYNCOUT;
+ output RXVALID;
+ output [1:0] TXBUFSTATUS;
+ output TXCOMFINISH;
+ output TXDCCDONE;
+ output TXDLYSRESETDONE;
+ output TXOUTCLK;
+ output TXOUTCLKFABRIC;
+ output TXOUTCLKPCS;
+ output TXPHALIGNDONE;
+ output TXPHINITDONE;
+ output TXPMARESETDONE;
+ output TXPRGDIVRESETDONE;
+ output TXRATEDONE;
+ output TXRESETDONE;
+ output TXSYNCDONE;
+ output TXSYNCOUT;
+ input CDRSTEPDIR;
+ input CDRSTEPSQ;
+ input CDRSTEPSX;
+ input CFGRESET;
+ input CLKRSVD0;
+ input CLKRSVD1;
+ input CPLLLOCKDETCLK;
+ input CPLLLOCKEN;
+ input CPLLPD;
+ input [2:0] CPLLREFCLKSEL;
+ input CPLLRESET;
+ input DMONFIFORESET;
+ input DMONITORCLK;
+ input [9:0] DRPADDR;
+ input DRPCLK;
+ input [15:0] DRPDI;
+ input DRPEN;
+ input DRPWE;
+ input ELPCALDVORWREN;
+ input ELPCALPAORWREN;
+ input EVODDPHICALDONE;
+ input EVODDPHICALSTART;
+ input EVODDPHIDRDEN;
+ input EVODDPHIDWREN;
+ input EVODDPHIXRDEN;
+ input EVODDPHIXWREN;
+ input EYESCANMODE;
+ input EYESCANRESET;
+ input EYESCANTRIGGER;
+ input GTGREFCLK;
+ input GTNORTHREFCLK0;
+ input GTNORTHREFCLK1;
+ input GTREFCLK0;
+ input GTREFCLK1;
+ input GTRESETSEL;
+ input [15:0] GTRSVD;
+ input GTRXRESET;
+ input GTSOUTHREFCLK0;
+ input GTSOUTHREFCLK1;
+ input GTTXRESET;
+ input GTYRXN;
+ input GTYRXP;
+ input [2:0] LOOPBACK;
+ input [15:0] LOOPRSVD;
+ input LPBKRXTXSEREN;
+ input LPBKTXRXSEREN;
+ input PCIEEQRXEQADAPTDONE;
+ input PCIERSTIDLE;
+ input PCIERSTTXSYNCSTART;
+ input PCIEUSERRATEDONE;
+ input [15:0] PCSRSVDIN;
+ input [4:0] PCSRSVDIN2;
+ input [4:0] PMARSVDIN;
+ input QPLL0CLK;
+ input QPLL0REFCLK;
+ input QPLL1CLK;
+ input QPLL1REFCLK;
+ input RESETOVRD;
+ input RSTCLKENTX;
+ input RX8B10BEN;
+ input RXBUFRESET;
+ input RXCDRFREQRESET;
+ input RXCDRHOLD;
+ input RXCDROVRDEN;
+ input RXCDRRESET;
+ input RXCDRRESETRSV;
+ input RXCHBONDEN;
+ input [4:0] RXCHBONDI;
+ input [2:0] RXCHBONDLEVEL;
+ input RXCHBONDMASTER;
+ input RXCHBONDSLAVE;
+ input RXCKCALRESET;
+ input RXCOMMADETEN;
+ input RXDCCFORCESTART;
+ input RXDFEAGCHOLD;
+ input RXDFEAGCOVRDEN;
+ input RXDFELFHOLD;
+ input RXDFELFOVRDEN;
+ input RXDFELPMRESET;
+ input RXDFETAP10HOLD;
+ input RXDFETAP10OVRDEN;
+ input RXDFETAP11HOLD;
+ input RXDFETAP11OVRDEN;
+ input RXDFETAP12HOLD;
+ input RXDFETAP12OVRDEN;
+ input RXDFETAP13HOLD;
+ input RXDFETAP13OVRDEN;
+ input RXDFETAP14HOLD;
+ input RXDFETAP14OVRDEN;
+ input RXDFETAP15HOLD;
+ input RXDFETAP15OVRDEN;
+ input RXDFETAP2HOLD;
+ input RXDFETAP2OVRDEN;
+ input RXDFETAP3HOLD;
+ input RXDFETAP3OVRDEN;
+ input RXDFETAP4HOLD;
+ input RXDFETAP4OVRDEN;
+ input RXDFETAP5HOLD;
+ input RXDFETAP5OVRDEN;
+ input RXDFETAP6HOLD;
+ input RXDFETAP6OVRDEN;
+ input RXDFETAP7HOLD;
+ input RXDFETAP7OVRDEN;
+ input RXDFETAP8HOLD;
+ input RXDFETAP8OVRDEN;
+ input RXDFETAP9HOLD;
+ input RXDFETAP9OVRDEN;
+ input RXDFEUTHOLD;
+ input RXDFEUTOVRDEN;
+ input RXDFEVPHOLD;
+ input RXDFEVPOVRDEN;
+ input RXDFEVSEN;
+ input RXDFEXYDEN;
+ input RXDLYBYPASS;
+ input RXDLYEN;
+ input RXDLYOVRDEN;
+ input RXDLYSRESET;
+ input [1:0] RXELECIDLEMODE;
+ input RXGEARBOXSLIP;
+ input RXLATCLK;
+ input RXLPMEN;
+ input RXLPMGCHOLD;
+ input RXLPMGCOVRDEN;
+ input RXLPMHFHOLD;
+ input RXLPMHFOVRDEN;
+ input RXLPMLFHOLD;
+ input RXLPMLFKLOVRDEN;
+ input RXLPMOSHOLD;
+ input RXLPMOSOVRDEN;
+ input RXMCOMMAALIGNEN;
+ input [1:0] RXMONITORSEL;
+ input RXOOBRESET;
+ input RXOSCALRESET;
+ input RXOSHOLD;
+ input [3:0] RXOSINTCFG;
+ input RXOSINTEN;
+ input RXOSINTHOLD;
+ input RXOSINTOVRDEN;
+ input RXOSINTSTROBE;
+ input RXOSINTTESTOVRDEN;
+ input RXOSOVRDEN;
+ input [2:0] RXOUTCLKSEL;
+ input RXPCOMMAALIGNEN;
+ input RXPCSRESET;
+ input [1:0] RXPD;
+ input RXPHALIGN;
+ input RXPHALIGNEN;
+ input RXPHDLYPD;
+ input RXPHDLYRESET;
+ input RXPHOVRDEN;
+ input [1:0] RXPLLCLKSEL;
+ input RXPMARESET;
+ input RXPOLARITY;
+ input RXPRBSCNTRESET;
+ input [3:0] RXPRBSSEL;
+ input RXPROGDIVRESET;
+ input [2:0] RXRATE;
+ input RXRATEMODE;
+ input RXSLIDE;
+ input RXSLIPOUTCLK;
+ input RXSLIPPMA;
+ input RXSYNCALLIN;
+ input RXSYNCIN;
+ input RXSYNCMODE;
+ input [1:0] RXSYSCLKSEL;
+ input RXUSERRDY;
+ input RXUSRCLK;
+ input RXUSRCLK2;
+ input SIGVALIDCLK;
+ input [19:0] TSTIN;
+ input [7:0] TX8B10BBYPASS;
+ input TX8B10BEN;
+ input [2:0] TXBUFDIFFCTRL;
+ input TXCOMINIT;
+ input TXCOMSAS;
+ input TXCOMWAKE;
+ input [15:0] TXCTRL0;
+ input [15:0] TXCTRL1;
+ input [7:0] TXCTRL2;
+ input [127:0] TXDATA;
+ input [7:0] TXDATAEXTENDRSVD;
+ input TXDCCFORCESTART;
+ input TXDCCRESET;
+ input TXDEEMPH;
+ input TXDETECTRX;
+ input [4:0] TXDIFFCTRL;
+ input TXDIFFPD;
+ input TXDLYBYPASS;
+ input TXDLYEN;
+ input TXDLYHOLD;
+ input TXDLYOVRDEN;
+ input TXDLYSRESET;
+ input TXDLYUPDOWN;
+ input TXELECIDLE;
+ input TXELFORCESTART;
+ input [5:0] TXHEADER;
+ input TXINHIBIT;
+ input TXLATCLK;
+ input [6:0] TXMAINCURSOR;
+ input [2:0] TXMARGIN;
+ input [2:0] TXOUTCLKSEL;
+ input TXPCSRESET;
+ input [1:0] TXPD;
+ input TXPDELECIDLEMODE;
+ input TXPHALIGN;
+ input TXPHALIGNEN;
+ input TXPHDLYPD;
+ input TXPHDLYRESET;
+ input TXPHDLYTSTCLK;
+ input TXPHINIT;
+ input TXPHOVRDEN;
+ input TXPIPPMEN;
+ input TXPIPPMOVRDEN;
+ input TXPIPPMPD;
+ input TXPIPPMSEL;
+ input [4:0] TXPIPPMSTEPSIZE;
+ input TXPISOPD;
+ input [1:0] TXPLLCLKSEL;
+ input TXPMARESET;
+ input TXPOLARITY;
+ input [4:0] TXPOSTCURSOR;
+ input TXPRBSFORCEERR;
+ input [3:0] TXPRBSSEL;
+ input [4:0] TXPRECURSOR;
+ input TXPROGDIVRESET;
+ input [2:0] TXRATE;
+ input TXRATEMODE;
+ input [6:0] TXSEQUENCE;
+ input TXSWING;
+ input TXSYNCALLIN;
+ input TXSYNCIN;
+ input TXSYNCMODE;
+ input [1:0] TXSYSCLKSEL;
+ input TXUSERRDY;
+ input TXUSRCLK;
+ input TXUSRCLK2;
+endmodule
+
+module GTYE3_COMMON (...);
+ parameter [15:0] A_SDM1DATA1_0 = 16'b0000000000000000;
+ parameter [8:0] A_SDM1DATA1_1 = 9'b000000000;
+ parameter [15:0] BIAS_CFG0 = 16'h0000;
+ parameter [15:0] BIAS_CFG1 = 16'h0000;
+ parameter [15:0] BIAS_CFG2 = 16'h0000;
+ parameter [15:0] BIAS_CFG3 = 16'h0000;
+ parameter [15:0] BIAS_CFG4 = 16'h0000;
+ parameter [9:0] BIAS_CFG_RSVD = 10'b0000000000;
+ parameter [15:0] COMMON_CFG0 = 16'h0000;
+ parameter [15:0] COMMON_CFG1 = 16'h0000;
+ parameter [15:0] POR_CFG = 16'h0004;
+ parameter [15:0] PPF0_CFG = 16'h0FFF;
+ parameter [15:0] PPF1_CFG = 16'h0FFF;
+ parameter QPLL0CLKOUT_RATE = "FULL";
+ parameter [15:0] QPLL0_CFG0 = 16'h301C;
+ parameter [15:0] QPLL0_CFG1 = 16'h0000;
+ parameter [15:0] QPLL0_CFG1_G3 = 16'h0020;
+ parameter [15:0] QPLL0_CFG2 = 16'h0780;
+ parameter [15:0] QPLL0_CFG2_G3 = 16'h0780;
+ parameter [15:0] QPLL0_CFG3 = 16'h0120;
+ parameter [15:0] QPLL0_CFG4 = 16'h0021;
+ parameter [9:0] QPLL0_CP = 10'b0000011111;
+ parameter [9:0] QPLL0_CP_G3 = 10'b0000011111;
+ parameter integer QPLL0_FBDIV = 66;
+ parameter integer QPLL0_FBDIV_G3 = 80;
+ parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000;
+ parameter [7:0] QPLL0_INIT_CFG1 = 8'h00;
+ parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8;
+ parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8;
+ parameter [9:0] QPLL0_LPF = 10'b1111111111;
+ parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111;
+ parameter integer QPLL0_REFCLK_DIV = 2;
+ parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040;
+ parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000;
+ parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000;
+ parameter QPLL1CLKOUT_RATE = "FULL";
+ parameter [15:0] QPLL1_CFG0 = 16'h301C;
+ parameter [15:0] QPLL1_CFG1 = 16'h0000;
+ parameter [15:0] QPLL1_CFG1_G3 = 16'h0020;
+ parameter [15:0] QPLL1_CFG2 = 16'h0780;
+ parameter [15:0] QPLL1_CFG2_G3 = 16'h0780;
+ parameter [15:0] QPLL1_CFG3 = 16'h0120;
+ parameter [15:0] QPLL1_CFG4 = 16'h0021;
+ parameter [9:0] QPLL1_CP = 10'b0000011111;
+ parameter [9:0] QPLL1_CP_G3 = 10'b0000011111;
+ parameter integer QPLL1_FBDIV = 66;
+ parameter integer QPLL1_FBDIV_G3 = 80;
+ parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000;
+ parameter [7:0] QPLL1_INIT_CFG1 = 8'h00;
+ parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8;
+ parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8;
+ parameter [9:0] QPLL1_LPF = 10'b1111111111;
+ parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111;
+ parameter integer QPLL1_REFCLK_DIV = 2;
+ parameter [15:0] QPLL1_SDM_CFG0 = 16'h0040;
+ parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000;
+ parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000;
+ parameter [15:0] RSVD_ATTR0 = 16'h0000;
+ parameter [15:0] RSVD_ATTR1 = 16'h0000;
+ parameter [15:0] RSVD_ATTR2 = 16'h0000;
+ parameter [15:0] RSVD_ATTR3 = 16'h0000;
+ parameter [1:0] RXRECCLKOUT0_SEL = 2'b00;
+ parameter [1:0] RXRECCLKOUT1_SEL = 2'b00;
+ parameter [0:0] SARC_EN = 1'b1;
+ parameter [0:0] SARC_SEL = 1'b0;
+ parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000;
+ parameter [8:0] SDM0INITSEED0_1 = 9'b000000000;
+ parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000;
+ parameter [8:0] SDM1INITSEED0_1 = 9'b000000000;
+ parameter SIM_MODE = "FAST";
+ parameter SIM_RESET_SPEEDUP = "TRUE";
+ parameter integer SIM_VERSION = 2;
+ output [15:0] DRPDO;
+ output DRPRDY;
+ output [7:0] PMARSVDOUT0;
+ output [7:0] PMARSVDOUT1;
+ output QPLL0FBCLKLOST;
+ output QPLL0LOCK;
+ output QPLL0OUTCLK;
+ output QPLL0OUTREFCLK;
+ output QPLL0REFCLKLOST;
+ output QPLL1FBCLKLOST;
+ output QPLL1LOCK;
+ output QPLL1OUTCLK;
+ output QPLL1OUTREFCLK;
+ output QPLL1REFCLKLOST;
+ output [7:0] QPLLDMONITOR0;
+ output [7:0] QPLLDMONITOR1;
+ output REFCLKOUTMONITOR0;
+ output REFCLKOUTMONITOR1;
+ output [1:0] RXRECCLK0_SEL;
+ output [1:0] RXRECCLK1_SEL;
+ output [3:0] SDM0FINALOUT;
+ output [14:0] SDM0TESTDATA;
+ output [3:0] SDM1FINALOUT;
+ output [14:0] SDM1TESTDATA;
+ input BGBYPASSB;
+ input BGMONITORENB;
+ input BGPDB;
+ input [4:0] BGRCALOVRD;
+ input BGRCALOVRDENB;
+ input [9:0] DRPADDR;
+ input DRPCLK;
+ input [15:0] DRPDI;
+ input DRPEN;
+ input DRPWE;
+ input GTGREFCLK0;
+ input GTGREFCLK1;
+ input GTNORTHREFCLK00;
+ input GTNORTHREFCLK01;
+ input GTNORTHREFCLK10;
+ input GTNORTHREFCLK11;
+ input GTREFCLK00;
+ input GTREFCLK01;
+ input GTREFCLK10;
+ input GTREFCLK11;
+ input GTSOUTHREFCLK00;
+ input GTSOUTHREFCLK01;
+ input GTSOUTHREFCLK10;
+ input GTSOUTHREFCLK11;
+ input [7:0] PMARSVD0;
+ input [7:0] PMARSVD1;
+ input QPLL0CLKRSVD0;
+ input QPLL0LOCKDETCLK;
+ input QPLL0LOCKEN;
+ input QPLL0PD;
+ input [2:0] QPLL0REFCLKSEL;
+ input QPLL0RESET;
+ input QPLL1CLKRSVD0;
+ input QPLL1LOCKDETCLK;
+ input QPLL1LOCKEN;
+ input QPLL1PD;
+ input [2:0] QPLL1REFCLKSEL;
+ input QPLL1RESET;
+ input [7:0] QPLLRSVD1;
+ input [4:0] QPLLRSVD2;
+ input [4:0] QPLLRSVD3;
+ input [7:0] QPLLRSVD4;
+ input RCALENB;
+ input [24:0] SDM0DATA;
+ input SDM0RESET;
+ input [1:0] SDM0WIDTH;
+ input [24:0] SDM1DATA;
+ input SDM1RESET;
+ input [1:0] SDM1WIDTH;
+endmodule
+
+module GTYE4_CHANNEL (...);
+ parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0;
+ parameter [0:0] ACJTAG_MODE = 1'b0;
+ parameter [0:0] ACJTAG_RESET = 1'b0;
+ parameter [15:0] ADAPT_CFG0 = 16'h9200;
+ parameter [15:0] ADAPT_CFG1 = 16'h801C;
+ parameter [15:0] ADAPT_CFG2 = 16'h0000;
+ parameter ALIGN_COMMA_DOUBLE = "FALSE";
+ parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111;
+ parameter integer ALIGN_COMMA_WORD = 1;
+ parameter ALIGN_MCOMMA_DET = "TRUE";
+ parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
+ parameter ALIGN_PCOMMA_DET = "TRUE";
+ parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
+ parameter [0:0] A_RXOSCALRESET = 1'b0;
+ parameter [0:0] A_RXPROGDIVRESET = 1'b0;
+ parameter [0:0] A_RXTERMINATION = 1'b1;
+ parameter [4:0] A_TXDIFFCTRL = 5'b01100;
+ parameter [0:0] A_TXPROGDIVRESET = 1'b0;
+ parameter CBCC_DATA_SOURCE_SEL = "DECODED";
+ parameter [0:0] CDR_SWAP_MODE_EN = 1'b0;
+ parameter [0:0] CFOK_PWRSVE_EN = 1'b1;
+ parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
+ parameter integer CHAN_BOND_MAX_SKEW = 7;
+ parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
+ parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000;
+ parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000;
+ parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000;
+ parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
+ parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000;
+ parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000;
+ parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000;
+ parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000;
+ parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
+ parameter CHAN_BOND_SEQ_2_USE = "FALSE";
+ parameter integer CHAN_BOND_SEQ_LEN = 2;
+ parameter [15:0] CH_HSPMUX = 16'h2424;
+ parameter [15:0] CKCAL1_CFG_0 = 16'b1100000011000000;
+ parameter [15:0] CKCAL1_CFG_1 = 16'b0101000011000000;
+ parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000;
+ parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000;
+ parameter [15:0] CKCAL2_CFG_0 = 16'b1100000011000000;
+ parameter [15:0] CKCAL2_CFG_1 = 16'b1000000011000000;
+ parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000;
+ parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000;
+ parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000;
+ parameter CLK_CORRECT_USE = "TRUE";
+ parameter CLK_COR_KEEP_IDLE = "FALSE";
+ parameter integer CLK_COR_MAX_LAT = 20;
+ parameter integer CLK_COR_MIN_LAT = 18;
+ parameter CLK_COR_PRECEDENCE = "TRUE";
+ parameter integer CLK_COR_REPEAT_WAIT = 0;
+ parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100;
+ parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000;
+ parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000;
+ parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111;
+ parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000;
+ parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000;
+ parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000;
+ parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000;
+ parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
+ parameter CLK_COR_SEQ_2_USE = "FALSE";
+ parameter integer CLK_COR_SEQ_LEN = 2;
+ parameter [15:0] CPLL_CFG0 = 16'h01FA;
+ parameter [15:0] CPLL_CFG1 = 16'h24A9;
+ parameter [15:0] CPLL_CFG2 = 16'h6807;
+ parameter [15:0] CPLL_CFG3 = 16'h0000;
+ parameter integer CPLL_FBDIV = 4;
+ parameter integer CPLL_FBDIV_45 = 4;
+ parameter [15:0] CPLL_INIT_CFG0 = 16'h001E;
+ parameter [15:0] CPLL_LOCK_CFG = 16'h01E8;
+ parameter integer CPLL_REFCLK_DIV = 1;
+ parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000;
+ parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0;
+ parameter [1:0] DDI_CTRL = 2'b00;
+ parameter integer DDI_REALIGN_WAIT = 15;
+ parameter DEC_MCOMMA_DETECT = "TRUE";
+ parameter DEC_PCOMMA_DETECT = "TRUE";
+ parameter DEC_VALID_COMMA_ONLY = "TRUE";
+ parameter [0:0] DELAY_ELEC = 1'b0;
+ parameter [9:0] DMONITOR_CFG0 = 10'h000;
+ parameter [7:0] DMONITOR_CFG1 = 8'h00;
+ parameter [0:0] ES_CLK_PHASE_SEL = 1'b0;
+ parameter [5:0] ES_CONTROL = 6'b000000;
+ parameter ES_ERRDET_EN = "FALSE";
+ parameter ES_EYE_SCAN_EN = "FALSE";
+ parameter [11:0] ES_HORZ_OFFSET = 12'h800;
+ parameter [4:0] ES_PRESCALE = 5'b00000;
+ parameter [15:0] ES_QUALIFIER0 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER1 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER2 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER3 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER4 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER5 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER6 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER7 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER8 = 16'h0000;
+ parameter [15:0] ES_QUALIFIER9 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK0 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK1 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK2 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK3 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK4 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK5 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK6 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK7 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK8 = 16'h0000;
+ parameter [15:0] ES_QUAL_MASK9 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK0 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK1 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK2 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK3 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK4 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK5 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK6 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK7 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK8 = 16'h0000;
+ parameter [15:0] ES_SDATA_MASK9 = 16'h0000;
+ parameter integer EYESCAN_VP_RANGE = 0;
+ parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0;
+ parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111;
+ parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111;
+ parameter FTS_LANE_DESKEW_EN = "FALSE";
+ parameter [4:0] GEARBOX_MODE = 5'b00000;
+ parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0;
+ parameter [0:0] LOCAL_MASTER = 1'b0;
+ parameter integer LPBK_BIAS_CTRL = 4;
+ parameter [0:0] LPBK_EN_RCAL_B = 1'b0;
+ parameter [3:0] LPBK_EXT_RCAL = 4'b0000;
+ parameter integer LPBK_IND_CTRL0 = 5;
+ parameter integer LPBK_IND_CTRL1 = 5;
+ parameter integer LPBK_IND_CTRL2 = 5;
+ parameter integer LPBK_RG_CTRL = 2;
+ parameter [1:0] OOBDIVCTL = 2'b00;
+ parameter [0:0] OOB_PWRUP = 1'b0;
+ parameter PCI3_AUTO_REALIGN = "FRST_SMPL";
+ parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1;
+ parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00;
+ parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0;
+ parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000;
+ parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000;
+ parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000;
+ parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0;
+ parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0;
+ parameter [4:0] PCIE3_CLK_COR_EMPTY_THRSH = 5'b00000;
+ parameter [5:0] PCIE3_CLK_COR_FULL_THRSH = 6'b010000;
+ parameter [4:0] PCIE3_CLK_COR_MAX_LAT = 5'b01000;
+ parameter [4:0] PCIE3_CLK_COR_MIN_LAT = 5'b00100;
+ parameter [5:0] PCIE3_CLK_COR_THRSH_TIMER = 6'b001000;
+ parameter PCIE_64B_DYN_CLKSW_DIS = "FALSE";
+ parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000;
+ parameter PCIE_GEN4_64BIT_INT_EN = "FALSE";
+ parameter [1:0] PCIE_PLL_SEL_MODE_GEN12 = 2'h0;
+ parameter [1:0] PCIE_PLL_SEL_MODE_GEN3 = 2'h0;
+ parameter [1:0] PCIE_PLL_SEL_MODE_GEN4 = 2'h0;
+ parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000;
+ parameter [15:0] PCIE_RXPMA_CFG = 16'h0000;
+ parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000;
+ parameter [15:0] PCIE_TXPMA_CFG = 16'h0000;
+ parameter PCS_PCIE_EN = "FALSE";
+ parameter [15:0] PCS_RSVD0 = 16'h0000;
+ parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C;
+ parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19;
+ parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64;
+ parameter integer PREIQ_FREQ_BST = 0;
+ parameter [0:0] RATE_SW_USE_DRP = 1'b0;
+ parameter [0:0] RCLK_SIPO_DLY_ENB = 1'b0;
+ parameter [0:0] RCLK_SIPO_INV_EN = 1'b0;
+ parameter [2:0] RTX_BUF_CML_CTRL = 3'b010;
+ parameter [1:0] RTX_BUF_TERM_CTRL = 2'b00;
+ parameter [4:0] RXBUFRESET_TIME = 5'b00001;
+ parameter RXBUF_ADDR_MODE = "FULL";
+ parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000;
+ parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000;
+ parameter RXBUF_EN = "TRUE";
+ parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
+ parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
+ parameter RXBUF_RESET_ON_EIDLE = "FALSE";
+ parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
+ parameter integer RXBUF_THRESH_OVFLW = 0;
+ parameter RXBUF_THRESH_OVRD = "FALSE";
+ parameter integer RXBUF_THRESH_UNDFLW = 4;
+ parameter [4:0] RXCDRFREQRESET_TIME = 5'b10000;
+ parameter [4:0] RXCDRPHRESET_TIME = 5'b00001;
+ parameter [15:0] RXCDR_CFG0 = 16'h0003;
+ parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0003;
+ parameter [15:0] RXCDR_CFG1 = 16'h0000;
+ parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000;
+ parameter [15:0] RXCDR_CFG2 = 16'h0164;
+ parameter [9:0] RXCDR_CFG2_GEN2 = 10'h164;
+ parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0034;
+ parameter [15:0] RXCDR_CFG2_GEN4 = 16'h0034;
+ parameter [15:0] RXCDR_CFG3 = 16'h0024;
+ parameter [5:0] RXCDR_CFG3_GEN2 = 6'h24;
+ parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0024;
+ parameter [15:0] RXCDR_CFG3_GEN4 = 16'h0024;
+ parameter [15:0] RXCDR_CFG4 = 16'h5CF6;
+ parameter [15:0] RXCDR_CFG4_GEN3 = 16'h5CF6;
+ parameter [15:0] RXCDR_CFG5 = 16'hB46B;
+ parameter [15:0] RXCDR_CFG5_GEN3 = 16'h146B;
+ parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0;
+ parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0;
+ parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0040;
+ parameter [15:0] RXCDR_LOCK_CFG1 = 16'h8000;
+ parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000;
+ parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000;
+ parameter [15:0] RXCDR_LOCK_CFG4 = 16'h0000;
+ parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0;
+ parameter [15:0] RXCFOK_CFG0 = 16'h0000;
+ parameter [15:0] RXCFOK_CFG1 = 16'h0002;
+ parameter [15:0] RXCFOK_CFG2 = 16'h002D;
+ parameter [15:0] RXCKCAL1_IQ_LOOP_RST_CFG = 16'h0000;
+ parameter [15:0] RXCKCAL1_I_LOOP_RST_CFG = 16'h0000;
+ parameter [15:0] RXCKCAL1_Q_LOOP_RST_CFG = 16'h0000;
+ parameter [15:0] RXCKCAL2_DX_LOOP_RST_CFG = 16'h0000;
+ parameter [15:0] RXCKCAL2_D_LOOP_RST_CFG = 16'h0000;
+ parameter [15:0] RXCKCAL2_S_LOOP_RST_CFG = 16'h0000;
+ parameter [15:0] RXCKCAL2_X_LOOP_RST_CFG = 16'h0000;
+ parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111;
+ parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000;
+ parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022;
+ parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100;
+ parameter [15:0] RXDFE_CFG0 = 16'h4000;
+ parameter [15:0] RXDFE_CFG1 = 16'h0000;
+ parameter [15:0] RXDFE_GC_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_GC_CFG1 = 16'h0000;
+ parameter [15:0] RXDFE_GC_CFG2 = 16'h0000;
+ parameter [15:0] RXDFE_H2_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H2_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_H3_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H3_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_H4_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H4_CFG1 = 16'h0003;
+ parameter [15:0] RXDFE_H5_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H5_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_H6_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H6_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_H7_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H7_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_H8_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H8_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_H9_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_H9_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_HA_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_HA_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_HB_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_HB_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_HC_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_HC_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_HD_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_HD_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_HE_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_HE_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_HF_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_HF_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_KH_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_KH_CFG1 = 16'h0000;
+ parameter [15:0] RXDFE_KH_CFG2 = 16'h0000;
+ parameter [15:0] RXDFE_KH_CFG3 = 16'h0000;
+ parameter [15:0] RXDFE_OS_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_OS_CFG1 = 16'h0000;
+ parameter [15:0] RXDFE_UT_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_UT_CFG1 = 16'h0002;
+ parameter [15:0] RXDFE_UT_CFG2 = 16'h0000;
+ parameter [15:0] RXDFE_VP_CFG0 = 16'h0000;
+ parameter [15:0] RXDFE_VP_CFG1 = 16'h0022;
+ parameter [15:0] RXDLY_CFG = 16'h0010;
+ parameter [15:0] RXDLY_LCFG = 16'h0030;
+ parameter RXELECIDLE_CFG = "SIGCFG_4";
+ parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4;
+ parameter RXGEARBOX_EN = "FALSE";
+ parameter [4:0] RXISCANRESET_TIME = 5'b00001;
+ parameter [15:0] RXLPM_CFG = 16'h0000;
+ parameter [15:0] RXLPM_GC_CFG = 16'h1000;
+ parameter [15:0] RXLPM_KH_CFG0 = 16'h0000;
+ parameter [15:0] RXLPM_KH_CFG1 = 16'h0002;
+ parameter [15:0] RXLPM_OS_CFG0 = 16'h0000;
+ parameter [15:0] RXLPM_OS_CFG1 = 16'h0000;
+ parameter [8:0] RXOOB_CFG = 9'b000110000;
+ parameter RXOOB_CLK_CFG = "PMA";
+ parameter [4:0] RXOSCALRESET_TIME = 5'b00011;
+ parameter integer RXOUT_DIV = 4;
+ parameter [4:0] RXPCSRESET_TIME = 5'b00001;
+ parameter [15:0] RXPHBEACON_CFG = 16'h0000;
+ parameter [15:0] RXPHDLY_CFG = 16'h2020;
+ parameter [15:0] RXPHSAMP_CFG = 16'h2100;
+ parameter [15:0] RXPHSLIP_CFG = 16'h9933;
+ parameter [4:0] RXPH_MONITOR_SEL = 5'b00000;
+ parameter [15:0] RXPI_CFG0 = 16'h0102;
+ parameter [15:0] RXPI_CFG1 = 16'b0000000001010100;
+ parameter RXPMACLK_SEL = "DATA";
+ parameter [4:0] RXPMARESET_TIME = 5'b00001;
+ parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0;
+ parameter integer RXPRBS_LINKACQ_CNT = 15;
+ parameter [0:0] RXREFCLKDIV2_SEL = 1'b0;
+ parameter integer RXSLIDE_AUTO_WAIT = 7;
+ parameter RXSLIDE_MODE = "OFF";
+ parameter [0:0] RXSYNC_MULTILANE = 1'b0;
+ parameter [0:0] RXSYNC_OVRD = 1'b0;
+ parameter [0:0] RXSYNC_SKIP_DA = 1'b0;
+ parameter [0:0] RX_AFE_CM_EN = 1'b0;
+ parameter [15:0] RX_BIAS_CFG0 = 16'h12B0;
+ parameter [5:0] RX_BUFFER_CFG = 6'b000000;
+ parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0;
+ parameter integer RX_CLK25_DIV = 8;
+ parameter [0:0] RX_CLKMUX_EN = 1'b1;
+ parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000;
+ parameter [3:0] RX_CM_BUF_CFG = 4'b1010;
+ parameter [0:0] RX_CM_BUF_PD = 1'b0;
+ parameter integer RX_CM_SEL = 3;
+ parameter integer RX_CM_TRIM = 12;
+ parameter [0:0] RX_CTLE_PWR_SAVING = 1'b0;
+ parameter [3:0] RX_CTLE_RES_CTRL = 4'b0000;
+ parameter integer RX_DATA_WIDTH = 20;
+ parameter [5:0] RX_DDI_SEL = 6'b000000;
+ parameter RX_DEFER_RESET_BUF_EN = "TRUE";
+ parameter [2:0] RX_DEGEN_CTRL = 3'b100;
+ parameter integer RX_DFELPM_CFG0 = 0;
+ parameter [0:0] RX_DFELPM_CFG1 = 1'b1;
+ parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1;
+ parameter integer RX_DFE_AGC_CFG1 = 4;
+ parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1;
+ parameter integer RX_DFE_KL_LPM_KH_CFG1 = 4;
+ parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01;
+ parameter integer RX_DFE_KL_LPM_KL_CFG1 = 4;
+ parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0;
+ parameter RX_DISPERR_SEQ_MATCH = "TRUE";
+ parameter [4:0] RX_DIVRESET_TIME = 5'b00001;
+ parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0;
+ parameter integer RX_EN_SUM_RCAL_B = 0;
+ parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000;
+ parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0;
+ parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b10;
+ parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0;
+ parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0;
+ parameter [0:0] RX_I2V_FILTER_EN = 1'b1;
+ parameter integer RX_INT_DATAWIDTH = 1;
+ parameter [0:0] RX_PMA_POWER_SAVE = 1'b0;
+ parameter [15:0] RX_PMA_RSV0 = 16'h000F;
+ parameter real RX_PROGDIV_CFG = 0.0;
+ parameter [15:0] RX_PROGDIV_RATE = 16'h0001;
+ parameter [3:0] RX_RESLOAD_CTRL = 4'b0000;
+ parameter [0:0] RX_RESLOAD_OVRD = 1'b0;
+ parameter [2:0] RX_SAMPLE_PERIOD = 3'b101;
+ parameter integer RX_SIG_VALID_DLY = 11;
+ parameter integer RX_SUM_DEGEN_AVTT_OVERITE = 0;
+ parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0;
+ parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000;
+ parameter integer RX_SUM_PWR_SAVING = 0;
+ parameter [3:0] RX_SUM_RES_CTRL = 4'b0000;
+ parameter [3:0] RX_SUM_VCMTUNE = 4'b0011;
+ parameter [0:0] RX_SUM_VCM_BIAS_TUNE_EN = 1'b1;
+ parameter [0:0] RX_SUM_VCM_OVWR = 1'b0;
+ parameter [2:0] RX_SUM_VREF_TUNE = 3'b100;
+ parameter [1:0] RX_TUNE_AFE_OS = 2'b00;
+ parameter [2:0] RX_VREG_CTRL = 3'b010;
+ parameter [0:0] RX_VREG_PDB = 1'b1;
+ parameter [1:0] RX_WIDEMODE_CDR = 2'b01;
+ parameter [1:0] RX_WIDEMODE_CDR_GEN3 = 2'b01;
+ parameter [1:0] RX_WIDEMODE_CDR_GEN4 = 2'b01;
+ parameter RX_XCLK_SEL = "RXDES";
+ parameter [0:0] RX_XMODE_SEL = 1'b0;
+ parameter [0:0] SAMPLE_CLK_PHASE = 1'b0;
+ parameter [0:0] SAS_12G_MODE = 1'b0;
+ parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
+ parameter [2:0] SATA_BURST_VAL = 3'b100;
+ parameter SATA_CPLL_CFG = "VCO_3000MHZ";
+ parameter [2:0] SATA_EIDLE_VAL = 3'b100;
+ parameter SHOW_REALIGN_COMMA = "TRUE";
+ parameter SIM_MODE = "FAST";
+ parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
+ parameter SIM_RESET_SPEEDUP = "TRUE";
+ parameter SIM_TX_EIDLE_DRIVE_LEVEL = "Z";
+ parameter SIM_DEVICE = "ULTRASCALE_PLUS";
+ parameter [0:0] SRSTMODE = 1'b0;
+ parameter [1:0] TAPDLY_SET_TX = 2'h0;
+ parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000;
+ parameter [2:0] TERM_RCAL_OVRD = 3'b000;
+ parameter [7:0] TRANS_TIME_RATE = 8'h0E;
+ parameter [7:0] TST_RSV0 = 8'h00;
+ parameter [7:0] TST_RSV1 = 8'h00;
+ parameter TXBUF_EN = "TRUE";
+ parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE";
+ parameter [15:0] TXDLY_CFG = 16'h0010;
+ parameter [15:0] TXDLY_LCFG = 16'h0030;
+ parameter integer TXDRV_FREQBAND = 0;
+ parameter [15:0] TXFE_CFG0 = 16'b0000000000000000;
+ parameter [15:0] TXFE_CFG1 = 16'b0000000000000000;
+ parameter [15:0] TXFE_CFG2 = 16'b0000000000000000;
+ parameter [15:0] TXFE_CFG3 = 16'b0000000000000000;
+ parameter TXFIFO_ADDR_CFG = "LOW";
+ parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4;
+ parameter TXGEARBOX_EN = "FALSE";
+ parameter integer TXOUT_DIV = 4;
+ parameter [4:0] TXPCSRESET_TIME = 5'b00001;
+ parameter [15:0] TXPHDLY_CFG0 = 16'h6020;
+ parameter [15:0] TXPHDLY_CFG1 = 16'h0002;
+ parameter [15:0] TXPH_CFG = 16'h0123;
+ parameter [15:0] TXPH_CFG2 = 16'h0000;
+ parameter [4:0] TXPH_MONITOR_SEL = 5'b00000;
+ parameter [15:0] TXPI_CFG0 = 16'b0000000100000000;
+ parameter [15:0] TXPI_CFG1 = 16'b0000000000000000;
+ parameter [0:0] TXPI_GRAY_SEL = 1'b0;
+ parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0;
+ parameter [0:0] TXPI_PPM = 1'b0;
+ parameter [7:0] TXPI_PPM_CFG = 8'b00000000;
+ parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000;
+ parameter [4:0] TXPMARESET_TIME = 5'b00001;
+ parameter [0:0] TXREFCLKDIV2_SEL = 1'b0;
+ parameter integer TXSWBST_BST = 1;
+ parameter integer TXSWBST_EN = 0;
+ parameter integer TXSWBST_MAG = 6;
+ parameter [0:0] TXSYNC_MULTILANE = 1'b0;
+ parameter [0:0] TXSYNC_OVRD = 1'b0;
+ parameter [0:0] TXSYNC_SKIP_DA = 1'b0;
+ parameter integer TX_CLK25_DIV = 8;
+ parameter [0:0] TX_CLKMUX_EN = 1'b1;
+ parameter integer TX_DATA_WIDTH = 20;
+ parameter [15:0] TX_DCC_LOOP_RST_CFG = 16'h0000;
+ parameter [5:0] TX_DEEMPH0 = 6'b000000;
+ parameter [5:0] TX_DEEMPH1 = 6'b000000;
+ parameter [5:0] TX_DEEMPH2 = 6'b000000;
+ parameter [5:0] TX_DEEMPH3 = 6'b000000;
+ parameter [4:0] TX_DIVRESET_TIME = 5'b00001;
+ parameter TX_DRIVE_MODE = "DIRECT";
+ parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110;
+ parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100;
+ parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0;
+ parameter [0:0] TX_FIFO_BYP_EN = 1'b0;
+ parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0;
+ parameter integer TX_INT_DATAWIDTH = 1;
+ parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
+ parameter [0:0] TX_MAINCURSOR_SEL = 1'b0;
+ parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110;
+ parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001;
+ parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101;
+ parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010;
+ parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000;
+ parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110;
+ parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100;
+ parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
+ parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
+ parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
+ parameter [15:0] TX_PHICAL_CFG0 = 16'h0000;
+ parameter [15:0] TX_PHICAL_CFG1 = 16'h003F;
+ parameter integer TX_PI_BIASSET = 0;
+ parameter [0:0] TX_PMADATA_OPT = 1'b0;
+ parameter [0:0] TX_PMA_POWER_SAVE = 1'b0;
+ parameter [15:0] TX_PMA_RSV0 = 16'h0000;
+ parameter [15:0] TX_PMA_RSV1 = 16'h0000;
+ parameter TX_PROGCLK_SEL = "POSTPI";
+ parameter real TX_PROGDIV_CFG = 0.0;
+ parameter [15:0] TX_PROGDIV_RATE = 16'h0001;
+ parameter [13:0] TX_RXDETECT_CFG = 14'h0032;
+ parameter integer TX_RXDETECT_REF = 3;
+ parameter [2:0] TX_SAMPLE_PERIOD = 3'b101;
+ parameter [1:0] TX_SW_MEAS = 2'b00;
+ parameter [2:0] TX_VREG_CTRL = 3'b000;
+ parameter [0:0] TX_VREG_PDB = 1'b0;
+ parameter [1:0] TX_VREG_VREFSEL = 2'b00;
+ parameter TX_XCLK_SEL = "TXOUT";
+ parameter [0:0] USB_BOTH_BURST_IDLE = 1'b0;
+ parameter [6:0] USB_BURSTMAX_U3WAKE = 7'b1111111;
+ parameter [6:0] USB_BURSTMIN_U3WAKE = 7'b1100011;
+ parameter [0:0] USB_CLK_COR_EQ_EN = 1'b0;
+ parameter [0:0] USB_EXT_CNTL = 1'b1;
+ parameter [9:0] USB_IDLEMAX_POLLING = 10'b1010111011;
+ parameter [9:0] USB_IDLEMIN_POLLING = 10'b0100101011;
+ parameter [8:0] USB_LFPSPING_BURST = 9'b000000101;
+ parameter [8:0] USB_LFPSPOLLING_BURST = 9'b000110001;
+ parameter [8:0] USB_LFPSPOLLING_IDLE_MS = 9'b000000100;
+ parameter [8:0] USB_LFPSU1EXIT_BURST = 9'b000011101;
+ parameter [8:0] USB_LFPSU2LPEXIT_BURST_MS = 9'b001100011;
+ parameter [8:0] USB_LFPSU3WAKE_BURST_MS = 9'b111110011;
+ parameter [3:0] USB_LFPS_TPERIOD = 4'b0011;
+ parameter [0:0] USB_LFPS_TPERIOD_ACCURATE = 1'b1;
+ parameter [0:0] USB_MODE = 1'b0;
+ parameter [0:0] USB_PCIE_ERR_REP_DIS = 1'b0;
+ parameter integer USB_PING_SATA_MAX_INIT = 21;
+ parameter integer USB_PING_SATA_MIN_INIT = 12;
+ parameter integer USB_POLL_SATA_MAX_BURST = 8;
+ parameter integer USB_POLL_SATA_MIN_BURST = 4;
+ parameter [0:0] USB_RAW_ELEC = 1'b0;
+ parameter [0:0] USB_RXIDLE_P0_CTRL = 1'b1;
+ parameter [0:0] USB_TXIDLE_TUNE_ENABLE = 1'b1;
+ parameter integer USB_U1_SATA_MAX_WAKE = 7;
+ parameter integer USB_U1_SATA_MIN_WAKE = 4;
+ parameter integer USB_U2_SAS_MAX_COM = 64;
+ parameter integer USB_U2_SAS_MIN_COM = 36;
+ parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0;
+ parameter [0:0] Y_ALL_MODE = 1'b0;
+ output BUFGTCE;
+ output [2:0] BUFGTCEMASK;
+ output [8:0] BUFGTDIV;
+ output BUFGTRESET;
+ output [2:0] BUFGTRSTMASK;
+ output CPLLFBCLKLOST;
+ output CPLLLOCK;
+ output CPLLREFCLKLOST;
+ output [15:0] DMONITOROUT;
+ output DMONITOROUTCLK;
+ output [15:0] DRPDO;
+ output DRPRDY;
+ output EYESCANDATAERROR;
+ output GTPOWERGOOD;
+ output GTREFCLKMONITOR;
+ output GTYTXN;
+ output GTYTXP;
+ output PCIERATEGEN3;
+ output PCIERATEIDLE;
+ output [1:0] PCIERATEQPLLPD;
+ output [1:0] PCIERATEQPLLRESET;
+ output PCIESYNCTXSYNCDONE;
+ output PCIEUSERGEN3RDY;
+ output PCIEUSERPHYSTATUSRST;
+ output PCIEUSERRATESTART;
+ output [15:0] PCSRSVDOUT;
+ output PHYSTATUS;
+ output [15:0] PINRSRVDAS;
+ output POWERPRESENT;
+ output RESETEXCEPTION;
+ output [2:0] RXBUFSTATUS;
+ output RXBYTEISALIGNED;
+ output RXBYTEREALIGN;
+ output RXCDRLOCK;
+ output RXCDRPHDONE;
+ output RXCHANBONDSEQ;
+ output RXCHANISALIGNED;
+ output RXCHANREALIGN;
+ output [4:0] RXCHBONDO;
+ output RXCKCALDONE;
+ output [1:0] RXCLKCORCNT;
+ output RXCOMINITDET;
+ output RXCOMMADET;
+ output RXCOMSASDET;
+ output RXCOMWAKEDET;
+ output [15:0] RXCTRL0;
+ output [15:0] RXCTRL1;
+ output [7:0] RXCTRL2;
+ output [7:0] RXCTRL3;
+ output [127:0] RXDATA;
+ output [7:0] RXDATAEXTENDRSVD;
+ output [1:0] RXDATAVALID;
+ output RXDLYSRESETDONE;
+ output RXELECIDLE;
+ output [5:0] RXHEADER;
+ output [1:0] RXHEADERVALID;
+ output RXLFPSTRESETDET;
+ output RXLFPSU2LPEXITDET;
+ output RXLFPSU3WAKEDET;
+ output [7:0] RXMONITOROUT;
+ output RXOSINTDONE;
+ output RXOSINTSTARTED;
+ output RXOSINTSTROBEDONE;
+ output RXOSINTSTROBESTARTED;
+ output RXOUTCLK;
+ output RXOUTCLKFABRIC;
+ output RXOUTCLKPCS;
+ output RXPHALIGNDONE;
+ output RXPHALIGNERR;
+ output RXPMARESETDONE;
+ output RXPRBSERR;
+ output RXPRBSLOCKED;
+ output RXPRGDIVRESETDONE;
+ output RXRATEDONE;
+ output RXRECCLKOUT;
+ output RXRESETDONE;
+ output RXSLIDERDY;
+ output RXSLIPDONE;
+ output RXSLIPOUTCLKRDY;
+ output RXSLIPPMARDY;
+ output [1:0] RXSTARTOFSEQ;
+ output [2:0] RXSTATUS;
+ output RXSYNCDONE;
+ output RXSYNCOUT;
+ output RXVALID;
+ output [1:0] TXBUFSTATUS;
+ output TXCOMFINISH;
+ output TXDCCDONE;
+ output TXDLYSRESETDONE;
+ output TXOUTCLK;
+ output TXOUTCLKFABRIC;
+ output TXOUTCLKPCS;
+ output TXPHALIGNDONE;
+ output TXPHINITDONE;
+ output TXPMARESETDONE;
+ output TXPRGDIVRESETDONE;
+ output TXRATEDONE;
+ output TXRESETDONE;
+ output TXSYNCDONE;
+ output TXSYNCOUT;
+ input CDRSTEPDIR;
+ input CDRSTEPSQ;
+ input CDRSTEPSX;
+ input CFGRESET;
+ input CLKRSVD0;
+ input CLKRSVD1;
+ input CPLLFREQLOCK;
+ input CPLLLOCKDETCLK;
+ input CPLLLOCKEN;
+ input CPLLPD;
+ input [2:0] CPLLREFCLKSEL;
+ input CPLLRESET;
+ input DMONFIFORESET;
+ input DMONITORCLK;
+ input [9:0] DRPADDR;
+ input DRPCLK;
+ input [15:0] DRPDI;
+ input DRPEN;
+ input DRPRST;
+ input DRPWE;
+ input EYESCANRESET;
+ input EYESCANTRIGGER;
+ input FREQOS;
+ input GTGREFCLK;
+ input GTNORTHREFCLK0;
+ input GTNORTHREFCLK1;
+ input GTREFCLK0;
+ input GTREFCLK1;
+ input [15:0] GTRSVD;
+ input GTRXRESET;
+ input GTRXRESETSEL;
+ input GTSOUTHREFCLK0;
+ input GTSOUTHREFCLK1;
+ input GTTXRESET;
+ input GTTXRESETSEL;
+ input GTYRXN;
+ input GTYRXP;
+ input INCPCTRL;
+ input [2:0] LOOPBACK;
+ input PCIEEQRXEQADAPTDONE;
+ input PCIERSTIDLE;
+ input PCIERSTTXSYNCSTART;
+ input PCIEUSERRATEDONE;
+ input [15:0] PCSRSVDIN;
+ input QPLL0CLK;
+ input QPLL0FREQLOCK;
+ input QPLL0REFCLK;
+ input QPLL1CLK;
+ input QPLL1FREQLOCK;
+ input QPLL1REFCLK;
+ input RESETOVRD;
+ input RX8B10BEN;
+ input RXAFECFOKEN;
+ input RXBUFRESET;
+ input RXCDRFREQRESET;
+ input RXCDRHOLD;
+ input RXCDROVRDEN;
+ input RXCDRRESET;
+ input RXCHBONDEN;
+ input [4:0] RXCHBONDI;
+ input [2:0] RXCHBONDLEVEL;
+ input RXCHBONDMASTER;
+ input RXCHBONDSLAVE;
+ input RXCKCALRESET;
+ input [6:0] RXCKCALSTART;
+ input RXCOMMADETEN;
+ input RXDFEAGCHOLD;
+ input RXDFEAGCOVRDEN;
+ input [3:0] RXDFECFOKFCNUM;
+ input RXDFECFOKFEN;
+ input RXDFECFOKFPULSE;
+ input RXDFECFOKHOLD;
+ input RXDFECFOKOVREN;
+ input RXDFEKHHOLD;
+ input RXDFEKHOVRDEN;
+ input RXDFELFHOLD;
+ input RXDFELFOVRDEN;
+ input RXDFELPMRESET;
+ input RXDFETAP10HOLD;
+ input RXDFETAP10OVRDEN;
+ input RXDFETAP11HOLD;
+ input RXDFETAP11OVRDEN;
+ input RXDFETAP12HOLD;
+ input RXDFETAP12OVRDEN;
+ input RXDFETAP13HOLD;
+ input RXDFETAP13OVRDEN;
+ input RXDFETAP14HOLD;
+ input RXDFETAP14OVRDEN;
+ input RXDFETAP15HOLD;
+ input RXDFETAP15OVRDEN;
+ input RXDFETAP2HOLD;
+ input RXDFETAP2OVRDEN;
+ input RXDFETAP3HOLD;
+ input RXDFETAP3OVRDEN;
+ input RXDFETAP4HOLD;
+ input RXDFETAP4OVRDEN;
+ input RXDFETAP5HOLD;
+ input RXDFETAP5OVRDEN;
+ input RXDFETAP6HOLD;
+ input RXDFETAP6OVRDEN;
+ input RXDFETAP7HOLD;
+ input RXDFETAP7OVRDEN;
+ input RXDFETAP8HOLD;
+ input RXDFETAP8OVRDEN;
+ input RXDFETAP9HOLD;
+ input RXDFETAP9OVRDEN;
+ input RXDFEUTHOLD;
+ input RXDFEUTOVRDEN;
+ input RXDFEVPHOLD;
+ input RXDFEVPOVRDEN;
+ input RXDFEXYDEN;
+ input RXDLYBYPASS;
+ input RXDLYEN;
+ input RXDLYOVRDEN;
+ input RXDLYSRESET;
+ input [1:0] RXELECIDLEMODE;
+ input RXEQTRAINING;
+ input RXGEARBOXSLIP;
+ input RXLATCLK;
+ input RXLPMEN;
+ input RXLPMGCHOLD;
+ input RXLPMGCOVRDEN;
+ input RXLPMHFHOLD;
+ input RXLPMHFOVRDEN;
+ input RXLPMLFHOLD;
+ input RXLPMLFKLOVRDEN;
+ input RXLPMOSHOLD;
+ input RXLPMOSOVRDEN;
+ input RXMCOMMAALIGNEN;
+ input [1:0] RXMONITORSEL;
+ input RXOOBRESET;
+ input RXOSCALRESET;
+ input RXOSHOLD;
+ input RXOSOVRDEN;
+ input [2:0] RXOUTCLKSEL;
+ input RXPCOMMAALIGNEN;
+ input RXPCSRESET;
+ input [1:0] RXPD;
+ input RXPHALIGN;
+ input RXPHALIGNEN;
+ input RXPHDLYPD;
+ input RXPHDLYRESET;
+ input [1:0] RXPLLCLKSEL;
+ input RXPMARESET;
+ input RXPOLARITY;
+ input RXPRBSCNTRESET;
+ input [3:0] RXPRBSSEL;
+ input RXPROGDIVRESET;
+ input [2:0] RXRATE;
+ input RXRATEMODE;
+ input RXSLIDE;
+ input RXSLIPOUTCLK;
+ input RXSLIPPMA;
+ input RXSYNCALLIN;
+ input RXSYNCIN;
+ input RXSYNCMODE;
+ input [1:0] RXSYSCLKSEL;
+ input RXTERMINATION;
+ input RXUSERRDY;
+ input RXUSRCLK;
+ input RXUSRCLK2;
+ input SIGVALIDCLK;
+ input [19:0] TSTIN;
+ input [7:0] TX8B10BBYPASS;
+ input TX8B10BEN;
+ input TXCOMINIT;
+ input TXCOMSAS;
+ input TXCOMWAKE;
+ input [15:0] TXCTRL0;
+ input [15:0] TXCTRL1;
+ input [7:0] TXCTRL2;
+ input [127:0] TXDATA;
+ input [7:0] TXDATAEXTENDRSVD;
+ input TXDCCFORCESTART;
+ input TXDCCRESET;
+ input [1:0] TXDEEMPH;
+ input TXDETECTRX;
+ input [4:0] TXDIFFCTRL;
+ input TXDLYBYPASS;
+ input TXDLYEN;
+ input TXDLYHOLD;
+ input TXDLYOVRDEN;
+ input TXDLYSRESET;
+ input TXDLYUPDOWN;
+ input TXELECIDLE;
+ input [5:0] TXHEADER;
+ input TXINHIBIT;
+ input TXLATCLK;
+ input TXLFPSTRESET;
+ input TXLFPSU2LPEXIT;
+ input TXLFPSU3WAKE;
+ input [6:0] TXMAINCURSOR;
+ input [2:0] TXMARGIN;
+ input TXMUXDCDEXHOLD;
+ input TXMUXDCDORWREN;
+ input TXONESZEROS;
+ input [2:0] TXOUTCLKSEL;
+ input TXPCSRESET;
+ input [1:0] TXPD;
+ input TXPDELECIDLEMODE;
+ input TXPHALIGN;
+ input TXPHALIGNEN;
+ input TXPHDLYPD;
+ input TXPHDLYRESET;
+ input TXPHDLYTSTCLK;
+ input TXPHINIT;
+ input TXPHOVRDEN;
+ input TXPIPPMEN;
+ input TXPIPPMOVRDEN;
+ input TXPIPPMPD;
+ input TXPIPPMSEL;
+ input [4:0] TXPIPPMSTEPSIZE;
+ input TXPISOPD;
+ input [1:0] TXPLLCLKSEL;
+ input TXPMARESET;
+ input TXPOLARITY;
+ input [4:0] TXPOSTCURSOR;
+ input TXPRBSFORCEERR;
+ input [3:0] TXPRBSSEL;
+ input [4:0] TXPRECURSOR;
+ input TXPROGDIVRESET;
+ input [2:0] TXRATE;
+ input TXRATEMODE;
+ input [6:0] TXSEQUENCE;
+ input TXSWING;
+ input TXSYNCALLIN;
+ input TXSYNCIN;
+ input TXSYNCMODE;
+ input [1:0] TXSYSCLKSEL;
+ input TXUSERRDY;
+ input TXUSRCLK;
+ input TXUSRCLK2;
+endmodule
+
+module GTYE4_COMMON (...);
+ parameter [0:0] AEN_QPLL0_FBDIV = 1'b1;
+ parameter [0:0] AEN_QPLL1_FBDIV = 1'b1;
+ parameter [0:0] AEN_SDM0TOGGLE = 1'b0;
+ parameter [0:0] AEN_SDM1TOGGLE = 1'b0;
+ parameter [0:0] A_SDM0TOGGLE = 1'b0;
+ parameter [8:0] A_SDM1DATA_HIGH = 9'b000000000;
+ parameter [15:0] A_SDM1DATA_LOW = 16'b0000000000000000;
+ parameter [0:0] A_SDM1TOGGLE = 1'b0;
+ parameter [15:0] BIAS_CFG0 = 16'h0000;
+ parameter [15:0] BIAS_CFG1 = 16'h0000;
+ parameter [15:0] BIAS_CFG2 = 16'h0000;
+ parameter [15:0] BIAS_CFG3 = 16'h0000;
+ parameter [15:0] BIAS_CFG4 = 16'h0000;
+ parameter [15:0] BIAS_CFG_RSVD = 16'h0000;
+ parameter [15:0] COMMON_CFG0 = 16'h0000;
+ parameter [15:0] COMMON_CFG1 = 16'h0000;
+ parameter [15:0] POR_CFG = 16'h0000;
+ parameter [15:0] PPF0_CFG = 16'h0F00;
+ parameter [15:0] PPF1_CFG = 16'h0F00;
+ parameter QPLL0CLKOUT_RATE = "FULL";
+ parameter [15:0] QPLL0_CFG0 = 16'h391C;
+ parameter [15:0] QPLL0_CFG1 = 16'h0000;
+ parameter [15:0] QPLL0_CFG1_G3 = 16'h0020;
+ parameter [15:0] QPLL0_CFG2 = 16'h0F80;
+ parameter [15:0] QPLL0_CFG2_G3 = 16'h0F80;
+ parameter [15:0] QPLL0_CFG3 = 16'h0120;
+ parameter [15:0] QPLL0_CFG4 = 16'h0002;
+ parameter [9:0] QPLL0_CP = 10'b0000011111;
+ parameter [9:0] QPLL0_CP_G3 = 10'b0000011111;
+ parameter integer QPLL0_FBDIV = 66;
+ parameter integer QPLL0_FBDIV_G3 = 80;
+ parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000;
+ parameter [7:0] QPLL0_INIT_CFG1 = 8'h00;
+ parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8;
+ parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8;
+ parameter [9:0] QPLL0_LPF = 10'b1011111111;
+ parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111;
+ parameter [0:0] QPLL0_PCI_EN = 1'b0;
+ parameter [0:0] QPLL0_RATE_SW_USE_DRP = 1'b0;
+ parameter integer QPLL0_REFCLK_DIV = 1;
+ parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040;
+ parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000;
+ parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000;
+ parameter QPLL1CLKOUT_RATE = "FULL";
+ parameter [15:0] QPLL1_CFG0 = 16'h691C;
+ parameter [15:0] QPLL1_CFG1 = 16'h0020;
+ parameter [15:0] QPLL1_CFG1_G3 = 16'h0020;
+ parameter [15:0] QPLL1_CFG2 = 16'h0F80;
+ parameter [15:0] QPLL1_CFG2_G3 = 16'h0F80;
+ parameter [15:0] QPLL1_CFG3 = 16'h0120;
+ parameter [15:0] QPLL1_CFG4 = 16'h0002;
+ parameter [9:0] QPLL1_CP = 10'b0000011111;
+ parameter [9:0] QPLL1_CP_G3 = 10'b0000011111;
+ parameter integer QPLL1_FBDIV = 66;
+ parameter integer QPLL1_FBDIV_G3 = 80;
+ parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000;
+ parameter [7:0] QPLL1_INIT_CFG1 = 8'h00;
+ parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8;
+ parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8;
+ parameter [9:0] QPLL1_LPF = 10'b1011111111;
+ parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111;
+ parameter [0:0] QPLL1_PCI_EN = 1'b0;
+ parameter [0:0] QPLL1_RATE_SW_USE_DRP = 1'b0;
+ parameter integer QPLL1_REFCLK_DIV = 1;
+ parameter [15:0] QPLL1_SDM_CFG0 = 16'h0000;
+ parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000;
+ parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000;
+ parameter [15:0] RSVD_ATTR0 = 16'h0000;
+ parameter [15:0] RSVD_ATTR1 = 16'h0000;
+ parameter [15:0] RSVD_ATTR2 = 16'h0000;
+ parameter [15:0] RSVD_ATTR3 = 16'h0000;
+ parameter [1:0] RXRECCLKOUT0_SEL = 2'b00;
+ parameter [1:0] RXRECCLKOUT1_SEL = 2'b00;
+ parameter [0:0] SARC_ENB = 1'b0;
+ parameter [0:0] SARC_SEL = 1'b0;
+ parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000;
+ parameter [8:0] SDM0INITSEED0_1 = 9'b000000000;
+ parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000;
+ parameter [8:0] SDM1INITSEED0_1 = 9'b000000000;
+ parameter SIM_MODE = "FAST";
+ parameter SIM_RESET_SPEEDUP = "TRUE";
+ parameter SIM_DEVICE = "ULTRASCALE_PLUS";
+ parameter [15:0] UB_CFG0 = 16'h0000;
+ parameter [15:0] UB_CFG1 = 16'h0000;
+ parameter [15:0] UB_CFG2 = 16'h0000;
+ parameter [15:0] UB_CFG3 = 16'h0000;
+ parameter [15:0] UB_CFG4 = 16'h0000;
+ parameter [15:0] UB_CFG5 = 16'h0400;
+ parameter [15:0] UB_CFG6 = 16'h0000;
+ output [15:0] DRPDO;
+ output DRPRDY;
+ output [7:0] PMARSVDOUT0;
+ output [7:0] PMARSVDOUT1;
+ output QPLL0FBCLKLOST;
+ output QPLL0LOCK;
+ output QPLL0OUTCLK;
+ output QPLL0OUTREFCLK;
+ output QPLL0REFCLKLOST;
+ output QPLL1FBCLKLOST;
+ output QPLL1LOCK;
+ output QPLL1OUTCLK;
+ output QPLL1OUTREFCLK;
+ output QPLL1REFCLKLOST;
+ output [7:0] QPLLDMONITOR0;
+ output [7:0] QPLLDMONITOR1;
+ output REFCLKOUTMONITOR0;
+ output REFCLKOUTMONITOR1;
+ output [1:0] RXRECCLK0SEL;
+ output [1:0] RXRECCLK1SEL;
+ output [3:0] SDM0FINALOUT;
+ output [14:0] SDM0TESTDATA;
+ output [3:0] SDM1FINALOUT;
+ output [14:0] SDM1TESTDATA;
+ output [15:0] UBDADDR;
+ output UBDEN;
+ output [15:0] UBDI;
+ output UBDWE;
+ output UBMDMTDO;
+ output UBRSVDOUT;
+ output UBTXUART;
+ input BGBYPASSB;
+ input BGMONITORENB;
+ input BGPDB;
+ input [4:0] BGRCALOVRD;
+ input BGRCALOVRDENB;
+ input [15:0] DRPADDR;
+ input DRPCLK;
+ input [15:0] DRPDI;
+ input DRPEN;
+ input DRPWE;
+ input GTGREFCLK0;
+ input GTGREFCLK1;
+ input GTNORTHREFCLK00;
+ input GTNORTHREFCLK01;
+ input GTNORTHREFCLK10;
+ input GTNORTHREFCLK11;
+ input GTREFCLK00;
+ input GTREFCLK01;
+ input GTREFCLK10;
+ input GTREFCLK11;
+ input GTSOUTHREFCLK00;
+ input GTSOUTHREFCLK01;
+ input GTSOUTHREFCLK10;
+ input GTSOUTHREFCLK11;
+ input [2:0] PCIERATEQPLL0;
+ input [2:0] PCIERATEQPLL1;
+ input [7:0] PMARSVD0;
+ input [7:0] PMARSVD1;
+ input QPLL0CLKRSVD0;
+ input QPLL0CLKRSVD1;
+ input [7:0] QPLL0FBDIV;
+ input QPLL0LOCKDETCLK;
+ input QPLL0LOCKEN;
+ input QPLL0PD;
+ input [2:0] QPLL0REFCLKSEL;
+ input QPLL0RESET;
+ input QPLL1CLKRSVD0;
+ input QPLL1CLKRSVD1;
+ input [7:0] QPLL1FBDIV;
+ input QPLL1LOCKDETCLK;
+ input QPLL1LOCKEN;
+ input QPLL1PD;
+ input [2:0] QPLL1REFCLKSEL;
+ input QPLL1RESET;
+ input [7:0] QPLLRSVD1;
+ input [4:0] QPLLRSVD2;
+ input [4:0] QPLLRSVD3;
+ input [7:0] QPLLRSVD4;
+ input RCALENB;
+ input [24:0] SDM0DATA;
+ input SDM0RESET;
+ input SDM0TOGGLE;
+ input [1:0] SDM0WIDTH;
+ input [24:0] SDM1DATA;
+ input SDM1RESET;
+ input SDM1TOGGLE;
+ input [1:0] SDM1WIDTH;
+ input UBCFGSTREAMEN;
+ input [15:0] UBDO;
+ input UBDRDY;
+ input UBENABLE;
+ input [1:0] UBGPI;
+ input [1:0] UBINTR;
+ input UBIOLMBRST;
+ input UBMBRST;
+ input UBMDMCAPTURE;
+ input UBMDMDBGRST;
+ input UBMDMDBGUPDATE;
+ input [3:0] UBMDMREGEN;
+ input UBMDMSHIFT;
+ input UBMDMSYSRST;
+ input UBMDMTCK;
+ input UBMDMTDI;
+endmodule
+
+module IBUFDS_GTE3 (...);
+ parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
+ parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00;
+ parameter [1:0] REFCLK_ICNTL_RX = 2'b00;
+ output O;
+ output ODIV2;
+ input CEB;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+endmodule
+
+module IBUFDS_GTE4 (...);
+ parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
+ parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00;
+ parameter [1:0] REFCLK_ICNTL_RX = 2'b00;
+ output O;
+ output ODIV2;
+ input CEB;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+endmodule
+
+module ILKN (...);
+ parameter BYPASS = "FALSE";
+ parameter [1:0] CTL_RX_BURSTMAX = 2'h3;
+ parameter [1:0] CTL_RX_CHAN_EXT = 2'h0;
+ parameter [3:0] CTL_RX_LAST_LANE = 4'hB;
+ parameter [15:0] CTL_RX_MFRAMELEN_MINUS1 = 16'h07FF;
+ parameter CTL_RX_PACKET_MODE = "TRUE";
+ parameter [2:0] CTL_RX_RETRANS_MULT = 3'h0;
+ parameter [3:0] CTL_RX_RETRANS_RETRY = 4'h2;
+ parameter [15:0] CTL_RX_RETRANS_TIMER1 = 16'h0000;
+ parameter [15:0] CTL_RX_RETRANS_TIMER2 = 16'h0008;
+ parameter [11:0] CTL_RX_RETRANS_WDOG = 12'h000;
+ parameter [7:0] CTL_RX_RETRANS_WRAP_TIMER = 8'h00;
+ parameter CTL_TEST_MODE_PIN_CHAR = "FALSE";
+ parameter [1:0] CTL_TX_BURSTMAX = 2'h3;
+ parameter [2:0] CTL_TX_BURSTSHORT = 3'h1;
+ parameter [1:0] CTL_TX_CHAN_EXT = 2'h0;
+ parameter CTL_TX_DISABLE_SKIPWORD = "TRUE";
+ parameter [6:0] CTL_TX_FC_CALLEN = 7'h00;
+ parameter [3:0] CTL_TX_LAST_LANE = 4'hB;
+ parameter [15:0] CTL_TX_MFRAMELEN_MINUS1 = 16'h07FF;
+ parameter [13:0] CTL_TX_RETRANS_DEPTH = 14'h0800;
+ parameter [2:0] CTL_TX_RETRANS_MULT = 3'h0;
+ parameter [1:0] CTL_TX_RETRANS_RAM_BANKS = 2'h3;
+ parameter MODE = "TRUE";
+ parameter SIM_VERSION = "2.0";
+ parameter TEST_MODE_PIN_CHAR = "FALSE";
+ output [15:0] DRP_DO;
+ output DRP_RDY;
+ output [65:0] RX_BYPASS_DATAOUT00;
+ output [65:0] RX_BYPASS_DATAOUT01;
+ output [65:0] RX_BYPASS_DATAOUT02;
+ output [65:0] RX_BYPASS_DATAOUT03;
+ output [65:0] RX_BYPASS_DATAOUT04;
+ output [65:0] RX_BYPASS_DATAOUT05;
+ output [65:0] RX_BYPASS_DATAOUT06;
+ output [65:0] RX_BYPASS_DATAOUT07;
+ output [65:0] RX_BYPASS_DATAOUT08;
+ output [65:0] RX_BYPASS_DATAOUT09;
+ output [65:0] RX_BYPASS_DATAOUT10;
+ output [65:0] RX_BYPASS_DATAOUT11;
+ output [11:0] RX_BYPASS_ENAOUT;
+ output [11:0] RX_BYPASS_IS_AVAILOUT;
+ output [11:0] RX_BYPASS_IS_BADLYFRAMEDOUT;
+ output [11:0] RX_BYPASS_IS_OVERFLOWOUT;
+ output [11:0] RX_BYPASS_IS_SYNCEDOUT;
+ output [11:0] RX_BYPASS_IS_SYNCWORDOUT;
+ output [10:0] RX_CHANOUT0;
+ output [10:0] RX_CHANOUT1;
+ output [10:0] RX_CHANOUT2;
+ output [10:0] RX_CHANOUT3;
+ output [127:0] RX_DATAOUT0;
+ output [127:0] RX_DATAOUT1;
+ output [127:0] RX_DATAOUT2;
+ output [127:0] RX_DATAOUT3;
+ output RX_ENAOUT0;
+ output RX_ENAOUT1;
+ output RX_ENAOUT2;
+ output RX_ENAOUT3;
+ output RX_EOPOUT0;
+ output RX_EOPOUT1;
+ output RX_EOPOUT2;
+ output RX_EOPOUT3;
+ output RX_ERROUT0;
+ output RX_ERROUT1;
+ output RX_ERROUT2;
+ output RX_ERROUT3;
+ output [3:0] RX_MTYOUT0;
+ output [3:0] RX_MTYOUT1;
+ output [3:0] RX_MTYOUT2;
+ output [3:0] RX_MTYOUT3;
+ output RX_OVFOUT;
+ output RX_SOPOUT0;
+ output RX_SOPOUT1;
+ output RX_SOPOUT2;
+ output RX_SOPOUT3;
+ output STAT_RX_ALIGNED;
+ output STAT_RX_ALIGNED_ERR;
+ output [11:0] STAT_RX_BAD_TYPE_ERR;
+ output STAT_RX_BURSTMAX_ERR;
+ output STAT_RX_BURST_ERR;
+ output STAT_RX_CRC24_ERR;
+ output [11:0] STAT_RX_CRC32_ERR;
+ output [11:0] STAT_RX_CRC32_VALID;
+ output [11:0] STAT_RX_DESCRAM_ERR;
+ output [11:0] STAT_RX_DIAGWORD_INTFSTAT;
+ output [11:0] STAT_RX_DIAGWORD_LANESTAT;
+ output [255:0] STAT_RX_FC_STAT;
+ output [11:0] STAT_RX_FRAMING_ERR;
+ output STAT_RX_MEOP_ERR;
+ output [11:0] STAT_RX_MF_ERR;
+ output [11:0] STAT_RX_MF_LEN_ERR;
+ output [11:0] STAT_RX_MF_REPEAT_ERR;
+ output STAT_RX_MISALIGNED;
+ output STAT_RX_MSOP_ERR;
+ output [7:0] STAT_RX_MUBITS;
+ output STAT_RX_MUBITS_UPDATED;
+ output STAT_RX_OVERFLOW_ERR;
+ output STAT_RX_RETRANS_CRC24_ERR;
+ output STAT_RX_RETRANS_DISC;
+ output [15:0] STAT_RX_RETRANS_LATENCY;
+ output STAT_RX_RETRANS_REQ;
+ output STAT_RX_RETRANS_RETRY_ERR;
+ output [7:0] STAT_RX_RETRANS_SEQ;
+ output STAT_RX_RETRANS_SEQ_UPDATED;
+ output [2:0] STAT_RX_RETRANS_STATE;
+ output [4:0] STAT_RX_RETRANS_SUBSEQ;
+ output STAT_RX_RETRANS_WDOG_ERR;
+ output STAT_RX_RETRANS_WRAP_ERR;
+ output [11:0] STAT_RX_SYNCED;
+ output [11:0] STAT_RX_SYNCED_ERR;
+ output [11:0] STAT_RX_WORD_SYNC;
+ output STAT_TX_BURST_ERR;
+ output STAT_TX_ERRINJ_BITERR_DONE;
+ output STAT_TX_OVERFLOW_ERR;
+ output STAT_TX_RETRANS_BURST_ERR;
+ output STAT_TX_RETRANS_BUSY;
+ output STAT_TX_RETRANS_RAM_PERROUT;
+ output [8:0] STAT_TX_RETRANS_RAM_RADDR;
+ output STAT_TX_RETRANS_RAM_RD_B0;
+ output STAT_TX_RETRANS_RAM_RD_B1;
+ output STAT_TX_RETRANS_RAM_RD_B2;
+ output STAT_TX_RETRANS_RAM_RD_B3;
+ output [1:0] STAT_TX_RETRANS_RAM_RSEL;
+ output [8:0] STAT_TX_RETRANS_RAM_WADDR;
+ output [643:0] STAT_TX_RETRANS_RAM_WDATA;
+ output STAT_TX_RETRANS_RAM_WE_B0;
+ output STAT_TX_RETRANS_RAM_WE_B1;
+ output STAT_TX_RETRANS_RAM_WE_B2;
+ output STAT_TX_RETRANS_RAM_WE_B3;
+ output STAT_TX_UNDERFLOW_ERR;
+ output TX_OVFOUT;
+ output TX_RDYOUT;
+ output [63:0] TX_SERDES_DATA00;
+ output [63:0] TX_SERDES_DATA01;
+ output [63:0] TX_SERDES_DATA02;
+ output [63:0] TX_SERDES_DATA03;
+ output [63:0] TX_SERDES_DATA04;
+ output [63:0] TX_SERDES_DATA05;
+ output [63:0] TX_SERDES_DATA06;
+ output [63:0] TX_SERDES_DATA07;
+ output [63:0] TX_SERDES_DATA08;
+ output [63:0] TX_SERDES_DATA09;
+ output [63:0] TX_SERDES_DATA10;
+ output [63:0] TX_SERDES_DATA11;
+ input CORE_CLK;
+ input CTL_RX_FORCE_RESYNC;
+ input CTL_RX_RETRANS_ACK;
+ input CTL_RX_RETRANS_ENABLE;
+ input CTL_RX_RETRANS_ERRIN;
+ input CTL_RX_RETRANS_FORCE_REQ;
+ input CTL_RX_RETRANS_RESET;
+ input CTL_RX_RETRANS_RESET_MODE;
+ input CTL_TX_DIAGWORD_INTFSTAT;
+ input [11:0] CTL_TX_DIAGWORD_LANESTAT;
+ input CTL_TX_ENABLE;
+ input CTL_TX_ERRINJ_BITERR_GO;
+ input [3:0] CTL_TX_ERRINJ_BITERR_LANE;
+ input [255:0] CTL_TX_FC_STAT;
+ input [7:0] CTL_TX_MUBITS;
+ input CTL_TX_RETRANS_ENABLE;
+ input CTL_TX_RETRANS_RAM_PERRIN;
+ input [643:0] CTL_TX_RETRANS_RAM_RDATA;
+ input CTL_TX_RETRANS_REQ;
+ input CTL_TX_RETRANS_REQ_VALID;
+ input [11:0] CTL_TX_RLIM_DELTA;
+ input CTL_TX_RLIM_ENABLE;
+ input [7:0] CTL_TX_RLIM_INTV;
+ input [11:0] CTL_TX_RLIM_MAX;
+ input [9:0] DRP_ADDR;
+ input DRP_CLK;
+ input [15:0] DRP_DI;
+ input DRP_EN;
+ input DRP_WE;
+ input LBUS_CLK;
+ input RX_BYPASS_FORCE_REALIGNIN;
+ input RX_BYPASS_RDIN;
+ input RX_RESET;
+ input [11:0] RX_SERDES_CLK;
+ input [63:0] RX_SERDES_DATA00;
+ input [63:0] RX_SERDES_DATA01;
+ input [63:0] RX_SERDES_DATA02;
+ input [63:0] RX_SERDES_DATA03;
+ input [63:0] RX_SERDES_DATA04;
+ input [63:0] RX_SERDES_DATA05;
+ input [63:0] RX_SERDES_DATA06;
+ input [63:0] RX_SERDES_DATA07;
+ input [63:0] RX_SERDES_DATA08;
+ input [63:0] RX_SERDES_DATA09;
+ input [63:0] RX_SERDES_DATA10;
+ input [63:0] RX_SERDES_DATA11;
+ input [11:0] RX_SERDES_RESET;
+ input TX_BCTLIN0;
+ input TX_BCTLIN1;
+ input TX_BCTLIN2;
+ input TX_BCTLIN3;
+ input [11:0] TX_BYPASS_CTRLIN;
+ input [63:0] TX_BYPASS_DATAIN00;
+ input [63:0] TX_BYPASS_DATAIN01;
+ input [63:0] TX_BYPASS_DATAIN02;
+ input [63:0] TX_BYPASS_DATAIN03;
+ input [63:0] TX_BYPASS_DATAIN04;
+ input [63:0] TX_BYPASS_DATAIN05;
+ input [63:0] TX_BYPASS_DATAIN06;
+ input [63:0] TX_BYPASS_DATAIN07;
+ input [63:0] TX_BYPASS_DATAIN08;
+ input [63:0] TX_BYPASS_DATAIN09;
+ input [63:0] TX_BYPASS_DATAIN10;
+ input [63:0] TX_BYPASS_DATAIN11;
+ input TX_BYPASS_ENAIN;
+ input [7:0] TX_BYPASS_GEARBOX_SEQIN;
+ input [3:0] TX_BYPASS_MFRAMER_STATEIN;
+ input [10:0] TX_CHANIN0;
+ input [10:0] TX_CHANIN1;
+ input [10:0] TX_CHANIN2;
+ input [10:0] TX_CHANIN3;
+ input [127:0] TX_DATAIN0;
+ input [127:0] TX_DATAIN1;
+ input [127:0] TX_DATAIN2;
+ input [127:0] TX_DATAIN3;
+ input TX_ENAIN0;
+ input TX_ENAIN1;
+ input TX_ENAIN2;
+ input TX_ENAIN3;
+ input TX_EOPIN0;
+ input TX_EOPIN1;
+ input TX_EOPIN2;
+ input TX_EOPIN3;
+ input TX_ERRIN0;
+ input TX_ERRIN1;
+ input TX_ERRIN2;
+ input TX_ERRIN3;
+ input [3:0] TX_MTYIN0;
+ input [3:0] TX_MTYIN1;
+ input [3:0] TX_MTYIN2;
+ input [3:0] TX_MTYIN3;
+ input TX_RESET;
+ input TX_SERDES_REFCLK;
+ input TX_SERDES_REFCLK_RESET;
+ input TX_SOPIN0;
+ input TX_SOPIN1;
+ input TX_SOPIN2;
+ input TX_SOPIN3;
+endmodule
+
+module ILKNE4 (...);
+ parameter BYPASS = "FALSE";
+ parameter [1:0] CTL_RX_BURSTMAX = 2'h3;
+ parameter [1:0] CTL_RX_CHAN_EXT = 2'h0;
+ parameter [3:0] CTL_RX_LAST_LANE = 4'hB;
+ parameter [15:0] CTL_RX_MFRAMELEN_MINUS1 = 16'h07FF;
+ parameter CTL_RX_PACKET_MODE = "FALSE";
+ parameter [2:0] CTL_RX_RETRANS_MULT = 3'h0;
+ parameter [3:0] CTL_RX_RETRANS_RETRY = 4'h2;
+ parameter [15:0] CTL_RX_RETRANS_TIMER1 = 16'h0009;
+ parameter [15:0] CTL_RX_RETRANS_TIMER2 = 16'h0000;
+ parameter [11:0] CTL_RX_RETRANS_WDOG = 12'h000;
+ parameter [7:0] CTL_RX_RETRANS_WRAP_TIMER = 8'h00;
+ parameter CTL_TEST_MODE_PIN_CHAR = "FALSE";
+ parameter [1:0] CTL_TX_BURSTMAX = 2'h3;
+ parameter [2:0] CTL_TX_BURSTSHORT = 3'h1;
+ parameter [1:0] CTL_TX_CHAN_EXT = 2'h0;
+ parameter CTL_TX_DISABLE_SKIPWORD = "FALSE";
+ parameter [3:0] CTL_TX_FC_CALLEN = 4'hF;
+ parameter [3:0] CTL_TX_LAST_LANE = 4'hB;
+ parameter [15:0] CTL_TX_MFRAMELEN_MINUS1 = 16'h07FF;
+ parameter [13:0] CTL_TX_RETRANS_DEPTH = 14'h0800;
+ parameter [2:0] CTL_TX_RETRANS_MULT = 3'h0;
+ parameter [1:0] CTL_TX_RETRANS_RAM_BANKS = 2'h3;
+ parameter MODE = "TRUE";
+ parameter SIM_DEVICE = "ULTRASCALE_PLUS";
+ parameter TEST_MODE_PIN_CHAR = "FALSE";
+ output [15:0] DRP_DO;
+ output DRP_RDY;
+ output [65:0] RX_BYPASS_DATAOUT00;
+ output [65:0] RX_BYPASS_DATAOUT01;
+ output [65:0] RX_BYPASS_DATAOUT02;
+ output [65:0] RX_BYPASS_DATAOUT03;
+ output [65:0] RX_BYPASS_DATAOUT04;
+ output [65:0] RX_BYPASS_DATAOUT05;
+ output [65:0] RX_BYPASS_DATAOUT06;
+ output [65:0] RX_BYPASS_DATAOUT07;
+ output [65:0] RX_BYPASS_DATAOUT08;
+ output [65:0] RX_BYPASS_DATAOUT09;
+ output [65:0] RX_BYPASS_DATAOUT10;
+ output [65:0] RX_BYPASS_DATAOUT11;
+ output [11:0] RX_BYPASS_ENAOUT;
+ output [11:0] RX_BYPASS_IS_AVAILOUT;
+ output [11:0] RX_BYPASS_IS_BADLYFRAMEDOUT;
+ output [11:0] RX_BYPASS_IS_OVERFLOWOUT;
+ output [11:0] RX_BYPASS_IS_SYNCEDOUT;
+ output [11:0] RX_BYPASS_IS_SYNCWORDOUT;
+ output [10:0] RX_CHANOUT0;
+ output [10:0] RX_CHANOUT1;
+ output [10:0] RX_CHANOUT2;
+ output [10:0] RX_CHANOUT3;
+ output [127:0] RX_DATAOUT0;
+ output [127:0] RX_DATAOUT1;
+ output [127:0] RX_DATAOUT2;
+ output [127:0] RX_DATAOUT3;
+ output RX_ENAOUT0;
+ output RX_ENAOUT1;
+ output RX_ENAOUT2;
+ output RX_ENAOUT3;
+ output RX_EOPOUT0;
+ output RX_EOPOUT1;
+ output RX_EOPOUT2;
+ output RX_EOPOUT3;
+ output RX_ERROUT0;
+ output RX_ERROUT1;
+ output RX_ERROUT2;
+ output RX_ERROUT3;
+ output [3:0] RX_MTYOUT0;
+ output [3:0] RX_MTYOUT1;
+ output [3:0] RX_MTYOUT2;
+ output [3:0] RX_MTYOUT3;
+ output RX_OVFOUT;
+ output RX_SOPOUT0;
+ output RX_SOPOUT1;
+ output RX_SOPOUT2;
+ output RX_SOPOUT3;
+ output STAT_RX_ALIGNED;
+ output STAT_RX_ALIGNED_ERR;
+ output [11:0] STAT_RX_BAD_TYPE_ERR;
+ output STAT_RX_BURSTMAX_ERR;
+ output STAT_RX_BURST_ERR;
+ output STAT_RX_CRC24_ERR;
+ output [11:0] STAT_RX_CRC32_ERR;
+ output [11:0] STAT_RX_CRC32_VALID;
+ output [11:0] STAT_RX_DESCRAM_ERR;
+ output [11:0] STAT_RX_DIAGWORD_INTFSTAT;
+ output [11:0] STAT_RX_DIAGWORD_LANESTAT;
+ output [255:0] STAT_RX_FC_STAT;
+ output [11:0] STAT_RX_FRAMING_ERR;
+ output STAT_RX_MEOP_ERR;
+ output [11:0] STAT_RX_MF_ERR;
+ output [11:0] STAT_RX_MF_LEN_ERR;
+ output [11:0] STAT_RX_MF_REPEAT_ERR;
+ output STAT_RX_MISALIGNED;
+ output STAT_RX_MSOP_ERR;
+ output [7:0] STAT_RX_MUBITS;
+ output STAT_RX_MUBITS_UPDATED;
+ output STAT_RX_OVERFLOW_ERR;
+ output STAT_RX_RETRANS_CRC24_ERR;
+ output STAT_RX_RETRANS_DISC;
+ output [15:0] STAT_RX_RETRANS_LATENCY;
+ output STAT_RX_RETRANS_REQ;
+ output STAT_RX_RETRANS_RETRY_ERR;
+ output [7:0] STAT_RX_RETRANS_SEQ;
+ output STAT_RX_RETRANS_SEQ_UPDATED;
+ output [2:0] STAT_RX_RETRANS_STATE;
+ output [4:0] STAT_RX_RETRANS_SUBSEQ;
+ output STAT_RX_RETRANS_WDOG_ERR;
+ output STAT_RX_RETRANS_WRAP_ERR;
+ output [11:0] STAT_RX_SYNCED;
+ output [11:0] STAT_RX_SYNCED_ERR;
+ output [11:0] STAT_RX_WORD_SYNC;
+ output STAT_TX_BURST_ERR;
+ output STAT_TX_ERRINJ_BITERR_DONE;
+ output STAT_TX_OVERFLOW_ERR;
+ output STAT_TX_RETRANS_BURST_ERR;
+ output STAT_TX_RETRANS_BUSY;
+ output STAT_TX_RETRANS_RAM_PERROUT;
+ output [8:0] STAT_TX_RETRANS_RAM_RADDR;
+ output STAT_TX_RETRANS_RAM_RD_B0;
+ output STAT_TX_RETRANS_RAM_RD_B1;
+ output STAT_TX_RETRANS_RAM_RD_B2;
+ output STAT_TX_RETRANS_RAM_RD_B3;
+ output [1:0] STAT_TX_RETRANS_RAM_RSEL;
+ output [8:0] STAT_TX_RETRANS_RAM_WADDR;
+ output [643:0] STAT_TX_RETRANS_RAM_WDATA;
+ output STAT_TX_RETRANS_RAM_WE_B0;
+ output STAT_TX_RETRANS_RAM_WE_B1;
+ output STAT_TX_RETRANS_RAM_WE_B2;
+ output STAT_TX_RETRANS_RAM_WE_B3;
+ output STAT_TX_UNDERFLOW_ERR;
+ output TX_OVFOUT;
+ output TX_RDYOUT;
+ output [63:0] TX_SERDES_DATA00;
+ output [63:0] TX_SERDES_DATA01;
+ output [63:0] TX_SERDES_DATA02;
+ output [63:0] TX_SERDES_DATA03;
+ output [63:0] TX_SERDES_DATA04;
+ output [63:0] TX_SERDES_DATA05;
+ output [63:0] TX_SERDES_DATA06;
+ output [63:0] TX_SERDES_DATA07;
+ output [63:0] TX_SERDES_DATA08;
+ output [63:0] TX_SERDES_DATA09;
+ output [63:0] TX_SERDES_DATA10;
+ output [63:0] TX_SERDES_DATA11;
+ input CORE_CLK;
+ input CTL_RX_FORCE_RESYNC;
+ input CTL_RX_RETRANS_ACK;
+ input CTL_RX_RETRANS_ENABLE;
+ input CTL_RX_RETRANS_ERRIN;
+ input CTL_RX_RETRANS_FORCE_REQ;
+ input CTL_RX_RETRANS_RESET;
+ input CTL_RX_RETRANS_RESET_MODE;
+ input CTL_TX_DIAGWORD_INTFSTAT;
+ input [11:0] CTL_TX_DIAGWORD_LANESTAT;
+ input CTL_TX_ENABLE;
+ input CTL_TX_ERRINJ_BITERR_GO;
+ input [3:0] CTL_TX_ERRINJ_BITERR_LANE;
+ input [255:0] CTL_TX_FC_STAT;
+ input [7:0] CTL_TX_MUBITS;
+ input CTL_TX_RETRANS_ENABLE;
+ input CTL_TX_RETRANS_RAM_PERRIN;
+ input [643:0] CTL_TX_RETRANS_RAM_RDATA;
+ input CTL_TX_RETRANS_REQ;
+ input CTL_TX_RETRANS_REQ_VALID;
+ input [11:0] CTL_TX_RLIM_DELTA;
+ input CTL_TX_RLIM_ENABLE;
+ input [7:0] CTL_TX_RLIM_INTV;
+ input [11:0] CTL_TX_RLIM_MAX;
+ input [9:0] DRP_ADDR;
+ input DRP_CLK;
+ input [15:0] DRP_DI;
+ input DRP_EN;
+ input DRP_WE;
+ input LBUS_CLK;
+ input RX_BYPASS_FORCE_REALIGNIN;
+ input RX_BYPASS_RDIN;
+ input RX_RESET;
+ input [11:0] RX_SERDES_CLK;
+ input [63:0] RX_SERDES_DATA00;
+ input [63:0] RX_SERDES_DATA01;
+ input [63:0] RX_SERDES_DATA02;
+ input [63:0] RX_SERDES_DATA03;
+ input [63:0] RX_SERDES_DATA04;
+ input [63:0] RX_SERDES_DATA05;
+ input [63:0] RX_SERDES_DATA06;
+ input [63:0] RX_SERDES_DATA07;
+ input [63:0] RX_SERDES_DATA08;
+ input [63:0] RX_SERDES_DATA09;
+ input [63:0] RX_SERDES_DATA10;
+ input [63:0] RX_SERDES_DATA11;
+ input [11:0] RX_SERDES_RESET;
+ input TX_BCTLIN0;
+ input TX_BCTLIN1;
+ input TX_BCTLIN2;
+ input TX_BCTLIN3;
+ input [11:0] TX_BYPASS_CTRLIN;
+ input [63:0] TX_BYPASS_DATAIN00;
+ input [63:0] TX_BYPASS_DATAIN01;
+ input [63:0] TX_BYPASS_DATAIN02;
+ input [63:0] TX_BYPASS_DATAIN03;
+ input [63:0] TX_BYPASS_DATAIN04;
+ input [63:0] TX_BYPASS_DATAIN05;
+ input [63:0] TX_BYPASS_DATAIN06;
+ input [63:0] TX_BYPASS_DATAIN07;
+ input [63:0] TX_BYPASS_DATAIN08;
+ input [63:0] TX_BYPASS_DATAIN09;
+ input [63:0] TX_BYPASS_DATAIN10;
+ input [63:0] TX_BYPASS_DATAIN11;
+ input TX_BYPASS_ENAIN;
+ input [7:0] TX_BYPASS_GEARBOX_SEQIN;
+ input [3:0] TX_BYPASS_MFRAMER_STATEIN;
+ input [10:0] TX_CHANIN0;
+ input [10:0] TX_CHANIN1;
+ input [10:0] TX_CHANIN2;
+ input [10:0] TX_CHANIN3;
+ input [127:0] TX_DATAIN0;
+ input [127:0] TX_DATAIN1;
+ input [127:0] TX_DATAIN2;
+ input [127:0] TX_DATAIN3;
+ input TX_ENAIN0;
+ input TX_ENAIN1;
+ input TX_ENAIN2;
+ input TX_ENAIN3;
+ input TX_EOPIN0;
+ input TX_EOPIN1;
+ input TX_EOPIN2;
+ input TX_EOPIN3;
+ input TX_ERRIN0;
+ input TX_ERRIN1;
+ input TX_ERRIN2;
+ input TX_ERRIN3;
+ input [3:0] TX_MTYIN0;
+ input [3:0] TX_MTYIN1;
+ input [3:0] TX_MTYIN2;
+ input [3:0] TX_MTYIN3;
+ input TX_RESET;
+ input TX_SERDES_REFCLK;
+ input TX_SERDES_REFCLK_RESET;
+ input TX_SOPIN0;
+ input TX_SOPIN1;
+ input TX_SOPIN2;
+ input TX_SOPIN3;
+endmodule
+
+module OBUFDS_GTE3 (...);
+ parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
+ parameter [4:0] REFCLK_ICNTL_TX = 5'b00000;
+ (* iopad_external_pin *)
+ output O;
+ (* iopad_external_pin *)
+ output OB;
+ input CEB;
+ input I;
+endmodule
+
+module OBUFDS_GTE3_ADV (...);
+ parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
+ parameter [4:0] REFCLK_ICNTL_TX = 5'b00000;
+ (* iopad_external_pin *)
+ output O;
+ (* iopad_external_pin *)
+ output OB;
+ input CEB;
+ input [3:0] I;
+ input [1:0] RXRECCLK_SEL;
+endmodule
+
+module OBUFDS_GTE4 (...);
+ parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
+ parameter [4:0] REFCLK_ICNTL_TX = 5'b00000;
+ (* iopad_external_pin *)
+ output O;
+ (* iopad_external_pin *)
+ output OB;
+ input CEB;
+ input I;
+endmodule
+
+module OBUFDS_GTE4_ADV (...);
+ parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
+ parameter [4:0] REFCLK_ICNTL_TX = 5'b00000;
+ (* iopad_external_pin *)
+ output O;
+ (* iopad_external_pin *)
+ output OB;
+ input CEB;
+ input [3:0] I;
+ input [1:0] RXRECCLK_SEL;
+endmodule
+
+module PCIE40E4 (...);
+ parameter ARI_CAP_ENABLE = "FALSE";
+ parameter AUTO_FLR_RESPONSE = "FALSE";
+ parameter [1:0] AXISTEN_IF_CC_ALIGNMENT_MODE = 2'h0;
+ parameter [23:0] AXISTEN_IF_COMPL_TIMEOUT_REG0 = 24'hBEBC20;
+ parameter [27:0] AXISTEN_IF_COMPL_TIMEOUT_REG1 = 28'h2FAF080;
+ parameter [1:0] AXISTEN_IF_CQ_ALIGNMENT_MODE = 2'h0;
+ parameter AXISTEN_IF_CQ_EN_POISONED_MEM_WR = "FALSE";
+ parameter AXISTEN_IF_ENABLE_256_TAGS = "FALSE";
+ parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE";
+ parameter AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = "FALSE";
+ parameter AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK = "TRUE";
+ parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000;
+ parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE";
+ parameter AXISTEN_IF_EXT_512 = "FALSE";
+ parameter AXISTEN_IF_EXT_512_CC_STRADDLE = "FALSE";
+ parameter AXISTEN_IF_EXT_512_CQ_STRADDLE = "FALSE";
+ parameter AXISTEN_IF_EXT_512_RC_STRADDLE = "FALSE";
+ parameter AXISTEN_IF_EXT_512_RQ_STRADDLE = "FALSE";
+ parameter AXISTEN_IF_LEGACY_MODE_ENABLE = "FALSE";
+ parameter AXISTEN_IF_MSIX_FROM_RAM_PIPELINE = "FALSE";
+ parameter AXISTEN_IF_MSIX_RX_PARITY_EN = "TRUE";
+ parameter AXISTEN_IF_MSIX_TO_RAM_PIPELINE = "FALSE";
+ parameter [1:0] AXISTEN_IF_RC_ALIGNMENT_MODE = 2'h0;
+ parameter AXISTEN_IF_RC_STRADDLE = "FALSE";
+ parameter [1:0] AXISTEN_IF_RQ_ALIGNMENT_MODE = 2'h0;
+ parameter AXISTEN_IF_RX_PARITY_EN = "TRUE";
+ parameter AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT = "FALSE";
+ parameter AXISTEN_IF_TX_PARITY_EN = "TRUE";
+ parameter [1:0] AXISTEN_IF_WIDTH = 2'h2;
+ parameter CFG_BYPASS_MODE_ENABLE = "FALSE";
+ parameter CRM_CORE_CLK_FREQ_500 = "TRUE";
+ parameter [1:0] CRM_USER_CLK_FREQ = 2'h2;
+ parameter [15:0] DEBUG_AXI4ST_SPARE = 16'h0000;
+ parameter [7:0] DEBUG_AXIST_DISABLE_FEATURE_BIT = 8'h00;
+ parameter [3:0] DEBUG_CAR_SPARE = 4'h0;
+ parameter [15:0] DEBUG_CFG_SPARE = 16'h0000;
+ parameter [15:0] DEBUG_LL_SPARE = 16'h0000;
+ parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR = "FALSE";
+ parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR = "FALSE";
+ parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR = "FALSE";
+ parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL = "FALSE";
+ parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW = "FALSE";
+ parameter DEBUG_PL_DISABLE_SCRAMBLING = "FALSE";
+ parameter DEBUG_PL_SIM_RESET_LFSR = "FALSE";
+ parameter [15:0] DEBUG_PL_SPARE = 16'h0000;
+ parameter DEBUG_TL_DISABLE_FC_TIMEOUT = "FALSE";
+ parameter DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS = "FALSE";
+ parameter [15:0] DEBUG_TL_SPARE = 16'h0000;
+ parameter [7:0] DNSTREAM_LINK_NUM = 8'h00;
+ parameter DSN_CAP_ENABLE = "FALSE";
+ parameter EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE";
+ parameter HEADER_TYPE_OVERRIDE = "FALSE";
+ parameter IS_SWITCH_PORT = "FALSE";
+ parameter LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE";
+ parameter [8:0] LL_ACK_TIMEOUT = 9'h000;
+ parameter LL_ACK_TIMEOUT_EN = "FALSE";
+ parameter integer LL_ACK_TIMEOUT_FUNC = 0;
+ parameter LL_DISABLE_SCHED_TX_NAK = "FALSE";
+ parameter LL_REPLAY_FROM_RAM_PIPELINE = "FALSE";
+ parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000;
+ parameter LL_REPLAY_TIMEOUT_EN = "FALSE";
+ parameter integer LL_REPLAY_TIMEOUT_FUNC = 0;
+ parameter LL_REPLAY_TO_RAM_PIPELINE = "FALSE";
+ parameter LL_RX_TLP_PARITY_GEN = "TRUE";
+ parameter LL_TX_TLP_PARITY_CHK = "TRUE";
+ parameter [15:0] LL_USER_SPARE = 16'h0000;
+ parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h250;
+ parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE";
+ parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE";
+ parameter [11:0] MCAP_CAP_NEXTPTR = 12'h000;
+ parameter MCAP_CONFIGURE_OVERRIDE = "FALSE";
+ parameter MCAP_ENABLE = "FALSE";
+ parameter MCAP_EOS_DESIGN_SWITCH = "FALSE";
+ parameter [31:0] MCAP_FPGA_BITSTREAM_VERSION = 32'h00000000;
+ parameter MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "FALSE";
+ parameter MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "FALSE";
+ parameter MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE";
+ parameter MCAP_INTERRUPT_ON_MCAP_EOS = "FALSE";
+ parameter MCAP_INTERRUPT_ON_MCAP_ERROR = "FALSE";
+ parameter [15:0] MCAP_VSEC_ID = 16'h0000;
+ parameter [11:0] MCAP_VSEC_LEN = 12'h02C;
+ parameter [3:0] MCAP_VSEC_REV = 4'h0;
+ parameter PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE = "FALSE";
+ parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000;
+ parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000;
+ parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00;
+ parameter [3:0] PF0_ARI_CAP_VER = 4'h1;
+ parameter [5:0] PF0_BAR0_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF0_BAR0_CONTROL = 3'h4;
+ parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00;
+ parameter [2:0] PF0_BAR1_CONTROL = 3'h0;
+ parameter [5:0] PF0_BAR2_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF0_BAR2_CONTROL = 3'h4;
+ parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF0_BAR3_CONTROL = 3'h0;
+ parameter [5:0] PF0_BAR4_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF0_BAR4_CONTROL = 3'h4;
+ parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF0_BAR5_CONTROL = 3'h0;
+ parameter [7:0] PF0_CAPABILITY_POINTER = 8'h80;
+ parameter [23:0] PF0_CLASS_CODE = 24'h000000;
+ parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE";
+ parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE";
+ parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE";
+ parameter PF0_DEV_CAP2_ARI_FORWARD_ENABLE = "FALSE";
+ parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE";
+ parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE";
+ parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0;
+ parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE";
+ parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0;
+ parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0;
+ parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE";
+ parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE";
+ parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
+ parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C;
+ parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
+ parameter PF0_EXPANSION_ROM_ENABLE = "FALSE";
+ parameter [2:0] PF0_INTERRUPT_PIN = 3'h1;
+ parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0;
+ parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7;
+ parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7;
+ parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7;
+ parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4 = 7;
+ parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7;
+ parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7;
+ parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7;
+ parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4 = 7;
+ parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7;
+ parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7;
+ parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7;
+ parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4 = 7;
+ parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7;
+ parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7;
+ parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7;
+ parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4 = 7;
+ parameter [0:0] PF0_LINK_CONTROL_RCB = 1'h0;
+ parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE";
+ parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000;
+ parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000;
+ parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000;
+ parameter [3:0] PF0_LTR_CAP_VER = 4'h1;
+ parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00;
+ parameter integer PF0_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer PF0_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter [5:0] PF0_MSIX_VECTOR_COUNT = 6'h04;
+ parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00;
+ parameter PF0_MSI_CAP_PERVECMASKCAP = "FALSE";
+ parameter [7:0] PF0_PCIE_CAP_NEXTPTR = 8'h00;
+ parameter [7:0] PF0_PM_CAP_ID = 8'h01;
+ parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00;
+ parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE";
+ parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE";
+ parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE";
+ parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE";
+ parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3;
+ parameter PF0_PM_CSR_NOSOFTRESET = "TRUE";
+ parameter [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR = 12'h000;
+ parameter PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE";
+ parameter [5:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4;
+ parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
+ parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0;
+ parameter [5:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4;
+ parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0;
+ parameter [5:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4;
+ parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0;
+ parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000;
+ parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000;
+ parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000;
+ parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1;
+ parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000;
+ parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000;
+ parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
+ parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000;
+ parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
+ parameter PF0_TPHR_CAP_ENABLE = "FALSE";
+ parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE";
+ parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0;
+ parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
+ parameter [3:0] PF0_TPHR_CAP_VER = 4'h1;
+ parameter PF0_VC_CAP_ENABLE = "FALSE";
+ parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000;
+ parameter [3:0] PF0_VC_CAP_VER = 4'h1;
+ parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000;
+ parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000;
+ parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00;
+ parameter [5:0] PF1_BAR0_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF1_BAR0_CONTROL = 3'h4;
+ parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00;
+ parameter [2:0] PF1_BAR1_CONTROL = 3'h0;
+ parameter [5:0] PF1_BAR2_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF1_BAR2_CONTROL = 3'h4;
+ parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF1_BAR3_CONTROL = 3'h0;
+ parameter [5:0] PF1_BAR4_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF1_BAR4_CONTROL = 3'h4;
+ parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF1_BAR5_CONTROL = 3'h0;
+ parameter [7:0] PF1_CAPABILITY_POINTER = 8'h80;
+ parameter [23:0] PF1_CLASS_CODE = 24'h000000;
+ parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
+ parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C;
+ parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
+ parameter PF1_EXPANSION_ROM_ENABLE = "FALSE";
+ parameter [2:0] PF1_INTERRUPT_PIN = 3'h1;
+ parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00;
+ parameter integer PF1_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer PF1_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00;
+ parameter PF1_MSI_CAP_PERVECMASKCAP = "FALSE";
+ parameter [7:0] PF1_PCIE_CAP_NEXTPTR = 8'h00;
+ parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00;
+ parameter PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE";
+ parameter [5:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4;
+ parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
+ parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0;
+ parameter [5:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4;
+ parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0;
+ parameter [5:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4;
+ parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0;
+ parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000;
+ parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000;
+ parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000;
+ parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1;
+ parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000;
+ parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000;
+ parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
+ parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000;
+ parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [11:0] PF2_AER_CAP_NEXTPTR = 12'h000;
+ parameter [11:0] PF2_ARI_CAP_NEXTPTR = 12'h000;
+ parameter [7:0] PF2_ARI_CAP_NEXT_FUNC = 8'h00;
+ parameter [5:0] PF2_BAR0_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF2_BAR0_CONTROL = 3'h4;
+ parameter [4:0] PF2_BAR1_APERTURE_SIZE = 5'h00;
+ parameter [2:0] PF2_BAR1_CONTROL = 3'h0;
+ parameter [5:0] PF2_BAR2_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF2_BAR2_CONTROL = 3'h4;
+ parameter [4:0] PF2_BAR3_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF2_BAR3_CONTROL = 3'h0;
+ parameter [5:0] PF2_BAR4_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF2_BAR4_CONTROL = 3'h4;
+ parameter [4:0] PF2_BAR5_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF2_BAR5_CONTROL = 3'h0;
+ parameter [7:0] PF2_CAPABILITY_POINTER = 8'h80;
+ parameter [23:0] PF2_CLASS_CODE = 24'h000000;
+ parameter [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
+ parameter [11:0] PF2_DSN_CAP_NEXTPTR = 12'h10C;
+ parameter [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
+ parameter PF2_EXPANSION_ROM_ENABLE = "FALSE";
+ parameter [2:0] PF2_INTERRUPT_PIN = 3'h1;
+ parameter [7:0] PF2_MSIX_CAP_NEXTPTR = 8'h00;
+ parameter integer PF2_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] PF2_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer PF2_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] PF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] PF2_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter integer PF2_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] PF2_MSI_CAP_NEXTPTR = 8'h00;
+ parameter PF2_MSI_CAP_PERVECMASKCAP = "FALSE";
+ parameter [7:0] PF2_PCIE_CAP_NEXTPTR = 8'h00;
+ parameter [7:0] PF2_PM_CAP_NEXTPTR = 8'h00;
+ parameter PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE";
+ parameter [5:0] PF2_SRIOV_BAR0_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF2_SRIOV_BAR0_CONTROL = 3'h4;
+ parameter [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
+ parameter [2:0] PF2_SRIOV_BAR1_CONTROL = 3'h0;
+ parameter [5:0] PF2_SRIOV_BAR2_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF2_SRIOV_BAR2_CONTROL = 3'h4;
+ parameter [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF2_SRIOV_BAR3_CONTROL = 3'h0;
+ parameter [5:0] PF2_SRIOV_BAR4_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF2_SRIOV_BAR4_CONTROL = 3'h4;
+ parameter [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF2_SRIOV_BAR5_CONTROL = 3'h0;
+ parameter [15:0] PF2_SRIOV_CAP_INITIAL_VF = 16'h0000;
+ parameter [11:0] PF2_SRIOV_CAP_NEXTPTR = 12'h000;
+ parameter [15:0] PF2_SRIOV_CAP_TOTAL_VF = 16'h0000;
+ parameter [3:0] PF2_SRIOV_CAP_VER = 4'h1;
+ parameter [15:0] PF2_SRIOV_FIRST_VF_OFFSET = 16'h0000;
+ parameter [15:0] PF2_SRIOV_FUNC_DEP_LINK = 16'h0000;
+ parameter [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
+ parameter [15:0] PF2_SRIOV_VF_DEVICE_ID = 16'h0000;
+ parameter [11:0] PF2_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] PF2_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [11:0] PF3_AER_CAP_NEXTPTR = 12'h000;
+ parameter [11:0] PF3_ARI_CAP_NEXTPTR = 12'h000;
+ parameter [7:0] PF3_ARI_CAP_NEXT_FUNC = 8'h00;
+ parameter [5:0] PF3_BAR0_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF3_BAR0_CONTROL = 3'h4;
+ parameter [4:0] PF3_BAR1_APERTURE_SIZE = 5'h00;
+ parameter [2:0] PF3_BAR1_CONTROL = 3'h0;
+ parameter [5:0] PF3_BAR2_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF3_BAR2_CONTROL = 3'h4;
+ parameter [4:0] PF3_BAR3_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF3_BAR3_CONTROL = 3'h0;
+ parameter [5:0] PF3_BAR4_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF3_BAR4_CONTROL = 3'h4;
+ parameter [4:0] PF3_BAR5_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF3_BAR5_CONTROL = 3'h0;
+ parameter [7:0] PF3_CAPABILITY_POINTER = 8'h80;
+ parameter [23:0] PF3_CLASS_CODE = 24'h000000;
+ parameter [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
+ parameter [11:0] PF3_DSN_CAP_NEXTPTR = 12'h10C;
+ parameter [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
+ parameter PF3_EXPANSION_ROM_ENABLE = "FALSE";
+ parameter [2:0] PF3_INTERRUPT_PIN = 3'h1;
+ parameter [7:0] PF3_MSIX_CAP_NEXTPTR = 8'h00;
+ parameter integer PF3_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] PF3_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer PF3_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] PF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] PF3_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter integer PF3_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] PF3_MSI_CAP_NEXTPTR = 8'h00;
+ parameter PF3_MSI_CAP_PERVECMASKCAP = "FALSE";
+ parameter [7:0] PF3_PCIE_CAP_NEXTPTR = 8'h00;
+ parameter [7:0] PF3_PM_CAP_NEXTPTR = 8'h00;
+ parameter PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE";
+ parameter [5:0] PF3_SRIOV_BAR0_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF3_SRIOV_BAR0_CONTROL = 3'h4;
+ parameter [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
+ parameter [2:0] PF3_SRIOV_BAR1_CONTROL = 3'h0;
+ parameter [5:0] PF3_SRIOV_BAR2_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF3_SRIOV_BAR2_CONTROL = 3'h4;
+ parameter [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF3_SRIOV_BAR3_CONTROL = 3'h0;
+ parameter [5:0] PF3_SRIOV_BAR4_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF3_SRIOV_BAR4_CONTROL = 3'h4;
+ parameter [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF3_SRIOV_BAR5_CONTROL = 3'h0;
+ parameter [15:0] PF3_SRIOV_CAP_INITIAL_VF = 16'h0000;
+ parameter [11:0] PF3_SRIOV_CAP_NEXTPTR = 12'h000;
+ parameter [15:0] PF3_SRIOV_CAP_TOTAL_VF = 16'h0000;
+ parameter [3:0] PF3_SRIOV_CAP_VER = 4'h1;
+ parameter [15:0] PF3_SRIOV_FIRST_VF_OFFSET = 16'h0000;
+ parameter [15:0] PF3_SRIOV_FUNC_DEP_LINK = 16'h0000;
+ parameter [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
+ parameter [15:0] PF3_SRIOV_VF_DEVICE_ID = 16'h0000;
+ parameter [11:0] PF3_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] PF3_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter PL_CFG_STATE_ROBUSTNESS_ENABLE = "TRUE";
+ parameter PL_DEEMPH_SOURCE_SELECT = "TRUE";
+ parameter PL_DESKEW_ON_SKIP_IN_GEN12 = "FALSE";
+ parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 = "FALSE";
+ parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4 = "FALSE";
+ parameter PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 = "FALSE";
+ parameter PL_DISABLE_DC_BALANCE = "FALSE";
+ parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE";
+ parameter PL_DISABLE_LANE_REVERSAL = "FALSE";
+ parameter [1:0] PL_DISABLE_LFSR_UPDATE_ON_SKP = 2'h0;
+ parameter PL_DISABLE_RETRAIN_ON_EB_ERROR = "FALSE";
+ parameter PL_DISABLE_RETRAIN_ON_FRAMING_ERROR = "FALSE";
+ parameter [15:0] PL_DISABLE_RETRAIN_ON_SPECIFIC_FRAMING_ERROR = 16'h0000;
+ parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE";
+ parameter [1:0] PL_EQ_ADAPT_DISABLE_COEFF_CHECK = 2'h0;
+ parameter [1:0] PL_EQ_ADAPT_DISABLE_PRESET_CHECK = 2'h0;
+ parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02;
+ parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1;
+ parameter [1:0] PL_EQ_BYPASS_PHASE23 = 2'h0;
+ parameter [5:0] PL_EQ_DEFAULT_RX_PRESET_HINT = 6'h33;
+ parameter [7:0] PL_EQ_DEFAULT_TX_PRESET = 8'h44;
+ parameter PL_EQ_DISABLE_MISMATCH_CHECK = "TRUE";
+ parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE0 = 2'h0;
+ parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE1 = 2'h0;
+ parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE";
+ parameter PL_EQ_TX_8G_EQ_TS2_ENABLE = "FALSE";
+ parameter PL_EXIT_LOOPBACK_ON_EI_ENTRY = "TRUE";
+ parameter PL_INFER_EI_DISABLE_LPBK_ACTIVE = "TRUE";
+ parameter PL_INFER_EI_DISABLE_REC_RC = "FALSE";
+ parameter PL_INFER_EI_DISABLE_REC_SPD = "FALSE";
+ parameter [31:0] PL_LANE0_EQ_CONTROL = 32'h00003F00;
+ parameter [31:0] PL_LANE10_EQ_CONTROL = 32'h00003F00;
+ parameter [31:0] PL_LANE11_EQ_CONTROL = 32'h00003F00;
+ parameter [31:0] PL_LANE12_EQ_CONTROL = 32'h00003F00;
+ parameter [31:0] PL_LANE13_EQ_CONTROL = 32'h00003F00;
+ parameter [31:0] PL_LANE14_EQ_CONTROL = 32'h00003F00;
+ parameter [31:0] PL_LANE15_EQ_CONTROL = 32'h00003F00;
+ parameter [31:0] PL_LANE1_EQ_CONTROL = 32'h00003F00;
+ parameter [31:0] PL_LANE2_EQ_CONTROL = 32'h00003F00;
+ parameter [31:0] PL_LANE3_EQ_CONTROL = 32'h00003F00;
+ parameter [31:0] PL_LANE4_EQ_CONTROL = 32'h00003F00;
+ parameter [31:0] PL_LANE5_EQ_CONTROL = 32'h00003F00;
+ parameter [31:0] PL_LANE6_EQ_CONTROL = 32'h00003F00;
+ parameter [31:0] PL_LANE7_EQ_CONTROL = 32'h00003F00;
+ parameter [31:0] PL_LANE8_EQ_CONTROL = 32'h00003F00;
+ parameter [31:0] PL_LANE9_EQ_CONTROL = 32'h00003F00;
+ parameter [3:0] PL_LINK_CAP_MAX_LINK_SPEED = 4'h4;
+ parameter [4:0] PL_LINK_CAP_MAX_LINK_WIDTH = 5'h08;
+ parameter integer PL_N_FTS = 255;
+ parameter PL_QUIESCE_GUARANTEE_DISABLE = "FALSE";
+ parameter PL_REDO_EQ_SOURCE_SELECT = "TRUE";
+ parameter [7:0] PL_REPORT_ALL_PHY_ERRORS = 8'h00;
+ parameter [1:0] PL_RX_ADAPT_TIMER_CLWS_CLOBBER_TX_TS = 2'h0;
+ parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN3 = 4'h0;
+ parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN4 = 4'h0;
+ parameter [1:0] PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS = 2'h0;
+ parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN3 = 4'h0;
+ parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN4 = 4'h0;
+ parameter [1:0] PL_RX_L0S_EXIT_TO_RECOVERY = 2'h0;
+ parameter [1:0] PL_SIM_FAST_LINK_TRAINING = 2'h0;
+ parameter PL_SRIS_ENABLE = "FALSE";
+ parameter [6:0] PL_SRIS_SKPOS_GEN_SPD_VEC = 7'h00;
+ parameter [6:0] PL_SRIS_SKPOS_REC_SPD_VEC = 7'h00;
+ parameter PL_UPSTREAM_FACING = "TRUE";
+ parameter [15:0] PL_USER_SPARE = 16'h0000;
+ parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h1500;
+ parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h003E8;
+ parameter PM_ENABLE_L23_ENTRY = "FALSE";
+ parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE";
+ parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000100;
+ parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h00000;
+ parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0100;
+ parameter SIM_DEVICE = "ULTRASCALE_PLUS";
+ parameter [31:0] SIM_JTAG_IDCODE = 32'h00000000;
+ parameter SIM_VERSION = "1.0";
+ parameter SPARE_BIT0 = "FALSE";
+ parameter integer SPARE_BIT1 = 0;
+ parameter integer SPARE_BIT2 = 0;
+ parameter SPARE_BIT3 = "FALSE";
+ parameter integer SPARE_BIT4 = 0;
+ parameter integer SPARE_BIT5 = 0;
+ parameter integer SPARE_BIT6 = 0;
+ parameter integer SPARE_BIT7 = 0;
+ parameter integer SPARE_BIT8 = 0;
+ parameter [7:0] SPARE_BYTE0 = 8'h00;
+ parameter [7:0] SPARE_BYTE1 = 8'h00;
+ parameter [7:0] SPARE_BYTE2 = 8'h00;
+ parameter [7:0] SPARE_BYTE3 = 8'h00;
+ parameter [31:0] SPARE_WORD0 = 32'h00000000;
+ parameter [31:0] SPARE_WORD1 = 32'h00000000;
+ parameter [31:0] SPARE_WORD2 = 32'h00000000;
+ parameter [31:0] SPARE_WORD3 = 32'h00000000;
+ parameter [3:0] SRIOV_CAP_ENABLE = 4'h0;
+ parameter TL2CFG_IF_PARITY_CHK = "TRUE";
+ parameter [1:0] TL_COMPLETION_RAM_NUM_TLPS = 2'h0;
+ parameter [1:0] TL_COMPLETION_RAM_SIZE = 2'h1;
+ parameter [11:0] TL_CREDITS_CD = 12'h000;
+ parameter [7:0] TL_CREDITS_CH = 8'h00;
+ parameter [11:0] TL_CREDITS_NPD = 12'h004;
+ parameter [7:0] TL_CREDITS_NPH = 8'h20;
+ parameter [11:0] TL_CREDITS_PD = 12'h0E0;
+ parameter [7:0] TL_CREDITS_PH = 8'h20;
+ parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TIME = 5'h02;
+ parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT = 5'h08;
+ parameter [1:0] TL_PF_ENABLE_REG = 2'h0;
+ parameter [0:0] TL_POSTED_RAM_SIZE = 1'h0;
+ parameter TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE = "FALSE";
+ parameter TL_RX_COMPLETION_TO_RAM_READ_PIPELINE = "FALSE";
+ parameter TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE = "FALSE";
+ parameter TL_RX_POSTED_FROM_RAM_READ_PIPELINE = "FALSE";
+ parameter TL_RX_POSTED_TO_RAM_READ_PIPELINE = "FALSE";
+ parameter TL_RX_POSTED_TO_RAM_WRITE_PIPELINE = "FALSE";
+ parameter TL_TX_MUX_STRICT_PRIORITY = "TRUE";
+ parameter TL_TX_TLP_STRADDLE_ENABLE = "FALSE";
+ parameter TL_TX_TLP_TERMINATE_PARITY = "FALSE";
+ parameter [15:0] TL_USER_SPARE = 16'h0000;
+ parameter TPH_FROM_RAM_PIPELINE = "FALSE";
+ parameter TPH_TO_RAM_PIPELINE = "FALSE";
+ parameter [7:0] VF0_CAPABILITY_POINTER = 8'h80;
+ parameter [11:0] VFG0_ARI_CAP_NEXTPTR = 12'h000;
+ parameter [7:0] VFG0_MSIX_CAP_NEXTPTR = 8'h00;
+ parameter integer VFG0_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] VFG0_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer VFG0_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] VFG0_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] VFG0_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter [7:0] VFG0_PCIE_CAP_NEXTPTR = 8'h00;
+ parameter [11:0] VFG0_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] VFG0_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [11:0] VFG1_ARI_CAP_NEXTPTR = 12'h000;
+ parameter [7:0] VFG1_MSIX_CAP_NEXTPTR = 8'h00;
+ parameter integer VFG1_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] VFG1_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer VFG1_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] VFG1_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] VFG1_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter [7:0] VFG1_PCIE_CAP_NEXTPTR = 8'h00;
+ parameter [11:0] VFG1_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] VFG1_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [11:0] VFG2_ARI_CAP_NEXTPTR = 12'h000;
+ parameter [7:0] VFG2_MSIX_CAP_NEXTPTR = 8'h00;
+ parameter integer VFG2_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] VFG2_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer VFG2_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] VFG2_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] VFG2_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter [7:0] VFG2_PCIE_CAP_NEXTPTR = 8'h00;
+ parameter [11:0] VFG2_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] VFG2_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [11:0] VFG3_ARI_CAP_NEXTPTR = 12'h000;
+ parameter [7:0] VFG3_MSIX_CAP_NEXTPTR = 8'h00;
+ parameter integer VFG3_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] VFG3_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer VFG3_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] VFG3_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] VFG3_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter [7:0] VFG3_PCIE_CAP_NEXTPTR = 8'h00;
+ parameter [11:0] VFG3_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] VFG3_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ output [7:0] AXIUSEROUT;
+ output [7:0] CFGBUSNUMBER;
+ output [1:0] CFGCURRENTSPEED;
+ output CFGERRCOROUT;
+ output CFGERRFATALOUT;
+ output CFGERRNONFATALOUT;
+ output [7:0] CFGEXTFUNCTIONNUMBER;
+ output CFGEXTREADRECEIVED;
+ output [9:0] CFGEXTREGISTERNUMBER;
+ output [3:0] CFGEXTWRITEBYTEENABLE;
+ output [31:0] CFGEXTWRITEDATA;
+ output CFGEXTWRITERECEIVED;
+ output [11:0] CFGFCCPLD;
+ output [7:0] CFGFCCPLH;
+ output [11:0] CFGFCNPD;
+ output [7:0] CFGFCNPH;
+ output [11:0] CFGFCPD;
+ output [7:0] CFGFCPH;
+ output [3:0] CFGFLRINPROCESS;
+ output [11:0] CFGFUNCTIONPOWERSTATE;
+ output [15:0] CFGFUNCTIONSTATUS;
+ output CFGHOTRESETOUT;
+ output [31:0] CFGINTERRUPTMSIDATA;
+ output [3:0] CFGINTERRUPTMSIENABLE;
+ output CFGINTERRUPTMSIFAIL;
+ output CFGINTERRUPTMSIMASKUPDATE;
+ output [11:0] CFGINTERRUPTMSIMMENABLE;
+ output CFGINTERRUPTMSISENT;
+ output [3:0] CFGINTERRUPTMSIXENABLE;
+ output [3:0] CFGINTERRUPTMSIXMASK;
+ output CFGINTERRUPTMSIXVECPENDINGSTATUS;
+ output CFGINTERRUPTSENT;
+ output [1:0] CFGLINKPOWERSTATE;
+ output [4:0] CFGLOCALERROROUT;
+ output CFGLOCALERRORVALID;
+ output CFGLTRENABLE;
+ output [5:0] CFGLTSSMSTATE;
+ output [1:0] CFGMAXPAYLOAD;
+ output [2:0] CFGMAXREADREQ;
+ output [31:0] CFGMGMTREADDATA;
+ output CFGMGMTREADWRITEDONE;
+ output CFGMSGRECEIVED;
+ output [7:0] CFGMSGRECEIVEDDATA;
+ output [4:0] CFGMSGRECEIVEDTYPE;
+ output CFGMSGTRANSMITDONE;
+ output [12:0] CFGMSIXRAMADDRESS;
+ output CFGMSIXRAMREADENABLE;
+ output [3:0] CFGMSIXRAMWRITEBYTEENABLE;
+ output [35:0] CFGMSIXRAMWRITEDATA;
+ output [2:0] CFGNEGOTIATEDWIDTH;
+ output [1:0] CFGOBFFENABLE;
+ output CFGPHYLINKDOWN;
+ output [1:0] CFGPHYLINKSTATUS;
+ output CFGPLSTATUSCHANGE;
+ output CFGPOWERSTATECHANGEINTERRUPT;
+ output [3:0] CFGRCBSTATUS;
+ output [1:0] CFGRXPMSTATE;
+ output [11:0] CFGTPHRAMADDRESS;
+ output CFGTPHRAMREADENABLE;
+ output [3:0] CFGTPHRAMWRITEBYTEENABLE;
+ output [35:0] CFGTPHRAMWRITEDATA;
+ output [3:0] CFGTPHREQUESTERENABLE;
+ output [11:0] CFGTPHSTMODE;
+ output [1:0] CFGTXPMSTATE;
+ output CONFMCAPDESIGNSWITCH;
+ output CONFMCAPEOS;
+ output CONFMCAPINUSEBYPCIE;
+ output CONFREQREADY;
+ output [31:0] CONFRESPRDATA;
+ output CONFRESPVALID;
+ output [31:0] DBGCTRL0OUT;
+ output [31:0] DBGCTRL1OUT;
+ output [255:0] DBGDATA0OUT;
+ output [255:0] DBGDATA1OUT;
+ output [15:0] DRPDO;
+ output DRPRDY;
+ output [255:0] MAXISCQTDATA;
+ output [7:0] MAXISCQTKEEP;
+ output MAXISCQTLAST;
+ output [87:0] MAXISCQTUSER;
+ output MAXISCQTVALID;
+ output [255:0] MAXISRCTDATA;
+ output [7:0] MAXISRCTKEEP;
+ output MAXISRCTLAST;
+ output [74:0] MAXISRCTUSER;
+ output MAXISRCTVALID;
+ output [8:0] MIREPLAYRAMADDRESS0;
+ output [8:0] MIREPLAYRAMADDRESS1;
+ output MIREPLAYRAMREADENABLE0;
+ output MIREPLAYRAMREADENABLE1;
+ output [127:0] MIREPLAYRAMWRITEDATA0;
+ output [127:0] MIREPLAYRAMWRITEDATA1;
+ output MIREPLAYRAMWRITEENABLE0;
+ output MIREPLAYRAMWRITEENABLE1;
+ output [8:0] MIRXCOMPLETIONRAMREADADDRESS0;
+ output [8:0] MIRXCOMPLETIONRAMREADADDRESS1;
+ output [1:0] MIRXCOMPLETIONRAMREADENABLE0;
+ output [1:0] MIRXCOMPLETIONRAMREADENABLE1;
+ output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS0;
+ output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS1;
+ output [143:0] MIRXCOMPLETIONRAMWRITEDATA0;
+ output [143:0] MIRXCOMPLETIONRAMWRITEDATA1;
+ output [1:0] MIRXCOMPLETIONRAMWRITEENABLE0;
+ output [1:0] MIRXCOMPLETIONRAMWRITEENABLE1;
+ output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS0;
+ output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS1;
+ output MIRXPOSTEDREQUESTRAMREADENABLE0;
+ output MIRXPOSTEDREQUESTRAMREADENABLE1;
+ output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS0;
+ output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS1;
+ output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA0;
+ output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA1;
+ output MIRXPOSTEDREQUESTRAMWRITEENABLE0;
+ output MIRXPOSTEDREQUESTRAMWRITEENABLE1;
+ output [5:0] PCIECQNPREQCOUNT;
+ output PCIEPERST0B;
+ output PCIEPERST1B;
+ output [5:0] PCIERQSEQNUM0;
+ output [5:0] PCIERQSEQNUM1;
+ output PCIERQSEQNUMVLD0;
+ output PCIERQSEQNUMVLD1;
+ output [7:0] PCIERQTAG0;
+ output [7:0] PCIERQTAG1;
+ output [3:0] PCIERQTAGAV;
+ output PCIERQTAGVLD0;
+ output PCIERQTAGVLD1;
+ output [3:0] PCIETFCNPDAV;
+ output [3:0] PCIETFCNPHAV;
+ output [1:0] PIPERX00EQCONTROL;
+ output PIPERX00POLARITY;
+ output [1:0] PIPERX01EQCONTROL;
+ output PIPERX01POLARITY;
+ output [1:0] PIPERX02EQCONTROL;
+ output PIPERX02POLARITY;
+ output [1:0] PIPERX03EQCONTROL;
+ output PIPERX03POLARITY;
+ output [1:0] PIPERX04EQCONTROL;
+ output PIPERX04POLARITY;
+ output [1:0] PIPERX05EQCONTROL;
+ output PIPERX05POLARITY;
+ output [1:0] PIPERX06EQCONTROL;
+ output PIPERX06POLARITY;
+ output [1:0] PIPERX07EQCONTROL;
+ output PIPERX07POLARITY;
+ output [1:0] PIPERX08EQCONTROL;
+ output PIPERX08POLARITY;
+ output [1:0] PIPERX09EQCONTROL;
+ output PIPERX09POLARITY;
+ output [1:0] PIPERX10EQCONTROL;
+ output PIPERX10POLARITY;
+ output [1:0] PIPERX11EQCONTROL;
+ output PIPERX11POLARITY;
+ output [1:0] PIPERX12EQCONTROL;
+ output PIPERX12POLARITY;
+ output [1:0] PIPERX13EQCONTROL;
+ output PIPERX13POLARITY;
+ output [1:0] PIPERX14EQCONTROL;
+ output PIPERX14POLARITY;
+ output [1:0] PIPERX15EQCONTROL;
+ output PIPERX15POLARITY;
+ output [5:0] PIPERXEQLPLFFS;
+ output [3:0] PIPERXEQLPTXPRESET;
+ output [1:0] PIPETX00CHARISK;
+ output PIPETX00COMPLIANCE;
+ output [31:0] PIPETX00DATA;
+ output PIPETX00DATAVALID;
+ output PIPETX00ELECIDLE;
+ output [1:0] PIPETX00EQCONTROL;
+ output [5:0] PIPETX00EQDEEMPH;
+ output [1:0] PIPETX00POWERDOWN;
+ output PIPETX00STARTBLOCK;
+ output [1:0] PIPETX00SYNCHEADER;
+ output [1:0] PIPETX01CHARISK;
+ output PIPETX01COMPLIANCE;
+ output [31:0] PIPETX01DATA;
+ output PIPETX01DATAVALID;
+ output PIPETX01ELECIDLE;
+ output [1:0] PIPETX01EQCONTROL;
+ output [5:0] PIPETX01EQDEEMPH;
+ output [1:0] PIPETX01POWERDOWN;
+ output PIPETX01STARTBLOCK;
+ output [1:0] PIPETX01SYNCHEADER;
+ output [1:0] PIPETX02CHARISK;
+ output PIPETX02COMPLIANCE;
+ output [31:0] PIPETX02DATA;
+ output PIPETX02DATAVALID;
+ output PIPETX02ELECIDLE;
+ output [1:0] PIPETX02EQCONTROL;
+ output [5:0] PIPETX02EQDEEMPH;
+ output [1:0] PIPETX02POWERDOWN;
+ output PIPETX02STARTBLOCK;
+ output [1:0] PIPETX02SYNCHEADER;
+ output [1:0] PIPETX03CHARISK;
+ output PIPETX03COMPLIANCE;
+ output [31:0] PIPETX03DATA;
+ output PIPETX03DATAVALID;
+ output PIPETX03ELECIDLE;
+ output [1:0] PIPETX03EQCONTROL;
+ output [5:0] PIPETX03EQDEEMPH;
+ output [1:0] PIPETX03POWERDOWN;
+ output PIPETX03STARTBLOCK;
+ output [1:0] PIPETX03SYNCHEADER;
+ output [1:0] PIPETX04CHARISK;
+ output PIPETX04COMPLIANCE;
+ output [31:0] PIPETX04DATA;
+ output PIPETX04DATAVALID;
+ output PIPETX04ELECIDLE;
+ output [1:0] PIPETX04EQCONTROL;
+ output [5:0] PIPETX04EQDEEMPH;
+ output [1:0] PIPETX04POWERDOWN;
+ output PIPETX04STARTBLOCK;
+ output [1:0] PIPETX04SYNCHEADER;
+ output [1:0] PIPETX05CHARISK;
+ output PIPETX05COMPLIANCE;
+ output [31:0] PIPETX05DATA;
+ output PIPETX05DATAVALID;
+ output PIPETX05ELECIDLE;
+ output [1:0] PIPETX05EQCONTROL;
+ output [5:0] PIPETX05EQDEEMPH;
+ output [1:0] PIPETX05POWERDOWN;
+ output PIPETX05STARTBLOCK;
+ output [1:0] PIPETX05SYNCHEADER;
+ output [1:0] PIPETX06CHARISK;
+ output PIPETX06COMPLIANCE;
+ output [31:0] PIPETX06DATA;
+ output PIPETX06DATAVALID;
+ output PIPETX06ELECIDLE;
+ output [1:0] PIPETX06EQCONTROL;
+ output [5:0] PIPETX06EQDEEMPH;
+ output [1:0] PIPETX06POWERDOWN;
+ output PIPETX06STARTBLOCK;
+ output [1:0] PIPETX06SYNCHEADER;
+ output [1:0] PIPETX07CHARISK;
+ output PIPETX07COMPLIANCE;
+ output [31:0] PIPETX07DATA;
+ output PIPETX07DATAVALID;
+ output PIPETX07ELECIDLE;
+ output [1:0] PIPETX07EQCONTROL;
+ output [5:0] PIPETX07EQDEEMPH;
+ output [1:0] PIPETX07POWERDOWN;
+ output PIPETX07STARTBLOCK;
+ output [1:0] PIPETX07SYNCHEADER;
+ output [1:0] PIPETX08CHARISK;
+ output PIPETX08COMPLIANCE;
+ output [31:0] PIPETX08DATA;
+ output PIPETX08DATAVALID;
+ output PIPETX08ELECIDLE;
+ output [1:0] PIPETX08EQCONTROL;
+ output [5:0] PIPETX08EQDEEMPH;
+ output [1:0] PIPETX08POWERDOWN;
+ output PIPETX08STARTBLOCK;
+ output [1:0] PIPETX08SYNCHEADER;
+ output [1:0] PIPETX09CHARISK;
+ output PIPETX09COMPLIANCE;
+ output [31:0] PIPETX09DATA;
+ output PIPETX09DATAVALID;
+ output PIPETX09ELECIDLE;
+ output [1:0] PIPETX09EQCONTROL;
+ output [5:0] PIPETX09EQDEEMPH;
+ output [1:0] PIPETX09POWERDOWN;
+ output PIPETX09STARTBLOCK;
+ output [1:0] PIPETX09SYNCHEADER;
+ output [1:0] PIPETX10CHARISK;
+ output PIPETX10COMPLIANCE;
+ output [31:0] PIPETX10DATA;
+ output PIPETX10DATAVALID;
+ output PIPETX10ELECIDLE;
+ output [1:0] PIPETX10EQCONTROL;
+ output [5:0] PIPETX10EQDEEMPH;
+ output [1:0] PIPETX10POWERDOWN;
+ output PIPETX10STARTBLOCK;
+ output [1:0] PIPETX10SYNCHEADER;
+ output [1:0] PIPETX11CHARISK;
+ output PIPETX11COMPLIANCE;
+ output [31:0] PIPETX11DATA;
+ output PIPETX11DATAVALID;
+ output PIPETX11ELECIDLE;
+ output [1:0] PIPETX11EQCONTROL;
+ output [5:0] PIPETX11EQDEEMPH;
+ output [1:0] PIPETX11POWERDOWN;
+ output PIPETX11STARTBLOCK;
+ output [1:0] PIPETX11SYNCHEADER;
+ output [1:0] PIPETX12CHARISK;
+ output PIPETX12COMPLIANCE;
+ output [31:0] PIPETX12DATA;
+ output PIPETX12DATAVALID;
+ output PIPETX12ELECIDLE;
+ output [1:0] PIPETX12EQCONTROL;
+ output [5:0] PIPETX12EQDEEMPH;
+ output [1:0] PIPETX12POWERDOWN;
+ output PIPETX12STARTBLOCK;
+ output [1:0] PIPETX12SYNCHEADER;
+ output [1:0] PIPETX13CHARISK;
+ output PIPETX13COMPLIANCE;
+ output [31:0] PIPETX13DATA;
+ output PIPETX13DATAVALID;
+ output PIPETX13ELECIDLE;
+ output [1:0] PIPETX13EQCONTROL;
+ output [5:0] PIPETX13EQDEEMPH;
+ output [1:0] PIPETX13POWERDOWN;
+ output PIPETX13STARTBLOCK;
+ output [1:0] PIPETX13SYNCHEADER;
+ output [1:0] PIPETX14CHARISK;
+ output PIPETX14COMPLIANCE;
+ output [31:0] PIPETX14DATA;
+ output PIPETX14DATAVALID;
+ output PIPETX14ELECIDLE;
+ output [1:0] PIPETX14EQCONTROL;
+ output [5:0] PIPETX14EQDEEMPH;
+ output [1:0] PIPETX14POWERDOWN;
+ output PIPETX14STARTBLOCK;
+ output [1:0] PIPETX14SYNCHEADER;
+ output [1:0] PIPETX15CHARISK;
+ output PIPETX15COMPLIANCE;
+ output [31:0] PIPETX15DATA;
+ output PIPETX15DATAVALID;
+ output PIPETX15ELECIDLE;
+ output [1:0] PIPETX15EQCONTROL;
+ output [5:0] PIPETX15EQDEEMPH;
+ output [1:0] PIPETX15POWERDOWN;
+ output PIPETX15STARTBLOCK;
+ output [1:0] PIPETX15SYNCHEADER;
+ output PIPETXDEEMPH;
+ output [2:0] PIPETXMARGIN;
+ output [1:0] PIPETXRATE;
+ output PIPETXRCVRDET;
+ output PIPETXRESET;
+ output PIPETXSWING;
+ output PLEQINPROGRESS;
+ output [1:0] PLEQPHASE;
+ output PLGEN34EQMISMATCH;
+ output [3:0] SAXISCCTREADY;
+ output [3:0] SAXISRQTREADY;
+ output [31:0] USERSPAREOUT;
+ input [7:0] AXIUSERIN;
+ input CFGCONFIGSPACEENABLE;
+ input [15:0] CFGDEVIDPF0;
+ input [15:0] CFGDEVIDPF1;
+ input [15:0] CFGDEVIDPF2;
+ input [15:0] CFGDEVIDPF3;
+ input [7:0] CFGDSBUSNUMBER;
+ input [4:0] CFGDSDEVICENUMBER;
+ input [2:0] CFGDSFUNCTIONNUMBER;
+ input [63:0] CFGDSN;
+ input [7:0] CFGDSPORTNUMBER;
+ input CFGERRCORIN;
+ input CFGERRUNCORIN;
+ input [31:0] CFGEXTREADDATA;
+ input CFGEXTREADDATAVALID;
+ input [2:0] CFGFCSEL;
+ input [3:0] CFGFLRDONE;
+ input CFGHOTRESETIN;
+ input [3:0] CFGINTERRUPTINT;
+ input [2:0] CFGINTERRUPTMSIATTR;
+ input [7:0] CFGINTERRUPTMSIFUNCTIONNUMBER;
+ input [31:0] CFGINTERRUPTMSIINT;
+ input [31:0] CFGINTERRUPTMSIPENDINGSTATUS;
+ input CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE;
+ input [1:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM;
+ input [1:0] CFGINTERRUPTMSISELECT;
+ input CFGINTERRUPTMSITPHPRESENT;
+ input [7:0] CFGINTERRUPTMSITPHSTTAG;
+ input [1:0] CFGINTERRUPTMSITPHTYPE;
+ input [63:0] CFGINTERRUPTMSIXADDRESS;
+ input [31:0] CFGINTERRUPTMSIXDATA;
+ input CFGINTERRUPTMSIXINT;
+ input [1:0] CFGINTERRUPTMSIXVECPENDING;
+ input [3:0] CFGINTERRUPTPENDING;
+ input CFGLINKTRAININGENABLE;
+ input [9:0] CFGMGMTADDR;
+ input [3:0] CFGMGMTBYTEENABLE;
+ input CFGMGMTDEBUGACCESS;
+ input [7:0] CFGMGMTFUNCTIONNUMBER;
+ input CFGMGMTREAD;
+ input CFGMGMTWRITE;
+ input [31:0] CFGMGMTWRITEDATA;
+ input CFGMSGTRANSMIT;
+ input [31:0] CFGMSGTRANSMITDATA;
+ input [2:0] CFGMSGTRANSMITTYPE;
+ input [35:0] CFGMSIXRAMREADDATA;
+ input CFGPMASPML1ENTRYREJECT;
+ input CFGPMASPMTXL0SENTRYDISABLE;
+ input CFGPOWERSTATECHANGEACK;
+ input CFGREQPMTRANSITIONL23READY;
+ input [7:0] CFGREVIDPF0;
+ input [7:0] CFGREVIDPF1;
+ input [7:0] CFGREVIDPF2;
+ input [7:0] CFGREVIDPF3;
+ input [15:0] CFGSUBSYSIDPF0;
+ input [15:0] CFGSUBSYSIDPF1;
+ input [15:0] CFGSUBSYSIDPF2;
+ input [15:0] CFGSUBSYSIDPF3;
+ input [15:0] CFGSUBSYSVENDID;
+ input [35:0] CFGTPHRAMREADDATA;
+ input [15:0] CFGVENDID;
+ input CFGVFFLRDONE;
+ input [7:0] CFGVFFLRFUNCNUM;
+ input CONFMCAPREQUESTBYCONF;
+ input [31:0] CONFREQDATA;
+ input [3:0] CONFREQREGNUM;
+ input [1:0] CONFREQTYPE;
+ input CONFREQVALID;
+ input CORECLK;
+ input CORECLKMIREPLAYRAM0;
+ input CORECLKMIREPLAYRAM1;
+ input CORECLKMIRXCOMPLETIONRAM0;
+ input CORECLKMIRXCOMPLETIONRAM1;
+ input CORECLKMIRXPOSTEDREQUESTRAM0;
+ input CORECLKMIRXPOSTEDREQUESTRAM1;
+ input [5:0] DBGSEL0;
+ input [5:0] DBGSEL1;
+ input [9:0] DRPADDR;
+ input DRPCLK;
+ input [15:0] DRPDI;
+ input DRPEN;
+ input DRPWE;
+ input [21:0] MAXISCQTREADY;
+ input [21:0] MAXISRCTREADY;
+ input MCAPCLK;
+ input MCAPPERST0B;
+ input MCAPPERST1B;
+ input MGMTRESETN;
+ input MGMTSTICKYRESETN;
+ input [5:0] MIREPLAYRAMERRCOR;
+ input [5:0] MIREPLAYRAMERRUNCOR;
+ input [127:0] MIREPLAYRAMREADDATA0;
+ input [127:0] MIREPLAYRAMREADDATA1;
+ input [11:0] MIRXCOMPLETIONRAMERRCOR;
+ input [11:0] MIRXCOMPLETIONRAMERRUNCOR;
+ input [143:0] MIRXCOMPLETIONRAMREADDATA0;
+ input [143:0] MIRXCOMPLETIONRAMREADDATA1;
+ input [5:0] MIRXPOSTEDREQUESTRAMERRCOR;
+ input [5:0] MIRXPOSTEDREQUESTRAMERRUNCOR;
+ input [143:0] MIRXPOSTEDREQUESTRAMREADDATA0;
+ input [143:0] MIRXPOSTEDREQUESTRAMREADDATA1;
+ input [1:0] PCIECOMPLDELIVERED;
+ input [7:0] PCIECOMPLDELIVEREDTAG0;
+ input [7:0] PCIECOMPLDELIVEREDTAG1;
+ input [1:0] PCIECQNPREQ;
+ input PCIECQNPUSERCREDITRCVD;
+ input PCIECQPIPELINEEMPTY;
+ input PCIEPOSTEDREQDELIVERED;
+ input PIPECLK;
+ input PIPECLKEN;
+ input [5:0] PIPEEQFS;
+ input [5:0] PIPEEQLF;
+ input PIPERESETN;
+ input [1:0] PIPERX00CHARISK;
+ input [31:0] PIPERX00DATA;
+ input PIPERX00DATAVALID;
+ input PIPERX00ELECIDLE;
+ input PIPERX00EQDONE;
+ input PIPERX00EQLPADAPTDONE;
+ input PIPERX00EQLPLFFSSEL;
+ input [17:0] PIPERX00EQLPNEWTXCOEFFORPRESET;
+ input PIPERX00PHYSTATUS;
+ input [1:0] PIPERX00STARTBLOCK;
+ input [2:0] PIPERX00STATUS;
+ input [1:0] PIPERX00SYNCHEADER;
+ input PIPERX00VALID;
+ input [1:0] PIPERX01CHARISK;
+ input [31:0] PIPERX01DATA;
+ input PIPERX01DATAVALID;
+ input PIPERX01ELECIDLE;
+ input PIPERX01EQDONE;
+ input PIPERX01EQLPADAPTDONE;
+ input PIPERX01EQLPLFFSSEL;
+ input [17:0] PIPERX01EQLPNEWTXCOEFFORPRESET;
+ input PIPERX01PHYSTATUS;
+ input [1:0] PIPERX01STARTBLOCK;
+ input [2:0] PIPERX01STATUS;
+ input [1:0] PIPERX01SYNCHEADER;
+ input PIPERX01VALID;
+ input [1:0] PIPERX02CHARISK;
+ input [31:0] PIPERX02DATA;
+ input PIPERX02DATAVALID;
+ input PIPERX02ELECIDLE;
+ input PIPERX02EQDONE;
+ input PIPERX02EQLPADAPTDONE;
+ input PIPERX02EQLPLFFSSEL;
+ input [17:0] PIPERX02EQLPNEWTXCOEFFORPRESET;
+ input PIPERX02PHYSTATUS;
+ input [1:0] PIPERX02STARTBLOCK;
+ input [2:0] PIPERX02STATUS;
+ input [1:0] PIPERX02SYNCHEADER;
+ input PIPERX02VALID;
+ input [1:0] PIPERX03CHARISK;
+ input [31:0] PIPERX03DATA;
+ input PIPERX03DATAVALID;
+ input PIPERX03ELECIDLE;
+ input PIPERX03EQDONE;
+ input PIPERX03EQLPADAPTDONE;
+ input PIPERX03EQLPLFFSSEL;
+ input [17:0] PIPERX03EQLPNEWTXCOEFFORPRESET;
+ input PIPERX03PHYSTATUS;
+ input [1:0] PIPERX03STARTBLOCK;
+ input [2:0] PIPERX03STATUS;
+ input [1:0] PIPERX03SYNCHEADER;
+ input PIPERX03VALID;
+ input [1:0] PIPERX04CHARISK;
+ input [31:0] PIPERX04DATA;
+ input PIPERX04DATAVALID;
+ input PIPERX04ELECIDLE;
+ input PIPERX04EQDONE;
+ input PIPERX04EQLPADAPTDONE;
+ input PIPERX04EQLPLFFSSEL;
+ input [17:0] PIPERX04EQLPNEWTXCOEFFORPRESET;
+ input PIPERX04PHYSTATUS;
+ input [1:0] PIPERX04STARTBLOCK;
+ input [2:0] PIPERX04STATUS;
+ input [1:0] PIPERX04SYNCHEADER;
+ input PIPERX04VALID;
+ input [1:0] PIPERX05CHARISK;
+ input [31:0] PIPERX05DATA;
+ input PIPERX05DATAVALID;
+ input PIPERX05ELECIDLE;
+ input PIPERX05EQDONE;
+ input PIPERX05EQLPADAPTDONE;
+ input PIPERX05EQLPLFFSSEL;
+ input [17:0] PIPERX05EQLPNEWTXCOEFFORPRESET;
+ input PIPERX05PHYSTATUS;
+ input [1:0] PIPERX05STARTBLOCK;
+ input [2:0] PIPERX05STATUS;
+ input [1:0] PIPERX05SYNCHEADER;
+ input PIPERX05VALID;
+ input [1:0] PIPERX06CHARISK;
+ input [31:0] PIPERX06DATA;
+ input PIPERX06DATAVALID;
+ input PIPERX06ELECIDLE;
+ input PIPERX06EQDONE;
+ input PIPERX06EQLPADAPTDONE;
+ input PIPERX06EQLPLFFSSEL;
+ input [17:0] PIPERX06EQLPNEWTXCOEFFORPRESET;
+ input PIPERX06PHYSTATUS;
+ input [1:0] PIPERX06STARTBLOCK;
+ input [2:0] PIPERX06STATUS;
+ input [1:0] PIPERX06SYNCHEADER;
+ input PIPERX06VALID;
+ input [1:0] PIPERX07CHARISK;
+ input [31:0] PIPERX07DATA;
+ input PIPERX07DATAVALID;
+ input PIPERX07ELECIDLE;
+ input PIPERX07EQDONE;
+ input PIPERX07EQLPADAPTDONE;
+ input PIPERX07EQLPLFFSSEL;
+ input [17:0] PIPERX07EQLPNEWTXCOEFFORPRESET;
+ input PIPERX07PHYSTATUS;
+ input [1:0] PIPERX07STARTBLOCK;
+ input [2:0] PIPERX07STATUS;
+ input [1:0] PIPERX07SYNCHEADER;
+ input PIPERX07VALID;
+ input [1:0] PIPERX08CHARISK;
+ input [31:0] PIPERX08DATA;
+ input PIPERX08DATAVALID;
+ input PIPERX08ELECIDLE;
+ input PIPERX08EQDONE;
+ input PIPERX08EQLPADAPTDONE;
+ input PIPERX08EQLPLFFSSEL;
+ input [17:0] PIPERX08EQLPNEWTXCOEFFORPRESET;
+ input PIPERX08PHYSTATUS;
+ input [1:0] PIPERX08STARTBLOCK;
+ input [2:0] PIPERX08STATUS;
+ input [1:0] PIPERX08SYNCHEADER;
+ input PIPERX08VALID;
+ input [1:0] PIPERX09CHARISK;
+ input [31:0] PIPERX09DATA;
+ input PIPERX09DATAVALID;
+ input PIPERX09ELECIDLE;
+ input PIPERX09EQDONE;
+ input PIPERX09EQLPADAPTDONE;
+ input PIPERX09EQLPLFFSSEL;
+ input [17:0] PIPERX09EQLPNEWTXCOEFFORPRESET;
+ input PIPERX09PHYSTATUS;
+ input [1:0] PIPERX09STARTBLOCK;
+ input [2:0] PIPERX09STATUS;
+ input [1:0] PIPERX09SYNCHEADER;
+ input PIPERX09VALID;
+ input [1:0] PIPERX10CHARISK;
+ input [31:0] PIPERX10DATA;
+ input PIPERX10DATAVALID;
+ input PIPERX10ELECIDLE;
+ input PIPERX10EQDONE;
+ input PIPERX10EQLPADAPTDONE;
+ input PIPERX10EQLPLFFSSEL;
+ input [17:0] PIPERX10EQLPNEWTXCOEFFORPRESET;
+ input PIPERX10PHYSTATUS;
+ input [1:0] PIPERX10STARTBLOCK;
+ input [2:0] PIPERX10STATUS;
+ input [1:0] PIPERX10SYNCHEADER;
+ input PIPERX10VALID;
+ input [1:0] PIPERX11CHARISK;
+ input [31:0] PIPERX11DATA;
+ input PIPERX11DATAVALID;
+ input PIPERX11ELECIDLE;
+ input PIPERX11EQDONE;
+ input PIPERX11EQLPADAPTDONE;
+ input PIPERX11EQLPLFFSSEL;
+ input [17:0] PIPERX11EQLPNEWTXCOEFFORPRESET;
+ input PIPERX11PHYSTATUS;
+ input [1:0] PIPERX11STARTBLOCK;
+ input [2:0] PIPERX11STATUS;
+ input [1:0] PIPERX11SYNCHEADER;
+ input PIPERX11VALID;
+ input [1:0] PIPERX12CHARISK;
+ input [31:0] PIPERX12DATA;
+ input PIPERX12DATAVALID;
+ input PIPERX12ELECIDLE;
+ input PIPERX12EQDONE;
+ input PIPERX12EQLPADAPTDONE;
+ input PIPERX12EQLPLFFSSEL;
+ input [17:0] PIPERX12EQLPNEWTXCOEFFORPRESET;
+ input PIPERX12PHYSTATUS;
+ input [1:0] PIPERX12STARTBLOCK;
+ input [2:0] PIPERX12STATUS;
+ input [1:0] PIPERX12SYNCHEADER;
+ input PIPERX12VALID;
+ input [1:0] PIPERX13CHARISK;
+ input [31:0] PIPERX13DATA;
+ input PIPERX13DATAVALID;
+ input PIPERX13ELECIDLE;
+ input PIPERX13EQDONE;
+ input PIPERX13EQLPADAPTDONE;
+ input PIPERX13EQLPLFFSSEL;
+ input [17:0] PIPERX13EQLPNEWTXCOEFFORPRESET;
+ input PIPERX13PHYSTATUS;
+ input [1:0] PIPERX13STARTBLOCK;
+ input [2:0] PIPERX13STATUS;
+ input [1:0] PIPERX13SYNCHEADER;
+ input PIPERX13VALID;
+ input [1:0] PIPERX14CHARISK;
+ input [31:0] PIPERX14DATA;
+ input PIPERX14DATAVALID;
+ input PIPERX14ELECIDLE;
+ input PIPERX14EQDONE;
+ input PIPERX14EQLPADAPTDONE;
+ input PIPERX14EQLPLFFSSEL;
+ input [17:0] PIPERX14EQLPNEWTXCOEFFORPRESET;
+ input PIPERX14PHYSTATUS;
+ input [1:0] PIPERX14STARTBLOCK;
+ input [2:0] PIPERX14STATUS;
+ input [1:0] PIPERX14SYNCHEADER;
+ input PIPERX14VALID;
+ input [1:0] PIPERX15CHARISK;
+ input [31:0] PIPERX15DATA;
+ input PIPERX15DATAVALID;
+ input PIPERX15ELECIDLE;
+ input PIPERX15EQDONE;
+ input PIPERX15EQLPADAPTDONE;
+ input PIPERX15EQLPLFFSSEL;
+ input [17:0] PIPERX15EQLPNEWTXCOEFFORPRESET;
+ input PIPERX15PHYSTATUS;
+ input [1:0] PIPERX15STARTBLOCK;
+ input [2:0] PIPERX15STATUS;
+ input [1:0] PIPERX15SYNCHEADER;
+ input PIPERX15VALID;
+ input [17:0] PIPETX00EQCOEFF;
+ input PIPETX00EQDONE;
+ input [17:0] PIPETX01EQCOEFF;
+ input PIPETX01EQDONE;
+ input [17:0] PIPETX02EQCOEFF;
+ input PIPETX02EQDONE;
+ input [17:0] PIPETX03EQCOEFF;
+ input PIPETX03EQDONE;
+ input [17:0] PIPETX04EQCOEFF;
+ input PIPETX04EQDONE;
+ input [17:0] PIPETX05EQCOEFF;
+ input PIPETX05EQDONE;
+ input [17:0] PIPETX06EQCOEFF;
+ input PIPETX06EQDONE;
+ input [17:0] PIPETX07EQCOEFF;
+ input PIPETX07EQDONE;
+ input [17:0] PIPETX08EQCOEFF;
+ input PIPETX08EQDONE;
+ input [17:0] PIPETX09EQCOEFF;
+ input PIPETX09EQDONE;
+ input [17:0] PIPETX10EQCOEFF;
+ input PIPETX10EQDONE;
+ input [17:0] PIPETX11EQCOEFF;
+ input PIPETX11EQDONE;
+ input [17:0] PIPETX12EQCOEFF;
+ input PIPETX12EQDONE;
+ input [17:0] PIPETX13EQCOEFF;
+ input PIPETX13EQDONE;
+ input [17:0] PIPETX14EQCOEFF;
+ input PIPETX14EQDONE;
+ input [17:0] PIPETX15EQCOEFF;
+ input PIPETX15EQDONE;
+ input PLEQRESETEIEOSCOUNT;
+ input PLGEN2UPSTREAMPREFERDEEMPH;
+ input PLGEN34REDOEQSPEED;
+ input PLGEN34REDOEQUALIZATION;
+ input RESETN;
+ input [255:0] SAXISCCTDATA;
+ input [7:0] SAXISCCTKEEP;
+ input SAXISCCTLAST;
+ input [32:0] SAXISCCTUSER;
+ input SAXISCCTVALID;
+ input [255:0] SAXISRQTDATA;
+ input [7:0] SAXISRQTKEEP;
+ input SAXISRQTLAST;
+ input [61:0] SAXISRQTUSER;
+ input SAXISRQTVALID;
+ input USERCLK;
+ input USERCLK2;
+ input USERCLKEN;
+ input [31:0] USERSPAREIN;
+endmodule
+
+module PCIE_3_1 (...);
+ parameter ARI_CAP_ENABLE = "FALSE";
+ parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE";
+ parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE";
+ parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE";
+ parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE";
+ parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000;
+ parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE";
+ parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE";
+ parameter AXISTEN_IF_RC_STRADDLE = "FALSE";
+ parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE";
+ parameter AXISTEN_IF_RQ_PARITY_CHK = "TRUE";
+ parameter [1:0] AXISTEN_IF_WIDTH = 2'h2;
+ parameter CRM_CORE_CLK_FREQ_500 = "TRUE";
+ parameter [1:0] CRM_USER_CLK_FREQ = 2'h2;
+ parameter DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE = "FALSE";
+ parameter DEBUG_PL_DISABLE_EI_INFER_IN_L0 = "FALSE";
+ parameter DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS = "FALSE";
+ parameter [7:0] DNSTREAM_LINK_NUM = 8'h00;
+ parameter [8:0] LL_ACK_TIMEOUT = 9'h000;
+ parameter LL_ACK_TIMEOUT_EN = "FALSE";
+ parameter integer LL_ACK_TIMEOUT_FUNC = 0;
+ parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0000;
+ parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
+ parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0000;
+ parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
+ parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0000;
+ parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
+ parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0000;
+ parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
+ parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000;
+ parameter LL_REPLAY_TIMEOUT_EN = "FALSE";
+ parameter integer LL_REPLAY_TIMEOUT_FUNC = 0;
+ parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0FA;
+ parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE";
+ parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE";
+ parameter [11:0] MCAP_CAP_NEXTPTR = 12'h000;
+ parameter MCAP_CONFIGURE_OVERRIDE = "FALSE";
+ parameter MCAP_ENABLE = "FALSE";
+ parameter MCAP_EOS_DESIGN_SWITCH = "FALSE";
+ parameter [31:0] MCAP_FPGA_BITSTREAM_VERSION = 32'h00000000;
+ parameter MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "FALSE";
+ parameter MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "FALSE";
+ parameter MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE";
+ parameter MCAP_INTERRUPT_ON_MCAP_EOS = "FALSE";
+ parameter MCAP_INTERRUPT_ON_MCAP_ERROR = "FALSE";
+ parameter [15:0] MCAP_VSEC_ID = 16'h0000;
+ parameter [11:0] MCAP_VSEC_LEN = 12'h02C;
+ parameter [3:0] MCAP_VSEC_REV = 4'h0;
+ parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
+ parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
+ parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000;
+ parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000;
+ parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00;
+ parameter [3:0] PF0_ARI_CAP_VER = 4'h1;
+ parameter [5:0] PF0_BAR0_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF0_BAR0_CONTROL = 3'h4;
+ parameter [5:0] PF0_BAR1_APERTURE_SIZE = 6'h00;
+ parameter [2:0] PF0_BAR1_CONTROL = 3'h0;
+ parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF0_BAR2_CONTROL = 3'h4;
+ parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF0_BAR3_CONTROL = 3'h0;
+ parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF0_BAR4_CONTROL = 3'h4;
+ parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF0_BAR5_CONTROL = 3'h0;
+ parameter [7:0] PF0_BIST_REGISTER = 8'h00;
+ parameter [7:0] PF0_CAPABILITY_POINTER = 8'h50;
+ parameter [23:0] PF0_CLASS_CODE = 24'h000000;
+ parameter [15:0] PF0_DEVICE_ID = 16'h0000;
+ parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE";
+ parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE";
+ parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE";
+ parameter PF0_DEV_CAP2_ARI_FORWARD_ENABLE = "FALSE";
+ parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE";
+ parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE";
+ parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0;
+ parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE";
+ parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0;
+ parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0;
+ parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE";
+ parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE";
+ parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
+ parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h000;
+ parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h00;
+ parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE";
+ parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00;
+ parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00;
+ parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00;
+ parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00;
+ parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00;
+ parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00;
+ parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00;
+ parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00;
+ parameter [3:0] PF0_DPA_CAP_VER = 4'h1;
+ parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C;
+ parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
+ parameter PF0_EXPANSION_ROM_ENABLE = "FALSE";
+ parameter [7:0] PF0_INTERRUPT_LINE = 8'h00;
+ parameter [2:0] PF0_INTERRUPT_PIN = 3'h1;
+ parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0;
+ parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7;
+ parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7;
+ parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7;
+ parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7;
+ parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7;
+ parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7;
+ parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7;
+ parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7;
+ parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7;
+ parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7;
+ parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7;
+ parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7;
+ parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE";
+ parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000;
+ parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000;
+ parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000;
+ parameter [3:0] PF0_LTR_CAP_VER = 4'h1;
+ parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00;
+ parameter integer PF0_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer PF0_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00;
+ parameter PF0_MSI_CAP_PERVECMASKCAP = "FALSE";
+ parameter [31:0] PF0_PB_CAP_DATA_REG_D0 = 32'h00000000;
+ parameter [31:0] PF0_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000;
+ parameter [31:0] PF0_PB_CAP_DATA_REG_D1 = 32'h00000000;
+ parameter [31:0] PF0_PB_CAP_DATA_REG_D3HOT = 32'h00000000;
+ parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h000;
+ parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE";
+ parameter [3:0] PF0_PB_CAP_VER = 4'h1;
+ parameter [7:0] PF0_PM_CAP_ID = 8'h01;
+ parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00;
+ parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE";
+ parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE";
+ parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE";
+ parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE";
+ parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3;
+ parameter PF0_PM_CSR_NOSOFTRESET = "TRUE";
+ parameter PF0_RBAR_CAP_ENABLE = "FALSE";
+ parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h000;
+ parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h00000;
+ parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h00000;
+ parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h00000;
+ parameter [3:0] PF0_RBAR_CAP_VER = 4'h1;
+ parameter [2:0] PF0_RBAR_CONTROL_INDEX0 = 3'h0;
+ parameter [2:0] PF0_RBAR_CONTROL_INDEX1 = 3'h0;
+ parameter [2:0] PF0_RBAR_CONTROL_INDEX2 = 3'h0;
+ parameter [4:0] PF0_RBAR_CONTROL_SIZE0 = 5'h00;
+ parameter [4:0] PF0_RBAR_CONTROL_SIZE1 = 5'h00;
+ parameter [4:0] PF0_RBAR_CONTROL_SIZE2 = 5'h00;
+ parameter [2:0] PF0_RBAR_NUM = 3'h1;
+ parameter [7:0] PF0_REVISION_ID = 8'h00;
+ parameter [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR = 12'h000;
+ parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4;
+ parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
+ parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0;
+ parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4;
+ parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0;
+ parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4;
+ parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0;
+ parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000;
+ parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000;
+ parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000;
+ parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1;
+ parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000;
+ parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000;
+ parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
+ parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000;
+ parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0000;
+ parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
+ parameter PF0_TPHR_CAP_ENABLE = "FALSE";
+ parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE";
+ parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0;
+ parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
+ parameter [3:0] PF0_TPHR_CAP_VER = 4'h1;
+ parameter PF0_VC_CAP_ENABLE = "FALSE";
+ parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000;
+ parameter [3:0] PF0_VC_CAP_VER = 4'h1;
+ parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
+ parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
+ parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000;
+ parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000;
+ parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00;
+ parameter [5:0] PF1_BAR0_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF1_BAR0_CONTROL = 3'h4;
+ parameter [5:0] PF1_BAR1_APERTURE_SIZE = 6'h00;
+ parameter [2:0] PF1_BAR1_CONTROL = 3'h0;
+ parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF1_BAR2_CONTROL = 3'h4;
+ parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF1_BAR3_CONTROL = 3'h0;
+ parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF1_BAR4_CONTROL = 3'h4;
+ parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF1_BAR5_CONTROL = 3'h0;
+ parameter [7:0] PF1_BIST_REGISTER = 8'h00;
+ parameter [7:0] PF1_CAPABILITY_POINTER = 8'h50;
+ parameter [23:0] PF1_CLASS_CODE = 24'h000000;
+ parameter [15:0] PF1_DEVICE_ID = 16'h0000;
+ parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
+ parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h000;
+ parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h00;
+ parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE";
+ parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00;
+ parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00;
+ parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00;
+ parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00;
+ parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00;
+ parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00;
+ parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00;
+ parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00;
+ parameter [3:0] PF1_DPA_CAP_VER = 4'h1;
+ parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C;
+ parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
+ parameter PF1_EXPANSION_ROM_ENABLE = "FALSE";
+ parameter [7:0] PF1_INTERRUPT_LINE = 8'h00;
+ parameter [2:0] PF1_INTERRUPT_PIN = 3'h1;
+ parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00;
+ parameter integer PF1_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer PF1_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00;
+ parameter PF1_MSI_CAP_PERVECMASKCAP = "FALSE";
+ parameter [31:0] PF1_PB_CAP_DATA_REG_D0 = 32'h00000000;
+ parameter [31:0] PF1_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000;
+ parameter [31:0] PF1_PB_CAP_DATA_REG_D1 = 32'h00000000;
+ parameter [31:0] PF1_PB_CAP_DATA_REG_D3HOT = 32'h00000000;
+ parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h000;
+ parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE";
+ parameter [3:0] PF1_PB_CAP_VER = 4'h1;
+ parameter [7:0] PF1_PM_CAP_ID = 8'h01;
+ parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00;
+ parameter [2:0] PF1_PM_CAP_VER_ID = 3'h3;
+ parameter PF1_RBAR_CAP_ENABLE = "FALSE";
+ parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h000;
+ parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h00000;
+ parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h00000;
+ parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h00000;
+ parameter [3:0] PF1_RBAR_CAP_VER = 4'h1;
+ parameter [2:0] PF1_RBAR_CONTROL_INDEX0 = 3'h0;
+ parameter [2:0] PF1_RBAR_CONTROL_INDEX1 = 3'h0;
+ parameter [2:0] PF1_RBAR_CONTROL_INDEX2 = 3'h0;
+ parameter [4:0] PF1_RBAR_CONTROL_SIZE0 = 5'h00;
+ parameter [4:0] PF1_RBAR_CONTROL_SIZE1 = 5'h00;
+ parameter [4:0] PF1_RBAR_CONTROL_SIZE2 = 5'h00;
+ parameter [2:0] PF1_RBAR_NUM = 3'h1;
+ parameter [7:0] PF1_REVISION_ID = 8'h00;
+ parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4;
+ parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
+ parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0;
+ parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4;
+ parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0;
+ parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4;
+ parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0;
+ parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000;
+ parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000;
+ parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000;
+ parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1;
+ parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000;
+ parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000;
+ parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
+ parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000;
+ parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0000;
+ parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
+ parameter PF1_TPHR_CAP_ENABLE = "FALSE";
+ parameter PF1_TPHR_CAP_INT_VEC_MODE = "TRUE";
+ parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'h0;
+ parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
+ parameter [3:0] PF1_TPHR_CAP_VER = 4'h1;
+ parameter PF2_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
+ parameter PF2_AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
+ parameter [11:0] PF2_AER_CAP_NEXTPTR = 12'h000;
+ parameter [11:0] PF2_ARI_CAP_NEXTPTR = 12'h000;
+ parameter [7:0] PF2_ARI_CAP_NEXT_FUNC = 8'h00;
+ parameter [5:0] PF2_BAR0_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF2_BAR0_CONTROL = 3'h4;
+ parameter [5:0] PF2_BAR1_APERTURE_SIZE = 6'h00;
+ parameter [2:0] PF2_BAR1_CONTROL = 3'h0;
+ parameter [4:0] PF2_BAR2_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF2_BAR2_CONTROL = 3'h4;
+ parameter [4:0] PF2_BAR3_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF2_BAR3_CONTROL = 3'h0;
+ parameter [4:0] PF2_BAR4_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF2_BAR4_CONTROL = 3'h4;
+ parameter [4:0] PF2_BAR5_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF2_BAR5_CONTROL = 3'h0;
+ parameter [7:0] PF2_BIST_REGISTER = 8'h00;
+ parameter [7:0] PF2_CAPABILITY_POINTER = 8'h50;
+ parameter [23:0] PF2_CLASS_CODE = 24'h000000;
+ parameter [15:0] PF2_DEVICE_ID = 16'h0000;
+ parameter [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
+ parameter [11:0] PF2_DPA_CAP_NEXTPTR = 12'h000;
+ parameter [4:0] PF2_DPA_CAP_SUB_STATE_CONTROL = 5'h00;
+ parameter PF2_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE";
+ parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00;
+ parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00;
+ parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00;
+ parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00;
+ parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00;
+ parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00;
+ parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00;
+ parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00;
+ parameter [3:0] PF2_DPA_CAP_VER = 4'h1;
+ parameter [11:0] PF2_DSN_CAP_NEXTPTR = 12'h10C;
+ parameter [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
+ parameter PF2_EXPANSION_ROM_ENABLE = "FALSE";
+ parameter [7:0] PF2_INTERRUPT_LINE = 8'h00;
+ parameter [2:0] PF2_INTERRUPT_PIN = 3'h1;
+ parameter [7:0] PF2_MSIX_CAP_NEXTPTR = 8'h00;
+ parameter integer PF2_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] PF2_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer PF2_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] PF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] PF2_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter integer PF2_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] PF2_MSI_CAP_NEXTPTR = 8'h00;
+ parameter PF2_MSI_CAP_PERVECMASKCAP = "FALSE";
+ parameter [31:0] PF2_PB_CAP_DATA_REG_D0 = 32'h00000000;
+ parameter [31:0] PF2_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000;
+ parameter [31:0] PF2_PB_CAP_DATA_REG_D1 = 32'h00000000;
+ parameter [31:0] PF2_PB_CAP_DATA_REG_D3HOT = 32'h00000000;
+ parameter [11:0] PF2_PB_CAP_NEXTPTR = 12'h000;
+ parameter PF2_PB_CAP_SYSTEM_ALLOCATED = "FALSE";
+ parameter [3:0] PF2_PB_CAP_VER = 4'h1;
+ parameter [7:0] PF2_PM_CAP_ID = 8'h01;
+ parameter [7:0] PF2_PM_CAP_NEXTPTR = 8'h00;
+ parameter [2:0] PF2_PM_CAP_VER_ID = 3'h3;
+ parameter PF2_RBAR_CAP_ENABLE = "FALSE";
+ parameter [11:0] PF2_RBAR_CAP_NEXTPTR = 12'h000;
+ parameter [19:0] PF2_RBAR_CAP_SIZE0 = 20'h00000;
+ parameter [19:0] PF2_RBAR_CAP_SIZE1 = 20'h00000;
+ parameter [19:0] PF2_RBAR_CAP_SIZE2 = 20'h00000;
+ parameter [3:0] PF2_RBAR_CAP_VER = 4'h1;
+ parameter [2:0] PF2_RBAR_CONTROL_INDEX0 = 3'h0;
+ parameter [2:0] PF2_RBAR_CONTROL_INDEX1 = 3'h0;
+ parameter [2:0] PF2_RBAR_CONTROL_INDEX2 = 3'h0;
+ parameter [4:0] PF2_RBAR_CONTROL_SIZE0 = 5'h00;
+ parameter [4:0] PF2_RBAR_CONTROL_SIZE1 = 5'h00;
+ parameter [4:0] PF2_RBAR_CONTROL_SIZE2 = 5'h00;
+ parameter [2:0] PF2_RBAR_NUM = 3'h1;
+ parameter [7:0] PF2_REVISION_ID = 8'h00;
+ parameter [4:0] PF2_SRIOV_BAR0_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF2_SRIOV_BAR0_CONTROL = 3'h4;
+ parameter [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
+ parameter [2:0] PF2_SRIOV_BAR1_CONTROL = 3'h0;
+ parameter [4:0] PF2_SRIOV_BAR2_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF2_SRIOV_BAR2_CONTROL = 3'h4;
+ parameter [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF2_SRIOV_BAR3_CONTROL = 3'h0;
+ parameter [4:0] PF2_SRIOV_BAR4_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF2_SRIOV_BAR4_CONTROL = 3'h4;
+ parameter [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF2_SRIOV_BAR5_CONTROL = 3'h0;
+ parameter [15:0] PF2_SRIOV_CAP_INITIAL_VF = 16'h0000;
+ parameter [11:0] PF2_SRIOV_CAP_NEXTPTR = 12'h000;
+ parameter [15:0] PF2_SRIOV_CAP_TOTAL_VF = 16'h0000;
+ parameter [3:0] PF2_SRIOV_CAP_VER = 4'h1;
+ parameter [15:0] PF2_SRIOV_FIRST_VF_OFFSET = 16'h0000;
+ parameter [15:0] PF2_SRIOV_FUNC_DEP_LINK = 16'h0000;
+ parameter [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
+ parameter [15:0] PF2_SRIOV_VF_DEVICE_ID = 16'h0000;
+ parameter [15:0] PF2_SUBSYSTEM_ID = 16'h0000;
+ parameter PF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
+ parameter PF2_TPHR_CAP_ENABLE = "FALSE";
+ parameter PF2_TPHR_CAP_INT_VEC_MODE = "TRUE";
+ parameter [11:0] PF2_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] PF2_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [1:0] PF2_TPHR_CAP_ST_TABLE_LOC = 2'h0;
+ parameter [10:0] PF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
+ parameter [3:0] PF2_TPHR_CAP_VER = 4'h1;
+ parameter PF3_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
+ parameter PF3_AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
+ parameter [11:0] PF3_AER_CAP_NEXTPTR = 12'h000;
+ parameter [11:0] PF3_ARI_CAP_NEXTPTR = 12'h000;
+ parameter [7:0] PF3_ARI_CAP_NEXT_FUNC = 8'h00;
+ parameter [5:0] PF3_BAR0_APERTURE_SIZE = 6'h03;
+ parameter [2:0] PF3_BAR0_CONTROL = 3'h4;
+ parameter [5:0] PF3_BAR1_APERTURE_SIZE = 6'h00;
+ parameter [2:0] PF3_BAR1_CONTROL = 3'h0;
+ parameter [4:0] PF3_BAR2_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF3_BAR2_CONTROL = 3'h4;
+ parameter [4:0] PF3_BAR3_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF3_BAR3_CONTROL = 3'h0;
+ parameter [4:0] PF3_BAR4_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF3_BAR4_CONTROL = 3'h4;
+ parameter [4:0] PF3_BAR5_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF3_BAR5_CONTROL = 3'h0;
+ parameter [7:0] PF3_BIST_REGISTER = 8'h00;
+ parameter [7:0] PF3_CAPABILITY_POINTER = 8'h50;
+ parameter [23:0] PF3_CLASS_CODE = 24'h000000;
+ parameter [15:0] PF3_DEVICE_ID = 16'h0000;
+ parameter [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
+ parameter [11:0] PF3_DPA_CAP_NEXTPTR = 12'h000;
+ parameter [4:0] PF3_DPA_CAP_SUB_STATE_CONTROL = 5'h00;
+ parameter PF3_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE";
+ parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00;
+ parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00;
+ parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00;
+ parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00;
+ parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00;
+ parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00;
+ parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00;
+ parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00;
+ parameter [3:0] PF3_DPA_CAP_VER = 4'h1;
+ parameter [11:0] PF3_DSN_CAP_NEXTPTR = 12'h10C;
+ parameter [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
+ parameter PF3_EXPANSION_ROM_ENABLE = "FALSE";
+ parameter [7:0] PF3_INTERRUPT_LINE = 8'h00;
+ parameter [2:0] PF3_INTERRUPT_PIN = 3'h1;
+ parameter [7:0] PF3_MSIX_CAP_NEXTPTR = 8'h00;
+ parameter integer PF3_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] PF3_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer PF3_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] PF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] PF3_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter integer PF3_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] PF3_MSI_CAP_NEXTPTR = 8'h00;
+ parameter PF3_MSI_CAP_PERVECMASKCAP = "FALSE";
+ parameter [31:0] PF3_PB_CAP_DATA_REG_D0 = 32'h00000000;
+ parameter [31:0] PF3_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000;
+ parameter [31:0] PF3_PB_CAP_DATA_REG_D1 = 32'h00000000;
+ parameter [31:0] PF3_PB_CAP_DATA_REG_D3HOT = 32'h00000000;
+ parameter [11:0] PF3_PB_CAP_NEXTPTR = 12'h000;
+ parameter PF3_PB_CAP_SYSTEM_ALLOCATED = "FALSE";
+ parameter [3:0] PF3_PB_CAP_VER = 4'h1;
+ parameter [7:0] PF3_PM_CAP_ID = 8'h01;
+ parameter [7:0] PF3_PM_CAP_NEXTPTR = 8'h00;
+ parameter [2:0] PF3_PM_CAP_VER_ID = 3'h3;
+ parameter PF3_RBAR_CAP_ENABLE = "FALSE";
+ parameter [11:0] PF3_RBAR_CAP_NEXTPTR = 12'h000;
+ parameter [19:0] PF3_RBAR_CAP_SIZE0 = 20'h00000;
+ parameter [19:0] PF3_RBAR_CAP_SIZE1 = 20'h00000;
+ parameter [19:0] PF3_RBAR_CAP_SIZE2 = 20'h00000;
+ parameter [3:0] PF3_RBAR_CAP_VER = 4'h1;
+ parameter [2:0] PF3_RBAR_CONTROL_INDEX0 = 3'h0;
+ parameter [2:0] PF3_RBAR_CONTROL_INDEX1 = 3'h0;
+ parameter [2:0] PF3_RBAR_CONTROL_INDEX2 = 3'h0;
+ parameter [4:0] PF3_RBAR_CONTROL_SIZE0 = 5'h00;
+ parameter [4:0] PF3_RBAR_CONTROL_SIZE1 = 5'h00;
+ parameter [4:0] PF3_RBAR_CONTROL_SIZE2 = 5'h00;
+ parameter [2:0] PF3_RBAR_NUM = 3'h1;
+ parameter [7:0] PF3_REVISION_ID = 8'h00;
+ parameter [4:0] PF3_SRIOV_BAR0_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF3_SRIOV_BAR0_CONTROL = 3'h4;
+ parameter [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
+ parameter [2:0] PF3_SRIOV_BAR1_CONTROL = 3'h0;
+ parameter [4:0] PF3_SRIOV_BAR2_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF3_SRIOV_BAR2_CONTROL = 3'h4;
+ parameter [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF3_SRIOV_BAR3_CONTROL = 3'h0;
+ parameter [4:0] PF3_SRIOV_BAR4_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF3_SRIOV_BAR4_CONTROL = 3'h4;
+ parameter [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
+ parameter [2:0] PF3_SRIOV_BAR5_CONTROL = 3'h0;
+ parameter [15:0] PF3_SRIOV_CAP_INITIAL_VF = 16'h0000;
+ parameter [11:0] PF3_SRIOV_CAP_NEXTPTR = 12'h000;
+ parameter [15:0] PF3_SRIOV_CAP_TOTAL_VF = 16'h0000;
+ parameter [3:0] PF3_SRIOV_CAP_VER = 4'h1;
+ parameter [15:0] PF3_SRIOV_FIRST_VF_OFFSET = 16'h0000;
+ parameter [15:0] PF3_SRIOV_FUNC_DEP_LINK = 16'h0000;
+ parameter [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
+ parameter [15:0] PF3_SRIOV_VF_DEVICE_ID = 16'h0000;
+ parameter [15:0] PF3_SUBSYSTEM_ID = 16'h0000;
+ parameter PF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
+ parameter PF3_TPHR_CAP_ENABLE = "FALSE";
+ parameter PF3_TPHR_CAP_INT_VEC_MODE = "TRUE";
+ parameter [11:0] PF3_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] PF3_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [1:0] PF3_TPHR_CAP_ST_TABLE_LOC = 2'h0;
+ parameter [10:0] PF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
+ parameter [3:0] PF3_TPHR_CAP_VER = 4'h1;
+ parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 = "FALSE";
+ parameter PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 = "FALSE";
+ parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE";
+ parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE";
+ parameter PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP = "TRUE";
+ parameter PL_DISABLE_RETRAIN_ON_FRAMING_ERROR = "FALSE";
+ parameter PL_DISABLE_SCRAMBLING = "FALSE";
+ parameter PL_DISABLE_SYNC_HEADER_FRAMING_ERROR = "FALSE";
+ parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE";
+ parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE";
+ parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE";
+ parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02;
+ parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1;
+ parameter PL_EQ_BYPASS_PHASE23 = "FALSE";
+ parameter [2:0] PL_EQ_DEFAULT_GEN3_RX_PRESET_HINT = 3'h3;
+ parameter [3:0] PL_EQ_DEFAULT_GEN3_TX_PRESET = 4'h4;
+ parameter PL_EQ_PHASE01_RX_ADAPT = "FALSE";
+ parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE";
+ parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h3F00;
+ parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h3F00;
+ parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h3F00;
+ parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h3F00;
+ parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h3F00;
+ parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h3F00;
+ parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h3F00;
+ parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h3F00;
+ parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4;
+ parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h8;
+ parameter integer PL_N_FTS_COMCLK_GEN1 = 255;
+ parameter integer PL_N_FTS_COMCLK_GEN2 = 255;
+ parameter integer PL_N_FTS_COMCLK_GEN3 = 255;
+ parameter integer PL_N_FTS_GEN1 = 255;
+ parameter integer PL_N_FTS_GEN2 = 255;
+ parameter integer PL_N_FTS_GEN3 = 255;
+ parameter PL_REPORT_ALL_PHY_ERRORS = "TRUE";
+ parameter PL_SIM_FAST_LINK_TRAINING = "FALSE";
+ parameter PL_UPSTREAM_FACING = "TRUE";
+ parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h05DC;
+ parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h00000;
+ parameter PM_ENABLE_L23_ENTRY = "FALSE";
+ parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE";
+ parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000000;
+ parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h186A0;
+ parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0064;
+ parameter [31:0] SIM_JTAG_IDCODE = 32'h00000000;
+ parameter SIM_VERSION = "1.0";
+ parameter integer SPARE_BIT0 = 0;
+ parameter integer SPARE_BIT1 = 0;
+ parameter integer SPARE_BIT2 = 0;
+ parameter integer SPARE_BIT3 = 0;
+ parameter integer SPARE_BIT4 = 0;
+ parameter integer SPARE_BIT5 = 0;
+ parameter integer SPARE_BIT6 = 0;
+ parameter integer SPARE_BIT7 = 0;
+ parameter integer SPARE_BIT8 = 0;
+ parameter [7:0] SPARE_BYTE0 = 8'h00;
+ parameter [7:0] SPARE_BYTE1 = 8'h00;
+ parameter [7:0] SPARE_BYTE2 = 8'h00;
+ parameter [7:0] SPARE_BYTE3 = 8'h00;
+ parameter [31:0] SPARE_WORD0 = 32'h00000000;
+ parameter [31:0] SPARE_WORD1 = 32'h00000000;
+ parameter [31:0] SPARE_WORD2 = 32'h00000000;
+ parameter [31:0] SPARE_WORD3 = 32'h00000000;
+ parameter SRIOV_CAP_ENABLE = "FALSE";
+ parameter TL_COMPLETION_RAM_SIZE_16K = "TRUE";
+ parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'hBEBC20;
+ parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h2FAF080;
+ parameter [11:0] TL_CREDITS_CD = 12'h3E0;
+ parameter [7:0] TL_CREDITS_CH = 8'h20;
+ parameter [11:0] TL_CREDITS_NPD = 12'h028;
+ parameter [7:0] TL_CREDITS_NPH = 8'h20;
+ parameter [11:0] TL_CREDITS_PD = 12'h198;
+ parameter [7:0] TL_CREDITS_PH = 8'h20;
+ parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "TRUE";
+ parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE";
+ parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE";
+ parameter TL_LEGACY_MODE_ENABLE = "FALSE";
+ parameter [1:0] TL_PF_ENABLE_REG = 2'h0;
+ parameter TL_TX_MUX_STRICT_PRIORITY = "TRUE";
+ parameter TWO_LAYER_MODE_DLCMSM_ENABLE = "TRUE";
+ parameter TWO_LAYER_MODE_ENABLE = "FALSE";
+ parameter TWO_LAYER_MODE_WIDTH_256 = "TRUE";
+ parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h000;
+ parameter [7:0] VF0_CAPABILITY_POINTER = 8'h50;
+ parameter integer VF0_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer VF0_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter integer VF0_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] VF0_PM_CAP_ID = 8'h01;
+ parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h00;
+ parameter [2:0] VF0_PM_CAP_VER_ID = 3'h3;
+ parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
+ parameter VF0_TPHR_CAP_ENABLE = "FALSE";
+ parameter VF0_TPHR_CAP_INT_VEC_MODE = "TRUE";
+ parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 2'h0;
+ parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
+ parameter [3:0] VF0_TPHR_CAP_VER = 4'h1;
+ parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h000;
+ parameter integer VF1_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer VF1_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter integer VF1_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] VF1_PM_CAP_ID = 8'h01;
+ parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h00;
+ parameter [2:0] VF1_PM_CAP_VER_ID = 3'h3;
+ parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
+ parameter VF1_TPHR_CAP_ENABLE = "FALSE";
+ parameter VF1_TPHR_CAP_INT_VEC_MODE = "TRUE";
+ parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 2'h0;
+ parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
+ parameter [3:0] VF1_TPHR_CAP_VER = 4'h1;
+ parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h000;
+ parameter integer VF2_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer VF2_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter integer VF2_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] VF2_PM_CAP_ID = 8'h01;
+ parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h00;
+ parameter [2:0] VF2_PM_CAP_VER_ID = 3'h3;
+ parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
+ parameter VF2_TPHR_CAP_ENABLE = "FALSE";
+ parameter VF2_TPHR_CAP_INT_VEC_MODE = "TRUE";
+ parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 2'h0;
+ parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
+ parameter [3:0] VF2_TPHR_CAP_VER = 4'h1;
+ parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h000;
+ parameter integer VF3_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer VF3_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter integer VF3_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] VF3_PM_CAP_ID = 8'h01;
+ parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h00;
+ parameter [2:0] VF3_PM_CAP_VER_ID = 3'h3;
+ parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
+ parameter VF3_TPHR_CAP_ENABLE = "FALSE";
+ parameter VF3_TPHR_CAP_INT_VEC_MODE = "TRUE";
+ parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 2'h0;
+ parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
+ parameter [3:0] VF3_TPHR_CAP_VER = 4'h1;
+ parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h000;
+ parameter integer VF4_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer VF4_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter integer VF4_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] VF4_PM_CAP_ID = 8'h01;
+ parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h00;
+ parameter [2:0] VF4_PM_CAP_VER_ID = 3'h3;
+ parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
+ parameter VF4_TPHR_CAP_ENABLE = "FALSE";
+ parameter VF4_TPHR_CAP_INT_VEC_MODE = "TRUE";
+ parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 2'h0;
+ parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
+ parameter [3:0] VF4_TPHR_CAP_VER = 4'h1;
+ parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h000;
+ parameter integer VF5_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer VF5_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter integer VF5_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] VF5_PM_CAP_ID = 8'h01;
+ parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h00;
+ parameter [2:0] VF5_PM_CAP_VER_ID = 3'h3;
+ parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
+ parameter VF5_TPHR_CAP_ENABLE = "FALSE";
+ parameter VF5_TPHR_CAP_INT_VEC_MODE = "TRUE";
+ parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 2'h0;
+ parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
+ parameter [3:0] VF5_TPHR_CAP_VER = 4'h1;
+ parameter [11:0] VF6_ARI_CAP_NEXTPTR = 12'h000;
+ parameter integer VF6_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] VF6_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer VF6_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] VF6_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] VF6_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter integer VF6_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] VF6_PM_CAP_ID = 8'h01;
+ parameter [7:0] VF6_PM_CAP_NEXTPTR = 8'h00;
+ parameter [2:0] VF6_PM_CAP_VER_ID = 3'h3;
+ parameter VF6_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
+ parameter VF6_TPHR_CAP_ENABLE = "FALSE";
+ parameter VF6_TPHR_CAP_INT_VEC_MODE = "TRUE";
+ parameter [11:0] VF6_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] VF6_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [1:0] VF6_TPHR_CAP_ST_TABLE_LOC = 2'h0;
+ parameter [10:0] VF6_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
+ parameter [3:0] VF6_TPHR_CAP_VER = 4'h1;
+ parameter [11:0] VF7_ARI_CAP_NEXTPTR = 12'h000;
+ parameter integer VF7_MSIX_CAP_PBA_BIR = 0;
+ parameter [28:0] VF7_MSIX_CAP_PBA_OFFSET = 29'h00000050;
+ parameter integer VF7_MSIX_CAP_TABLE_BIR = 0;
+ parameter [28:0] VF7_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
+ parameter [10:0] VF7_MSIX_CAP_TABLE_SIZE = 11'h000;
+ parameter integer VF7_MSI_CAP_MULTIMSGCAP = 0;
+ parameter [7:0] VF7_PM_CAP_ID = 8'h01;
+ parameter [7:0] VF7_PM_CAP_NEXTPTR = 8'h00;
+ parameter [2:0] VF7_PM_CAP_VER_ID = 3'h3;
+ parameter VF7_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
+ parameter VF7_TPHR_CAP_ENABLE = "FALSE";
+ parameter VF7_TPHR_CAP_INT_VEC_MODE = "TRUE";
+ parameter [11:0] VF7_TPHR_CAP_NEXTPTR = 12'h000;
+ parameter [2:0] VF7_TPHR_CAP_ST_MODE_SEL = 3'h0;
+ parameter [1:0] VF7_TPHR_CAP_ST_TABLE_LOC = 2'h0;
+ parameter [10:0] VF7_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
+ parameter [3:0] VF7_TPHR_CAP_VER = 4'h1;
+ output [2:0] CFGCURRENTSPEED;
+ output [3:0] CFGDPASUBSTATECHANGE;
+ output CFGERRCOROUT;
+ output CFGERRFATALOUT;
+ output CFGERRNONFATALOUT;
+ output [7:0] CFGEXTFUNCTIONNUMBER;
+ output CFGEXTREADRECEIVED;
+ output [9:0] CFGEXTREGISTERNUMBER;
+ output [3:0] CFGEXTWRITEBYTEENABLE;
+ output [31:0] CFGEXTWRITEDATA;
+ output CFGEXTWRITERECEIVED;
+ output [11:0] CFGFCCPLD;
+ output [7:0] CFGFCCPLH;
+ output [11:0] CFGFCNPD;
+ output [7:0] CFGFCNPH;
+ output [11:0] CFGFCPD;
+ output [7:0] CFGFCPH;
+ output [3:0] CFGFLRINPROCESS;
+ output [11:0] CFGFUNCTIONPOWERSTATE;
+ output [15:0] CFGFUNCTIONSTATUS;
+ output CFGHOTRESETOUT;
+ output [31:0] CFGINTERRUPTMSIDATA;
+ output [3:0] CFGINTERRUPTMSIENABLE;
+ output CFGINTERRUPTMSIFAIL;
+ output CFGINTERRUPTMSIMASKUPDATE;
+ output [11:0] CFGINTERRUPTMSIMMENABLE;
+ output CFGINTERRUPTMSISENT;
+ output [7:0] CFGINTERRUPTMSIVFENABLE;
+ output [3:0] CFGINTERRUPTMSIXENABLE;
+ output CFGINTERRUPTMSIXFAIL;
+ output [3:0] CFGINTERRUPTMSIXMASK;
+ output CFGINTERRUPTMSIXSENT;
+ output [7:0] CFGINTERRUPTMSIXVFENABLE;
+ output [7:0] CFGINTERRUPTMSIXVFMASK;
+ output CFGINTERRUPTSENT;
+ output [1:0] CFGLINKPOWERSTATE;
+ output CFGLOCALERROR;
+ output CFGLTRENABLE;
+ output [5:0] CFGLTSSMSTATE;
+ output [2:0] CFGMAXPAYLOAD;
+ output [2:0] CFGMAXREADREQ;
+ output [31:0] CFGMGMTREADDATA;
+ output CFGMGMTREADWRITEDONE;
+ output CFGMSGRECEIVED;
+ output [7:0] CFGMSGRECEIVEDDATA;
+ output [4:0] CFGMSGRECEIVEDTYPE;
+ output CFGMSGTRANSMITDONE;
+ output [3:0] CFGNEGOTIATEDWIDTH;
+ output [1:0] CFGOBFFENABLE;
+ output [15:0] CFGPERFUNCSTATUSDATA;
+ output CFGPERFUNCTIONUPDATEDONE;
+ output CFGPHYLINKDOWN;
+ output [1:0] CFGPHYLINKSTATUS;
+ output CFGPLSTATUSCHANGE;
+ output CFGPOWERSTATECHANGEINTERRUPT;
+ output [3:0] CFGRCBSTATUS;
+ output [3:0] CFGTPHFUNCTIONNUM;
+ output [3:0] CFGTPHREQUESTERENABLE;
+ output [11:0] CFGTPHSTMODE;
+ output [4:0] CFGTPHSTTADDRESS;
+ output CFGTPHSTTREADENABLE;
+ output [3:0] CFGTPHSTTWRITEBYTEVALID;
+ output [31:0] CFGTPHSTTWRITEDATA;
+ output CFGTPHSTTWRITEENABLE;
+ output [7:0] CFGVFFLRINPROCESS;
+ output [23:0] CFGVFPOWERSTATE;
+ output [15:0] CFGVFSTATUS;
+ output [7:0] CFGVFTPHREQUESTERENABLE;
+ output [23:0] CFGVFTPHSTMODE;
+ output CONFMCAPDESIGNSWITCH;
+ output CONFMCAPEOS;
+ output CONFMCAPINUSEBYPCIE;
+ output CONFREQREADY;
+ output [31:0] CONFRESPRDATA;
+ output CONFRESPVALID;
+ output [15:0] DBGDATAOUT;
+ output DBGMCAPCSB;
+ output [31:0] DBGMCAPDATA;
+ output DBGMCAPEOS;
+ output DBGMCAPERROR;
+ output DBGMCAPMODE;
+ output DBGMCAPRDATAVALID;
+ output DBGMCAPRDWRB;
+ output DBGMCAPRESET;
+ output DBGPLDATABLOCKRECEIVEDAFTEREDS;
+ output DBGPLGEN3FRAMINGERRORDETECTED;
+ output DBGPLGEN3SYNCHEADERERRORDETECTED;
+ output [7:0] DBGPLINFERREDRXELECTRICALIDLE;
+ output [15:0] DRPDO;
+ output DRPRDY;
+ output LL2LMMASTERTLPSENT0;
+ output LL2LMMASTERTLPSENT1;
+ output [3:0] LL2LMMASTERTLPSENTTLPID0;
+ output [3:0] LL2LMMASTERTLPSENTTLPID1;
+ output [255:0] LL2LMMAXISRXTDATA;
+ output [17:0] LL2LMMAXISRXTUSER;
+ output [7:0] LL2LMMAXISRXTVALID;
+ output [7:0] LL2LMSAXISTXTREADY;
+ output [255:0] MAXISCQTDATA;
+ output [7:0] MAXISCQTKEEP;
+ output MAXISCQTLAST;
+ output [84:0] MAXISCQTUSER;
+ output MAXISCQTVALID;
+ output [255:0] MAXISRCTDATA;
+ output [7:0] MAXISRCTKEEP;
+ output MAXISRCTLAST;
+ output [74:0] MAXISRCTUSER;
+ output MAXISRCTVALID;
+ output [9:0] MICOMPLETIONRAMREADADDRESSAL;
+ output [9:0] MICOMPLETIONRAMREADADDRESSAU;
+ output [9:0] MICOMPLETIONRAMREADADDRESSBL;
+ output [9:0] MICOMPLETIONRAMREADADDRESSBU;
+ output [3:0] MICOMPLETIONRAMREADENABLEL;
+ output [3:0] MICOMPLETIONRAMREADENABLEU;
+ output [9:0] MICOMPLETIONRAMWRITEADDRESSAL;
+ output [9:0] MICOMPLETIONRAMWRITEADDRESSAU;
+ output [9:0] MICOMPLETIONRAMWRITEADDRESSBL;
+ output [9:0] MICOMPLETIONRAMWRITEADDRESSBU;
+ output [71:0] MICOMPLETIONRAMWRITEDATAL;
+ output [71:0] MICOMPLETIONRAMWRITEDATAU;
+ output [3:0] MICOMPLETIONRAMWRITEENABLEL;
+ output [3:0] MICOMPLETIONRAMWRITEENABLEU;
+ output [8:0] MIREPLAYRAMADDRESS;
+ output [1:0] MIREPLAYRAMREADENABLE;
+ output [143:0] MIREPLAYRAMWRITEDATA;
+ output [1:0] MIREPLAYRAMWRITEENABLE;
+ output [8:0] MIREQUESTRAMREADADDRESSA;
+ output [8:0] MIREQUESTRAMREADADDRESSB;
+ output [3:0] MIREQUESTRAMREADENABLE;
+ output [8:0] MIREQUESTRAMWRITEADDRESSA;
+ output [8:0] MIREQUESTRAMWRITEADDRESSB;
+ output [143:0] MIREQUESTRAMWRITEDATA;
+ output [3:0] MIREQUESTRAMWRITEENABLE;
+ output [5:0] PCIECQNPREQCOUNT;
+ output PCIEPERST0B;
+ output PCIEPERST1B;
+ output [3:0] PCIERQSEQNUM;
+ output PCIERQSEQNUMVLD;
+ output [5:0] PCIERQTAG;
+ output [1:0] PCIERQTAGAV;
+ output PCIERQTAGVLD;
+ output [1:0] PCIETFCNPDAV;
+ output [1:0] PCIETFCNPHAV;
+ output [1:0] PIPERX0EQCONTROL;
+ output [5:0] PIPERX0EQLPLFFS;
+ output [3:0] PIPERX0EQLPTXPRESET;
+ output [2:0] PIPERX0EQPRESET;
+ output PIPERX0POLARITY;
+ output [1:0] PIPERX1EQCONTROL;
+ output [5:0] PIPERX1EQLPLFFS;
+ output [3:0] PIPERX1EQLPTXPRESET;
+ output [2:0] PIPERX1EQPRESET;
+ output PIPERX1POLARITY;
+ output [1:0] PIPERX2EQCONTROL;
+ output [5:0] PIPERX2EQLPLFFS;
+ output [3:0] PIPERX2EQLPTXPRESET;
+ output [2:0] PIPERX2EQPRESET;
+ output PIPERX2POLARITY;
+ output [1:0] PIPERX3EQCONTROL;
+ output [5:0] PIPERX3EQLPLFFS;
+ output [3:0] PIPERX3EQLPTXPRESET;
+ output [2:0] PIPERX3EQPRESET;
+ output PIPERX3POLARITY;
+ output [1:0] PIPERX4EQCONTROL;
+ output [5:0] PIPERX4EQLPLFFS;
+ output [3:0] PIPERX4EQLPTXPRESET;
+ output [2:0] PIPERX4EQPRESET;
+ output PIPERX4POLARITY;
+ output [1:0] PIPERX5EQCONTROL;
+ output [5:0] PIPERX5EQLPLFFS;
+ output [3:0] PIPERX5EQLPTXPRESET;
+ output [2:0] PIPERX5EQPRESET;
+ output PIPERX5POLARITY;
+ output [1:0] PIPERX6EQCONTROL;
+ output [5:0] PIPERX6EQLPLFFS;
+ output [3:0] PIPERX6EQLPTXPRESET;
+ output [2:0] PIPERX6EQPRESET;
+ output PIPERX6POLARITY;
+ output [1:0] PIPERX7EQCONTROL;
+ output [5:0] PIPERX7EQLPLFFS;
+ output [3:0] PIPERX7EQLPTXPRESET;
+ output [2:0] PIPERX7EQPRESET;
+ output PIPERX7POLARITY;
+ output [1:0] PIPETX0CHARISK;
+ output PIPETX0COMPLIANCE;
+ output [31:0] PIPETX0DATA;
+ output PIPETX0DATAVALID;
+ output PIPETX0DEEMPH;
+ output PIPETX0ELECIDLE;
+ output [1:0] PIPETX0EQCONTROL;
+ output [5:0] PIPETX0EQDEEMPH;
+ output [3:0] PIPETX0EQPRESET;
+ output [2:0] PIPETX0MARGIN;
+ output [1:0] PIPETX0POWERDOWN;
+ output [1:0] PIPETX0RATE;
+ output PIPETX0RCVRDET;
+ output PIPETX0RESET;
+ output PIPETX0STARTBLOCK;
+ output PIPETX0SWING;
+ output [1:0] PIPETX0SYNCHEADER;
+ output [1:0] PIPETX1CHARISK;
+ output PIPETX1COMPLIANCE;
+ output [31:0] PIPETX1DATA;
+ output PIPETX1DATAVALID;
+ output PIPETX1DEEMPH;
+ output PIPETX1ELECIDLE;
+ output [1:0] PIPETX1EQCONTROL;
+ output [5:0] PIPETX1EQDEEMPH;
+ output [3:0] PIPETX1EQPRESET;
+ output [2:0] PIPETX1MARGIN;
+ output [1:0] PIPETX1POWERDOWN;
+ output [1:0] PIPETX1RATE;
+ output PIPETX1RCVRDET;
+ output PIPETX1RESET;
+ output PIPETX1STARTBLOCK;
+ output PIPETX1SWING;
+ output [1:0] PIPETX1SYNCHEADER;
+ output [1:0] PIPETX2CHARISK;
+ output PIPETX2COMPLIANCE;
+ output [31:0] PIPETX2DATA;
+ output PIPETX2DATAVALID;
+ output PIPETX2DEEMPH;
+ output PIPETX2ELECIDLE;
+ output [1:0] PIPETX2EQCONTROL;
+ output [5:0] PIPETX2EQDEEMPH;
+ output [3:0] PIPETX2EQPRESET;
+ output [2:0] PIPETX2MARGIN;
+ output [1:0] PIPETX2POWERDOWN;
+ output [1:0] PIPETX2RATE;
+ output PIPETX2RCVRDET;
+ output PIPETX2RESET;
+ output PIPETX2STARTBLOCK;
+ output PIPETX2SWING;
+ output [1:0] PIPETX2SYNCHEADER;
+ output [1:0] PIPETX3CHARISK;
+ output PIPETX3COMPLIANCE;
+ output [31:0] PIPETX3DATA;
+ output PIPETX3DATAVALID;
+ output PIPETX3DEEMPH;
+ output PIPETX3ELECIDLE;
+ output [1:0] PIPETX3EQCONTROL;
+ output [5:0] PIPETX3EQDEEMPH;
+ output [3:0] PIPETX3EQPRESET;
+ output [2:0] PIPETX3MARGIN;
+ output [1:0] PIPETX3POWERDOWN;
+ output [1:0] PIPETX3RATE;
+ output PIPETX3RCVRDET;
+ output PIPETX3RESET;
+ output PIPETX3STARTBLOCK;
+ output PIPETX3SWING;
+ output [1:0] PIPETX3SYNCHEADER;
+ output [1:0] PIPETX4CHARISK;
+ output PIPETX4COMPLIANCE;
+ output [31:0] PIPETX4DATA;
+ output PIPETX4DATAVALID;
+ output PIPETX4DEEMPH;
+ output PIPETX4ELECIDLE;
+ output [1:0] PIPETX4EQCONTROL;
+ output [5:0] PIPETX4EQDEEMPH;
+ output [3:0] PIPETX4EQPRESET;
+ output [2:0] PIPETX4MARGIN;
+ output [1:0] PIPETX4POWERDOWN;
+ output [1:0] PIPETX4RATE;
+ output PIPETX4RCVRDET;
+ output PIPETX4RESET;
+ output PIPETX4STARTBLOCK;
+ output PIPETX4SWING;
+ output [1:0] PIPETX4SYNCHEADER;
+ output [1:0] PIPETX5CHARISK;
+ output PIPETX5COMPLIANCE;
+ output [31:0] PIPETX5DATA;
+ output PIPETX5DATAVALID;
+ output PIPETX5DEEMPH;
+ output PIPETX5ELECIDLE;
+ output [1:0] PIPETX5EQCONTROL;
+ output [5:0] PIPETX5EQDEEMPH;
+ output [3:0] PIPETX5EQPRESET;
+ output [2:0] PIPETX5MARGIN;
+ output [1:0] PIPETX5POWERDOWN;
+ output [1:0] PIPETX5RATE;
+ output PIPETX5RCVRDET;
+ output PIPETX5RESET;
+ output PIPETX5STARTBLOCK;
+ output PIPETX5SWING;
+ output [1:0] PIPETX5SYNCHEADER;
+ output [1:0] PIPETX6CHARISK;
+ output PIPETX6COMPLIANCE;
+ output [31:0] PIPETX6DATA;
+ output PIPETX6DATAVALID;
+ output PIPETX6DEEMPH;
+ output PIPETX6ELECIDLE;
+ output [1:0] PIPETX6EQCONTROL;
+ output [5:0] PIPETX6EQDEEMPH;
+ output [3:0] PIPETX6EQPRESET;
+ output [2:0] PIPETX6MARGIN;
+ output [1:0] PIPETX6POWERDOWN;
+ output [1:0] PIPETX6RATE;
+ output PIPETX6RCVRDET;
+ output PIPETX6RESET;
+ output PIPETX6STARTBLOCK;
+ output PIPETX6SWING;
+ output [1:0] PIPETX6SYNCHEADER;
+ output [1:0] PIPETX7CHARISK;
+ output PIPETX7COMPLIANCE;
+ output [31:0] PIPETX7DATA;
+ output PIPETX7DATAVALID;
+ output PIPETX7DEEMPH;
+ output PIPETX7ELECIDLE;
+ output [1:0] PIPETX7EQCONTROL;
+ output [5:0] PIPETX7EQDEEMPH;
+ output [3:0] PIPETX7EQPRESET;
+ output [2:0] PIPETX7MARGIN;
+ output [1:0] PIPETX7POWERDOWN;
+ output [1:0] PIPETX7RATE;
+ output PIPETX7RCVRDET;
+ output PIPETX7RESET;
+ output PIPETX7STARTBLOCK;
+ output PIPETX7SWING;
+ output [1:0] PIPETX7SYNCHEADER;
+ output PLEQINPROGRESS;
+ output [1:0] PLEQPHASE;
+ output [3:0] SAXISCCTREADY;
+ output [3:0] SAXISRQTREADY;
+ output [31:0] SPAREOUT;
+ input CFGCONFIGSPACEENABLE;
+ input [15:0] CFGDEVID;
+ input [7:0] CFGDSBUSNUMBER;
+ input [4:0] CFGDSDEVICENUMBER;
+ input [2:0] CFGDSFUNCTIONNUMBER;
+ input [63:0] CFGDSN;
+ input [7:0] CFGDSPORTNUMBER;
+ input CFGERRCORIN;
+ input CFGERRUNCORIN;
+ input [31:0] CFGEXTREADDATA;
+ input CFGEXTREADDATAVALID;
+ input [2:0] CFGFCSEL;
+ input [3:0] CFGFLRDONE;
+ input CFGHOTRESETIN;
+ input [3:0] CFGINTERRUPTINT;
+ input [2:0] CFGINTERRUPTMSIATTR;
+ input [3:0] CFGINTERRUPTMSIFUNCTIONNUMBER;
+ input [31:0] CFGINTERRUPTMSIINT;
+ input [31:0] CFGINTERRUPTMSIPENDINGSTATUS;
+ input CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE;
+ input [3:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM;
+ input [3:0] CFGINTERRUPTMSISELECT;
+ input CFGINTERRUPTMSITPHPRESENT;
+ input [8:0] CFGINTERRUPTMSITPHSTTAG;
+ input [1:0] CFGINTERRUPTMSITPHTYPE;
+ input [63:0] CFGINTERRUPTMSIXADDRESS;
+ input [31:0] CFGINTERRUPTMSIXDATA;
+ input CFGINTERRUPTMSIXINT;
+ input [3:0] CFGINTERRUPTPENDING;
+ input CFGLINKTRAININGENABLE;
+ input [18:0] CFGMGMTADDR;
+ input [3:0] CFGMGMTBYTEENABLE;
+ input CFGMGMTREAD;
+ input CFGMGMTTYPE1CFGREGACCESS;
+ input CFGMGMTWRITE;
+ input [31:0] CFGMGMTWRITEDATA;
+ input CFGMSGTRANSMIT;
+ input [31:0] CFGMSGTRANSMITDATA;
+ input [2:0] CFGMSGTRANSMITTYPE;
+ input [2:0] CFGPERFUNCSTATUSCONTROL;
+ input [3:0] CFGPERFUNCTIONNUMBER;
+ input CFGPERFUNCTIONOUTPUTREQUEST;
+ input CFGPOWERSTATECHANGEACK;
+ input CFGREQPMTRANSITIONL23READY;
+ input [7:0] CFGREVID;
+ input [15:0] CFGSUBSYSID;
+ input [15:0] CFGSUBSYSVENDID;
+ input [31:0] CFGTPHSTTREADDATA;
+ input CFGTPHSTTREADDATAVALID;
+ input [15:0] CFGVENDID;
+ input [7:0] CFGVFFLRDONE;
+ input CONFMCAPREQUESTBYCONF;
+ input [31:0] CONFREQDATA;
+ input [3:0] CONFREQREGNUM;
+ input [1:0] CONFREQTYPE;
+ input CONFREQVALID;
+ input CORECLK;
+ input CORECLKMICOMPLETIONRAML;
+ input CORECLKMICOMPLETIONRAMU;
+ input CORECLKMIREPLAYRAM;
+ input CORECLKMIREQUESTRAM;
+ input DBGCFGLOCALMGMTREGOVERRIDE;
+ input [3:0] DBGDATASEL;
+ input [9:0] DRPADDR;
+ input DRPCLK;
+ input [15:0] DRPDI;
+ input DRPEN;
+ input DRPWE;
+ input [13:0] LL2LMSAXISTXTUSER;
+ input LL2LMSAXISTXTVALID;
+ input [3:0] LL2LMTXTLPID0;
+ input [3:0] LL2LMTXTLPID1;
+ input [21:0] MAXISCQTREADY;
+ input [21:0] MAXISRCTREADY;
+ input MCAPCLK;
+ input MCAPPERST0B;
+ input MCAPPERST1B;
+ input MGMTRESETN;
+ input MGMTSTICKYRESETN;
+ input [143:0] MICOMPLETIONRAMREADDATA;
+ input [143:0] MIREPLAYRAMREADDATA;
+ input [143:0] MIREQUESTRAMREADDATA;
+ input PCIECQNPREQ;
+ input PIPECLK;
+ input [5:0] PIPEEQFS;
+ input [5:0] PIPEEQLF;
+ input PIPERESETN;
+ input [1:0] PIPERX0CHARISK;
+ input [31:0] PIPERX0DATA;
+ input PIPERX0DATAVALID;
+ input PIPERX0ELECIDLE;
+ input PIPERX0EQDONE;
+ input PIPERX0EQLPADAPTDONE;
+ input PIPERX0EQLPLFFSSEL;
+ input [17:0] PIPERX0EQLPNEWTXCOEFFORPRESET;
+ input PIPERX0PHYSTATUS;
+ input PIPERX0STARTBLOCK;
+ input [2:0] PIPERX0STATUS;
+ input [1:0] PIPERX0SYNCHEADER;
+ input PIPERX0VALID;
+ input [1:0] PIPERX1CHARISK;
+ input [31:0] PIPERX1DATA;
+ input PIPERX1DATAVALID;
+ input PIPERX1ELECIDLE;
+ input PIPERX1EQDONE;
+ input PIPERX1EQLPADAPTDONE;
+ input PIPERX1EQLPLFFSSEL;
+ input [17:0] PIPERX1EQLPNEWTXCOEFFORPRESET;
+ input PIPERX1PHYSTATUS;
+ input PIPERX1STARTBLOCK;
+ input [2:0] PIPERX1STATUS;
+ input [1:0] PIPERX1SYNCHEADER;
+ input PIPERX1VALID;
+ input [1:0] PIPERX2CHARISK;
+ input [31:0] PIPERX2DATA;
+ input PIPERX2DATAVALID;
+ input PIPERX2ELECIDLE;
+ input PIPERX2EQDONE;
+ input PIPERX2EQLPADAPTDONE;
+ input PIPERX2EQLPLFFSSEL;
+ input [17:0] PIPERX2EQLPNEWTXCOEFFORPRESET;
+ input PIPERX2PHYSTATUS;
+ input PIPERX2STARTBLOCK;
+ input [2:0] PIPERX2STATUS;
+ input [1:0] PIPERX2SYNCHEADER;
+ input PIPERX2VALID;
+ input [1:0] PIPERX3CHARISK;
+ input [31:0] PIPERX3DATA;
+ input PIPERX3DATAVALID;
+ input PIPERX3ELECIDLE;
+ input PIPERX3EQDONE;
+ input PIPERX3EQLPADAPTDONE;
+ input PIPERX3EQLPLFFSSEL;
+ input [17:0] PIPERX3EQLPNEWTXCOEFFORPRESET;
+ input PIPERX3PHYSTATUS;
+ input PIPERX3STARTBLOCK;
+ input [2:0] PIPERX3STATUS;
+ input [1:0] PIPERX3SYNCHEADER;
+ input PIPERX3VALID;
+ input [1:0] PIPERX4CHARISK;
+ input [31:0] PIPERX4DATA;
+ input PIPERX4DATAVALID;
+ input PIPERX4ELECIDLE;
+ input PIPERX4EQDONE;
+ input PIPERX4EQLPADAPTDONE;
+ input PIPERX4EQLPLFFSSEL;
+ input [17:0] PIPERX4EQLPNEWTXCOEFFORPRESET;
+ input PIPERX4PHYSTATUS;
+ input PIPERX4STARTBLOCK;
+ input [2:0] PIPERX4STATUS;
+ input [1:0] PIPERX4SYNCHEADER;
+ input PIPERX4VALID;
+ input [1:0] PIPERX5CHARISK;
+ input [31:0] PIPERX5DATA;
+ input PIPERX5DATAVALID;
+ input PIPERX5ELECIDLE;
+ input PIPERX5EQDONE;
+ input PIPERX5EQLPADAPTDONE;
+ input PIPERX5EQLPLFFSSEL;
+ input [17:0] PIPERX5EQLPNEWTXCOEFFORPRESET;
+ input PIPERX5PHYSTATUS;
+ input PIPERX5STARTBLOCK;
+ input [2:0] PIPERX5STATUS;
+ input [1:0] PIPERX5SYNCHEADER;
+ input PIPERX5VALID;
+ input [1:0] PIPERX6CHARISK;
+ input [31:0] PIPERX6DATA;
+ input PIPERX6DATAVALID;
+ input PIPERX6ELECIDLE;
+ input PIPERX6EQDONE;
+ input PIPERX6EQLPADAPTDONE;
+ input PIPERX6EQLPLFFSSEL;
+ input [17:0] PIPERX6EQLPNEWTXCOEFFORPRESET;
+ input PIPERX6PHYSTATUS;
+ input PIPERX6STARTBLOCK;
+ input [2:0] PIPERX6STATUS;
+ input [1:0] PIPERX6SYNCHEADER;
+ input PIPERX6VALID;
+ input [1:0] PIPERX7CHARISK;
+ input [31:0] PIPERX7DATA;
+ input PIPERX7DATAVALID;
+ input PIPERX7ELECIDLE;
+ input PIPERX7EQDONE;
+ input PIPERX7EQLPADAPTDONE;
+ input PIPERX7EQLPLFFSSEL;
+ input [17:0] PIPERX7EQLPNEWTXCOEFFORPRESET;
+ input PIPERX7PHYSTATUS;
+ input PIPERX7STARTBLOCK;
+ input [2:0] PIPERX7STATUS;
+ input [1:0] PIPERX7SYNCHEADER;
+ input PIPERX7VALID;
+ input [17:0] PIPETX0EQCOEFF;
+ input PIPETX0EQDONE;
+ input [17:0] PIPETX1EQCOEFF;
+ input PIPETX1EQDONE;
+ input [17:0] PIPETX2EQCOEFF;
+ input PIPETX2EQDONE;
+ input [17:0] PIPETX3EQCOEFF;
+ input PIPETX3EQDONE;
+ input [17:0] PIPETX4EQCOEFF;
+ input PIPETX4EQDONE;
+ input [17:0] PIPETX5EQCOEFF;
+ input PIPETX5EQDONE;
+ input [17:0] PIPETX6EQCOEFF;
+ input PIPETX6EQDONE;
+ input [17:0] PIPETX7EQCOEFF;
+ input PIPETX7EQDONE;
+ input PLEQRESETEIEOSCOUNT;
+ input PLGEN2UPSTREAMPREFERDEEMPH;
+ input RESETN;
+ input [255:0] SAXISCCTDATA;
+ input [7:0] SAXISCCTKEEP;
+ input SAXISCCTLAST;
+ input [32:0] SAXISCCTUSER;
+ input SAXISCCTVALID;
+ input [255:0] SAXISRQTDATA;
+ input [7:0] SAXISRQTKEEP;
+ input SAXISRQTLAST;
+ input [59:0] SAXISRQTUSER;
+ input SAXISRQTVALID;
+ input [31:0] SPAREIN;
+ input USERCLK;
+endmodule
+
+module SYSMONE1 (...);
+ parameter [15:0] INIT_40 = 16'h0;
+ parameter [15:0] INIT_41 = 16'h0;
+ parameter [15:0] INIT_42 = 16'h0;
+ parameter [15:0] INIT_43 = 16'h0;
+ parameter [15:0] INIT_44 = 16'h0;
+ parameter [15:0] INIT_45 = 16'h0;
+ parameter [15:0] INIT_46 = 16'h0;
+ parameter [15:0] INIT_47 = 16'h0;
+ parameter [15:0] INIT_48 = 16'h0;
+ parameter [15:0] INIT_49 = 16'h0;
+ parameter [15:0] INIT_4A = 16'h0;
+ parameter [15:0] INIT_4B = 16'h0;
+ parameter [15:0] INIT_4C = 16'h0;
+ parameter [15:0] INIT_4D = 16'h0;
+ parameter [15:0] INIT_4E = 16'h0;
+ parameter [15:0] INIT_4F = 16'h0;
+ parameter [15:0] INIT_50 = 16'h0;
+ parameter [15:0] INIT_51 = 16'h0;
+ parameter [15:0] INIT_52 = 16'h0;
+ parameter [15:0] INIT_53 = 16'h0;
+ parameter [15:0] INIT_54 = 16'h0;
+ parameter [15:0] INIT_55 = 16'h0;
+ parameter [15:0] INIT_56 = 16'h0;
+ parameter [15:0] INIT_57 = 16'h0;
+ parameter [15:0] INIT_58 = 16'h0;
+ parameter [15:0] INIT_59 = 16'h0;
+ parameter [15:0] INIT_5A = 16'h0;
+ parameter [15:0] INIT_5B = 16'h0;
+ parameter [15:0] INIT_5C = 16'h0;
+ parameter [15:0] INIT_5D = 16'h0;
+ parameter [15:0] INIT_5E = 16'h0;
+ parameter [15:0] INIT_5F = 16'h0;
+ parameter [15:0] INIT_60 = 16'h0;
+ parameter [15:0] INIT_61 = 16'h0;
+ parameter [15:0] INIT_62 = 16'h0;
+ parameter [15:0] INIT_63 = 16'h0;
+ parameter [15:0] INIT_64 = 16'h0;
+ parameter [15:0] INIT_65 = 16'h0;
+ parameter [15:0] INIT_66 = 16'h0;
+ parameter [15:0] INIT_67 = 16'h0;
+ parameter [15:0] INIT_68 = 16'h0;
+ parameter [15:0] INIT_69 = 16'h0;
+ parameter [15:0] INIT_6A = 16'h0;
+ parameter [15:0] INIT_6B = 16'h0;
+ parameter [15:0] INIT_6C = 16'h0;
+ parameter [15:0] INIT_6D = 16'h0;
+ parameter [15:0] INIT_6E = 16'h0;
+ parameter [15:0] INIT_6F = 16'h0;
+ parameter [15:0] INIT_70 = 16'h0;
+ parameter [15:0] INIT_71 = 16'h0;
+ parameter [15:0] INIT_72 = 16'h0;
+ parameter [15:0] INIT_73 = 16'h0;
+ parameter [15:0] INIT_74 = 16'h0;
+ parameter [15:0] INIT_75 = 16'h0;
+ parameter [15:0] INIT_76 = 16'h0;
+ parameter [15:0] INIT_77 = 16'h0;
+ parameter [15:0] INIT_78 = 16'h0;
+ parameter [15:0] INIT_79 = 16'h0;
+ parameter [15:0] INIT_7A = 16'h0;
+ parameter [15:0] INIT_7B = 16'h0;
+ parameter [15:0] INIT_7C = 16'h0;
+ parameter [15:0] INIT_7D = 16'h0;
+ parameter [15:0] INIT_7E = 16'h0;
+ parameter [15:0] INIT_7F = 16'h0;
+ parameter [0:0] IS_CONVSTCLK_INVERTED = 1'b0;
+ parameter [0:0] IS_DCLK_INVERTED = 1'b0;
+ parameter SIM_MONITOR_FILE = "design.txt";
+ parameter integer SYSMON_VUSER0_BANK = 0;
+ parameter SYSMON_VUSER0_MONITOR = "NONE";
+ parameter integer SYSMON_VUSER1_BANK = 0;
+ parameter SYSMON_VUSER1_MONITOR = "NONE";
+ parameter integer SYSMON_VUSER2_BANK = 0;
+ parameter SYSMON_VUSER2_MONITOR = "NONE";
+ parameter integer SYSMON_VUSER3_BANK = 0;
+ parameter SYSMON_VUSER3_MONITOR = "NONE";
+ output [15:0] ALM;
+ output BUSY;
+ output [5:0] CHANNEL;
+ output [15:0] DO;
+ output DRDY;
+ output EOC;
+ output EOS;
+ output I2C_SCLK_TS;
+ output I2C_SDA_TS;
+ output JTAGBUSY;
+ output JTAGLOCKED;
+ output JTAGMODIFIED;
+ output [4:0] MUXADDR;
+ output OT;
+ input CONVST;
+ (* invertible_pin = "IS_CONVSTCLK_INVERTED" *)
+ input CONVSTCLK;
+ input [7:0] DADDR;
+ (* invertible_pin = "IS_DCLK_INVERTED" *)
+ input DCLK;
+ input DEN;
+ input [15:0] DI;
+ input DWE;
+ input I2C_SCLK;
+ input I2C_SDA;
+ input RESET;
+ input [15:0] VAUXN;
+ input [15:0] VAUXP;
+ input VN;
+ input VP;
+endmodule
+
+module SYSMONE4 (...);
+ parameter [15:0] COMMON_N_SOURCE = 16'hFFFF;
+ parameter [15:0] INIT_40 = 16'h0000;
+ parameter [15:0] INIT_41 = 16'h0000;
+ parameter [15:0] INIT_42 = 16'h0000;
+ parameter [15:0] INIT_43 = 16'h0000;
+ parameter [15:0] INIT_44 = 16'h0000;
+ parameter [15:0] INIT_45 = 16'h0000;
+ parameter [15:0] INIT_46 = 16'h0000;
+ parameter [15:0] INIT_47 = 16'h0000;
+ parameter [15:0] INIT_48 = 16'h0000;
+ parameter [15:0] INIT_49 = 16'h0000;
+ parameter [15:0] INIT_4A = 16'h0000;
+ parameter [15:0] INIT_4B = 16'h0000;
+ parameter [15:0] INIT_4C = 16'h0000;
+ parameter [15:0] INIT_4D = 16'h0000;
+ parameter [15:0] INIT_4E = 16'h0000;
+ parameter [15:0] INIT_4F = 16'h0000;
+ parameter [15:0] INIT_50 = 16'h0000;
+ parameter [15:0] INIT_51 = 16'h0000;
+ parameter [15:0] INIT_52 = 16'h0000;
+ parameter [15:0] INIT_53 = 16'h0000;
+ parameter [15:0] INIT_54 = 16'h0000;
+ parameter [15:0] INIT_55 = 16'h0000;
+ parameter [15:0] INIT_56 = 16'h0000;
+ parameter [15:0] INIT_57 = 16'h0000;
+ parameter [15:0] INIT_58 = 16'h0000;
+ parameter [15:0] INIT_59 = 16'h0000;
+ parameter [15:0] INIT_5A = 16'h0000;
+ parameter [15:0] INIT_5B = 16'h0000;
+ parameter [15:0] INIT_5C = 16'h0000;
+ parameter [15:0] INIT_5D = 16'h0000;
+ parameter [15:0] INIT_5E = 16'h0000;
+ parameter [15:0] INIT_5F = 16'h0000;
+ parameter [15:0] INIT_60 = 16'h0000;
+ parameter [15:0] INIT_61 = 16'h0000;
+ parameter [15:0] INIT_62 = 16'h0000;
+ parameter [15:0] INIT_63 = 16'h0000;
+ parameter [15:0] INIT_64 = 16'h0000;
+ parameter [15:0] INIT_65 = 16'h0000;
+ parameter [15:0] INIT_66 = 16'h0000;
+ parameter [15:0] INIT_67 = 16'h0000;
+ parameter [15:0] INIT_68 = 16'h0000;
+ parameter [15:0] INIT_69 = 16'h0000;
+ parameter [15:0] INIT_6A = 16'h0000;
+ parameter [15:0] INIT_6B = 16'h0000;
+ parameter [15:0] INIT_6C = 16'h0000;
+ parameter [15:0] INIT_6D = 16'h0000;
+ parameter [15:0] INIT_6E = 16'h0000;
+ parameter [15:0] INIT_6F = 16'h0000;
+ parameter [15:0] INIT_70 = 16'h0000;
+ parameter [15:0] INIT_71 = 16'h0000;
+ parameter [15:0] INIT_72 = 16'h0000;
+ parameter [15:0] INIT_73 = 16'h0000;
+ parameter [15:0] INIT_74 = 16'h0000;
+ parameter [15:0] INIT_75 = 16'h0000;
+ parameter [15:0] INIT_76 = 16'h0000;
+ parameter [15:0] INIT_77 = 16'h0000;
+ parameter [15:0] INIT_78 = 16'h0000;
+ parameter [15:0] INIT_79 = 16'h0000;
+ parameter [15:0] INIT_7A = 16'h0000;
+ parameter [15:0] INIT_7B = 16'h0000;
+ parameter [15:0] INIT_7C = 16'h0000;
+ parameter [15:0] INIT_7D = 16'h0000;
+ parameter [15:0] INIT_7E = 16'h0000;
+ parameter [15:0] INIT_7F = 16'h0000;
+ parameter [0:0] IS_CONVSTCLK_INVERTED = 1'b0;
+ parameter [0:0] IS_DCLK_INVERTED = 1'b0;
+ parameter SIM_DEVICE = "ULTRASCALE_PLUS";
+ parameter SIM_MONITOR_FILE = "design.txt";
+ parameter integer SYSMON_VUSER0_BANK = 0;
+ parameter SYSMON_VUSER0_MONITOR = "NONE";
+ parameter integer SYSMON_VUSER1_BANK = 0;
+ parameter SYSMON_VUSER1_MONITOR = "NONE";
+ parameter integer SYSMON_VUSER2_BANK = 0;
+ parameter SYSMON_VUSER2_MONITOR = "NONE";
+ parameter integer SYSMON_VUSER3_BANK = 0;
+ parameter SYSMON_VUSER3_MONITOR = "NONE";
+ output [15:0] ADC_DATA;
+ output [15:0] ALM;
+ output BUSY;
+ output [5:0] CHANNEL;
+ output [15:0] DO;
+ output DRDY;
+ output EOC;
+ output EOS;
+ output I2C_SCLK_TS;
+ output I2C_SDA_TS;
+ output JTAGBUSY;
+ output JTAGLOCKED;
+ output JTAGMODIFIED;
+ output [4:0] MUXADDR;
+ output OT;
+ output SMBALERT_TS;
+ input CONVST;
+ (* invertible_pin = "IS_CONVSTCLK_INVERTED" *)
+ input CONVSTCLK;
+ input [7:0] DADDR;
+ (* invertible_pin = "IS_DCLK_INVERTED" *)
+ input DCLK;
+ input DEN;
+ input [15:0] DI;
+ input DWE;
+ input I2C_SCLK;
+ input I2C_SDA;
+ input RESET;
+ input [15:0] VAUXN;
+ input [15:0] VAUXP;
+ input VN;
+ input VP;
+endmodule
+
+module DSP48E2 (...);
+ parameter integer ACASCREG = 1;
+ parameter integer ADREG = 1;
+ parameter integer ALUMODEREG = 1;
+ parameter AMULTSEL = "A";
+ parameter integer AREG = 1;
+ parameter AUTORESET_PATDET = "NO_RESET";
+ parameter AUTORESET_PRIORITY = "RESET";
+ parameter A_INPUT = "DIRECT";
+ parameter integer BCASCREG = 1;
+ parameter BMULTSEL = "B";
+ parameter integer BREG = 1;
+ parameter B_INPUT = "DIRECT";
+ parameter integer CARRYINREG = 1;
+ parameter integer CARRYINSELREG = 1;
+ parameter integer CREG = 1;
+ parameter integer DREG = 1;
+ parameter integer INMODEREG = 1;
+ parameter [3:0] IS_ALUMODE_INVERTED = 4'b0000;
+ parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ parameter [4:0] IS_INMODE_INVERTED = 5'b00000;
+ parameter [8:0] IS_OPMODE_INVERTED = 9'b000000000;
+ parameter [0:0] IS_RSTALLCARRYIN_INVERTED = 1'b0;
+ parameter [0:0] IS_RSTALUMODE_INVERTED = 1'b0;
+ parameter [0:0] IS_RSTA_INVERTED = 1'b0;
+ parameter [0:0] IS_RSTB_INVERTED = 1'b0;
+ parameter [0:0] IS_RSTCTRL_INVERTED = 1'b0;
+ parameter [0:0] IS_RSTC_INVERTED = 1'b0;
+ parameter [0:0] IS_RSTD_INVERTED = 1'b0;
+ parameter [0:0] IS_RSTINMODE_INVERTED = 1'b0;
+ parameter [0:0] IS_RSTM_INVERTED = 1'b0;
+ parameter [0:0] IS_RSTP_INVERTED = 1'b0;
+ parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
+ parameter integer MREG = 1;
+ parameter integer OPMODEREG = 1;
+ parameter [47:0] PATTERN = 48'h000000000000;
+ parameter PREADDINSEL = "A";
+ parameter integer PREG = 1;
+ parameter [47:0] RND = 48'h000000000000;
+ parameter SEL_MASK = "MASK";
+ parameter SEL_PATTERN = "PATTERN";
+ parameter USE_MULT = "MULTIPLY";
+ parameter USE_PATTERN_DETECT = "NO_PATDET";
+ parameter USE_SIMD = "ONE48";
+ parameter USE_WIDEXOR = "FALSE";
+ parameter XORSIMD = "XOR24_48_96";
+ output [29:0] ACOUT;
+ output [17:0] BCOUT;
+ output CARRYCASCOUT;
+ output [3:0] CARRYOUT;
+ output MULTSIGNOUT;
+ output OVERFLOW;
+ output [47:0] P;
+ output PATTERNBDETECT;
+ output PATTERNDETECT;
+ output [47:0] PCOUT;
+ output UNDERFLOW;
+ output [7:0] XOROUT;
+ input [29:0] A;
+ input [29:0] ACIN;
+ (* invertible_pin = "IS_ALUMODE_INVERTED" *)
+ input [3:0] ALUMODE;
+ input [17:0] B;
+ input [17:0] BCIN;
+ input [47:0] C;
+ input CARRYCASCIN;
+ (* invertible_pin = "IS_CARRYIN_INVERTED" *)
+ input CARRYIN;
+ input [2:0] CARRYINSEL;
+ input CEA1;
+ input CEA2;
+ input CEAD;
+ input CEALUMODE;
+ input CEB1;
+ input CEB2;
+ input CEC;
+ input CECARRYIN;
+ input CECTRL;
+ input CED;
+ input CEINMODE;
+ input CEM;
+ input CEP;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLK_INVERTED" *)
+ input CLK;
+ input [26:0] D;
+ (* invertible_pin = "IS_INMODE_INVERTED" *)
+ input [4:0] INMODE;
+ input MULTSIGNIN;
+ (* invertible_pin = "IS_OPMODE_INVERTED" *)
+ input [8:0] OPMODE;
+ input [47:0] PCIN;
+ (* invertible_pin = "IS_RSTA_INVERTED" *)
+ input RSTA;
+ (* invertible_pin = "IS_RSTALLCARRYIN_INVERTED" *)
+ input RSTALLCARRYIN;
+ (* invertible_pin = "IS_RSTALUMODE_INVERTED" *)
+ input RSTALUMODE;
+ (* invertible_pin = "IS_RSTB_INVERTED" *)
+ input RSTB;
+ (* invertible_pin = "IS_RSTC_INVERTED" *)
+ input RSTC;
+ (* invertible_pin = "IS_RSTCTRL_INVERTED" *)
+ input RSTCTRL;
+ (* invertible_pin = "IS_RSTD_INVERTED" *)
+ input RSTD;
+ (* invertible_pin = "IS_RSTINMODE_INVERTED" *)
+ input RSTINMODE;
+ (* invertible_pin = "IS_RSTM_INVERTED" *)
+ input RSTM;
+ (* invertible_pin = "IS_RSTP_INVERTED" *)
+ input RSTP;
+endmodule
+
+module FIFO18E2 (...);
+ parameter CASCADE_ORDER = "NONE";
+ parameter CLOCK_DOMAINS = "INDEPENDENT";
+ parameter FIRST_WORD_FALL_THROUGH = "FALSE";
+ parameter [35:0] INIT = 36'h000000000;
+ parameter [0:0] IS_RDCLK_INVERTED = 1'b0;
+ parameter [0:0] IS_RDEN_INVERTED = 1'b0;
+ parameter [0:0] IS_RSTREG_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_INVERTED = 1'b0;
+ parameter [0:0] IS_WRCLK_INVERTED = 1'b0;
+ parameter [0:0] IS_WREN_INVERTED = 1'b0;
+ parameter integer PROG_EMPTY_THRESH = 256;
+ parameter integer PROG_FULL_THRESH = 256;
+ parameter RDCOUNT_TYPE = "RAW_PNTR";
+ parameter integer READ_WIDTH = 4;
+ parameter REGISTER_MODE = "UNREGISTERED";
+ parameter RSTREG_PRIORITY = "RSTREG";
+ parameter SLEEP_ASYNC = "FALSE";
+ parameter [35:0] SRVAL = 36'h000000000;
+ parameter WRCOUNT_TYPE = "RAW_PNTR";
+ parameter integer WRITE_WIDTH = 4;
+ output [31:0] CASDOUT;
+ output [3:0] CASDOUTP;
+ output CASNXTEMPTY;
+ output CASPRVRDEN;
+ output [31:0] DOUT;
+ output [3:0] DOUTP;
+ output EMPTY;
+ output FULL;
+ output PROGEMPTY;
+ output PROGFULL;
+ output [12:0] RDCOUNT;
+ output RDERR;
+ output RDRSTBUSY;
+ output [12:0] WRCOUNT;
+ output WRERR;
+ output WRRSTBUSY;
+ input [31:0] CASDIN;
+ input [3:0] CASDINP;
+ input CASDOMUX;
+ input CASDOMUXEN;
+ input CASNXTRDEN;
+ input CASOREGIMUX;
+ input CASOREGIMUXEN;
+ input CASPRVEMPTY;
+ input [31:0] DIN;
+ input [3:0] DINP;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_RDCLK_INVERTED" *)
+ input RDCLK;
+ (* invertible_pin = "IS_RDEN_INVERTED" *)
+ input RDEN;
+ input REGCE;
+ (* invertible_pin = "IS_RST_INVERTED" *)
+ input RST;
+ (* invertible_pin = "IS_RSTREG_INVERTED" *)
+ input RSTREG;
+ input SLEEP;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WRCLK_INVERTED" *)
+ input WRCLK;
+ (* invertible_pin = "IS_WREN_INVERTED" *)
+ input WREN;
+endmodule
+
+module FIFO36E2 (...);
+ parameter CASCADE_ORDER = "NONE";
+ parameter CLOCK_DOMAINS = "INDEPENDENT";
+ parameter EN_ECC_PIPE = "FALSE";
+ parameter EN_ECC_READ = "FALSE";
+ parameter EN_ECC_WRITE = "FALSE";
+ parameter FIRST_WORD_FALL_THROUGH = "FALSE";
+ parameter [71:0] INIT = 72'h000000000000000000;
+ parameter [0:0] IS_RDCLK_INVERTED = 1'b0;
+ parameter [0:0] IS_RDEN_INVERTED = 1'b0;
+ parameter [0:0] IS_RSTREG_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_INVERTED = 1'b0;
+ parameter [0:0] IS_WRCLK_INVERTED = 1'b0;
+ parameter [0:0] IS_WREN_INVERTED = 1'b0;
+ parameter integer PROG_EMPTY_THRESH = 256;
+ parameter integer PROG_FULL_THRESH = 256;
+ parameter RDCOUNT_TYPE = "RAW_PNTR";
+ parameter integer READ_WIDTH = 4;
+ parameter REGISTER_MODE = "UNREGISTERED";
+ parameter RSTREG_PRIORITY = "RSTREG";
+ parameter SLEEP_ASYNC = "FALSE";
+ parameter [71:0] SRVAL = 72'h000000000000000000;
+ parameter WRCOUNT_TYPE = "RAW_PNTR";
+ parameter integer WRITE_WIDTH = 4;
+ output [63:0] CASDOUT;
+ output [7:0] CASDOUTP;
+ output CASNXTEMPTY;
+ output CASPRVRDEN;
+ output DBITERR;
+ output [63:0] DOUT;
+ output [7:0] DOUTP;
+ output [7:0] ECCPARITY;
+ output EMPTY;
+ output FULL;
+ output PROGEMPTY;
+ output PROGFULL;
+ output [13:0] RDCOUNT;
+ output RDERR;
+ output RDRSTBUSY;
+ output SBITERR;
+ output [13:0] WRCOUNT;
+ output WRERR;
+ output WRRSTBUSY;
+ input [63:0] CASDIN;
+ input [7:0] CASDINP;
+ input CASDOMUX;
+ input CASDOMUXEN;
+ input CASNXTRDEN;
+ input CASOREGIMUX;
+ input CASOREGIMUXEN;
+ input CASPRVEMPTY;
+ input [63:0] DIN;
+ input [7:0] DINP;
+ input INJECTDBITERR;
+ input INJECTSBITERR;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_RDCLK_INVERTED" *)
+ input RDCLK;
+ (* invertible_pin = "IS_RDEN_INVERTED" *)
+ input RDEN;
+ input REGCE;
+ (* invertible_pin = "IS_RST_INVERTED" *)
+ input RST;
+ (* invertible_pin = "IS_RSTREG_INVERTED" *)
+ input RSTREG;
+ input SLEEP;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WRCLK_INVERTED" *)
+ input WRCLK;
+ (* invertible_pin = "IS_WREN_INVERTED" *)
+ input WREN;
+endmodule
+
+module RAMB18E2 (...);
+ parameter CASCADE_ORDER_A = "NONE";
+ parameter CASCADE_ORDER_B = "NONE";
+ parameter CLOCK_DOMAINS = "INDEPENDENT";
+ parameter integer DOA_REG = 1;
+ parameter integer DOB_REG = 1;
+ parameter ENADDRENA = "FALSE";
+ parameter ENADDRENB = "FALSE";
+ parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [17:0] INIT_A = 18'h00000;
+ parameter [17:0] INIT_B = 18'h00000;
+ parameter INIT_FILE = "NONE";
+ parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0;
+ parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0;
+ parameter [0:0] IS_ENARDEN_INVERTED = 1'b0;
+ parameter [0:0] IS_ENBWREN_INVERTED = 1'b0;
+ parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0;
+ parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0;
+ parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0;
+ parameter [0:0] IS_RSTREGB_INVERTED = 1'b0;
+ parameter RDADDRCHANGEA = "FALSE";
+ parameter RDADDRCHANGEB = "FALSE";
+ parameter integer READ_WIDTH_A = 0;
+ parameter integer READ_WIDTH_B = 0;
+ parameter RSTREG_PRIORITY_A = "RSTREG";
+ parameter RSTREG_PRIORITY_B = "RSTREG";
+ parameter SIM_COLLISION_CHECK = "ALL";
+ parameter SLEEP_ASYNC = "FALSE";
+ parameter [17:0] SRVAL_A = 18'h00000;
+ parameter [17:0] SRVAL_B = 18'h00000;
+ parameter WRITE_MODE_A = "NO_CHANGE";
+ parameter WRITE_MODE_B = "NO_CHANGE";
+ parameter integer WRITE_WIDTH_A = 0;
+ parameter integer WRITE_WIDTH_B = 0;
+ output [15:0] CASDOUTA;
+ output [15:0] CASDOUTB;
+ output [1:0] CASDOUTPA;
+ output [1:0] CASDOUTPB;
+ output [15:0] DOUTADOUT;
+ output [15:0] DOUTBDOUT;
+ output [1:0] DOUTPADOUTP;
+ output [1:0] DOUTPBDOUTP;
+ input [13:0] ADDRARDADDR;
+ input [13:0] ADDRBWRADDR;
+ input ADDRENA;
+ input ADDRENB;
+ input CASDIMUXA;
+ input CASDIMUXB;
+ input [15:0] CASDINA;
+ input [15:0] CASDINB;
+ input [1:0] CASDINPA;
+ input [1:0] CASDINPB;
+ input CASDOMUXA;
+ input CASDOMUXB;
+ input CASDOMUXEN_A;
+ input CASDOMUXEN_B;
+ input CASOREGIMUXA;
+ input CASOREGIMUXB;
+ input CASOREGIMUXEN_A;
+ input CASOREGIMUXEN_B;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
+ input CLKARDCLK;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
+ input CLKBWRCLK;
+ input [15:0] DINADIN;
+ input [15:0] DINBDIN;
+ input [1:0] DINPADINP;
+ input [1:0] DINPBDINP;
+ (* invertible_pin = "IS_ENARDEN_INVERTED" *)
+ input ENARDEN;
+ (* invertible_pin = "IS_ENBWREN_INVERTED" *)
+ input ENBWREN;
+ input REGCEAREGCE;
+ input REGCEB;
+ (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
+ input RSTRAMARSTRAM;
+ (* invertible_pin = "IS_RSTRAMB_INVERTED" *)
+ input RSTRAMB;
+ (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
+ input RSTREGARSTREG;
+ (* invertible_pin = "IS_RSTREGB_INVERTED" *)
+ input RSTREGB;
+ input SLEEP;
+ input [1:0] WEA;
+ input [3:0] WEBWE;
+endmodule
+
+module RAMB36E2 (...);
+ parameter CASCADE_ORDER_A = "NONE";
+ parameter CASCADE_ORDER_B = "NONE";
+ parameter CLOCK_DOMAINS = "INDEPENDENT";
+ parameter integer DOA_REG = 1;
+ parameter integer DOB_REG = 1;
+ parameter ENADDRENA = "FALSE";
+ parameter ENADDRENB = "FALSE";
+ parameter EN_ECC_PIPE = "FALSE";
+ parameter EN_ECC_READ = "FALSE";
+ parameter EN_ECC_WRITE = "FALSE";
+ parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [35:0] INIT_A = 36'h000000000;
+ parameter [35:0] INIT_B = 36'h000000000;
+ parameter INIT_FILE = "NONE";
+ parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0;
+ parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0;
+ parameter [0:0] IS_ENARDEN_INVERTED = 1'b0;
+ parameter [0:0] IS_ENBWREN_INVERTED = 1'b0;
+ parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0;
+ parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0;
+ parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0;
+ parameter [0:0] IS_RSTREGB_INVERTED = 1'b0;
+ parameter RDADDRCHANGEA = "FALSE";
+ parameter RDADDRCHANGEB = "FALSE";
+ parameter integer READ_WIDTH_A = 0;
+ parameter integer READ_WIDTH_B = 0;
+ parameter RSTREG_PRIORITY_A = "RSTREG";
+ parameter RSTREG_PRIORITY_B = "RSTREG";
+ parameter SIM_COLLISION_CHECK = "ALL";
+ parameter SLEEP_ASYNC = "FALSE";
+ parameter [35:0] SRVAL_A = 36'h000000000;
+ parameter [35:0] SRVAL_B = 36'h000000000;
+ parameter WRITE_MODE_A = "NO_CHANGE";
+ parameter WRITE_MODE_B = "NO_CHANGE";
+ parameter integer WRITE_WIDTH_A = 0;
+ parameter integer WRITE_WIDTH_B = 0;
+ output [31:0] CASDOUTA;
+ output [31:0] CASDOUTB;
+ output [3:0] CASDOUTPA;
+ output [3:0] CASDOUTPB;
+ output CASOUTDBITERR;
+ output CASOUTSBITERR;
+ output DBITERR;
+ output [31:0] DOUTADOUT;
+ output [31:0] DOUTBDOUT;
+ output [3:0] DOUTPADOUTP;
+ output [3:0] DOUTPBDOUTP;
+ output [7:0] ECCPARITY;
+ output [8:0] RDADDRECC;
+ output SBITERR;
+ input [14:0] ADDRARDADDR;
+ input [14:0] ADDRBWRADDR;
+ input ADDRENA;
+ input ADDRENB;
+ input CASDIMUXA;
+ input CASDIMUXB;
+ input [31:0] CASDINA;
+ input [31:0] CASDINB;
+ input [3:0] CASDINPA;
+ input [3:0] CASDINPB;
+ input CASDOMUXA;
+ input CASDOMUXB;
+ input CASDOMUXEN_A;
+ input CASDOMUXEN_B;
+ input CASINDBITERR;
+ input CASINSBITERR;
+ input CASOREGIMUXA;
+ input CASOREGIMUXB;
+ input CASOREGIMUXEN_A;
+ input CASOREGIMUXEN_B;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
+ input CLKARDCLK;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
+ input CLKBWRCLK;
+ input [31:0] DINADIN;
+ input [31:0] DINBDIN;
+ input [3:0] DINPADINP;
+ input [3:0] DINPBDINP;
+ input ECCPIPECE;
+ (* invertible_pin = "IS_ENARDEN_INVERTED" *)
+ input ENARDEN;
+ (* invertible_pin = "IS_ENBWREN_INVERTED" *)
+ input ENBWREN;
+ input INJECTDBITERR;
+ input INJECTSBITERR;
+ input REGCEAREGCE;
+ input REGCEB;
+ (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
+ input RSTRAMARSTRAM;
+ (* invertible_pin = "IS_RSTRAMB_INVERTED" *)
+ input RSTRAMB;
+ (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
+ input RSTREGARSTREG;
+ (* invertible_pin = "IS_RSTREGB_INVERTED" *)
+ input RSTREGB;
+ input SLEEP;
+ input [3:0] WEA;
+ input [7:0] WEBWE;
+endmodule
+
+module URAM288 (...);
+ parameter integer AUTO_SLEEP_LATENCY = 8;
+ parameter integer AVG_CONS_INACTIVE_CYCLES = 10;
+ parameter BWE_MODE_A = "PARITY_INTERLEAVED";
+ parameter BWE_MODE_B = "PARITY_INTERLEAVED";
+ parameter CASCADE_ORDER_A = "NONE";
+ parameter CASCADE_ORDER_B = "NONE";
+ parameter EN_AUTO_SLEEP_MODE = "FALSE";
+ parameter EN_ECC_RD_A = "FALSE";
+ parameter EN_ECC_RD_B = "FALSE";
+ parameter EN_ECC_WR_A = "FALSE";
+ parameter EN_ECC_WR_B = "FALSE";
+ parameter IREG_PRE_A = "FALSE";
+ parameter IREG_PRE_B = "FALSE";
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ parameter [0:0] IS_EN_A_INVERTED = 1'b0;
+ parameter [0:0] IS_EN_B_INVERTED = 1'b0;
+ parameter [0:0] IS_RDB_WR_A_INVERTED = 1'b0;
+ parameter [0:0] IS_RDB_WR_B_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_A_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_B_INVERTED = 1'b0;
+ parameter MATRIX_ID = "NONE";
+ parameter integer NUM_UNIQUE_SELF_ADDR_A = 1;
+ parameter integer NUM_UNIQUE_SELF_ADDR_B = 1;
+ parameter integer NUM_URAM_IN_MATRIX = 1;
+ parameter OREG_A = "FALSE";
+ parameter OREG_B = "FALSE";
+ parameter OREG_ECC_A = "FALSE";
+ parameter OREG_ECC_B = "FALSE";
+ parameter REG_CAS_A = "FALSE";
+ parameter REG_CAS_B = "FALSE";
+ parameter RST_MODE_A = "SYNC";
+ parameter RST_MODE_B = "SYNC";
+ parameter [10:0] SELF_ADDR_A = 11'h000;
+ parameter [10:0] SELF_ADDR_B = 11'h000;
+ parameter [10:0] SELF_MASK_A = 11'h7FF;
+ parameter [10:0] SELF_MASK_B = 11'h7FF;
+ parameter USE_EXT_CE_A = "FALSE";
+ parameter USE_EXT_CE_B = "FALSE";
+ output [22:0] CAS_OUT_ADDR_A;
+ output [22:0] CAS_OUT_ADDR_B;
+ output [8:0] CAS_OUT_BWE_A;
+ output [8:0] CAS_OUT_BWE_B;
+ output CAS_OUT_DBITERR_A;
+ output CAS_OUT_DBITERR_B;
+ output [71:0] CAS_OUT_DIN_A;
+ output [71:0] CAS_OUT_DIN_B;
+ output [71:0] CAS_OUT_DOUT_A;
+ output [71:0] CAS_OUT_DOUT_B;
+ output CAS_OUT_EN_A;
+ output CAS_OUT_EN_B;
+ output CAS_OUT_RDACCESS_A;
+ output CAS_OUT_RDACCESS_B;
+ output CAS_OUT_RDB_WR_A;
+ output CAS_OUT_RDB_WR_B;
+ output CAS_OUT_SBITERR_A;
+ output CAS_OUT_SBITERR_B;
+ output DBITERR_A;
+ output DBITERR_B;
+ output [71:0] DOUT_A;
+ output [71:0] DOUT_B;
+ output RDACCESS_A;
+ output RDACCESS_B;
+ output SBITERR_A;
+ output SBITERR_B;
+ input [22:0] ADDR_A;
+ input [22:0] ADDR_B;
+ input [8:0] BWE_A;
+ input [8:0] BWE_B;
+ input [22:0] CAS_IN_ADDR_A;
+ input [22:0] CAS_IN_ADDR_B;
+ input [8:0] CAS_IN_BWE_A;
+ input [8:0] CAS_IN_BWE_B;
+ input CAS_IN_DBITERR_A;
+ input CAS_IN_DBITERR_B;
+ input [71:0] CAS_IN_DIN_A;
+ input [71:0] CAS_IN_DIN_B;
+ input [71:0] CAS_IN_DOUT_A;
+ input [71:0] CAS_IN_DOUT_B;
+ input CAS_IN_EN_A;
+ input CAS_IN_EN_B;
+ input CAS_IN_RDACCESS_A;
+ input CAS_IN_RDACCESS_B;
+ input CAS_IN_RDB_WR_A;
+ input CAS_IN_RDB_WR_B;
+ input CAS_IN_SBITERR_A;
+ input CAS_IN_SBITERR_B;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLK_INVERTED" *)
+ input CLK;
+ input [71:0] DIN_A;
+ input [71:0] DIN_B;
+ (* invertible_pin = "IS_EN_A_INVERTED" *)
+ input EN_A;
+ (* invertible_pin = "IS_EN_B_INVERTED" *)
+ input EN_B;
+ input INJECT_DBITERR_A;
+ input INJECT_DBITERR_B;
+ input INJECT_SBITERR_A;
+ input INJECT_SBITERR_B;
+ input OREG_CE_A;
+ input OREG_CE_B;
+ input OREG_ECC_CE_A;
+ input OREG_ECC_CE_B;
+ (* invertible_pin = "IS_RDB_WR_A_INVERTED" *)
+ input RDB_WR_A;
+ (* invertible_pin = "IS_RDB_WR_B_INVERTED" *)
+ input RDB_WR_B;
+ (* invertible_pin = "IS_RST_A_INVERTED" *)
+ input RST_A;
+ (* invertible_pin = "IS_RST_B_INVERTED" *)
+ input RST_B;
+ input SLEEP;
+endmodule
+
+module URAM288_BASE (...);
+ parameter integer AUTO_SLEEP_LATENCY = 8;
+ parameter integer AVG_CONS_INACTIVE_CYCLES = 10;
+ parameter BWE_MODE_A = "PARITY_INTERLEAVED";
+ parameter BWE_MODE_B = "PARITY_INTERLEAVED";
+ parameter EN_AUTO_SLEEP_MODE = "FALSE";
+ parameter EN_ECC_RD_A = "FALSE";
+ parameter EN_ECC_RD_B = "FALSE";
+ parameter EN_ECC_WR_A = "FALSE";
+ parameter EN_ECC_WR_B = "FALSE";
+ parameter IREG_PRE_A = "FALSE";
+ parameter IREG_PRE_B = "FALSE";
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ parameter [0:0] IS_EN_A_INVERTED = 1'b0;
+ parameter [0:0] IS_EN_B_INVERTED = 1'b0;
+ parameter [0:0] IS_RDB_WR_A_INVERTED = 1'b0;
+ parameter [0:0] IS_RDB_WR_B_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_A_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_B_INVERTED = 1'b0;
+ parameter OREG_A = "FALSE";
+ parameter OREG_B = "FALSE";
+ parameter OREG_ECC_A = "FALSE";
+ parameter OREG_ECC_B = "FALSE";
+ parameter RST_MODE_A = "SYNC";
+ parameter RST_MODE_B = "SYNC";
+ parameter USE_EXT_CE_A = "FALSE";
+ parameter USE_EXT_CE_B = "FALSE";
+ output DBITERR_A;
+ output DBITERR_B;
+ output [71:0] DOUT_A;
+ output [71:0] DOUT_B;
+ output SBITERR_A;
+ output SBITERR_B;
+ input [22:0] ADDR_A;
+ input [22:0] ADDR_B;
+ input [8:0] BWE_A;
+ input [8:0] BWE_B;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLK_INVERTED" *)
+ input CLK;
+ input [71:0] DIN_A;
+ input [71:0] DIN_B;
+ (* invertible_pin = "IS_EN_A_INVERTED" *)
+ input EN_A;
+ (* invertible_pin = "IS_EN_B_INVERTED" *)
+ input EN_B;
+ input INJECT_DBITERR_A;
+ input INJECT_DBITERR_B;
+ input INJECT_SBITERR_A;
+ input INJECT_SBITERR_B;
+ input OREG_CE_A;
+ input OREG_CE_B;
+ input OREG_ECC_CE_A;
+ input OREG_ECC_CE_B;
+ (* invertible_pin = "IS_RDB_WR_A_INVERTED" *)
+ input RDB_WR_A;
+ (* invertible_pin = "IS_RDB_WR_B_INVERTED" *)
+ input RDB_WR_B;
+ (* invertible_pin = "IS_RST_A_INVERTED" *)
+ input RST_A;
+ (* invertible_pin = "IS_RST_B_INVERTED" *)
+ input RST_B;
+ input SLEEP;
+endmodule
+
+module RAM128X1S (...);
+ parameter [127:0] INIT = 128'h00000000000000000000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input A5;
+ input A6;
+ input D;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM256X1D (...);
+ parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output DPO;
+ output SPO;
+ input [7:0] A;
+ input D;
+ input [7:0] DPRA;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM256X1S (...);
+ parameter [255:0] INIT = 256'h0;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O;
+ input [7:0] A;
+ input D;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM32M (...);
+ parameter [63:0] INIT_A = 64'h0000000000000000;
+ parameter [63:0] INIT_B = 64'h0000000000000000;
+ parameter [63:0] INIT_C = 64'h0000000000000000;
+ parameter [63:0] INIT_D = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output [1:0] DOA;
+ output [1:0] DOB;
+ output [1:0] DOC;
+ output [1:0] DOD;
+ input [4:0] ADDRA;
+ input [4:0] ADDRB;
+ input [4:0] ADDRC;
+ input [4:0] ADDRD;
+ input [1:0] DIA;
+ input [1:0] DIB;
+ input [1:0] DIC;
+ input [1:0] DID;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM32M16 (...);
+ parameter [63:0] INIT_A = 64'h0000000000000000;
+ parameter [63:0] INIT_B = 64'h0000000000000000;
+ parameter [63:0] INIT_C = 64'h0000000000000000;
+ parameter [63:0] INIT_D = 64'h0000000000000000;
+ parameter [63:0] INIT_E = 64'h0000000000000000;
+ parameter [63:0] INIT_F = 64'h0000000000000000;
+ parameter [63:0] INIT_G = 64'h0000000000000000;
+ parameter [63:0] INIT_H = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output [1:0] DOA;
+ output [1:0] DOB;
+ output [1:0] DOC;
+ output [1:0] DOD;
+ output [1:0] DOE;
+ output [1:0] DOF;
+ output [1:0] DOG;
+ output [1:0] DOH;
+ input [4:0] ADDRA;
+ input [4:0] ADDRB;
+ input [4:0] ADDRC;
+ input [4:0] ADDRD;
+ input [4:0] ADDRE;
+ input [4:0] ADDRF;
+ input [4:0] ADDRG;
+ input [4:0] ADDRH;
+ input [1:0] DIA;
+ input [1:0] DIB;
+ input [1:0] DIC;
+ input [1:0] DID;
+ input [1:0] DIE;
+ input [1:0] DIF;
+ input [1:0] DIG;
+ input [1:0] DIH;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM32X1S (...);
+ parameter [31:0] INIT = 32'h00000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input D;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM512X1S (...);
+ parameter [511:0] INIT = 512'h0;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O;
+ input [8:0] A;
+ input D;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM64M (...);
+ parameter [63:0] INIT_A = 64'h0000000000000000;
+ parameter [63:0] INIT_B = 64'h0000000000000000;
+ parameter [63:0] INIT_C = 64'h0000000000000000;
+ parameter [63:0] INIT_D = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output DOA;
+ output DOB;
+ output DOC;
+ output DOD;
+ input [5:0] ADDRA;
+ input [5:0] ADDRB;
+ input [5:0] ADDRC;
+ input [5:0] ADDRD;
+ input DIA;
+ input DIB;
+ input DIC;
+ input DID;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM64M8 (...);
+ parameter [63:0] INIT_A = 64'h0000000000000000;
+ parameter [63:0] INIT_B = 64'h0000000000000000;
+ parameter [63:0] INIT_C = 64'h0000000000000000;
+ parameter [63:0] INIT_D = 64'h0000000000000000;
+ parameter [63:0] INIT_E = 64'h0000000000000000;
+ parameter [63:0] INIT_F = 64'h0000000000000000;
+ parameter [63:0] INIT_G = 64'h0000000000000000;
+ parameter [63:0] INIT_H = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output DOA;
+ output DOB;
+ output DOC;
+ output DOD;
+ output DOE;
+ output DOF;
+ output DOG;
+ output DOH;
+ input [5:0] ADDRA;
+ input [5:0] ADDRB;
+ input [5:0] ADDRC;
+ input [5:0] ADDRD;
+ input [5:0] ADDRE;
+ input [5:0] ADDRF;
+ input [5:0] ADDRG;
+ input [5:0] ADDRH;
+ input DIA;
+ input DIB;
+ input DIC;
+ input DID;
+ input DIE;
+ input DIF;
+ input DIG;
+ input DIH;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module RAM64X1S (...);
+ parameter [63:0] INIT = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ output O;
+ input A0;
+ input A1;
+ input A2;
+ input A3;
+ input A4;
+ input A5;
+ input D;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK;
+ input WE;
+endmodule
+
+module AND2B1L (...);
+ parameter [0:0] IS_SRI_INVERTED = 1'b0;
+ output O;
+ input DI;
+ (* invertible_pin = "IS_SRI_INVERTED" *)
+ input SRI;
+endmodule
+
+module CARRY8 (...);
+ parameter CARRY_TYPE = "SINGLE_CY8";
+ output [7:0] CO;
+ output [7:0] O;
+ input CI;
+ input CI_TOP;
+ input [7:0] DI;
+ input [7:0] S;
+endmodule
+
+module CFGLUT5 (...);
+ parameter [31:0] INIT = 32'h00000000;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ output CDO;
+ output O5;
+ output O6;
+ input I4;
+ input I3;
+ input I2;
+ input I1;
+ input I0;
+ input CDI;
+ input CE;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLK_INVERTED" *)
+ input CLK;
+endmodule
+
+module MUXF9 (...);
+ output O;
+ input I0;
+ input I1;
+ input S;
+endmodule
+
+module OR2L (...);
+ parameter [0:0] IS_SRI_INVERTED = 1'b0;
+ output O;
+ input DI;
+ (* invertible_pin = "IS_SRI_INVERTED" *)
+ input SRI;
+endmodule
+
+module BUFG_GT (...);
+ (* clkbuf_driver *)
+ output O;
+ input CE;
+ input CEMASK;
+ input CLR;
+ input CLRMASK;
+ input [2:0] DIV;
+ input I;
+endmodule
+
+module BUFG_GT_SYNC (...);
+ output CESYNC;
+ output CLRSYNC;
+ input CE;
+ input CLK;
+ input CLR;
+endmodule
+
+module BUFG_PS (...);
+ (* clkbuf_driver *)
+ output O;
+ input I;
+endmodule
+
+module BUFGCE (...);
+ parameter CE_TYPE = "SYNC";
+ parameter [0:0] IS_CE_INVERTED = 1'b0;
+ parameter [0:0] IS_I_INVERTED = 1'b0;
+ (* clkbuf_driver *)
+ output O;
+ (* invertible_pin = "IS_CE_INVERTED" *)
+ input CE;
+ (* invertible_pin = "IS_I_INVERTED" *)
+ input I;
+endmodule
+
+module BUFGCE_1 (...);
+ (* clkbuf_driver *)
+ output O;
+ input CE;
+ input I;
+endmodule
+
+module BUFGCE_DIV (...);
+ parameter integer BUFGCE_DIVIDE = 1;
+ parameter [0:0] IS_CE_INVERTED = 1'b0;
+ parameter [0:0] IS_CLR_INVERTED = 1'b0;
+ parameter [0:0] IS_I_INVERTED = 1'b0;
+ (* clkbuf_driver *)
+ output O;
+ (* invertible_pin = "IS_CE_INVERTED" *)
+ input CE;
+ (* invertible_pin = "IS_CLR_INVERTED" *)
+ input CLR;
+ (* invertible_pin = "IS_I_INVERTED" *)
+ input I;
+endmodule
+
+module BUFGMUX (...);
+ parameter CLK_SEL_TYPE = "SYNC";
+ (* clkbuf_driver *)
+ output O;
+ input I0;
+ input I1;
+ input S;
+endmodule
+
+module BUFGMUX_1 (...);
+ parameter CLK_SEL_TYPE = "SYNC";
+ (* clkbuf_driver *)
+ output O;
+ input I0;
+ input I1;
+ input S;
+endmodule
+
+module BUFGMUX_CTRL (...);
+ (* clkbuf_driver *)
+ output O;
+ input I0;
+ input I1;
+ input S;
+endmodule
+
+module MMCME3_ADV (...);
+ parameter BANDWIDTH = "OPTIMIZED";
+ parameter real CLKFBOUT_MULT_F = 5.000;
+ parameter real CLKFBOUT_PHASE = 0.000;
+ parameter CLKFBOUT_USE_FINE_PS = "FALSE";
+ parameter real CLKIN1_PERIOD = 0.000;
+ parameter real CLKIN2_PERIOD = 0.000;
+ parameter real CLKIN_FREQ_MAX = 1066.000;
+ parameter real CLKIN_FREQ_MIN = 10.000;
+ parameter real CLKOUT0_DIVIDE_F = 1.000;
+ parameter real CLKOUT0_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT0_PHASE = 0.000;
+ parameter CLKOUT0_USE_FINE_PS = "FALSE";
+ parameter integer CLKOUT1_DIVIDE = 1;
+ parameter real CLKOUT1_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT1_PHASE = 0.000;
+ parameter CLKOUT1_USE_FINE_PS = "FALSE";
+ parameter integer CLKOUT2_DIVIDE = 1;
+ parameter real CLKOUT2_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT2_PHASE = 0.000;
+ parameter CLKOUT2_USE_FINE_PS = "FALSE";
+ parameter integer CLKOUT3_DIVIDE = 1;
+ parameter real CLKOUT3_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT3_PHASE = 0.000;
+ parameter CLKOUT3_USE_FINE_PS = "FALSE";
+ parameter CLKOUT4_CASCADE = "FALSE";
+ parameter integer CLKOUT4_DIVIDE = 1;
+ parameter real CLKOUT4_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT4_PHASE = 0.000;
+ parameter CLKOUT4_USE_FINE_PS = "FALSE";
+ parameter integer CLKOUT5_DIVIDE = 1;
+ parameter real CLKOUT5_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT5_PHASE = 0.000;
+ parameter CLKOUT5_USE_FINE_PS = "FALSE";
+ parameter integer CLKOUT6_DIVIDE = 1;
+ parameter real CLKOUT6_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT6_PHASE = 0.000;
+ parameter CLKOUT6_USE_FINE_PS = "FALSE";
+ parameter real CLKPFD_FREQ_MAX = 550.000;
+ parameter real CLKPFD_FREQ_MIN = 10.000;
+ parameter COMPENSATION = "AUTO";
+ parameter integer DIVCLK_DIVIDE = 1;
+ parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0;
+ parameter [0:0] IS_CLKIN1_INVERTED = 1'b0;
+ parameter [0:0] IS_CLKIN2_INVERTED = 1'b0;
+ parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0;
+ parameter [0:0] IS_PSEN_INVERTED = 1'b0;
+ parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0;
+ parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_INVERTED = 1'b0;
+ parameter real REF_JITTER1 = 0.010;
+ parameter real REF_JITTER2 = 0.010;
+ parameter SS_EN = "FALSE";
+ parameter SS_MODE = "CENTER_HIGH";
+ parameter integer SS_MOD_PERIOD = 10000;
+ parameter STARTUP_WAIT = "FALSE";
+ parameter real VCOCLK_FREQ_MAX = 1600.000;
+ parameter real VCOCLK_FREQ_MIN = 600.000;
+ parameter STARTUP_WAIT = "FALSE";
+ output CDDCDONE;
+ output CLKFBOUT;
+ output CLKFBOUTB;
+ output CLKFBSTOPPED;
+ output CLKINSTOPPED;
+ output CLKOUT0;
+ output CLKOUT0B;
+ output CLKOUT1;
+ output CLKOUT1B;
+ output CLKOUT2;
+ output CLKOUT2B;
+ output CLKOUT3;
+ output CLKOUT3B;
+ output CLKOUT4;
+ output CLKOUT5;
+ output CLKOUT6;
+ output [15:0] DO;
+ output DRDY;
+ output LOCKED;
+ output PSDONE;
+ input CDDCREQ;
+ (* invertible_pin = "IS_CLKFBIN_INVERTED" *)
+ input CLKFBIN;
+ (* invertible_pin = "IS_CLKIN1_INVERTED" *)
+ input CLKIN1;
+ (* invertible_pin = "IS_CLKIN2_INVERTED" *)
+ input CLKIN2;
+ (* invertible_pin = "IS_CLKINSEL_INVERTED" *)
+ input CLKINSEL;
+ input [6:0] DADDR;
+ input DCLK;
+ input DEN;
+ input [15:0] DI;
+ input DWE;
+ input PSCLK;
+ (* invertible_pin = "IS_PSEN_INVERTED" *)
+ input PSEN;
+ (* invertible_pin = "IS_PSINCDEC_INVERTED" *)
+ input PSINCDEC;
+ (* invertible_pin = "IS_PWRDWN_INVERTED" *)
+ input PWRDWN;
+ (* invertible_pin = "IS_RST_INVERTED" *)
+ input RST;
+endmodule
+
+module MMCME3_BASE (...);
+ parameter BANDWIDTH = "OPTIMIZED";
+ parameter real CLKFBOUT_MULT_F = 5.000;
+ parameter real CLKFBOUT_PHASE = 0.000;
+ parameter real CLKIN1_PERIOD = 0.000;
+ parameter real CLKOUT0_DIVIDE_F = 1.000;
+ parameter real CLKOUT0_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT0_PHASE = 0.000;
+ parameter integer CLKOUT1_DIVIDE = 1;
+ parameter real CLKOUT1_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT1_PHASE = 0.000;
+ parameter integer CLKOUT2_DIVIDE = 1;
+ parameter real CLKOUT2_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT2_PHASE = 0.000;
+ parameter integer CLKOUT3_DIVIDE = 1;
+ parameter real CLKOUT3_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT3_PHASE = 0.000;
+ parameter CLKOUT4_CASCADE = "FALSE";
+ parameter integer CLKOUT4_DIVIDE = 1;
+ parameter real CLKOUT4_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT4_PHASE = 0.000;
+ parameter integer CLKOUT5_DIVIDE = 1;
+ parameter real CLKOUT5_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT5_PHASE = 0.000;
+ parameter integer CLKOUT6_DIVIDE = 1;
+ parameter real CLKOUT6_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT6_PHASE = 0.000;
+ parameter integer DIVCLK_DIVIDE = 1;
+ parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0;
+ parameter [0:0] IS_CLKIN1_INVERTED = 1'b0;
+ parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_INVERTED = 1'b0;
+ parameter real REF_JITTER1 = 0.010;
+ parameter STARTUP_WAIT = "FALSE";
+ output CLKFBOUT;
+ output CLKFBOUTB;
+ output CLKOUT0;
+ output CLKOUT0B;
+ output CLKOUT1;
+ output CLKOUT1B;
+ output CLKOUT2;
+ output CLKOUT2B;
+ output CLKOUT3;
+ output CLKOUT3B;
+ output CLKOUT4;
+ output CLKOUT5;
+ output CLKOUT6;
+ output LOCKED;
+ (* invertible_pin = "IS_CLKFBIN_INVERTED" *)
+ input CLKFBIN;
+ (* invertible_pin = "IS_CLKIN1_INVERTED" *)
+ input CLKIN1;
+ (* invertible_pin = "IS_PWRDWN_INVERTED" *)
+ input PWRDWN;
+ (* invertible_pin = "IS_RST_INVERTED" *)
+ input RST;
+endmodule
+
+module MMCME4_ADV (...);
+ parameter BANDWIDTH = "OPTIMIZED";
+ parameter real CLKFBOUT_MULT_F = 5.000;
+ parameter real CLKFBOUT_PHASE = 0.000;
+ parameter CLKFBOUT_USE_FINE_PS = "FALSE";
+ parameter real CLKIN1_PERIOD = 0.000;
+ parameter real CLKIN2_PERIOD = 0.000;
+ parameter real CLKIN_FREQ_MAX = 1066.000;
+ parameter real CLKIN_FREQ_MIN = 10.000;
+ parameter real CLKOUT0_DIVIDE_F = 1.000;
+ parameter real CLKOUT0_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT0_PHASE = 0.000;
+ parameter CLKOUT0_USE_FINE_PS = "FALSE";
+ parameter integer CLKOUT1_DIVIDE = 1;
+ parameter real CLKOUT1_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT1_PHASE = 0.000;
+ parameter CLKOUT1_USE_FINE_PS = "FALSE";
+ parameter integer CLKOUT2_DIVIDE = 1;
+ parameter real CLKOUT2_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT2_PHASE = 0.000;
+ parameter CLKOUT2_USE_FINE_PS = "FALSE";
+ parameter integer CLKOUT3_DIVIDE = 1;
+ parameter real CLKOUT3_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT3_PHASE = 0.000;
+ parameter CLKOUT3_USE_FINE_PS = "FALSE";
+ parameter CLKOUT4_CASCADE = "FALSE";
+ parameter integer CLKOUT4_DIVIDE = 1;
+ parameter real CLKOUT4_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT4_PHASE = 0.000;
+ parameter CLKOUT4_USE_FINE_PS = "FALSE";
+ parameter integer CLKOUT5_DIVIDE = 1;
+ parameter real CLKOUT5_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT5_PHASE = 0.000;
+ parameter CLKOUT5_USE_FINE_PS = "FALSE";
+ parameter integer CLKOUT6_DIVIDE = 1;
+ parameter real CLKOUT6_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT6_PHASE = 0.000;
+ parameter CLKOUT6_USE_FINE_PS = "FALSE";
+ parameter real CLKPFD_FREQ_MAX = 550.000;
+ parameter real CLKPFD_FREQ_MIN = 10.000;
+ parameter COMPENSATION = "AUTO";
+ parameter integer DIVCLK_DIVIDE = 1;
+ parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0;
+ parameter [0:0] IS_CLKIN1_INVERTED = 1'b0;
+ parameter [0:0] IS_CLKIN2_INVERTED = 1'b0;
+ parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0;
+ parameter [0:0] IS_PSEN_INVERTED = 1'b0;
+ parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0;
+ parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_INVERTED = 1'b0;
+ parameter real REF_JITTER1 = 0.010;
+ parameter real REF_JITTER2 = 0.010;
+ parameter SS_EN = "FALSE";
+ parameter SS_MODE = "CENTER_HIGH";
+ parameter integer SS_MOD_PERIOD = 10000;
+ parameter STARTUP_WAIT = "FALSE";
+ parameter real VCOCLK_FREQ_MAX = 1600.000;
+ parameter real VCOCLK_FREQ_MIN = 800.000;
+ parameter STARTUP_WAIT = "FALSE";
+ output CDDCDONE;
+ output CLKFBOUT;
+ output CLKFBOUTB;
+ output CLKFBSTOPPED;
+ output CLKINSTOPPED;
+ output CLKOUT0;
+ output CLKOUT0B;
+ output CLKOUT1;
+ output CLKOUT1B;
+ output CLKOUT2;
+ output CLKOUT2B;
+ output CLKOUT3;
+ output CLKOUT3B;
+ output CLKOUT4;
+ output CLKOUT5;
+ output CLKOUT6;
+ output [15:0] DO;
+ output DRDY;
+ output LOCKED;
+ output PSDONE;
+ input CDDCREQ;
+ (* invertible_pin = "IS_CLKFBIN_INVERTED" *)
+ input CLKFBIN;
+ (* invertible_pin = "IS_CLKIN1_INVERTED" *)
+ input CLKIN1;
+ (* invertible_pin = "IS_CLKIN2_INVERTED" *)
+ input CLKIN2;
+ (* invertible_pin = "IS_CLKINSEL_INVERTED" *)
+ input CLKINSEL;
+ input [6:0] DADDR;
+ input DCLK;
+ input DEN;
+ input [15:0] DI;
+ input DWE;
+ input PSCLK;
+ (* invertible_pin = "IS_PSEN_INVERTED" *)
+ input PSEN;
+ (* invertible_pin = "IS_PSINCDEC_INVERTED" *)
+ input PSINCDEC;
+ (* invertible_pin = "IS_PWRDWN_INVERTED" *)
+ input PWRDWN;
+ (* invertible_pin = "IS_RST_INVERTED" *)
+ input RST;
+endmodule
+
+module MMCME4_BASE (...);
+ parameter BANDWIDTH = "OPTIMIZED";
+ parameter real CLKFBOUT_MULT_F = 5.000;
+ parameter real CLKFBOUT_PHASE = 0.000;
+ parameter real CLKIN1_PERIOD = 0.000;
+ parameter real CLKOUT0_DIVIDE_F = 1.000;
+ parameter real CLKOUT0_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT0_PHASE = 0.000;
+ parameter integer CLKOUT1_DIVIDE = 1;
+ parameter real CLKOUT1_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT1_PHASE = 0.000;
+ parameter integer CLKOUT2_DIVIDE = 1;
+ parameter real CLKOUT2_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT2_PHASE = 0.000;
+ parameter integer CLKOUT3_DIVIDE = 1;
+ parameter real CLKOUT3_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT3_PHASE = 0.000;
+ parameter CLKOUT4_CASCADE = "FALSE";
+ parameter integer CLKOUT4_DIVIDE = 1;
+ parameter real CLKOUT4_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT4_PHASE = 0.000;
+ parameter integer CLKOUT5_DIVIDE = 1;
+ parameter real CLKOUT5_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT5_PHASE = 0.000;
+ parameter integer CLKOUT6_DIVIDE = 1;
+ parameter real CLKOUT6_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT6_PHASE = 0.000;
+ parameter integer DIVCLK_DIVIDE = 1;
+ parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0;
+ parameter [0:0] IS_CLKIN1_INVERTED = 1'b0;
+ parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_INVERTED = 1'b0;
+ parameter real REF_JITTER1 = 0.010;
+ parameter STARTUP_WAIT = "FALSE";
+ output CLKFBOUT;
+ output CLKFBOUTB;
+ output CLKOUT0;
+ output CLKOUT0B;
+ output CLKOUT1;
+ output CLKOUT1B;
+ output CLKOUT2;
+ output CLKOUT2B;
+ output CLKOUT3;
+ output CLKOUT3B;
+ output CLKOUT4;
+ output CLKOUT5;
+ output CLKOUT6;
+ output LOCKED;
+ (* invertible_pin = "IS_CLKFBIN_INVERTED" *)
+ input CLKFBIN;
+ (* invertible_pin = "IS_CLKIN1_INVERTED" *)
+ input CLKIN1;
+ (* invertible_pin = "IS_PWRDWN_INVERTED" *)
+ input PWRDWN;
+ (* invertible_pin = "IS_RST_INVERTED" *)
+ input RST;
+endmodule
+
+module PLLE3_ADV (...);
+ parameter integer CLKFBOUT_MULT = 5;
+ parameter real CLKFBOUT_PHASE = 0.000;
+ parameter real CLKIN_FREQ_MAX = 1066.000;
+ parameter real CLKIN_FREQ_MIN = 70.000;
+ parameter real CLKIN_PERIOD = 0.000;
+ parameter integer CLKOUT0_DIVIDE = 1;
+ parameter real CLKOUT0_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT0_PHASE = 0.000;
+ parameter integer CLKOUT1_DIVIDE = 1;
+ parameter real CLKOUT1_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT1_PHASE = 0.000;
+ parameter CLKOUTPHY_MODE = "VCO_2X";
+ parameter real CLKPFD_FREQ_MAX = 667.500;
+ parameter real CLKPFD_FREQ_MIN = 70.000;
+ parameter COMPENSATION = "AUTO";
+ parameter integer DIVCLK_DIVIDE = 1;
+ parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0;
+ parameter [0:0] IS_CLKIN_INVERTED = 1'b0;
+ parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_INVERTED = 1'b0;
+ parameter real REF_JITTER = 0.010;
+ parameter STARTUP_WAIT = "FALSE";
+ parameter real VCOCLK_FREQ_MAX = 1335.000;
+ parameter real VCOCLK_FREQ_MIN = 600.000;
+ parameter STARTUP_WAIT = "FALSE";
+ output CLKFBOUT;
+ output CLKOUT0;
+ output CLKOUT0B;
+ output CLKOUT1;
+ output CLKOUT1B;
+ output CLKOUTPHY;
+ output [15:0] DO;
+ output DRDY;
+ output LOCKED;
+ (* invertible_pin = "IS_CLKFBIN_INVERTED" *)
+ input CLKFBIN;
+ (* invertible_pin = "IS_CLKIN_INVERTED" *)
+ input CLKIN;
+ input CLKOUTPHYEN;
+ input [6:0] DADDR;
+ input DCLK;
+ input DEN;
+ input [15:0] DI;
+ input DWE;
+ (* invertible_pin = "IS_PWRDWN_INVERTED" *)
+ input PWRDWN;
+ (* invertible_pin = "IS_RST_INVERTED" *)
+ input RST;
+endmodule
+
+module PLLE3_BASE (...);
+ parameter integer CLKFBOUT_MULT = 5;
+ parameter real CLKFBOUT_PHASE = 0.000;
+ parameter real CLKIN_PERIOD = 0.000;
+ parameter integer CLKOUT0_DIVIDE = 1;
+ parameter real CLKOUT0_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT0_PHASE = 0.000;
+ parameter integer CLKOUT1_DIVIDE = 1;
+ parameter real CLKOUT1_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT1_PHASE = 0.000;
+ parameter CLKOUTPHY_MODE = "VCO_2X";
+ parameter integer DIVCLK_DIVIDE = 1;
+ parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0;
+ parameter [0:0] IS_CLKIN_INVERTED = 1'b0;
+ parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_INVERTED = 1'b0;
+ parameter real REF_JITTER = 0.010;
+ parameter STARTUP_WAIT = "FALSE";
+ output CLKFBOUT;
+ output CLKOUT0;
+ output CLKOUT0B;
+ output CLKOUT1;
+ output CLKOUT1B;
+ output CLKOUTPHY;
+ output LOCKED;
+ (* invertible_pin = "IS_CLKFBIN_INVERTED" *)
+ input CLKFBIN;
+ (* invertible_pin = "IS_CLKIN_INVERTED" *)
+ input CLKIN;
+ input CLKOUTPHYEN;
+ (* invertible_pin = "IS_PWRDWN_INVERTED" *)
+ input PWRDWN;
+ (* invertible_pin = "IS_RST_INVERTED" *)
+ input RST;
+endmodule
+
+module PLLE4_ADV (...);
+ parameter integer CLKFBOUT_MULT = 5;
+ parameter real CLKFBOUT_PHASE = 0.000;
+ parameter real CLKIN_FREQ_MAX = 1066.000;
+ parameter real CLKIN_FREQ_MIN = 70.000;
+ parameter real CLKIN_PERIOD = 0.000;
+ parameter integer CLKOUT0_DIVIDE = 1;
+ parameter real CLKOUT0_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT0_PHASE = 0.000;
+ parameter integer CLKOUT1_DIVIDE = 1;
+ parameter real CLKOUT1_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT1_PHASE = 0.000;
+ parameter CLKOUTPHY_MODE = "VCO_2X";
+ parameter real CLKPFD_FREQ_MAX = 667.500;
+ parameter real CLKPFD_FREQ_MIN = 70.000;
+ parameter COMPENSATION = "AUTO";
+ parameter integer DIVCLK_DIVIDE = 1;
+ parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0;
+ parameter [0:0] IS_CLKIN_INVERTED = 1'b0;
+ parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_INVERTED = 1'b0;
+ parameter real REF_JITTER = 0.010;
+ parameter STARTUP_WAIT = "FALSE";
+ parameter real VCOCLK_FREQ_MAX = 1500.000;
+ parameter real VCOCLK_FREQ_MIN = 750.000;
+ parameter STARTUP_WAIT = "FALSE";
+ output CLKFBOUT;
+ output CLKOUT0;
+ output CLKOUT0B;
+ output CLKOUT1;
+ output CLKOUT1B;
+ output CLKOUTPHY;
+ output [15:0] DO;
+ output DRDY;
+ output LOCKED;
+ (* invertible_pin = "IS_CLKFBIN_INVERTED" *)
+ input CLKFBIN;
+ (* invertible_pin = "IS_CLKIN_INVERTED" *)
+ input CLKIN;
+ input CLKOUTPHYEN;
+ input [6:0] DADDR;
+ input DCLK;
+ input DEN;
+ input [15:0] DI;
+ input DWE;
+ (* invertible_pin = "IS_PWRDWN_INVERTED" *)
+ input PWRDWN;
+ (* invertible_pin = "IS_RST_INVERTED" *)
+ input RST;
+endmodule
+
+module PLLE4_BASE (...);
+ parameter integer CLKFBOUT_MULT = 5;
+ parameter real CLKFBOUT_PHASE = 0.000;
+ parameter real CLKIN_PERIOD = 0.000;
+ parameter integer CLKOUT0_DIVIDE = 1;
+ parameter real CLKOUT0_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT0_PHASE = 0.000;
+ parameter integer CLKOUT1_DIVIDE = 1;
+ parameter real CLKOUT1_DUTY_CYCLE = 0.500;
+ parameter real CLKOUT1_PHASE = 0.000;
+ parameter CLKOUTPHY_MODE = "VCO_2X";
+ parameter integer DIVCLK_DIVIDE = 1;
+ parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0;
+ parameter [0:0] IS_CLKIN_INVERTED = 1'b0;
+ parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_INVERTED = 1'b0;
+ parameter real REF_JITTER = 0.010;
+ parameter STARTUP_WAIT = "FALSE";
+ output CLKFBOUT;
+ output CLKOUT0;
+ output CLKOUT0B;
+ output CLKOUT1;
+ output CLKOUT1B;
+ output CLKOUTPHY;
+ output LOCKED;
+ (* invertible_pin = "IS_CLKFBIN_INVERTED" *)
+ input CLKFBIN;
+ (* invertible_pin = "IS_CLKIN_INVERTED" *)
+ input CLKIN;
+ input CLKOUTPHYEN;
+ (* invertible_pin = "IS_PWRDWN_INVERTED" *)
+ input PWRDWN;
+ (* invertible_pin = "IS_RST_INVERTED" *)
+ input RST;
+endmodule
+
+(* keep *)
+module BSCANE2 (...);
+ parameter DISABLE_JTAG = "FALSE";
+ parameter integer JTAG_CHAIN = 1;
+ output CAPTURE;
+ output DRCK;
+ output RESET;
+ output RUNTEST;
+ output SEL;
+ output SHIFT;
+ output TCK;
+ output TDI;
+ output TMS;
+ output UPDATE;
+ input TDO;
+endmodule
+
+module DNA_PORTE2 (...);
+ parameter [95:0] SIM_DNA_VALUE = 96'h000000000000000000000000;
+ output DOUT;
+ input CLK;
+ input DIN;
+ input READ;
+ input SHIFT;
+endmodule
+
+module EFUSE_USR (...);
+ parameter [31:0] SIM_EFUSE_VALUE = 32'h00000000;
+ output [31:0] EFUSEUSR;
+endmodule
+
+module FRAME_ECCE3 (...);
+ output CRCERROR;
+ output ECCERRORNOTSINGLE;
+ output ECCERRORSINGLE;
+ output ENDOFFRAME;
+ output ENDOFSCAN;
+ output [25:0] FAR;
+ input [1:0] FARSEL;
+ input ICAPBOTCLK;
+ input ICAPTOPCLK;
+endmodule
+
+(* keep *)
+module ICAPE3 (...);
+ parameter [31:0] DEVICE_ID = 32'h03628093;
+ parameter ICAP_AUTO_SWITCH = "DISABLE";
+ parameter SIM_CFG_FILE_NAME = "NONE";
+ output AVAIL;
+ output [31:0] O;
+ output PRDONE;
+ output PRERROR;
+ input CLK;
+ input CSIB;
+ input RDWRB;
+ input [31:0] I;
+endmodule
+
+(* keep *)
+module MASTER_JTAG (...);
+ output TDO;
+ input TCK;
+ input TDI;
+ input TMS;
+endmodule
+
+(* keep *)
+module STARTUPE3 (...);
+ parameter PROG_USR = "FALSE";
+ parameter real SIM_CCLK_FREQ = 0.0;
+ output CFGCLK;
+ output CFGMCLK;
+ output [3:0] DI;
+ output EOS;
+ output PREQ;
+ input [3:0] DO;
+ input [3:0] DTS;
+ input FCSBO;
+ input FCSBTS;
+ input GSR;
+ input GTS;
+ input KEYCLEARB;
+ input PACK;
+ input USRCCLKO;
+ input USRCCLKTS;
+ input USRDONEO;
+ input USRDONETS;
+endmodule
+
+module USR_ACCESSE2 (...);
+ output CFGCLK;
+ output DATAVALID;
+ output [31:0] DATA;
+endmodule
+
+(* keep *)
+module BITSLICE_CONTROL (...);
+ parameter CTRL_CLK = "EXTERNAL";
+ parameter DIV_MODE = "DIV2";
+ parameter EN_CLK_TO_EXT_NORTH = "DISABLE";
+ parameter EN_CLK_TO_EXT_SOUTH = "DISABLE";
+ parameter EN_DYN_ODLY_MODE = "FALSE";
+ parameter EN_OTHER_NCLK = "FALSE";
+ parameter EN_OTHER_PCLK = "FALSE";
+ parameter IDLY_VT_TRACK = "TRUE";
+ parameter INV_RXCLK = "FALSE";
+ parameter ODLY_VT_TRACK = "TRUE";
+ parameter QDLY_VT_TRACK = "TRUE";
+ parameter [5:0] READ_IDLE_COUNT = 6'h00;
+ parameter REFCLK_SRC = "PLLCLK";
+ parameter integer ROUNDING_FACTOR = 16;
+ parameter RXGATE_EXTEND = "FALSE";
+ parameter RX_CLK_PHASE_N = "SHIFT_0";
+ parameter RX_CLK_PHASE_P = "SHIFT_0";
+ parameter RX_GATING = "DISABLE";
+ parameter SELF_CALIBRATE = "ENABLE";
+ parameter SERIAL_MODE = "FALSE";
+ parameter SIM_DEVICE = "ULTRASCALE";
+ parameter SIM_SPEEDUP = "FAST";
+ parameter real SIM_VERSION = 2.0;
+ parameter TX_GATING = "DISABLE";
+ output CLK_TO_EXT_NORTH;
+ output CLK_TO_EXT_SOUTH;
+ output DLY_RDY;
+ output [6:0] DYN_DCI;
+ output NCLK_NIBBLE_OUT;
+ output PCLK_NIBBLE_OUT;
+ output [15:0] RIU_RD_DATA;
+ output RIU_VALID;
+ output [39:0] RX_BIT_CTRL_OUT0;
+ output [39:0] RX_BIT_CTRL_OUT1;
+ output [39:0] RX_BIT_CTRL_OUT2;
+ output [39:0] RX_BIT_CTRL_OUT3;
+ output [39:0] RX_BIT_CTRL_OUT4;
+ output [39:0] RX_BIT_CTRL_OUT5;
+ output [39:0] RX_BIT_CTRL_OUT6;
+ output [39:0] TX_BIT_CTRL_OUT0;
+ output [39:0] TX_BIT_CTRL_OUT1;
+ output [39:0] TX_BIT_CTRL_OUT2;
+ output [39:0] TX_BIT_CTRL_OUT3;
+ output [39:0] TX_BIT_CTRL_OUT4;
+ output [39:0] TX_BIT_CTRL_OUT5;
+ output [39:0] TX_BIT_CTRL_OUT6;
+ output [39:0] TX_BIT_CTRL_OUT_TRI;
+ output VTC_RDY;
+ input CLK_FROM_EXT;
+ input EN_VTC;
+ input NCLK_NIBBLE_IN;
+ input PCLK_NIBBLE_IN;
+ input [3:0] PHY_RDCS0;
+ input [3:0] PHY_RDCS1;
+ input [3:0] PHY_RDEN;
+ input [3:0] PHY_WRCS0;
+ input [3:0] PHY_WRCS1;
+ input PLL_CLK;
+ input REFCLK;
+ input [5:0] RIU_ADDR;
+ input RIU_CLK;
+ input RIU_NIBBLE_SEL;
+ input [15:0] RIU_WR_DATA;
+ input RIU_WR_EN;
+ input RST;
+ input [39:0] RX_BIT_CTRL_IN0;
+ input [39:0] RX_BIT_CTRL_IN1;
+ input [39:0] RX_BIT_CTRL_IN2;
+ input [39:0] RX_BIT_CTRL_IN3;
+ input [39:0] RX_BIT_CTRL_IN4;
+ input [39:0] RX_BIT_CTRL_IN5;
+ input [39:0] RX_BIT_CTRL_IN6;
+ input [3:0] TBYTE_IN;
+ input [39:0] TX_BIT_CTRL_IN0;
+ input [39:0] TX_BIT_CTRL_IN1;
+ input [39:0] TX_BIT_CTRL_IN2;
+ input [39:0] TX_BIT_CTRL_IN3;
+ input [39:0] TX_BIT_CTRL_IN4;
+ input [39:0] TX_BIT_CTRL_IN5;
+ input [39:0] TX_BIT_CTRL_IN6;
+ input [39:0] TX_BIT_CTRL_IN_TRI;
+endmodule
+
+(* keep *)
+module DCIRESET (...);
+ output LOCKED;
+ input RST;
+endmodule
+
+module HPIO_VREF (...);
+ parameter VREF_CNTR = "OFF";
+ output VREF;
+ input [6:0] FABRIC_VREF_TUNE;
+endmodule
+
+module IBUF_ANALOG (...);
+ output O;
+ (* iopad_external_pin *)
+ input I;
+endmodule
+
+module IBUF_IBUFDISABLE (...);
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ (* iopad_external_pin *)
+ input I;
+ input IBUFDISABLE;
+endmodule
+
+module IBUF_INTERMDISABLE (...);
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ (* iopad_external_pin *)
+ input I;
+ input IBUFDISABLE;
+ input INTERMDISABLE;
+endmodule
+
+module IBUFDS (...);
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_DELAY_VALUE = "0";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IFD_DELAY_VALUE = "AUTO";
+ parameter IOSTANDARD = "DEFAULT";
+ output O;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+endmodule
+
+module IBUFDS_DIFF_OUT (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ output O;
+ output OB;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+endmodule
+
+module IBUFDS_DIFF_OUT_IBUFDISABLE (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ output OB;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+ input IBUFDISABLE;
+endmodule
+
+module IBUFDS_DIFF_OUT_INTERMDISABLE (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ output OB;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+ input IBUFDISABLE;
+ input INTERMDISABLE;
+endmodule
+
+module IBUFDS_DPHY (...);
+ parameter DIFF_TERM = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ output HSRX_O;
+ output LPRX_O_N;
+ output LPRX_O_P;
+ input HSRX_DISABLE;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+ input LPRX_DISABLE;
+endmodule
+
+module IBUFDS_IBUFDISABLE (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+ input IBUFDISABLE;
+endmodule
+
+module IBUFDS_INTERMDISABLE (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+ input IBUFDISABLE;
+ input INTERMDISABLE;
+endmodule
+
+module IBUFDSE3 (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter USE_IBUFDISABLE = "FALSE";
+ parameter integer SIM_INPUT_BUFFER_OFFSET = 0;
+ output O;
+ (* iopad_external_pin *)
+ input I;
+ (* iopad_external_pin *)
+ input IB;
+ input IBUFDISABLE;
+ input [3:0] OSC;
+ input [1:0] OSC_EN;
+endmodule
+
+module IBUFE3 (...);
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter USE_IBUFDISABLE = "FALSE";
+ parameter integer SIM_INPUT_BUFFER_OFFSET = 0;
+ output O;
+ (* iopad_external_pin *)
+ input I;
+ input IBUFDISABLE;
+ input [3:0] OSC;
+ input OSC_EN;
+ input VREF;
+endmodule
+
+(* keep *)
+module IDELAYCTRL (...);
+ parameter SIM_DEVICE = "7SERIES";
+ output RDY;
+ (* clkbuf_sink *)
+ input REFCLK;
+ input RST;
+endmodule
+
+module IDELAYE3 (...);
+ parameter CASCADE = "NONE";
+ parameter DELAY_FORMAT = "TIME";
+ parameter DELAY_SRC = "IDATAIN";
+ parameter DELAY_TYPE = "FIXED";
+ parameter integer DELAY_VALUE = 0;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_INVERTED = 1'b0;
+ parameter LOOPBACK = "FALSE";
+ parameter real REFCLK_FREQUENCY = 300.0;
+ parameter SIM_DEVICE = "ULTRASCALE";
+ parameter real SIM_VERSION = 2.0;
+ parameter UPDATE_MODE = "ASYNC";
+ output CASC_OUT;
+ output [8:0] CNTVALUEOUT;
+ output DATAOUT;
+ input CASC_IN;
+ input CASC_RETURN;
+ input CE;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLK_INVERTED" *)
+ input CLK;
+ input [8:0] CNTVALUEIN;
+ input DATAIN;
+ input EN_VTC;
+ input IDATAIN;
+ input INC;
+ input LOAD;
+ (* invertible_pin = "IS_RST_INVERTED" *)
+ input RST;
+endmodule
+
+module IOBUF (...);
+ parameter integer DRIVE = 12;
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SLEW = "SLOW";
+ output O;
+ (* iopad_external_pin *)
+ inout IO;
+ input I;
+ input T;
+endmodule
+
+module IOBUF_DCIEN (...);
+ parameter integer DRIVE = 12;
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter SLEW = "SLOW";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ (* iopad_external_pin *)
+ inout IO;
+ input DCITERMDISABLE;
+ input I;
+ input IBUFDISABLE;
+ input T;
+endmodule
+
+module IOBUF_INTERMDISABLE (...);
+ parameter integer DRIVE = 12;
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter SLEW = "SLOW";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ (* iopad_external_pin *)
+ inout IO;
+ input I;
+ input IBUFDISABLE;
+ input INTERMDISABLE;
+ input T;
+endmodule
+
+module IOBUFDS (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SLEW = "SLOW";
+ output O;
+ (* iopad_external_pin *)
+ inout IO;
+ inout IOB;
+ input I;
+ input T;
+endmodule
+
+module IOBUFDS_DCIEN (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter SLEW = "SLOW";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ (* iopad_external_pin *)
+ inout IO;
+ (* iopad_external_pin *)
+ inout IOB;
+ input DCITERMDISABLE;
+ input I;
+ input IBUFDISABLE;
+ input T;
+endmodule
+
+module IOBUFDS_DIFF_OUT (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ output O;
+ output OB;
+ (* iopad_external_pin *)
+ inout IO;
+ (* iopad_external_pin *)
+ inout IOB;
+ input I;
+ input TM;
+ input TS;
+endmodule
+
+module IOBUFDS_DIFF_OUT_DCIEN (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ output OB;
+ (* iopad_external_pin *)
+ inout IO;
+ (* iopad_external_pin *)
+ inout IOB;
+ input DCITERMDISABLE;
+ input I;
+ input IBUFDISABLE;
+ input TM;
+ input TS;
+endmodule
+
+module IOBUFDS_DIFF_OUT_INTERMDISABLE (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ output OB;
+ (* iopad_external_pin *)
+ inout IO;
+ (* iopad_external_pin *)
+ inout IOB;
+ input I;
+ input IBUFDISABLE;
+ input INTERMDISABLE;
+ input TM;
+ input TS;
+endmodule
+
+module IOBUFDS_INTERMDISABLE (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SIM_DEVICE = "7SERIES";
+ parameter SLEW = "SLOW";
+ parameter USE_IBUFDISABLE = "TRUE";
+ output O;
+ (* iopad_external_pin *)
+ inout IO;
+ (* iopad_external_pin *)
+ inout IOB;
+ input I;
+ input IBUFDISABLE;
+ input INTERMDISABLE;
+ input T;
+endmodule
+
+module IOBUFDSE3 (...);
+ parameter DIFF_TERM = "FALSE";
+ parameter DQS_BIAS = "FALSE";
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter integer SIM_INPUT_BUFFER_OFFSET = 0;
+ parameter USE_IBUFDISABLE = "FALSE";
+ output O;
+ (* iopad_external_pin *)
+ inout IO;
+ inout IOB;
+ input DCITERMDISABLE;
+ input I;
+ input IBUFDISABLE;
+ input [3:0] OSC;
+ input [1:0] OSC_EN;
+ input T;
+endmodule
+
+module IOBUFE3 (...);
+ parameter integer DRIVE = 12;
+ parameter IBUF_LOW_PWR = "TRUE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter USE_IBUFDISABLE = "FALSE";
+ parameter integer SIM_INPUT_BUFFER_OFFSET = 0;
+ output O;
+ (* iopad_external_pin *)
+ inout IO;
+ input DCITERMDISABLE;
+ input I;
+ input IBUFDISABLE;
+ input [3:0] OSC;
+ input OSC_EN;
+ input T;
+ input VREF;
+endmodule
+
+module ISERDESE3 (...);
+ parameter integer DATA_WIDTH = 8;
+ parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
+ parameter FIFO_ENABLE = "FALSE";
+ parameter FIFO_SYNC_MODE = "FALSE";
+ parameter IDDR_MODE = "FALSE";
+ parameter [0:0] IS_CLK_B_INVERTED = 1'b0;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_INVERTED = 1'b0;
+ parameter SIM_DEVICE = "ULTRASCALE";
+ parameter real SIM_VERSION = 2.0;
+ output FIFO_EMPTY;
+ output INTERNAL_DIVCLK;
+ output [7:0] Q;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLK_INVERTED" *)
+ input CLK;
+ (* clkbuf_sink *)
+ input CLKDIV;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLK_B_INVERTED" *)
+ input CLK_B;
+ input D;
+ (* clkbuf_sink *)
+ input FIFO_RD_CLK;
+ input FIFO_RD_EN;
+ (* invertible_pin = "IS_RST_INVERTED" *)
+ input RST;
+endmodule
+
+module KEEPER (...);
+ inout O;
+endmodule
+
+module OBUFDS (...);
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SLEW = "SLOW";
+ (* iopad_external_pin *)
+ output O;
+ (* iopad_external_pin *)
+ output OB;
+ input I;
+endmodule
+
+module OBUFDS_DPHY (...);
+ parameter IOSTANDARD = "DEFAULT";
+ (* iopad_external_pin *)
+ output O;
+ (* iopad_external_pin *)
+ output OB;
+ input HSTX_I;
+ input HSTX_T;
+ input LPTX_I_N;
+ input LPTX_I_P;
+ input LPTX_T;
+endmodule
+
+module OBUFT (...);
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter integer DRIVE = 12;
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SLEW = "SLOW";
+ (* iopad_external_pin *)
+ output O;
+ input I;
+ input T;
+endmodule
+
+module OBUFTDS (...);
+ parameter CAPACITANCE = "DONT_CARE";
+ parameter IOSTANDARD = "DEFAULT";
+ parameter SLEW = "SLOW";
+ (* iopad_external_pin *)
+ output O;
+ (* iopad_external_pin *)
+ output OB;
+ input I;
+ input T;
+endmodule
+
+module ODELAYE3 (...);
+ parameter CASCADE = "NONE";
+ parameter DELAY_FORMAT = "TIME";
+ parameter DELAY_TYPE = "FIXED";
+ parameter integer DELAY_VALUE = 0;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_INVERTED = 1'b0;
+ parameter real REFCLK_FREQUENCY = 300.0;
+ parameter SIM_DEVICE = "ULTRASCALE";
+ parameter real SIM_VERSION = 2.0;
+ parameter UPDATE_MODE = "ASYNC";
+ output CASC_OUT;
+ output [8:0] CNTVALUEOUT;
+ output DATAOUT;
+ input CASC_IN;
+ input CASC_RETURN;
+ input CE;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLK_INVERTED" *)
+ input CLK;
+ input [8:0] CNTVALUEIN;
+ input EN_VTC;
+ input INC;
+ input LOAD;
+ input ODATAIN;
+ (* invertible_pin = "IS_RST_INVERTED" *)
+ input RST;
+endmodule
+
+module OSERDESE3 (...);
+ parameter integer DATA_WIDTH = 8;
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_CLKDIV_INVERTED = 1'b0;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_INVERTED = 1'b0;
+ parameter ODDR_MODE = "FALSE";
+ parameter OSERDES_D_BYPASS = "FALSE";
+ parameter OSERDES_T_BYPASS = "FALSE";
+ parameter SIM_DEVICE = "ULTRASCALE";
+ parameter real SIM_VERSION = 2.0;
+ output OQ;
+ output T_OUT;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLK_INVERTED" *)
+ input CLK;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLKDIV_INVERTED" *)
+ input CLKDIV;
+ input [7:0] D;
+ (* invertible_pin = "IS_RST_INVERTED" *)
+ input RST;
+ input T;
+endmodule
+
+module PULLDOWN (...);
+ output O;
+endmodule
+
+module PULLUP (...);
+ output O;
+endmodule
+
+module RIU_OR (...);
+ parameter SIM_DEVICE = "ULTRASCALE";
+ parameter real SIM_VERSION = 2.0;
+ output [15:0] RIU_RD_DATA;
+ output RIU_RD_VALID;
+ input [15:0] RIU_RD_DATA_LOW;
+ input [15:0] RIU_RD_DATA_UPP;
+ input RIU_RD_VALID_LOW;
+ input RIU_RD_VALID_UPP;
+endmodule
+
+module RX_BITSLICE (...);
+ parameter CASCADE = "TRUE";
+ parameter DATA_TYPE = "NONE";
+ parameter integer DATA_WIDTH = 8;
+ parameter DELAY_FORMAT = "TIME";
+ parameter DELAY_TYPE = "FIXED";
+ parameter integer DELAY_VALUE = 0;
+ parameter integer DELAY_VALUE_EXT = 0;
+ parameter FIFO_SYNC_MODE = "FALSE";
+ parameter [0:0] IS_CLK_EXT_INVERTED = 1'b0;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_DLY_EXT_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_DLY_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_INVERTED = 1'b0;
+ parameter real REFCLK_FREQUENCY = 300.0;
+ parameter SIM_DEVICE = "ULTRASCALE";
+ parameter real SIM_VERSION = 2.0;
+ parameter UPDATE_MODE = "ASYNC";
+ parameter UPDATE_MODE_EXT = "ASYNC";
+ output [8:0] CNTVALUEOUT;
+ output [8:0] CNTVALUEOUT_EXT;
+ output FIFO_EMPTY;
+ output FIFO_WRCLK_OUT;
+ output [7:0] Q;
+ output [39:0] RX_BIT_CTRL_OUT;
+ output [39:0] TX_BIT_CTRL_OUT;
+ input CE;
+ input CE_EXT;
+ (* invertible_pin = "IS_CLK_INVERTED" *)
+ input CLK;
+ (* invertible_pin = "IS_CLK_EXT_INVERTED" *)
+ input CLK_EXT;
+ input [8:0] CNTVALUEIN;
+ input [8:0] CNTVALUEIN_EXT;
+ input DATAIN;
+ input EN_VTC;
+ input EN_VTC_EXT;
+ input FIFO_RD_CLK;
+ input FIFO_RD_EN;
+ input INC;
+ input INC_EXT;
+ input LOAD;
+ input LOAD_EXT;
+ (* invertible_pin = "IS_RST_INVERTED" *)
+ input RST;
+ (* invertible_pin = "IS_RST_DLY_INVERTED" *)
+ input RST_DLY;
+ (* invertible_pin = "IS_RST_DLY_EXT_INVERTED" *)
+ input RST_DLY_EXT;
+ input [39:0] RX_BIT_CTRL_IN;
+ input [39:0] TX_BIT_CTRL_IN;
+endmodule
+
+module RXTX_BITSLICE (...);
+ parameter FIFO_SYNC_MODE = "FALSE";
+ parameter [0:0] INIT = 1'b1;
+ parameter [0:0] IS_RX_CLK_INVERTED = 1'b0;
+ parameter [0:0] IS_RX_RST_DLY_INVERTED = 1'b0;
+ parameter [0:0] IS_RX_RST_INVERTED = 1'b0;
+ parameter [0:0] IS_TX_CLK_INVERTED = 1'b0;
+ parameter [0:0] IS_TX_RST_DLY_INVERTED = 1'b0;
+ parameter [0:0] IS_TX_RST_INVERTED = 1'b0;
+ parameter LOOPBACK = "FALSE";
+ parameter NATIVE_ODELAY_BYPASS = "FALSE";
+ parameter ENABLE_PRE_EMPHASIS = "FALSE";
+ parameter RX_DATA_TYPE = "NONE";
+ parameter integer RX_DATA_WIDTH = 8;
+ parameter RX_DELAY_FORMAT = "TIME";
+ parameter RX_DELAY_TYPE = "FIXED";
+ parameter integer RX_DELAY_VALUE = 0;
+ parameter real RX_REFCLK_FREQUENCY = 300.0;
+ parameter RX_UPDATE_MODE = "ASYNC";
+ parameter SIM_DEVICE = "ULTRASCALE";
+ parameter real SIM_VERSION = 2.0;
+ parameter TBYTE_CTL = "TBYTE_IN";
+ parameter integer TX_DATA_WIDTH = 8;
+ parameter TX_DELAY_FORMAT = "TIME";
+ parameter TX_DELAY_TYPE = "FIXED";
+ parameter integer TX_DELAY_VALUE = 0;
+ parameter TX_OUTPUT_PHASE_90 = "FALSE";
+ parameter real TX_REFCLK_FREQUENCY = 300.0;
+ parameter TX_UPDATE_MODE = "ASYNC";
+ output FIFO_EMPTY;
+ output FIFO_WRCLK_OUT;
+ output O;
+ output [7:0] Q;
+ output [39:0] RX_BIT_CTRL_OUT;
+ output [8:0] RX_CNTVALUEOUT;
+ output [39:0] TX_BIT_CTRL_OUT;
+ output [8:0] TX_CNTVALUEOUT;
+ output T_OUT;
+ input [7:0] D;
+ input DATAIN;
+ input FIFO_RD_CLK;
+ input FIFO_RD_EN;
+ input [39:0] RX_BIT_CTRL_IN;
+ input RX_CE;
+ (* invertible_pin = "IS_RX_CLK_INVERTED" *)
+ input RX_CLK;
+ input [8:0] RX_CNTVALUEIN;
+ input RX_EN_VTC;
+ input RX_INC;
+ input RX_LOAD;
+ (* invertible_pin = "IS_RX_RST_INVERTED" *)
+ input RX_RST;
+ (* invertible_pin = "IS_RX_RST_DLY_INVERTED" *)
+ input RX_RST_DLY;
+ input T;
+ input TBYTE_IN;
+ input [39:0] TX_BIT_CTRL_IN;
+ input TX_CE;
+ (* invertible_pin = "IS_TX_CLK_INVERTED" *)
+ input TX_CLK;
+ input [8:0] TX_CNTVALUEIN;
+ input TX_EN_VTC;
+ input TX_INC;
+ input TX_LOAD;
+ (* invertible_pin = "IS_TX_RST_INVERTED" *)
+ input TX_RST;
+ (* invertible_pin = "IS_TX_RST_DLY_INVERTED" *)
+ input TX_RST_DLY;
+endmodule
+
+module TX_BITSLICE (...);
+ parameter integer DATA_WIDTH = 8;
+ parameter DELAY_FORMAT = "TIME";
+ parameter DELAY_TYPE = "FIXED";
+ parameter integer DELAY_VALUE = 0;
+ parameter ENABLE_PRE_EMPHASIS = "FALSE";
+ parameter [0:0] INIT = 1'b1;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_DLY_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_INVERTED = 1'b0;
+ parameter NATIVE_ODELAY_BYPASS = "FALSE";
+ parameter OUTPUT_PHASE_90 = "FALSE";
+ parameter real REFCLK_FREQUENCY = 300.0;
+ parameter SIM_DEVICE = "ULTRASCALE";
+ parameter real SIM_VERSION = 2.0;
+ parameter TBYTE_CTL = "TBYTE_IN";
+ parameter UPDATE_MODE = "ASYNC";
+ output [8:0] CNTVALUEOUT;
+ output O;
+ output [39:0] RX_BIT_CTRL_OUT;
+ output [39:0] TX_BIT_CTRL_OUT;
+ output T_OUT;
+ input CE;
+ (* invertible_pin = "IS_CLK_INVERTED" *)
+ input CLK;
+ input [8:0] CNTVALUEIN;
+ input [7:0] D;
+ input EN_VTC;
+ input INC;
+ input LOAD;
+ (* invertible_pin = "IS_RST_INVERTED" *)
+ input RST;
+ (* invertible_pin = "IS_RST_DLY_INVERTED" *)
+ input RST_DLY;
+ input [39:0] RX_BIT_CTRL_IN;
+ input T;
+ input TBYTE_IN;
+ input [39:0] TX_BIT_CTRL_IN;
+endmodule
+
+module TX_BITSLICE_TRI (...);
+ parameter integer DATA_WIDTH = 8;
+ parameter DELAY_FORMAT = "TIME";
+ parameter DELAY_TYPE = "FIXED";
+ parameter integer DELAY_VALUE = 0;
+ parameter [0:0] INIT = 1'b1;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_DLY_INVERTED = 1'b0;
+ parameter [0:0] IS_RST_INVERTED = 1'b0;
+ parameter NATIVE_ODELAY_BYPASS = "FALSE";
+ parameter OUTPUT_PHASE_90 = "FALSE";
+ parameter real REFCLK_FREQUENCY = 300.0;
+ parameter SIM_DEVICE = "ULTRASCALE";
+ parameter real SIM_VERSION = 2.0;
+ parameter UPDATE_MODE = "ASYNC";
+ output [39:0] BIT_CTRL_OUT;
+ output [8:0] CNTVALUEOUT;
+ output TRI_OUT;
+ input [39:0] BIT_CTRL_IN;
+ input CE;
+ (* invertible_pin = "IS_CLK_INVERTED" *)
+ input CLK;
+ input [8:0] CNTVALUEIN;
+ input EN_VTC;
+ input INC;
+ input LOAD;
+ (* invertible_pin = "IS_RST_INVERTED" *)
+ input RST;
+ (* invertible_pin = "IS_RST_DLY_INVERTED" *)
+ input RST_DLY;
+endmodule
+
+module HARD_SYNC (...);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ parameter integer LATENCY = 2;
+ output DOUT;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CLK_INVERTED" *)
+ input CLK;
+ input DIN;
+endmodule
+
+module IDDRE1 (...);
+ parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
+ parameter [0:0] IS_CB_INVERTED = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ output Q1;
+ output Q2;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_CB_INVERTED" *)
+ input CB;
+ input D;
+ input R;
+endmodule
+
+module LDCE (...);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_CLR_INVERTED = 1'b0;
+ parameter [0:0] IS_G_INVERTED = 1'b0;
+ parameter MSGON = "TRUE";
+ parameter XON = "TRUE";
+ output Q;
+ (* invertible_pin = "IS_CLR_INVERTED" *)
+ input CLR;
+ input D;
+ (* invertible_pin = "IS_G_INVERTED" *)
+ input G;
+ input GE;
+endmodule
+
+module LDPE (...);
+ parameter [0:0] INIT = 1'b1;
+ parameter [0:0] IS_G_INVERTED = 1'b0;
+ parameter [0:0] IS_PRE_INVERTED = 1'b0;
+ parameter MSGON = "TRUE";
+ parameter XON = "TRUE";
+ output Q;
+ input D;
+ (* invertible_pin = "IS_G_INVERTED" *)
+ input G;
+ input GE;
+ (* invertible_pin = "IS_PRE_INVERTED" *)
+ input PRE;
+endmodule
+
+module ODDRE1 (...);
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D1_INVERTED = 1'b0;
+ parameter [0:0] IS_D2_INVERTED = 1'b0;
+ parameter [0:0] SRVAL = 1'b0;
+ output Q;
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C;
+ (* invertible_pin = "IS_D1_INVERTED" *)
+ input D1;
+ (* invertible_pin = "IS_D2_INVERTED" *)
+ input D2;
+ input SR;
+endmodule
+
+(* keep *)
+module PS8 (...);
+ output [7:0] ADMA2PLCACK;
+ output [7:0] ADMA2PLTVLD;
+ output DPAUDIOREFCLK;
+ output DPAUXDATAOEN;
+ output DPAUXDATAOUT;
+ output DPLIVEVIDEODEOUT;
+ output [31:0] DPMAXISMIXEDAUDIOTDATA;
+ output DPMAXISMIXEDAUDIOTID;
+ output DPMAXISMIXEDAUDIOTVALID;
+ output DPSAXISAUDIOTREADY;
+ output DPVIDEOOUTHSYNC;
+ output [35:0] DPVIDEOOUTPIXEL1;
+ output DPVIDEOOUTVSYNC;
+ output DPVIDEOREFCLK;
+ output EMIOCAN0PHYTX;
+ output EMIOCAN1PHYTX;
+ output [1:0] EMIOENET0DMABUSWIDTH;
+ output EMIOENET0DMATXENDTOG;
+ output [93:0] EMIOENET0GEMTSUTIMERCNT;
+ output [7:0] EMIOENET0GMIITXD;
+ output EMIOENET0GMIITXEN;
+ output EMIOENET0GMIITXER;
+ output EMIOENET0MDIOMDC;
+ output EMIOENET0MDIOO;
+ output EMIOENET0MDIOTN;
+ output [7:0] EMIOENET0RXWDATA;
+ output EMIOENET0RXWEOP;
+ output EMIOENET0RXWERR;
+ output EMIOENET0RXWFLUSH;
+ output EMIOENET0RXWSOP;
+ output [44:0] EMIOENET0RXWSTATUS;
+ output EMIOENET0RXWWR;
+ output [2:0] EMIOENET0SPEEDMODE;
+ output EMIOENET0TXRRD;
+ output [3:0] EMIOENET0TXRSTATUS;
+ output [1:0] EMIOENET1DMABUSWIDTH;
+ output EMIOENET1DMATXENDTOG;
+ output [7:0] EMIOENET1GMIITXD;
+ output EMIOENET1GMIITXEN;
+ output EMIOENET1GMIITXER;
+ output EMIOENET1MDIOMDC;
+ output EMIOENET1MDIOO;
+ output EMIOENET1MDIOTN;
+ output [7:0] EMIOENET1RXWDATA;
+ output EMIOENET1RXWEOP;
+ output EMIOENET1RXWERR;
+ output EMIOENET1RXWFLUSH;
+ output EMIOENET1RXWSOP;
+ output [44:0] EMIOENET1RXWSTATUS;
+ output EMIOENET1RXWWR;
+ output [2:0] EMIOENET1SPEEDMODE;
+ output EMIOENET1TXRRD;
+ output [3:0] EMIOENET1TXRSTATUS;
+ output [1:0] EMIOENET2DMABUSWIDTH;
+ output EMIOENET2DMATXENDTOG;
+ output [7:0] EMIOENET2GMIITXD;
+ output EMIOENET2GMIITXEN;
+ output EMIOENET2GMIITXER;
+ output EMIOENET2MDIOMDC;
+ output EMIOENET2MDIOO;
+ output EMIOENET2MDIOTN;
+ output [7:0] EMIOENET2RXWDATA;
+ output EMIOENET2RXWEOP;
+ output EMIOENET2RXWERR;
+ output EMIOENET2RXWFLUSH;
+ output EMIOENET2RXWSOP;
+ output [44:0] EMIOENET2RXWSTATUS;
+ output EMIOENET2RXWWR;
+ output [2:0] EMIOENET2SPEEDMODE;
+ output EMIOENET2TXRRD;
+ output [3:0] EMIOENET2TXRSTATUS;
+ output [1:0] EMIOENET3DMABUSWIDTH;
+ output EMIOENET3DMATXENDTOG;
+ output [7:0] EMIOENET3GMIITXD;
+ output EMIOENET3GMIITXEN;
+ output EMIOENET3GMIITXER;
+ output EMIOENET3MDIOMDC;
+ output EMIOENET3MDIOO;
+ output EMIOENET3MDIOTN;
+ output [7:0] EMIOENET3RXWDATA;
+ output EMIOENET3RXWEOP;
+ output EMIOENET3RXWERR;
+ output EMIOENET3RXWFLUSH;
+ output EMIOENET3RXWSOP;
+ output [44:0] EMIOENET3RXWSTATUS;
+ output EMIOENET3RXWWR;
+ output [2:0] EMIOENET3SPEEDMODE;
+ output EMIOENET3TXRRD;
+ output [3:0] EMIOENET3TXRSTATUS;
+ output EMIOGEM0DELAYREQRX;
+ output EMIOGEM0DELAYREQTX;
+ output EMIOGEM0PDELAYREQRX;
+ output EMIOGEM0PDELAYREQTX;
+ output EMIOGEM0PDELAYRESPRX;
+ output EMIOGEM0PDELAYRESPTX;
+ output EMIOGEM0RXSOF;
+ output EMIOGEM0SYNCFRAMERX;
+ output EMIOGEM0SYNCFRAMETX;
+ output EMIOGEM0TSUTIMERCMPVAL;
+ output EMIOGEM0TXRFIXEDLAT;
+ output EMIOGEM0TXSOF;
+ output EMIOGEM1DELAYREQRX;
+ output EMIOGEM1DELAYREQTX;
+ output EMIOGEM1PDELAYREQRX;
+ output EMIOGEM1PDELAYREQTX;
+ output EMIOGEM1PDELAYRESPRX;
+ output EMIOGEM1PDELAYRESPTX;
+ output EMIOGEM1RXSOF;
+ output EMIOGEM1SYNCFRAMERX;
+ output EMIOGEM1SYNCFRAMETX;
+ output EMIOGEM1TSUTIMERCMPVAL;
+ output EMIOGEM1TXRFIXEDLAT;
+ output EMIOGEM1TXSOF;
+ output EMIOGEM2DELAYREQRX;
+ output EMIOGEM2DELAYREQTX;
+ output EMIOGEM2PDELAYREQRX;
+ output EMIOGEM2PDELAYREQTX;
+ output EMIOGEM2PDELAYRESPRX;
+ output EMIOGEM2PDELAYRESPTX;
+ output EMIOGEM2RXSOF;
+ output EMIOGEM2SYNCFRAMERX;
+ output EMIOGEM2SYNCFRAMETX;
+ output EMIOGEM2TSUTIMERCMPVAL;
+ output EMIOGEM2TXRFIXEDLAT;
+ output EMIOGEM2TXSOF;
+ output EMIOGEM3DELAYREQRX;
+ output EMIOGEM3DELAYREQTX;
+ output EMIOGEM3PDELAYREQRX;
+ output EMIOGEM3PDELAYREQTX;
+ output EMIOGEM3PDELAYRESPRX;
+ output EMIOGEM3PDELAYRESPTX;
+ output EMIOGEM3RXSOF;
+ output EMIOGEM3SYNCFRAMERX;
+ output EMIOGEM3SYNCFRAMETX;
+ output EMIOGEM3TSUTIMERCMPVAL;
+ output EMIOGEM3TXRFIXEDLAT;
+ output EMIOGEM3TXSOF;
+ output [95:0] EMIOGPIOO;
+ output [95:0] EMIOGPIOTN;
+ output EMIOI2C0SCLO;
+ output EMIOI2C0SCLTN;
+ output EMIOI2C0SDAO;
+ output EMIOI2C0SDATN;
+ output EMIOI2C1SCLO;
+ output EMIOI2C1SCLTN;
+ output EMIOI2C1SDAO;
+ output EMIOI2C1SDATN;
+ output EMIOSDIO0BUSPOWER;
+ output [2:0] EMIOSDIO0BUSVOLT;
+ output EMIOSDIO0CLKOUT;
+ output EMIOSDIO0CMDENA;
+ output EMIOSDIO0CMDOUT;
+ output [7:0] EMIOSDIO0DATAENA;
+ output [7:0] EMIOSDIO0DATAOUT;
+ output EMIOSDIO0LEDCONTROL;
+ output EMIOSDIO1BUSPOWER;
+ output [2:0] EMIOSDIO1BUSVOLT;
+ output EMIOSDIO1CLKOUT;
+ output EMIOSDIO1CMDENA;
+ output EMIOSDIO1CMDOUT;
+ output [7:0] EMIOSDIO1DATAENA;
+ output [7:0] EMIOSDIO1DATAOUT;
+ output EMIOSDIO1LEDCONTROL;
+ output EMIOSPI0MO;
+ output EMIOSPI0MOTN;
+ output EMIOSPI0SCLKO;
+ output EMIOSPI0SCLKTN;
+ output EMIOSPI0SO;
+ output EMIOSPI0SSNTN;
+ output [2:0] EMIOSPI0SSON;
+ output EMIOSPI0STN;
+ output EMIOSPI1MO;
+ output EMIOSPI1MOTN;
+ output EMIOSPI1SCLKO;
+ output EMIOSPI1SCLKTN;
+ output EMIOSPI1SO;
+ output EMIOSPI1SSNTN;
+ output [2:0] EMIOSPI1SSON;
+ output EMIOSPI1STN;
+ output [2:0] EMIOTTC0WAVEO;
+ output [2:0] EMIOTTC1WAVEO;
+ output [2:0] EMIOTTC2WAVEO;
+ output [2:0] EMIOTTC3WAVEO;
+ output EMIOU2DSPORTVBUSCTRLUSB30;
+ output EMIOU2DSPORTVBUSCTRLUSB31;
+ output EMIOU3DSPORTVBUSCTRLUSB30;
+ output EMIOU3DSPORTVBUSCTRLUSB31;
+ output EMIOUART0DTRN;
+ output EMIOUART0RTSN;
+ output EMIOUART0TX;
+ output EMIOUART1DTRN;
+ output EMIOUART1RTSN;
+ output EMIOUART1TX;
+ output EMIOWDT0RSTO;
+ output EMIOWDT1RSTO;
+ output FMIOGEM0FIFORXCLKTOPLBUFG;
+ output FMIOGEM0FIFOTXCLKTOPLBUFG;
+ output FMIOGEM1FIFORXCLKTOPLBUFG;
+ output FMIOGEM1FIFOTXCLKTOPLBUFG;
+ output FMIOGEM2FIFORXCLKTOPLBUFG;
+ output FMIOGEM2FIFOTXCLKTOPLBUFG;
+ output FMIOGEM3FIFORXCLKTOPLBUFG;
+ output FMIOGEM3FIFOTXCLKTOPLBUFG;
+ output FMIOGEMTSUCLKTOPLBUFG;
+ output [31:0] FTMGPO;
+ output [7:0] GDMA2PLCACK;
+ output [7:0] GDMA2PLTVLD;
+ output [39:0] MAXIGP0ARADDR;
+ output [1:0] MAXIGP0ARBURST;
+ output [3:0] MAXIGP0ARCACHE;
+ output [15:0] MAXIGP0ARID;
+ output [7:0] MAXIGP0ARLEN;
+ output MAXIGP0ARLOCK;
+ output [2:0] MAXIGP0ARPROT;
+ output [3:0] MAXIGP0ARQOS;
+ output [2:0] MAXIGP0ARSIZE;
+ output [15:0] MAXIGP0ARUSER;
+ output MAXIGP0ARVALID;
+ output [39:0] MAXIGP0AWADDR;
+ output [1:0] MAXIGP0AWBURST;
+ output [3:0] MAXIGP0AWCACHE;
+ output [15:0] MAXIGP0AWID;
+ output [7:0] MAXIGP0AWLEN;
+ output MAXIGP0AWLOCK;
+ output [2:0] MAXIGP0AWPROT;
+ output [3:0] MAXIGP0AWQOS;
+ output [2:0] MAXIGP0AWSIZE;
+ output [15:0] MAXIGP0AWUSER;
+ output MAXIGP0AWVALID;
+ output MAXIGP0BREADY;
+ output MAXIGP0RREADY;
+ output [127:0] MAXIGP0WDATA;
+ output MAXIGP0WLAST;
+ output [15:0] MAXIGP0WSTRB;
+ output MAXIGP0WVALID;
+ output [39:0] MAXIGP1ARADDR;
+ output [1:0] MAXIGP1ARBURST;
+ output [3:0] MAXIGP1ARCACHE;
+ output [15:0] MAXIGP1ARID;
+ output [7:0] MAXIGP1ARLEN;
+ output MAXIGP1ARLOCK;
+ output [2:0] MAXIGP1ARPROT;
+ output [3:0] MAXIGP1ARQOS;
+ output [2:0] MAXIGP1ARSIZE;
+ output [15:0] MAXIGP1ARUSER;
+ output MAXIGP1ARVALID;
+ output [39:0] MAXIGP1AWADDR;
+ output [1:0] MAXIGP1AWBURST;
+ output [3:0] MAXIGP1AWCACHE;
+ output [15:0] MAXIGP1AWID;
+ output [7:0] MAXIGP1AWLEN;
+ output MAXIGP1AWLOCK;
+ output [2:0] MAXIGP1AWPROT;
+ output [3:0] MAXIGP1AWQOS;
+ output [2:0] MAXIGP1AWSIZE;
+ output [15:0] MAXIGP1AWUSER;
+ output MAXIGP1AWVALID;
+ output MAXIGP1BREADY;
+ output MAXIGP1RREADY;
+ output [127:0] MAXIGP1WDATA;
+ output MAXIGP1WLAST;
+ output [15:0] MAXIGP1WSTRB;
+ output MAXIGP1WVALID;
+ output [39:0] MAXIGP2ARADDR;
+ output [1:0] MAXIGP2ARBURST;
+ output [3:0] MAXIGP2ARCACHE;
+ output [15:0] MAXIGP2ARID;
+ output [7:0] MAXIGP2ARLEN;
+ output MAXIGP2ARLOCK;
+ output [2:0] MAXIGP2ARPROT;
+ output [3:0] MAXIGP2ARQOS;
+ output [2:0] MAXIGP2ARSIZE;
+ output [15:0] MAXIGP2ARUSER;
+ output MAXIGP2ARVALID;
+ output [39:0] MAXIGP2AWADDR;
+ output [1:0] MAXIGP2AWBURST;
+ output [3:0] MAXIGP2AWCACHE;
+ output [15:0] MAXIGP2AWID;
+ output [7:0] MAXIGP2AWLEN;
+ output MAXIGP2AWLOCK;
+ output [2:0] MAXIGP2AWPROT;
+ output [3:0] MAXIGP2AWQOS;
+ output [2:0] MAXIGP2AWSIZE;
+ output [15:0] MAXIGP2AWUSER;
+ output MAXIGP2AWVALID;
+ output MAXIGP2BREADY;
+ output MAXIGP2RREADY;
+ output [127:0] MAXIGP2WDATA;
+ output MAXIGP2WLAST;
+ output [15:0] MAXIGP2WSTRB;
+ output MAXIGP2WVALID;
+ output OSCRTCCLK;
+ output [3:0] PLCLK;
+ output PMUAIBAFIFMFPDREQ;
+ output PMUAIBAFIFMLPDREQ;
+ output [46:0] PMUERRORTOPL;
+ output [31:0] PMUPLGPO;
+ output PSPLEVENTO;
+ output [63:0] PSPLIRQFPD;
+ output [99:0] PSPLIRQLPD;
+ output [3:0] PSPLSTANDBYWFE;
+ output [3:0] PSPLSTANDBYWFI;
+ output PSPLTRACECTL;
+ output [31:0] PSPLTRACEDATA;
+ output [3:0] PSPLTRIGACK;
+ output [3:0] PSPLTRIGGER;
+ output PSS_ALTO_CORE_PAD_MGTTXN0OUT;
+ output PSS_ALTO_CORE_PAD_MGTTXN1OUT;
+ output PSS_ALTO_CORE_PAD_MGTTXN2OUT;
+ output PSS_ALTO_CORE_PAD_MGTTXN3OUT;
+ output PSS_ALTO_CORE_PAD_MGTTXP0OUT;
+ output PSS_ALTO_CORE_PAD_MGTTXP1OUT;
+ output PSS_ALTO_CORE_PAD_MGTTXP2OUT;
+ output PSS_ALTO_CORE_PAD_MGTTXP3OUT;
+ output PSS_ALTO_CORE_PAD_PADO;
+ output RPUEVENTO0;
+ output RPUEVENTO1;
+ output [43:0] SACEFPDACADDR;
+ output [2:0] SACEFPDACPROT;
+ output [3:0] SACEFPDACSNOOP;
+ output SACEFPDACVALID;
+ output SACEFPDARREADY;
+ output SACEFPDAWREADY;
+ output [5:0] SACEFPDBID;
+ output [1:0] SACEFPDBRESP;
+ output SACEFPDBUSER;
+ output SACEFPDBVALID;
+ output SACEFPDCDREADY;
+ output SACEFPDCRREADY;
+ output [127:0] SACEFPDRDATA;
+ output [5:0] SACEFPDRID;
+ output SACEFPDRLAST;
+ output [3:0] SACEFPDRRESP;
+ output SACEFPDRUSER;
+ output SACEFPDRVALID;
+ output SACEFPDWREADY;
+ output SAXIACPARREADY;
+ output SAXIACPAWREADY;
+ output [4:0] SAXIACPBID;
+ output [1:0] SAXIACPBRESP;
+ output SAXIACPBVALID;
+ output [127:0] SAXIACPRDATA;
+ output [4:0] SAXIACPRID;
+ output SAXIACPRLAST;
+ output [1:0] SAXIACPRRESP;
+ output SAXIACPRVALID;
+ output SAXIACPWREADY;
+ output SAXIGP0ARREADY;
+ output SAXIGP0AWREADY;
+ output [5:0] SAXIGP0BID;
+ output [1:0] SAXIGP0BRESP;
+ output SAXIGP0BVALID;
+ output [3:0] SAXIGP0RACOUNT;
+ output [7:0] SAXIGP0RCOUNT;
+ output [127:0] SAXIGP0RDATA;
+ output [5:0] SAXIGP0RID;
+ output SAXIGP0RLAST;
+ output [1:0] SAXIGP0RRESP;
+ output SAXIGP0RVALID;
+ output [3:0] SAXIGP0WACOUNT;
+ output [7:0] SAXIGP0WCOUNT;
+ output SAXIGP0WREADY;
+ output SAXIGP1ARREADY;
+ output SAXIGP1AWREADY;
+ output [5:0] SAXIGP1BID;
+ output [1:0] SAXIGP1BRESP;
+ output SAXIGP1BVALID;
+ output [3:0] SAXIGP1RACOUNT;
+ output [7:0] SAXIGP1RCOUNT;
+ output [127:0] SAXIGP1RDATA;
+ output [5:0] SAXIGP1RID;
+ output SAXIGP1RLAST;
+ output [1:0] SAXIGP1RRESP;
+ output SAXIGP1RVALID;
+ output [3:0] SAXIGP1WACOUNT;
+ output [7:0] SAXIGP1WCOUNT;
+ output SAXIGP1WREADY;
+ output SAXIGP2ARREADY;
+ output SAXIGP2AWREADY;
+ output [5:0] SAXIGP2BID;
+ output [1:0] SAXIGP2BRESP;
+ output SAXIGP2BVALID;
+ output [3:0] SAXIGP2RACOUNT;
+ output [7:0] SAXIGP2RCOUNT;
+ output [127:0] SAXIGP2RDATA;
+ output [5:0] SAXIGP2RID;
+ output SAXIGP2RLAST;
+ output [1:0] SAXIGP2RRESP;
+ output SAXIGP2RVALID;
+ output [3:0] SAXIGP2WACOUNT;
+ output [7:0] SAXIGP2WCOUNT;
+ output SAXIGP2WREADY;
+ output SAXIGP3ARREADY;
+ output SAXIGP3AWREADY;
+ output [5:0] SAXIGP3BID;
+ output [1:0] SAXIGP3BRESP;
+ output SAXIGP3BVALID;
+ output [3:0] SAXIGP3RACOUNT;
+ output [7:0] SAXIGP3RCOUNT;
+ output [127:0] SAXIGP3RDATA;
+ output [5:0] SAXIGP3RID;
+ output SAXIGP3RLAST;
+ output [1:0] SAXIGP3RRESP;
+ output SAXIGP3RVALID;
+ output [3:0] SAXIGP3WACOUNT;
+ output [7:0] SAXIGP3WCOUNT;
+ output SAXIGP3WREADY;
+ output SAXIGP4ARREADY;
+ output SAXIGP4AWREADY;
+ output [5:0] SAXIGP4BID;
+ output [1:0] SAXIGP4BRESP;
+ output SAXIGP4BVALID;
+ output [3:0] SAXIGP4RACOUNT;
+ output [7:0] SAXIGP4RCOUNT;
+ output [127:0] SAXIGP4RDATA;
+ output [5:0] SAXIGP4RID;
+ output SAXIGP4RLAST;
+ output [1:0] SAXIGP4RRESP;
+ output SAXIGP4RVALID;
+ output [3:0] SAXIGP4WACOUNT;
+ output [7:0] SAXIGP4WCOUNT;
+ output SAXIGP4WREADY;
+ output SAXIGP5ARREADY;
+ output SAXIGP5AWREADY;
+ output [5:0] SAXIGP5BID;
+ output [1:0] SAXIGP5BRESP;
+ output SAXIGP5BVALID;
+ output [3:0] SAXIGP5RACOUNT;
+ output [7:0] SAXIGP5RCOUNT;
+ output [127:0] SAXIGP5RDATA;
+ output [5:0] SAXIGP5RID;
+ output SAXIGP5RLAST;
+ output [1:0] SAXIGP5RRESP;
+ output SAXIGP5RVALID;
+ output [3:0] SAXIGP5WACOUNT;
+ output [7:0] SAXIGP5WCOUNT;
+ output SAXIGP5WREADY;
+ output SAXIGP6ARREADY;
+ output SAXIGP6AWREADY;
+ output [5:0] SAXIGP6BID;
+ output [1:0] SAXIGP6BRESP;
+ output SAXIGP6BVALID;
+ output [3:0] SAXIGP6RACOUNT;
+ output [7:0] SAXIGP6RCOUNT;
+ output [127:0] SAXIGP6RDATA;
+ output [5:0] SAXIGP6RID;
+ output SAXIGP6RLAST;
+ output [1:0] SAXIGP6RRESP;
+ output SAXIGP6RVALID;
+ output [3:0] SAXIGP6WACOUNT;
+ output [7:0] SAXIGP6WCOUNT;
+ output SAXIGP6WREADY;
+ inout [3:0] PSS_ALTO_CORE_PAD_BOOTMODE;
+ inout PSS_ALTO_CORE_PAD_CLK;
+ inout PSS_ALTO_CORE_PAD_DONEB;
+ inout [17:0] PSS_ALTO_CORE_PAD_DRAMA;
+ inout PSS_ALTO_CORE_PAD_DRAMACTN;
+ inout PSS_ALTO_CORE_PAD_DRAMALERTN;
+ inout [1:0] PSS_ALTO_CORE_PAD_DRAMBA;
+ inout [1:0] PSS_ALTO_CORE_PAD_DRAMBG;
+ inout [1:0] PSS_ALTO_CORE_PAD_DRAMCK;
+ inout [1:0] PSS_ALTO_CORE_PAD_DRAMCKE;
+ inout [1:0] PSS_ALTO_CORE_PAD_DRAMCKN;
+ inout [1:0] PSS_ALTO_CORE_PAD_DRAMCSN;
+ inout [8:0] PSS_ALTO_CORE_PAD_DRAMDM;
+ inout [71:0] PSS_ALTO_CORE_PAD_DRAMDQ;
+ inout [8:0] PSS_ALTO_CORE_PAD_DRAMDQS;
+ inout [8:0] PSS_ALTO_CORE_PAD_DRAMDQSN;
+ inout [1:0] PSS_ALTO_CORE_PAD_DRAMODT;
+ inout PSS_ALTO_CORE_PAD_DRAMPARITY;
+ inout PSS_ALTO_CORE_PAD_DRAMRAMRSTN;
+ inout PSS_ALTO_CORE_PAD_ERROROUT;
+ inout PSS_ALTO_CORE_PAD_ERRORSTATUS;
+ inout PSS_ALTO_CORE_PAD_INITB;
+ inout PSS_ALTO_CORE_PAD_JTAGTCK;
+ inout PSS_ALTO_CORE_PAD_JTAGTDI;
+ inout PSS_ALTO_CORE_PAD_JTAGTDO;
+ inout PSS_ALTO_CORE_PAD_JTAGTMS;
+ inout [77:0] PSS_ALTO_CORE_PAD_MIO;
+ inout PSS_ALTO_CORE_PAD_PORB;
+ inout PSS_ALTO_CORE_PAD_PROGB;
+ inout PSS_ALTO_CORE_PAD_RCALIBINOUT;
+ inout PSS_ALTO_CORE_PAD_SRSTB;
+ inout PSS_ALTO_CORE_PAD_ZQ;
+ input [7:0] ADMAFCICLK;
+ input AIBPMUAFIFMFPDACK;
+ input AIBPMUAFIFMLPDACK;
+ input DDRCEXTREFRESHRANK0REQ;
+ input DDRCEXTREFRESHRANK1REQ;
+ input DDRCREFRESHPLCLK;
+ input DPAUXDATAIN;
+ input DPEXTERNALCUSTOMEVENT1;
+ input DPEXTERNALCUSTOMEVENT2;
+ input DPEXTERNALVSYNCEVENT;
+ input DPHOTPLUGDETECT;
+ input [7:0] DPLIVEGFXALPHAIN;
+ input [35:0] DPLIVEGFXPIXEL1IN;
+ input DPLIVEVIDEOINDE;
+ input DPLIVEVIDEOINHSYNC;
+ input [35:0] DPLIVEVIDEOINPIXEL1;
+ input DPLIVEVIDEOINVSYNC;
+ input DPMAXISMIXEDAUDIOTREADY;
+ input DPSAXISAUDIOCLK;
+ input [31:0] DPSAXISAUDIOTDATA;
+ input DPSAXISAUDIOTID;
+ input DPSAXISAUDIOTVALID;
+ input DPVIDEOINCLK;
+ input EMIOCAN0PHYRX;
+ input EMIOCAN1PHYRX;
+ input EMIOENET0DMATXSTATUSTOG;
+ input EMIOENET0EXTINTIN;
+ input EMIOENET0GMIICOL;
+ input EMIOENET0GMIICRS;
+ input EMIOENET0GMIIRXCLK;
+ input [7:0] EMIOENET0GMIIRXD;
+ input EMIOENET0GMIIRXDV;
+ input EMIOENET0GMIIRXER;
+ input EMIOENET0GMIITXCLK;
+ input EMIOENET0MDIOI;
+ input EMIOENET0RXWOVERFLOW;
+ input EMIOENET0TXRCONTROL;
+ input [7:0] EMIOENET0TXRDATA;
+ input EMIOENET0TXRDATARDY;
+ input EMIOENET0TXREOP;
+ input EMIOENET0TXRERR;
+ input EMIOENET0TXRFLUSHED;
+ input EMIOENET0TXRSOP;
+ input EMIOENET0TXRUNDERFLOW;
+ input EMIOENET0TXRVALID;
+ input EMIOENET1DMATXSTATUSTOG;
+ input EMIOENET1EXTINTIN;
+ input EMIOENET1GMIICOL;
+ input EMIOENET1GMIICRS;
+ input EMIOENET1GMIIRXCLK;
+ input [7:0] EMIOENET1GMIIRXD;
+ input EMIOENET1GMIIRXDV;
+ input EMIOENET1GMIIRXER;
+ input EMIOENET1GMIITXCLK;
+ input EMIOENET1MDIOI;
+ input EMIOENET1RXWOVERFLOW;
+ input EMIOENET1TXRCONTROL;
+ input [7:0] EMIOENET1TXRDATA;
+ input EMIOENET1TXRDATARDY;
+ input EMIOENET1TXREOP;
+ input EMIOENET1TXRERR;
+ input EMIOENET1TXRFLUSHED;
+ input EMIOENET1TXRSOP;
+ input EMIOENET1TXRUNDERFLOW;
+ input EMIOENET1TXRVALID;
+ input EMIOENET2DMATXSTATUSTOG;
+ input EMIOENET2EXTINTIN;
+ input EMIOENET2GMIICOL;
+ input EMIOENET2GMIICRS;
+ input EMIOENET2GMIIRXCLK;
+ input [7:0] EMIOENET2GMIIRXD;
+ input EMIOENET2GMIIRXDV;
+ input EMIOENET2GMIIRXER;
+ input EMIOENET2GMIITXCLK;
+ input EMIOENET2MDIOI;
+ input EMIOENET2RXWOVERFLOW;
+ input EMIOENET2TXRCONTROL;
+ input [7:0] EMIOENET2TXRDATA;
+ input EMIOENET2TXRDATARDY;
+ input EMIOENET2TXREOP;
+ input EMIOENET2TXRERR;
+ input EMIOENET2TXRFLUSHED;
+ input EMIOENET2TXRSOP;
+ input EMIOENET2TXRUNDERFLOW;
+ input EMIOENET2TXRVALID;
+ input EMIOENET3DMATXSTATUSTOG;
+ input EMIOENET3EXTINTIN;
+ input EMIOENET3GMIICOL;
+ input EMIOENET3GMIICRS;
+ input EMIOENET3GMIIRXCLK;
+ input [7:0] EMIOENET3GMIIRXD;
+ input EMIOENET3GMIIRXDV;
+ input EMIOENET3GMIIRXER;
+ input EMIOENET3GMIITXCLK;
+ input EMIOENET3MDIOI;
+ input EMIOENET3RXWOVERFLOW;
+ input EMIOENET3TXRCONTROL;
+ input [7:0] EMIOENET3TXRDATA;
+ input EMIOENET3TXRDATARDY;
+ input EMIOENET3TXREOP;
+ input EMIOENET3TXRERR;
+ input EMIOENET3TXRFLUSHED;
+ input EMIOENET3TXRSOP;
+ input EMIOENET3TXRUNDERFLOW;
+ input EMIOENET3TXRVALID;
+ input EMIOENETTSUCLK;
+ input [1:0] EMIOGEM0TSUINCCTRL;
+ input [1:0] EMIOGEM1TSUINCCTRL;
+ input [1:0] EMIOGEM2TSUINCCTRL;
+ input [1:0] EMIOGEM3TSUINCCTRL;
+ input [95:0] EMIOGPIOI;
+ input EMIOHUBPORTOVERCRNTUSB20;
+ input EMIOHUBPORTOVERCRNTUSB21;
+ input EMIOHUBPORTOVERCRNTUSB30;
+ input EMIOHUBPORTOVERCRNTUSB31;
+ input EMIOI2C0SCLI;
+ input EMIOI2C0SDAI;
+ input EMIOI2C1SCLI;
+ input EMIOI2C1SDAI;
+ input EMIOSDIO0CDN;
+ input EMIOSDIO0CMDIN;
+ input [7:0] EMIOSDIO0DATAIN;
+ input EMIOSDIO0FBCLKIN;
+ input EMIOSDIO0WP;
+ input EMIOSDIO1CDN;
+ input EMIOSDIO1CMDIN;
+ input [7:0] EMIOSDIO1DATAIN;
+ input EMIOSDIO1FBCLKIN;
+ input EMIOSDIO1WP;
+ input EMIOSPI0MI;
+ input EMIOSPI0SCLKI;
+ input EMIOSPI0SI;
+ input EMIOSPI0SSIN;
+ input EMIOSPI1MI;
+ input EMIOSPI1SCLKI;
+ input EMIOSPI1SI;
+ input EMIOSPI1SSIN;
+ input [2:0] EMIOTTC0CLKI;
+ input [2:0] EMIOTTC1CLKI;
+ input [2:0] EMIOTTC2CLKI;
+ input [2:0] EMIOTTC3CLKI;
+ input EMIOUART0CTSN;
+ input EMIOUART0DCDN;
+ input EMIOUART0DSRN;
+ input EMIOUART0RIN;
+ input EMIOUART0RX;
+ input EMIOUART1CTSN;
+ input EMIOUART1DCDN;
+ input EMIOUART1DSRN;
+ input EMIOUART1RIN;
+ input EMIOUART1RX;
+ input EMIOWDT0CLKI;
+ input EMIOWDT1CLKI;
+ input FMIOGEM0FIFORXCLKFROMPL;
+ input FMIOGEM0FIFOTXCLKFROMPL;
+ input FMIOGEM0SIGNALDETECT;
+ input FMIOGEM1FIFORXCLKFROMPL;
+ input FMIOGEM1FIFOTXCLKFROMPL;
+ input FMIOGEM1SIGNALDETECT;
+ input FMIOGEM2FIFORXCLKFROMPL;
+ input FMIOGEM2FIFOTXCLKFROMPL;
+ input FMIOGEM2SIGNALDETECT;
+ input FMIOGEM3FIFORXCLKFROMPL;
+ input FMIOGEM3FIFOTXCLKFROMPL;
+ input FMIOGEM3SIGNALDETECT;
+ input FMIOGEMTSUCLKFROMPL;
+ input [31:0] FTMGPI;
+ input [7:0] GDMAFCICLK;
+ input MAXIGP0ACLK;
+ input MAXIGP0ARREADY;
+ input MAXIGP0AWREADY;
+ input [15:0] MAXIGP0BID;
+ input [1:0] MAXIGP0BRESP;
+ input MAXIGP0BVALID;
+ input [127:0] MAXIGP0RDATA;
+ input [15:0] MAXIGP0RID;
+ input MAXIGP0RLAST;
+ input [1:0] MAXIGP0RRESP;
+ input MAXIGP0RVALID;
+ input MAXIGP0WREADY;
+ input MAXIGP1ACLK;
+ input MAXIGP1ARREADY;
+ input MAXIGP1AWREADY;
+ input [15:0] MAXIGP1BID;
+ input [1:0] MAXIGP1BRESP;
+ input MAXIGP1BVALID;
+ input [127:0] MAXIGP1RDATA;
+ input [15:0] MAXIGP1RID;
+ input MAXIGP1RLAST;
+ input [1:0] MAXIGP1RRESP;
+ input MAXIGP1RVALID;
+ input MAXIGP1WREADY;
+ input MAXIGP2ACLK;
+ input MAXIGP2ARREADY;
+ input MAXIGP2AWREADY;
+ input [15:0] MAXIGP2BID;
+ input [1:0] MAXIGP2BRESP;
+ input MAXIGP2BVALID;
+ input [127:0] MAXIGP2RDATA;
+ input [15:0] MAXIGP2RID;
+ input MAXIGP2RLAST;
+ input [1:0] MAXIGP2RRESP;
+ input MAXIGP2RVALID;
+ input MAXIGP2WREADY;
+ input NFIQ0LPDRPU;
+ input NFIQ1LPDRPU;
+ input NIRQ0LPDRPU;
+ input NIRQ1LPDRPU;
+ input [7:0] PL2ADMACVLD;
+ input [7:0] PL2ADMATACK;
+ input [7:0] PL2GDMACVLD;
+ input [7:0] PL2GDMATACK;
+ input PLACECLK;
+ input PLACPINACT;
+ input [3:0] PLFPGASTOP;
+ input [2:0] PLLAUXREFCLKFPD;
+ input [1:0] PLLAUXREFCLKLPD;
+ input [31:0] PLPMUGPI;
+ input [3:0] PLPSAPUGICFIQ;
+ input [3:0] PLPSAPUGICIRQ;
+ input PLPSEVENTI;
+ input [7:0] PLPSIRQ0;
+ input [7:0] PLPSIRQ1;
+ input PLPSTRACECLK;
+ input [3:0] PLPSTRIGACK;
+ input [3:0] PLPSTRIGGER;
+ input [3:0] PMUERRORFROMPL;
+ input PSS_ALTO_CORE_PAD_MGTRXN0IN;
+ input PSS_ALTO_CORE_PAD_MGTRXN1IN;
+ input PSS_ALTO_CORE_PAD_MGTRXN2IN;
+ input PSS_ALTO_CORE_PAD_MGTRXN3IN;
+ input PSS_ALTO_CORE_PAD_MGTRXP0IN;
+ input PSS_ALTO_CORE_PAD_MGTRXP1IN;
+ input PSS_ALTO_CORE_PAD_MGTRXP2IN;
+ input PSS_ALTO_CORE_PAD_MGTRXP3IN;
+ input PSS_ALTO_CORE_PAD_PADI;
+ input PSS_ALTO_CORE_PAD_REFN0IN;
+ input PSS_ALTO_CORE_PAD_REFN1IN;
+ input PSS_ALTO_CORE_PAD_REFN2IN;
+ input PSS_ALTO_CORE_PAD_REFN3IN;
+ input PSS_ALTO_CORE_PAD_REFP0IN;
+ input PSS_ALTO_CORE_PAD_REFP1IN;
+ input PSS_ALTO_CORE_PAD_REFP2IN;
+ input PSS_ALTO_CORE_PAD_REFP3IN;
+ input RPUEVENTI0;
+ input RPUEVENTI1;
+ input SACEFPDACREADY;
+ input [43:0] SACEFPDARADDR;
+ input [1:0] SACEFPDARBAR;
+ input [1:0] SACEFPDARBURST;
+ input [3:0] SACEFPDARCACHE;
+ input [1:0] SACEFPDARDOMAIN;
+ input [5:0] SACEFPDARID;
+ input [7:0] SACEFPDARLEN;
+ input SACEFPDARLOCK;
+ input [2:0] SACEFPDARPROT;
+ input [3:0] SACEFPDARQOS;
+ input [3:0] SACEFPDARREGION;
+ input [2:0] SACEFPDARSIZE;
+ input [3:0] SACEFPDARSNOOP;
+ input [15:0] SACEFPDARUSER;
+ input SACEFPDARVALID;
+ input [43:0] SACEFPDAWADDR;
+ input [1:0] SACEFPDAWBAR;
+ input [1:0] SACEFPDAWBURST;
+ input [3:0] SACEFPDAWCACHE;
+ input [1:0] SACEFPDAWDOMAIN;
+ input [5:0] SACEFPDAWID;
+ input [7:0] SACEFPDAWLEN;
+ input SACEFPDAWLOCK;
+ input [2:0] SACEFPDAWPROT;
+ input [3:0] SACEFPDAWQOS;
+ input [3:0] SACEFPDAWREGION;
+ input [2:0] SACEFPDAWSIZE;
+ input [2:0] SACEFPDAWSNOOP;
+ input [15:0] SACEFPDAWUSER;
+ input SACEFPDAWVALID;
+ input SACEFPDBREADY;
+ input [127:0] SACEFPDCDDATA;
+ input SACEFPDCDLAST;
+ input SACEFPDCDVALID;
+ input [4:0] SACEFPDCRRESP;
+ input SACEFPDCRVALID;
+ input SACEFPDRACK;
+ input SACEFPDRREADY;
+ input SACEFPDWACK;
+ input [127:0] SACEFPDWDATA;
+ input SACEFPDWLAST;
+ input [15:0] SACEFPDWSTRB;
+ input SACEFPDWUSER;
+ input SACEFPDWVALID;
+ input SAXIACPACLK;
+ input [39:0] SAXIACPARADDR;
+ input [1:0] SAXIACPARBURST;
+ input [3:0] SAXIACPARCACHE;
+ input [4:0] SAXIACPARID;
+ input [7:0] SAXIACPARLEN;
+ input SAXIACPARLOCK;
+ input [2:0] SAXIACPARPROT;
+ input [3:0] SAXIACPARQOS;
+ input [2:0] SAXIACPARSIZE;
+ input [1:0] SAXIACPARUSER;
+ input SAXIACPARVALID;
+ input [39:0] SAXIACPAWADDR;
+ input [1:0] SAXIACPAWBURST;
+ input [3:0] SAXIACPAWCACHE;
+ input [4:0] SAXIACPAWID;
+ input [7:0] SAXIACPAWLEN;
+ input SAXIACPAWLOCK;
+ input [2:0] SAXIACPAWPROT;
+ input [3:0] SAXIACPAWQOS;
+ input [2:0] SAXIACPAWSIZE;
+ input [1:0] SAXIACPAWUSER;
+ input SAXIACPAWVALID;
+ input SAXIACPBREADY;
+ input SAXIACPRREADY;
+ input [127:0] SAXIACPWDATA;
+ input SAXIACPWLAST;
+ input [15:0] SAXIACPWSTRB;
+ input SAXIACPWVALID;
+ input [48:0] SAXIGP0ARADDR;
+ input [1:0] SAXIGP0ARBURST;
+ input [3:0] SAXIGP0ARCACHE;
+ input [5:0] SAXIGP0ARID;
+ input [7:0] SAXIGP0ARLEN;
+ input SAXIGP0ARLOCK;
+ input [2:0] SAXIGP0ARPROT;
+ input [3:0] SAXIGP0ARQOS;
+ input [2:0] SAXIGP0ARSIZE;
+ input SAXIGP0ARUSER;
+ input SAXIGP0ARVALID;
+ input [48:0] SAXIGP0AWADDR;
+ input [1:0] SAXIGP0AWBURST;
+ input [3:0] SAXIGP0AWCACHE;
+ input [5:0] SAXIGP0AWID;
+ input [7:0] SAXIGP0AWLEN;
+ input SAXIGP0AWLOCK;
+ input [2:0] SAXIGP0AWPROT;
+ input [3:0] SAXIGP0AWQOS;
+ input [2:0] SAXIGP0AWSIZE;
+ input SAXIGP0AWUSER;
+ input SAXIGP0AWVALID;
+ input SAXIGP0BREADY;
+ input SAXIGP0RCLK;
+ input SAXIGP0RREADY;
+ input SAXIGP0WCLK;
+ input [127:0] SAXIGP0WDATA;
+ input SAXIGP0WLAST;
+ input [15:0] SAXIGP0WSTRB;
+ input SAXIGP0WVALID;
+ input [48:0] SAXIGP1ARADDR;
+ input [1:0] SAXIGP1ARBURST;
+ input [3:0] SAXIGP1ARCACHE;
+ input [5:0] SAXIGP1ARID;
+ input [7:0] SAXIGP1ARLEN;
+ input SAXIGP1ARLOCK;
+ input [2:0] SAXIGP1ARPROT;
+ input [3:0] SAXIGP1ARQOS;
+ input [2:0] SAXIGP1ARSIZE;
+ input SAXIGP1ARUSER;
+ input SAXIGP1ARVALID;
+ input [48:0] SAXIGP1AWADDR;
+ input [1:0] SAXIGP1AWBURST;
+ input [3:0] SAXIGP1AWCACHE;
+ input [5:0] SAXIGP1AWID;
+ input [7:0] SAXIGP1AWLEN;
+ input SAXIGP1AWLOCK;
+ input [2:0] SAXIGP1AWPROT;
+ input [3:0] SAXIGP1AWQOS;
+ input [2:0] SAXIGP1AWSIZE;
+ input SAXIGP1AWUSER;
+ input SAXIGP1AWVALID;
+ input SAXIGP1BREADY;
+ input SAXIGP1RCLK;
+ input SAXIGP1RREADY;
+ input SAXIGP1WCLK;
+ input [127:0] SAXIGP1WDATA;
+ input SAXIGP1WLAST;
+ input [15:0] SAXIGP1WSTRB;
+ input SAXIGP1WVALID;
+ input [48:0] SAXIGP2ARADDR;
+ input [1:0] SAXIGP2ARBURST;
+ input [3:0] SAXIGP2ARCACHE;
+ input [5:0] SAXIGP2ARID;
+ input [7:0] SAXIGP2ARLEN;
+ input SAXIGP2ARLOCK;
+ input [2:0] SAXIGP2ARPROT;
+ input [3:0] SAXIGP2ARQOS;
+ input [2:0] SAXIGP2ARSIZE;
+ input SAXIGP2ARUSER;
+ input SAXIGP2ARVALID;
+ input [48:0] SAXIGP2AWADDR;
+ input [1:0] SAXIGP2AWBURST;
+ input [3:0] SAXIGP2AWCACHE;
+ input [5:0] SAXIGP2AWID;
+ input [7:0] SAXIGP2AWLEN;
+ input SAXIGP2AWLOCK;
+ input [2:0] SAXIGP2AWPROT;
+ input [3:0] SAXIGP2AWQOS;
+ input [2:0] SAXIGP2AWSIZE;
+ input SAXIGP2AWUSER;
+ input SAXIGP2AWVALID;
+ input SAXIGP2BREADY;
+ input SAXIGP2RCLK;
+ input SAXIGP2RREADY;
+ input SAXIGP2WCLK;
+ input [127:0] SAXIGP2WDATA;
+ input SAXIGP2WLAST;
+ input [15:0] SAXIGP2WSTRB;
+ input SAXIGP2WVALID;
+ input [48:0] SAXIGP3ARADDR;
+ input [1:0] SAXIGP3ARBURST;
+ input [3:0] SAXIGP3ARCACHE;
+ input [5:0] SAXIGP3ARID;
+ input [7:0] SAXIGP3ARLEN;
+ input SAXIGP3ARLOCK;
+ input [2:0] SAXIGP3ARPROT;
+ input [3:0] SAXIGP3ARQOS;
+ input [2:0] SAXIGP3ARSIZE;
+ input SAXIGP3ARUSER;
+ input SAXIGP3ARVALID;
+ input [48:0] SAXIGP3AWADDR;
+ input [1:0] SAXIGP3AWBURST;
+ input [3:0] SAXIGP3AWCACHE;
+ input [5:0] SAXIGP3AWID;
+ input [7:0] SAXIGP3AWLEN;
+ input SAXIGP3AWLOCK;
+ input [2:0] SAXIGP3AWPROT;
+ input [3:0] SAXIGP3AWQOS;
+ input [2:0] SAXIGP3AWSIZE;
+ input SAXIGP3AWUSER;
+ input SAXIGP3AWVALID;
+ input SAXIGP3BREADY;
+ input SAXIGP3RCLK;
+ input SAXIGP3RREADY;
+ input SAXIGP3WCLK;
+ input [127:0] SAXIGP3WDATA;
+ input SAXIGP3WLAST;
+ input [15:0] SAXIGP3WSTRB;
+ input SAXIGP3WVALID;
+ input [48:0] SAXIGP4ARADDR;
+ input [1:0] SAXIGP4ARBURST;
+ input [3:0] SAXIGP4ARCACHE;
+ input [5:0] SAXIGP4ARID;
+ input [7:0] SAXIGP4ARLEN;
+ input SAXIGP4ARLOCK;
+ input [2:0] SAXIGP4ARPROT;
+ input [3:0] SAXIGP4ARQOS;
+ input [2:0] SAXIGP4ARSIZE;
+ input SAXIGP4ARUSER;
+ input SAXIGP4ARVALID;
+ input [48:0] SAXIGP4AWADDR;
+ input [1:0] SAXIGP4AWBURST;
+ input [3:0] SAXIGP4AWCACHE;
+ input [5:0] SAXIGP4AWID;
+ input [7:0] SAXIGP4AWLEN;
+ input SAXIGP4AWLOCK;
+ input [2:0] SAXIGP4AWPROT;
+ input [3:0] SAXIGP4AWQOS;
+ input [2:0] SAXIGP4AWSIZE;
+ input SAXIGP4AWUSER;
+ input SAXIGP4AWVALID;
+ input SAXIGP4BREADY;
+ input SAXIGP4RCLK;
+ input SAXIGP4RREADY;
+ input SAXIGP4WCLK;
+ input [127:0] SAXIGP4WDATA;
+ input SAXIGP4WLAST;
+ input [15:0] SAXIGP4WSTRB;
+ input SAXIGP4WVALID;
+ input [48:0] SAXIGP5ARADDR;
+ input [1:0] SAXIGP5ARBURST;
+ input [3:0] SAXIGP5ARCACHE;
+ input [5:0] SAXIGP5ARID;
+ input [7:0] SAXIGP5ARLEN;
+ input SAXIGP5ARLOCK;
+ input [2:0] SAXIGP5ARPROT;
+ input [3:0] SAXIGP5ARQOS;
+ input [2:0] SAXIGP5ARSIZE;
+ input SAXIGP5ARUSER;
+ input SAXIGP5ARVALID;
+ input [48:0] SAXIGP5AWADDR;
+ input [1:0] SAXIGP5AWBURST;
+ input [3:0] SAXIGP5AWCACHE;
+ input [5:0] SAXIGP5AWID;
+ input [7:0] SAXIGP5AWLEN;
+ input SAXIGP5AWLOCK;
+ input [2:0] SAXIGP5AWPROT;
+ input [3:0] SAXIGP5AWQOS;
+ input [2:0] SAXIGP5AWSIZE;
+ input SAXIGP5AWUSER;
+ input SAXIGP5AWVALID;
+ input SAXIGP5BREADY;
+ input SAXIGP5RCLK;
+ input SAXIGP5RREADY;
+ input SAXIGP5WCLK;
+ input [127:0] SAXIGP5WDATA;
+ input SAXIGP5WLAST;
+ input [15:0] SAXIGP5WSTRB;
+ input SAXIGP5WVALID;
+ input [48:0] SAXIGP6ARADDR;
+ input [1:0] SAXIGP6ARBURST;
+ input [3:0] SAXIGP6ARCACHE;
+ input [5:0] SAXIGP6ARID;
+ input [7:0] SAXIGP6ARLEN;
+ input SAXIGP6ARLOCK;
+ input [2:0] SAXIGP6ARPROT;
+ input [3:0] SAXIGP6ARQOS;
+ input [2:0] SAXIGP6ARSIZE;
+ input SAXIGP6ARUSER;
+ input SAXIGP6ARVALID;
+ input [48:0] SAXIGP6AWADDR;
+ input [1:0] SAXIGP6AWBURST;
+ input [3:0] SAXIGP6AWCACHE;
+ input [5:0] SAXIGP6AWID;
+ input [7:0] SAXIGP6AWLEN;
+ input SAXIGP6AWLOCK;
+ input [2:0] SAXIGP6AWPROT;
+ input [3:0] SAXIGP6AWQOS;
+ input [2:0] SAXIGP6AWSIZE;
+ input SAXIGP6AWUSER;
+ input SAXIGP6AWVALID;
+ input SAXIGP6BREADY;
+ input SAXIGP6RCLK;
+ input SAXIGP6RREADY;
+ input SAXIGP6WCLK;
+ input [127:0] SAXIGP6WDATA;
+ input SAXIGP6WLAST;
+ input [15:0] SAXIGP6WSTRB;
+ input SAXIGP6WVALID;
+ input [59:0] STMEVENT;
+endmodule
+
diff --git a/tests/ice40/.gitignore b/tests/ice40/.gitignore
new file mode 100644
index 000000000..9a71dca69
--- /dev/null
+++ b/tests/ice40/.gitignore
@@ -0,0 +1,4 @@
+*.log
+/run-test.mk
++*_synth.v
++*_testbench
diff --git a/tests/ice40/add_sub.v b/tests/ice40/add_sub.v
new file mode 100644
index 000000000..177c32e30
--- /dev/null
+++ b/tests/ice40/add_sub.v
@@ -0,0 +1,13 @@
+module top
+(
+ input [3:0] x,
+ input [3:0] y,
+
+ output [3:0] A,
+ output [3:0] B
+ );
+
+assign A = x + y;
+assign B = x - y;
+
+endmodule
diff --git a/tests/ice40/add_sub.ys b/tests/ice40/add_sub.ys
new file mode 100644
index 000000000..4a998d98d
--- /dev/null
+++ b/tests/ice40/add_sub.ys
@@ -0,0 +1,9 @@
+read_verilog add_sub.v
+hierarchy -top top
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 11 t:SB_LUT4
+select -assert-count 6 t:SB_CARRY
+select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D
+
diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v
new file mode 100644
index 000000000..09dc36001
--- /dev/null
+++ b/tests/ice40/adffs.v
@@ -0,0 +1,87 @@
+module adff
+ ( input d, clk, clr, output reg q );
+ initial begin
+ q = 0;
+ end
+ always @( posedge clk, posedge clr )
+ if ( clr )
+ q <= 1'b0;
+ else
+ q <= d;
+endmodule
+
+module adffn
+ ( input d, clk, clr, output reg q );
+ initial begin
+ q = 0;
+ end
+ always @( posedge clk, negedge clr )
+ if ( !clr )
+ q <= 1'b0;
+ else
+ q <= d;
+endmodule
+
+module dffs
+ ( input d, clk, pre, clr, output reg q );
+ initial begin
+ q = 0;
+ end
+ always @( posedge clk, posedge pre )
+ if ( pre )
+ q <= 1'b1;
+ else
+ q <= d;
+endmodule
+
+module ndffnr
+ ( input d, clk, pre, clr, output reg q );
+ initial begin
+ q = 0;
+ end
+ always @( negedge clk, negedge pre )
+ if ( !pre )
+ q <= 1'b1;
+ else
+ q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3
+);
+
+dffs u_dffs (
+ .clk (clk ),
+ .clr (clr),
+ .pre (pre),
+ .d (a ),
+ .q (b )
+ );
+
+ndffnr u_ndffnr (
+ .clk (clk ),
+ .clr (clr),
+ .pre (pre),
+ .d (a ),
+ .q (b1 )
+ );
+
+adff u_adff (
+ .clk (clk ),
+ .clr (clr),
+ .d (a ),
+ .q (b2 )
+ );
+
+adffn u_adffn (
+ .clk (clk ),
+ .clr (clr),
+ .d (a ),
+ .q (b3 )
+ );
+
+endmodule
diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys
new file mode 100644
index 000000000..548060b66
--- /dev/null
+++ b/tests/ice40/adffs.ys
@@ -0,0 +1,11 @@
+read_verilog adffs.v
+proc
+flatten
+equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFFNS
+select -assert-count 2 t:SB_DFFR
+select -assert-count 1 t:SB_DFFS
+select -assert-count 2 t:SB_LUT4
+select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/alu.v b/tests/ice40/alu.v
new file mode 100644
index 000000000..f82cc2e21
--- /dev/null
+++ b/tests/ice40/alu.v
@@ -0,0 +1,19 @@
+module top (
+ input clock,
+ input [31:0] dinA, dinB,
+ input [2:0] opcode,
+ output reg [31:0] dout
+);
+ always @(posedge clock) begin
+ case (opcode)
+ 0: dout <= dinA + dinB;
+ 1: dout <= dinA - dinB;
+ 2: dout <= dinA >> dinB;
+ 3: dout <= $signed(dinA) >>> dinB;
+ 4: dout <= dinA << dinB;
+ 5: dout <= dinA & dinB;
+ 6: dout <= dinA | dinB;
+ 7: dout <= dinA ^ dinB;
+ endcase
+ end
+endmodule
diff --git a/tests/ice40/alu.ys b/tests/ice40/alu.ys
new file mode 100644
index 000000000..bd859efc4
--- /dev/null
+++ b/tests/ice40/alu.ys
@@ -0,0 +1,11 @@
+read_verilog alu.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 62 t:SB_CARRY
+select -assert-count 32 t:SB_DFF
+select -assert-count 655 t:SB_LUT4
+select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/counter.v b/tests/ice40/counter.v
new file mode 100644
index 000000000..52852f8ac
--- /dev/null
+++ b/tests/ice40/counter.v
@@ -0,0 +1,17 @@
+module top (
+out,
+clk,
+reset
+);
+ output [7:0] out;
+ input clk, reset;
+ reg [7:0] out;
+
+ always @(posedge clk, posedge reset)
+ if (reset) begin
+ out <= 8'b0 ;
+ end else
+ out <= out + 1;
+
+
+endmodule
diff --git a/tests/ice40/counter.ys b/tests/ice40/counter.ys
new file mode 100644
index 000000000..c65c21622
--- /dev/null
+++ b/tests/ice40/counter.ys
@@ -0,0 +1,11 @@
+read_verilog counter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 6 t:SB_CARRY
+select -assert-count 8 t:SB_DFFR
+select -assert-count 8 t:SB_LUT4
+select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/dffs.v b/tests/ice40/dffs.v
new file mode 100644
index 000000000..d97840c43
--- /dev/null
+++ b/tests/ice40/dffs.v
@@ -0,0 +1,37 @@
+module dff
+ ( input d, clk, output reg q );
+ always @( posedge clk )
+ q <= d;
+endmodule
+
+module dffe
+ ( input d, clk, en, output reg q );
+ initial begin
+ q = 0;
+ end
+ always @( posedge clk )
+ if ( en )
+ q <= d;
+endmodule
+
+module top (
+input clk,
+input en,
+input a,
+output b,b1,
+);
+
+dff u_dff (
+ .clk (clk ),
+ .d (a ),
+ .q (b )
+ );
+
+dffe u_ndffe (
+ .clk (clk ),
+ .en (en),
+ .d (a ),
+ .q (b1 )
+ );
+
+endmodule
diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys
new file mode 100644
index 000000000..ee7f884b1
--- /dev/null
+++ b/tests/ice40/dffs.ys
@@ -0,0 +1,10 @@
+read_verilog dffs.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFF
+select -assert-count 1 t:SB_DFFE
+select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D
diff --git a/tests/ice40/div_mod.v b/tests/ice40/div_mod.v
new file mode 100644
index 000000000..64a36707d
--- /dev/null
+++ b/tests/ice40/div_mod.v
@@ -0,0 +1,13 @@
+module top
+(
+ input [3:0] x,
+ input [3:0] y,
+
+ output [3:0] A,
+ output [3:0] B
+ );
+
+assign A = x % y;
+assign B = x / y;
+
+endmodule
diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys
new file mode 100644
index 000000000..821d6c301
--- /dev/null
+++ b/tests/ice40/div_mod.ys
@@ -0,0 +1,9 @@
+read_verilog div_mod.v
+hierarchy -top top
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 59 t:SB_LUT4
+select -assert-count 41 t:SB_CARRY
+select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D
diff --git a/tests/ice40/dpram.v b/tests/ice40/dpram.v
new file mode 100644
index 000000000..3ea4c1f27
--- /dev/null
+++ b/tests/ice40/dpram.v
@@ -0,0 +1,23 @@
+/*
+Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72].
+*/
+module top (din, write_en, waddr, wclk, raddr, rclk, dout);
+parameter addr_width = 8;
+parameter data_width = 8;
+input [addr_width-1:0] waddr, raddr;
+input [data_width-1:0] din;
+input write_en, wclk, rclk;
+output [data_width-1:0] dout;
+reg [data_width-1:0] dout;
+reg [data_width-1:0] mem [(1<<addr_width)-1:0]
+/* synthesis syn_ramstyle = "no_rw_check" */ ;
+always @(posedge wclk) // Write memory.
+begin
+if (write_en)
+mem[waddr] <= din; // Using write address bus.
+end
+always @(posedge rclk) // Read memory.
+begin
+dout <= mem[raddr]; // Using read address bus.
+end
+endmodule
diff --git a/tests/ice40/dpram.ys b/tests/ice40/dpram.ys
new file mode 100644
index 000000000..4f6a253ea
--- /dev/null
+++ b/tests/ice40/dpram.ys
@@ -0,0 +1,15 @@
+read_verilog dpram.v
+hierarchy -top top
+proc
+memory -nomap
+equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd top
+select -assert-count 1 t:SB_RAM40_4K
+select -assert-none t:SB_RAM40_4K %% t:* %D
diff --git a/tests/ice40/fsm.v b/tests/ice40/fsm.v
new file mode 100644
index 000000000..0605bd102
--- /dev/null
+++ b/tests/ice40/fsm.v
@@ -0,0 +1,73 @@
+ module fsm (
+ clock,
+ reset,
+ req_0,
+ req_1,
+ gnt_0,
+ gnt_1
+ );
+ input clock,reset,req_0,req_1;
+ output gnt_0,gnt_1;
+ wire clock,reset,req_0,req_1;
+ reg gnt_0,gnt_1;
+
+ parameter SIZE = 3 ;
+ parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
+
+ reg [SIZE-1:0] state;
+ reg [SIZE-1:0] next_state;
+
+ always @ (posedge clock)
+ begin : FSM
+ if (reset == 1'b1) begin
+ state <= #1 IDLE;
+ gnt_0 <= 0;
+ gnt_1 <= 0;
+ end else
+ case(state)
+ IDLE : if (req_0 == 1'b1) begin
+ state <= #1 GNT0;
+ gnt_0 <= 1;
+ end else if (req_1 == 1'b1) begin
+ gnt_1 <= 1;
+ state <= #1 GNT0;
+ end else begin
+ state <= #1 IDLE;
+ end
+ GNT0 : if (req_0 == 1'b1) begin
+ state <= #1 GNT0;
+ end else begin
+ gnt_0 <= 0;
+ state <= #1 IDLE;
+ end
+ GNT1 : if (req_1 == 1'b1) begin
+ state <= #1 GNT2;
+ gnt_1 <= req_0;
+ end
+ GNT2 : if (req_0 == 1'b1) begin
+ state <= #1 GNT1;
+ gnt_1 <= req_1;
+ end
+ default : state <= #1 IDLE;
+ endcase
+ end
+
+ endmodule
+
+ module top (
+input clk,
+input rst,
+input a,
+input b,
+output g0,
+output g1
+);
+
+fsm u_fsm ( .clock(clk),
+ .reset(rst),
+ .req_0(a),
+ .req_1(b),
+ .gnt_0(g0),
+ .gnt_1(g1));
+
+endmodule
diff --git a/tests/ice40/fsm.ys b/tests/ice40/fsm.ys
new file mode 100644
index 000000000..4cc8629d6
--- /dev/null
+++ b/tests/ice40/fsm.ys
@@ -0,0 +1,13 @@
+read_verilog fsm.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 2 t:SB_DFFESR
+select -assert-count 2 t:SB_DFFSR
+select -assert-count 1 t:SB_DFFSS
+select -assert-count 13 t:SB_LUT4
+select -assert-none t:SB_DFFESR t:SB_DFFSR t:SB_DFFSS t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/ice40_opt.ys b/tests/ice40/ice40_opt.ys
new file mode 100644
index 000000000..b17c69c91
--- /dev/null
+++ b/tests/ice40/ice40_opt.ys
@@ -0,0 +1,26 @@
+read_verilog -icells -formal <<EOT
+module top(input CI, I0, output [1:0] CO, output O);
+ wire A = 1'b0, B = 1'b0;
+ \$__ICE40_CARRY_WRAPPER #(
+ // A[0]: 1010 1010 1010 1010
+ // A[1]: 1100 1100 1100 1100
+ // A[2]: 1111 0000 1111 0000
+ // A[3]: 1111 1111 0000 0000
+ .LUT(~16'b 0110_1001_1001_0110)
+ ) u0 (
+ .A(A),
+ .B(B),
+ .CI(CI),
+ .I0(I0),
+ .I3(CI),
+ .CO(CO[0]),
+ .O(O)
+ );
+ SB_CARRY u1 (.I0(~A), .I1(~B), .CI(CI), .CO(CO[1]));
+endmodule
+EOT
+
+equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt
+design -load postopt
+select -assert-count 1 t:*
+select -assert-count 1 t:$lut
diff --git a/tests/ice40/latches.v b/tests/ice40/latches.v
new file mode 100644
index 000000000..9dc43e4c2
--- /dev/null
+++ b/tests/ice40/latches.v
@@ -0,0 +1,58 @@
+module latchp
+ ( input d, clk, en, output reg q );
+ always @*
+ if ( en )
+ q <= d;
+endmodule
+
+module latchn
+ ( input d, clk, en, output reg q );
+ always @*
+ if ( !en )
+ q <= d;
+endmodule
+
+module latchsr
+ ( input d, clk, en, clr, pre, output reg q );
+ always @*
+ if ( clr )
+ q <= 1'b0;
+ else if ( pre )
+ q <= 1'b1;
+ else if ( en )
+ q <= d;
+endmodule
+
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2
+);
+
+
+latchp u_latchp (
+ .en (clk ),
+ .d (a ),
+ .q (b )
+ );
+
+
+latchn u_latchn (
+ .en (clk ),
+ .d (a ),
+ .q (b1 )
+ );
+
+
+latchsr u_latchsr (
+ .en (clk ),
+ .clr (clr),
+ .pre (pre),
+ .d (a ),
+ .q (b2 )
+ );
+
+endmodule
diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys
new file mode 100644
index 000000000..f3562559e
--- /dev/null
+++ b/tests/ice40/latches.ys
@@ -0,0 +1,15 @@
+read_verilog latches.v
+design -save read
+
+proc
+async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
+flatten
+synth_ice40
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+
+design -load read
+synth_ice40
+cd top
+select -assert-count 4 t:SB_LUT4
+select -assert-none t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/logic.v b/tests/ice40/logic.v
new file mode 100644
index 000000000..e5343cae0
--- /dev/null
+++ b/tests/ice40/logic.v
@@ -0,0 +1,18 @@
+module top
+(
+ input [0:7] in,
+ output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
+ );
+
+ assign B1 = in[0] & in[1];
+ assign B2 = in[0] | in[1];
+ assign B3 = in[0] ~& in[1];
+ assign B4 = in[0] ~| in[1];
+ assign B5 = in[0] ^ in[1];
+ assign B6 = in[0] ~^ in[1];
+ assign B7 = ~in[0];
+ assign B8 = in[0];
+ assign B9 = in[0:1] && in [2:3];
+ assign B10 = in[0:1] || in [2:3];
+
+endmodule
diff --git a/tests/ice40/logic.ys b/tests/ice40/logic.ys
new file mode 100644
index 000000000..fc5e5b1d8
--- /dev/null
+++ b/tests/ice40/logic.ys
@@ -0,0 +1,7 @@
+read_verilog logic.v
+hierarchy -top top
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 9 t:SB_LUT4
+select -assert-none t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/macc.v b/tests/ice40/macc.v
new file mode 100644
index 000000000..6c3676c83
--- /dev/null
+++ b/tests/ice40/macc.v
@@ -0,0 +1,25 @@
+/*
+Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 77].
+*/
+module top(clk,a,b,c,set);
+parameter A_WIDTH = 6 /*4*/;
+parameter B_WIDTH = 6 /*3*/;
+input set;
+input clk;
+input signed [(A_WIDTH - 1):0] a;
+input signed [(B_WIDTH - 1):0] b;
+output signed [(A_WIDTH + B_WIDTH - 1):0] c;
+reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c;
+assign c = reg_tmp_c;
+always @(posedge clk)
+begin
+if(set)
+begin
+reg_tmp_c <= 0;
+end
+else
+begin
+reg_tmp_c <= a * b + c;
+end
+end
+endmodule
diff --git a/tests/ice40/macc.ys b/tests/ice40/macc.ys
new file mode 100644
index 000000000..0f4c19be5
--- /dev/null
+++ b/tests/ice40/macc.ys
@@ -0,0 +1,13 @@
+read_verilog macc.v
+proc
+hierarchy -top top
+#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
+
+equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 -dsp
+async2sync
+equiv_opt -run prove: -assert null
+
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_MAC16
+select -assert-none t:SB_MAC16 %% t:* %D
diff --git a/tests/ice40/memory.v b/tests/ice40/memory.v
new file mode 100644
index 000000000..cb7753f7b
--- /dev/null
+++ b/tests/ice40/memory.v
@@ -0,0 +1,21 @@
+module top
+(
+ input [7:0] data_a,
+ input [6:1] addr_a,
+ input we_a, clk,
+ output reg [7:0] q_a
+);
+ // Declare the RAM variable
+ reg [7:0] ram[63:0];
+
+ // Port A
+ always @ (posedge clk)
+ begin
+ if (we_a)
+ begin
+ ram[addr_a] <= data_a;
+ q_a <= data_a;
+ end
+ q_a <= ram[addr_a];
+ end
+endmodule
diff --git a/tests/ice40/memory.ys b/tests/ice40/memory.ys
new file mode 100644
index 000000000..a66afbae6
--- /dev/null
+++ b/tests/ice40/memory.ys
@@ -0,0 +1,15 @@
+read_verilog memory.v
+hierarchy -top top
+proc
+memory -nomap
+equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd top
+select -assert-count 1 t:SB_RAM40_4K
+select -assert-none t:SB_RAM40_4K %% t:* %D
diff --git a/tests/ice40/mul.v b/tests/ice40/mul.v
new file mode 100644
index 000000000..d5b48b1d7
--- /dev/null
+++ b/tests/ice40/mul.v
@@ -0,0 +1,11 @@
+module top
+(
+ input [5:0] x,
+ input [5:0] y,
+
+ output [11:0] A,
+ );
+
+assign A = x * y;
+
+endmodule
diff --git a/tests/ice40/mul.ys b/tests/ice40/mul.ys
new file mode 100644
index 000000000..8a0822a84
--- /dev/null
+++ b/tests/ice40/mul.ys
@@ -0,0 +1,7 @@
+read_verilog mul.v
+hierarchy -top top
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_MAC16
+select -assert-none t:SB_MAC16 %% t:* %D
diff --git a/tests/ice40/mux.v b/tests/ice40/mux.v
new file mode 100644
index 000000000..0814b733e
--- /dev/null
+++ b/tests/ice40/mux.v
@@ -0,0 +1,100 @@
+module mux2 (S,A,B,Y);
+ input S;
+ input A,B;
+ output reg Y;
+
+ always @(*)
+ Y = (S)? B : A;
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+ case( S )
+ 0 : Y = D[0];
+ 1 : Y = D[1];
+ 2 : Y = D[2];
+ 3 : Y = D[3];
+ endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+ case( S )
+ 0 : Y = D[0];
+ 1 : Y = D[1];
+ 2 : Y = D[2];
+ 3 : Y = D[3];
+ 4 : Y = D[4];
+ 5 : Y = D[5];
+ 6 : Y = D[6];
+ 7 : Y = D[7];
+ endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y);
+ input [15:0] D;
+ input [3:0] S;
+ output Y;
+
+assign Y = D[S];
+
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+mux2 u_mux2 (
+ .S (S[0]),
+ .A (D[0]),
+ .B (D[1]),
+ .Y (M2)
+ );
+
+
+mux4 u_mux4 (
+ .S (S[1:0]),
+ .D (D[3:0]),
+ .Y (M4)
+ );
+
+mux8 u_mux8 (
+ .S (S[2:0]),
+ .D (D[7:0]),
+ .Y (M8)
+ );
+
+mux16 u_mux16 (
+ .S (S[3:0]),
+ .D (D[15:0]),
+ .Y (M16)
+ );
+
+endmodule
diff --git a/tests/ice40/mux.ys b/tests/ice40/mux.ys
new file mode 100644
index 000000000..182b49499
--- /dev/null
+++ b/tests/ice40/mux.ys
@@ -0,0 +1,8 @@
+read_verilog mux.v
+proc
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 19 t:SB_LUT4
+select -assert-none t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/rom.v b/tests/ice40/rom.v
new file mode 100644
index 000000000..0a0f41f37
--- /dev/null
+++ b/tests/ice40/rom.v
@@ -0,0 +1,18 @@
+/*
+Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 74].
+*/
+module top(data, addr);
+output [3:0] data;
+input [4:0] addr;
+always @(addr) begin
+case (addr)
+0 : data = 'h4;
+1 : data = 'h9;
+2 : data = 'h1;
+15 : data = 'h8;
+16 : data = 'h1;
+17 : data = 'h0;
+default : data = 'h0;
+endcase
+end
+endmodule
diff --git a/tests/ice40/rom.ys b/tests/ice40/rom.ys
new file mode 100644
index 000000000..41d214e2a
--- /dev/null
+++ b/tests/ice40/rom.ys
@@ -0,0 +1,8 @@
+read_verilog rom.v
+proc
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 5 t:SB_LUT4
+select -assert-none t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh
new file mode 100755
index 000000000..46716f9a0
--- /dev/null
+++ b/tests/ice40/run-test.sh
@@ -0,0 +1,20 @@
+#!/usr/bin/env bash
+set -e
+{
+echo "all::"
+for x in *.ys; do
+ echo "all:: run-$x"
+ echo "run-$x:"
+ echo " @echo 'Running $x..'"
+ echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
+done
+for s in *.sh; do
+ if [ "$s" != "run-test.sh" ]; then
+ echo "all:: run-$s"
+ echo "run-$s:"
+ echo " @echo 'Running $s..'"
+ echo " @bash $s"
+ fi
+done
+} > run-test.mk
+exec ${MAKE:-make} -f run-test.mk
diff --git a/tests/ice40/shifter.v b/tests/ice40/shifter.v
new file mode 100644
index 000000000..c55632552
--- /dev/null
+++ b/tests/ice40/shifter.v
@@ -0,0 +1,22 @@
+module top (
+out,
+clk,
+in
+);
+ output [7:0] out;
+ input signed clk, in;
+ reg signed [7:0] out = 0;
+
+ always @(posedge clk)
+ begin
+`ifndef BUG
+ out <= out >> 1;
+ out[7] <= in;
+`else
+
+ out <= out << 1;
+ out[7] <= in;
+`endif
+ end
+
+endmodule
diff --git a/tests/ice40/shifter.ys b/tests/ice40/shifter.ys
new file mode 100644
index 000000000..47d95d298
--- /dev/null
+++ b/tests/ice40/shifter.ys
@@ -0,0 +1,9 @@
+read_verilog shifter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 8 t:SB_DFF
+select -assert-none t:SB_DFF %% t:* %D
diff --git a/tests/ice40/tribuf.v b/tests/ice40/tribuf.v
new file mode 100644
index 000000000..870a02584
--- /dev/null
+++ b/tests/ice40/tribuf.v
@@ -0,0 +1,23 @@
+module tristate (en, i, o);
+ input en;
+ input i;
+ output o;
+
+ assign o = en ? i : 1'bz;
+
+endmodule
+
+
+module top (
+input en,
+input a,
+output b
+);
+
+tristate u_tri (
+ .en (en ),
+ .i (a ),
+ .o (b )
+ );
+
+endmodule
diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys
new file mode 100644
index 000000000..d1e1b3108
--- /dev/null
+++ b/tests/ice40/tribuf.ys
@@ -0,0 +1,9 @@
+read_verilog tribuf.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:$_TBUF_
+select -assert-none t:$_TBUF_ %% t:* %D
diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys
index f0306efa1..e0acead82 100644
--- a/tests/opt/opt_expr.ys
+++ b/tests/opt/opt_expr.ys
@@ -204,7 +204,7 @@ endmodule
EOT
check
-equiv_opt opt_expr -fine
+equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
@@ -218,6 +218,76 @@ endmodule
EOT
check
-equiv_opt opt_expr -fine
+equiv_opt -assert opt_expr -fine
design -load postopt
select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
+
+###########
+
+design -reset
+read_verilog -icells <<EOT
+module opt_expr_shiftx_1bit(input [2:0] a, input [1:0] b, output y);
+ \$shiftx #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) shiftx (.A({1'bx,a}), .B(b), .Y(y));
+endmodule
+EOT
+check
+
+equiv_opt -assert opt_expr
+design -load postopt
+select -assert-count 1 t:$shiftx r:A_WIDTH=3 %i
+
+###########
+
+design -reset
+read_verilog -icells <<EOT
+module opt_expr_shiftx_3bit(input [9:0] a, input [3:0] b, output [2:0] y);
+ \$shiftx #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(14), .B_WIDTH(4), .Y_WIDTH(3)) shiftx (.A({4'bxx00,a}), .B(b), .Y(y));
+endmodule
+EOT
+check
+
+equiv_opt -assert opt_expr
+design -load postopt
+select -assert-count 1 t:$shiftx r:A_WIDTH=12 %i
+
+###########
+
+design -reset
+read_verilog -icells <<EOT
+module opt_expr_shift_1bit(input [2:0] a, input [1:0] b, output y);
+ \$shift #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) shift (.A({1'b0,a}), .B(b), .Y(y));
+endmodule
+EOT
+check
+
+equiv_opt -assert opt_expr
+design -load postopt
+select -assert-count 1 t:$shift r:A_WIDTH=3 %i
+
+###########
+
+design -reset
+read_verilog -icells <<EOT
+module opt_expr_shift_3bit(input [9:0] a, input [3:0] b, output [2:0] y);
+ \$shift #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(14), .B_WIDTH(4), .Y_WIDTH(3)) shift (.A({4'b0x0x,a}), .B(b), .Y(y));
+endmodule
+EOT
+check
+
+equiv_opt -assert opt_expr
+design -load postopt
+select -assert-count 1 t:$shift r:A_WIDTH=10 %i
+
+###########
+
+design -reset
+read_verilog -icells <<EOT
+module opt_expr_shift_3bit_keepdc(input [9:0] a, input [3:0] b, output [2:0] y);
+ \$shift #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(14), .B_WIDTH(4), .Y_WIDTH(3)) shift (.A({4'b0x0x,a}), .B(b), .Y(y));
+endmodule
+EOT
+check
+
+equiv_opt -assert opt_expr -keepdc
+design -load postopt
+select -assert-count 1 t:$shift r:A_WIDTH=13 %i
diff --git a/tests/sat/initval.v b/tests/sat/initval.v
index 5b661f8d6..81f71b5ba 100644
--- a/tests/sat/initval.v
+++ b/tests/sat/initval.v
@@ -1,6 +1,7 @@
-module test(input clk, input [3:0] bar, output [3:0] foo);
+module test(input clk, input [3:0] bar, output [3:0] foo, asdf);
reg [3:0] foo = 0;
reg [3:0] last_bar = 0;
+ reg [3:0] asdf = 4'b1xxx;
always @*
foo[1:0] <= bar[1:0];
@@ -11,5 +12,10 @@ module test(input clk, input [3:0] bar, output [3:0] foo);
always @(posedge clk)
last_bar <= bar;
+ always @(posedge clk)
+ asdf[3] <= bar[3];
+ always @*
+ asdf[2:0] = 3'b111;
+
assert property (foo == {last_bar[3:2], bar[1:0]});
endmodule
diff --git a/tests/simple/peepopt.v b/tests/simple/peepopt.v
deleted file mode 100644
index 1bf427897..000000000
--- a/tests/simple/peepopt.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o);
-assign o = i[s*W+:W];
-endmodule
-
-module peepopt_shiftmul_1 (output y, input [2:0] w);
-assign y = 1'b1 >> (w * (3'b110));
-endmodule
-
-module peepopt_muldiv_0(input [1:0] i, output [1:0] o);
-wire [3:0] t;
-assign t = i * 3;
-assign o = t / 3;
-endmodule
diff --git a/tests/simple/run-test.sh b/tests/simple/run-test.sh
index 967ac49f2..f20fd0d30 100755
--- a/tests/simple/run-test.sh
+++ b/tests/simple/run-test.sh
@@ -12,7 +12,7 @@ done
shift "$((OPTIND-1))"
# check for Icarus Verilog
-if ! which iverilog > /dev/null ; then
+if ! command -v iverilog > /dev/null ; then
echo "$0: Error: Icarus Verilog 'iverilog' not found."
exit 1
fi
diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh
index 49ae23338..0d4262005 100755
--- a/tests/simple_abc9/run-test.sh
+++ b/tests/simple_abc9/run-test.sh
@@ -12,7 +12,7 @@ done
shift "$((OPTIND-1))"
# check for Icarus Verilog
-if ! which iverilog > /dev/null ; then
+if ! command -v iverilog > /dev/null ; then
echo "$0: Error: Icarus Verilog 'iverilog' not found."
exit 1
fi
@@ -20,4 +20,10 @@ fi
cp ../simple/*.v .
cp ../simple/*.sv .
DOLLAR='?'
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-n 300 -p 'hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4 -box ../abc.box; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'"
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-n 300 -p '\
+ hierarchy; \
+ synth -run coarse; \
+ opt -full; \
+ techmap; abc9 -lut 4 -box ../abc.box; \
+ check -assert; \
+ select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'"
diff --git a/tests/techmap/.gitignore b/tests/techmap/.gitignore
index 397b4a762..cfed22fc5 100644
--- a/tests/techmap/.gitignore
+++ b/tests/techmap/.gitignore
@@ -1 +1,2 @@
*.log
+/*.mk
diff --git a/tests/techmap/autopurge.ys b/tests/techmap/autopurge.ys
new file mode 100644
index 000000000..1eb99ec37
--- /dev/null
+++ b/tests/techmap/autopurge.ys
@@ -0,0 +1,62 @@
+# https://github.com/YosysHQ/yosys/issues/1381
+read_verilog <<EOT
+module sub(input i, output o, (* techmap_autopurge *) input j);
+foobar f(i, o, j);
+endmodule
+EOT
+design -stash techmap
+
+read_verilog <<EOT
+(* blackbox *)
+module sub(input i, output o, input j);
+endmodule
+
+(* blackbox *)
+module foobar(input i, output o, input j);
+endmodule
+
+module top(input i, output o);
+sub s0(i, o);
+endmodule
+EOT
+
+techmap -map %techmap
+hierarchy
+check -assert
+
+# https://github.com/YosysHQ/yosys/issues/1391
+design -reset
+read_verilog <<EOT
+module sub(input i, output o, (* techmap_autopurge *) input [1:0] j);
+foobar f(i, o, j);
+endmodule
+EOT
+design -stash techmap
+
+read_verilog <<EOT
+(* blackbox *)
+module sub(input i, output o, input j);
+endmodule
+
+(* blackbox *)
+module foobar(input i, output o, input j);
+endmodule
+
+module top(input i, output o);
+sub s0(i, o);
+endmodule
+EOT
+
+techmap -map %techmap
+hierarchy
+check -assert
+
+read_verilog -overwrite <<EOT
+module top(input i, output o);
+wire j;
+sub s0(i, o, j);
+endmodule
+EOT
+
+techmap -map %techmap
+hierarchy
diff --git a/tests/techmap/clkbufmap.ys b/tests/techmap/clkbufmap.ys
new file mode 100644
index 000000000..f1277864e
--- /dev/null
+++ b/tests/techmap/clkbufmap.ys
@@ -0,0 +1,96 @@
+read_verilog <<EOT
+module clkbuf (input i, (* clkbuf_driver *) output o); endmodule
+module dff ((* clkbuf_sink *) input clk, input d, output q); endmodule
+module dffe ((* clkbuf_sink *) input c, input d, e, output q); endmodule
+module latch (input e, d, output q); endmodule
+module clkgen (output o); endmodule
+
+module top(input clk1, clk2, clk3, d, e, output [4:0] q);
+wire clk4, clk5, clk6;
+dff s0 (.clk(clk1), .d(d), .q(q[0]));
+dffe s1 (.c(clk2), .d(d), .e(e), .q(q[1]));
+latch s2 (.e(clk3), .d(d), .q(q[2]));
+sub s3 (.sclk4(clk4), .sclk5(clk5), .sclk6(clk6), .sd(d), .sq(q[3]));
+dff s4 (.clk(clk4), .d(d), .q(q[4]));
+dff s5 (.clk(clk5), .d(d), .q(q[4]));
+dff s6 (.clk(clk6), .d(d), .q(q[4]));
+endmodule
+
+module sub(output sclk4, output sclk5, output sclk6, input sd, output sq);
+wire tmp;
+clkgen s7(.o(sclk4));
+clkgen s8(.o(sclk5));
+clkgen s9(.o(tmp));
+clkbuf s10(.i(tmp), .o(sclk6));
+dff s11(.clk(sclk4), .d(sd), .q(sq));
+endmodule
+EOT
+
+hierarchy -auto-top
+design -save ref
+
+# ----------------------
+
+design -load ref
+clkbufmap -buf clkbuf o:i
+select -assert-count 3 top/t:clkbuf
+select -assert-count 2 sub/t:clkbuf
+select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf'
+select -assert-count 1 @clk1 # Check there is one such fanout
+select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout
+select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i # And that one fanout is 's0'
+select -set clk2 w:clk2 %a %co t:clkbuf %i
+select -assert-count 1 @clk2
+select -assert-count 1 @clk2 %x:+[o] %co c:s* %i
+select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i
+select -set clk5 w:clk5 %a %ci t:clkbuf %i
+select -assert-count 1 @clk5
+select -assert-count 1 @clk5 %x:+[o] %co c:s5 %i
+select -assert-count 1 @clk5 %x:+[i] %ci c:s3 %i
+select -set sclk4 w:sclk4 %a %ci t:clkbuf %i
+select -assert-count 1 @sclk4
+select -assert-count 1 @sclk4 %x:+[o] %co c:s11 %i
+select -assert-count 1 @sclk4 %x:+[i] %ci c:s7 %i
+
+# ----------------------
+
+design -load ref
+setattr -set clkbuf_inhibit 0 w:clk1
+setattr -set clkbuf_inhibit 1 w:clk2
+clkbufmap -buf clkbuf o:i
+select -assert-count 2 top/t:clkbuf
+select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf'
+select -assert-count 1 @clk1 # Check there is one such fanout
+select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout
+select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i # And that one fanout is 's0'
+select -assert-count 0 w:clk2 %a %co t:clkbuf %i
+
+# ----------------------
+
+design -load ref
+setattr -set clkbuf_inhibit 1 w:clk1
+setattr -set buffer_type "bufg" w:clk2
+clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
+select -assert-count 3 top/t:clkbuf
+select -assert-count 2 sub/t:clkbuf
+select -set clk1 w:clk1 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf'
+select -assert-count 1 @clk1 # Check there is one such fanout
+select -assert-count 1 @clk1 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout
+select -assert-count 1 @clk1 %x:+[o] %co c:s0 %i # And that one fanout is 's0'
+select -set clk2 w:clk2 %a %co t:clkbuf %i # Find 'clk1' fanouts that are 'clkbuf'
+select -assert-count 1 @clk2 # Check there is one such fanout
+select -assert-count 1 @clk2 %x:+[o] %co c:s* %i # Check that the 'o' of that clkbuf drives one fanout
+select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i # And that one fanout is 's0'
+
+# ----------------------
+
+design -load ref
+setattr -set buffer_type "none" w:clk1
+setattr -set buffer_type "bufr" w:clk2
+setattr -set buffer_type "bufr" w:sclk4
+setattr -set buffer_type "bufr" w:sclk5
+clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
+select -assert-count 0 w:clk1 %a %co t:clkbuf %i
+select -assert-count 0 w:clk2 %a %co t:clkbuf %i
+select -assert-count 0 top/t:clkbuf
+select -assert-count 1 sub/t:clkbuf
diff --git a/tests/techmap/dff2dffs.ys b/tests/techmap/dff2dffs.ys
new file mode 100644
index 000000000..13f1a3cf3
--- /dev/null
+++ b/tests/techmap/dff2dffs.ys
@@ -0,0 +1,50 @@
+read_verilog << EOT
+module top(...);
+input clk;
+input d;
+input sr;
+output reg q0, q1, q2, q3, q4, q5;
+
+initial q0 = 1'b0;
+initial q1 = 1'b0;
+initial q2 = 1'b1;
+initial q3 = 1'b1;
+initial q4 = 1'bx;
+initial q5 = 1'bx;
+
+always @(posedge clk) begin
+ q0 <= sr ? 1'b0 : d;
+ q1 <= sr ? 1'b1 : d;
+ q2 <= sr ? 1'b0 : d;
+ q3 <= sr ? 1'b1 : d;
+ q4 <= sr ? 1'b0 : d;
+ q5 <= sr ? 1'b1 : d;
+end
+
+endmodule
+EOT
+
+proc
+simplemap
+design -save ref
+
+dff2dffs
+clean
+
+select -assert-count 1 w:q0 %x t:$__DFFS_PP0_ %i
+select -assert-count 1 w:q1 %x t:$__DFFS_PP1_ %i
+select -assert-count 1 w:q2 %x t:$__DFFS_PP0_ %i
+select -assert-count 1 w:q3 %x t:$__DFFS_PP1_ %i
+select -assert-count 1 w:q4 %x t:$__DFFS_PP0_ %i
+select -assert-count 1 w:q5 %x t:$__DFFS_PP1_ %i
+
+design -load ref
+dff2dffs -match-init
+clean
+
+select -assert-count 1 w:q0 %x t:$__DFFS_PP0_ %i
+select -assert-count 0 w:q1 %x t:$__DFFS_PP1_ %i
+select -assert-count 0 w:q2 %x t:$__DFFS_PP0_ %i
+select -assert-count 1 w:q3 %x t:$__DFFS_PP1_ %i
+select -assert-count 1 w:q4 %x t:$__DFFS_PP0_ %i
+select -assert-count 1 w:q5 %x t:$__DFFS_PP1_ %i
diff --git a/tests/techmap/extractinv.ys b/tests/techmap/extractinv.ys
new file mode 100644
index 000000000..6146f829a
--- /dev/null
+++ b/tests/techmap/extractinv.ys
@@ -0,0 +1,41 @@
+read_verilog << EOT
+
+module ff4(...);
+parameter [0:0] CLK_INV = 1'b0;
+parameter [3:0] DATA_INV = 4'b0000;
+(* invertible_pin = "CLK_INV" *)
+input clk;
+(* invertible_pin = "DATA_INV" *)
+input [3:0] d;
+output [3:0] q;
+endmodule
+
+module inv(...);
+output o;
+input i;
+endmodule
+
+module top(...);
+input d0, d1, d2, d3;
+input clk;
+output q;
+ff4 #(.DATA_INV(4'h5)) ff_inst (.clk(clk), .d({d3, d2, d1, d0}), .q(q));
+endmodule
+
+EOT
+
+extractinv -inv inv o:i
+clean
+
+select -assert-count 2 top/t:inv
+select -assert-count 2 top/t:inv top/t:ff4 %ci:+[d] %ci:+[o] %i
+
+select -assert-count 1 top/t:inv top/w:d0 %co:+[i] %i
+select -assert-count 0 top/t:inv top/w:d1 %co:+[i] %i
+select -assert-count 1 top/t:inv top/w:d2 %co:+[i] %i
+select -assert-count 0 top/t:inv top/w:d3 %co:+[i] %i
+
+select -assert-count 0 top/t:ff4 top/w:d0 %co:+[d] %i
+select -assert-count 1 top/t:ff4 top/w:d1 %co:+[d] %i
+select -assert-count 0 top/t:ff4 top/w:d2 %co:+[d] %i
+select -assert-count 1 top/t:ff4 top/w:d3 %co:+[d] %i
diff --git a/tests/techmap/recursive.v b/tests/techmap/recursive.v
new file mode 100644
index 000000000..d281b21d8
--- /dev/null
+++ b/tests/techmap/recursive.v
@@ -0,0 +1,8 @@
+module top;
+sub s0();
+foo f0();
+endmodule
+
+module foo;
+sub s0();
+endmodule
diff --git a/tests/techmap/recursive_map.v b/tests/techmap/recursive_map.v
new file mode 100644
index 000000000..934256552
--- /dev/null
+++ b/tests/techmap/recursive_map.v
@@ -0,0 +1,4 @@
+module sub;
+ sub _TECHMAP_REPLACE_ ();
+ bar f0();
+endmodule
diff --git a/tests/techmap/recursive_runtest.sh b/tests/techmap/recursive_runtest.sh
new file mode 100644
index 000000000..30c79bf03
--- /dev/null
+++ b/tests/techmap/recursive_runtest.sh
@@ -0,0 +1,3 @@
+set -ev
+
+../../yosys -p 'hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar' recursive.v
diff --git a/tests/techmap/run-test.sh b/tests/techmap/run-test.sh
index e2fc11e52..96489ff15 100755
--- a/tests/techmap/run-test.sh
+++ b/tests/techmap/run-test.sh
@@ -1,10 +1,20 @@
-#!/bin/bash
+#!/usr/bin/env bash
set -e
-for x in *_runtest.sh; do
- echo "Running $x.."
- if ! bash $x &> ${x%.sh}.log; then
- tail ${x%.sh}.log
- echo ERROR
- exit 1
+{
+echo "all::"
+for x in *.ys; do
+ echo "all:: run-$x"
+ echo "run-$x:"
+ echo " @echo 'Running $x..'"
+ echo " @../../yosys -ql ${x%.ys}.log $x"
+done
+for s in *.sh; do
+ if [ "$s" != "run-test.sh" ]; then
+ echo "all:: run-$s"
+ echo "run-$s:"
+ echo " @echo 'Running $s..'"
+ echo " @bash $s > ${s%.sh}.log 2>&1"
fi
done
+} > run-test.mk
+exec ${MAKE:-make} -f run-test.mk
diff --git a/tests/techmap/wireinit.ys b/tests/techmap/wireinit.ys
new file mode 100644
index 000000000..89afaafb5
--- /dev/null
+++ b/tests/techmap/wireinit.ys
@@ -0,0 +1,108 @@
+read_verilog <<EOT
+(* techmap_celltype = "$_DFF_P_" *)
+module ffmap(...);
+input D;
+input C;
+output Q;
+parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+
+ffbb #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_(.D(D), .Q(Q), .C(C));
+
+wire _TECHMAP_FAIL_ = _TECHMAP_WIREINIT_Q_ === 1'b1;
+
+wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
+
+endmodule
+EOT
+design -stash map
+
+read_verilog <<EOT
+(* techmap_celltype = "$_DFF_P_" *)
+module ffmap(...);
+input D;
+input C;
+output Q;
+parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+
+ffbb #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_(.D(D), .Q(Q), .C(C));
+
+wire _TECHMAP_FAIL_ = _TECHMAP_WIREINIT_Q_ === 1'b1;
+
+wire _TECHMAP_REMOVEINIT_Q_ = 1'b0;
+
+endmodule
+EOT
+design -stash map_noremove
+
+read_verilog <<EOT
+module ffbb (...);
+parameter [0:0] INIT = 1'bx;
+input D, C;
+output Q;
+endmodule
+
+module top(...);
+input clk;
+input d;
+output reg q0 = 0;
+output reg q1 = 1;
+output reg qq0 = 0;
+output reg qx;
+
+always @(posedge clk) begin
+ q0 <= d;
+ q1 <= d;
+ qq0 <= q0;
+ qx <= d;
+end
+endmodule
+EOT
+
+design -save ref
+
+hierarchy -auto-top
+proc
+simplemap
+techmap -map %map
+clean
+# Make sure the parameter was used properly.
+select -assert-count 3 top/t:ffbb
+select -set ff0 top/w:q0 %ci t:ffbb %i
+select -set ffq0 top/w:qq0 %ci t:ffbb %i
+select -set ffx top/w:qx %ci t:ffbb %i
+select -assert-count 1 @ff0
+select -assert-count 1 @ffq0
+select -assert-count 1 @ffx
+select -assert-count 1 @ff0 r:INIT=1'b0 %i
+select -assert-count 1 @ffq0 r:INIT=1'b0 %i
+select -assert-count 1 @ffx r:INIT=1'bx %i
+select -assert-count 0 top/w:q1 %ci t:ffbb %i
+# Make sure the init values are dropped from the wires iff mapping was performed.
+select -assert-count 0 top/w:q0 a:init %i
+select -assert-count 0 top/w:qq0 a:init %i
+select -assert-count 1 top/w:q1 a:init=1'b1 %i
+select -assert-count 0 top/w:qx a:init %i
+
+design -load ref
+hierarchy -auto-top
+proc
+simplemap
+techmap -map %map_noremove
+clean
+# Make sure the parameter was used properly.
+select -assert-count 3 top/t:ffbb
+select -set ff0 top/w:q0 %ci t:ffbb %i
+select -set ffq0 top/w:qq0 %ci t:ffbb %i
+select -set ffx top/w:qx %ci t:ffbb %i
+select -assert-count 1 @ff0
+select -assert-count 1 @ffq0
+select -assert-count 1 @ffx
+select -assert-count 1 @ff0 r:INIT=1'b0 %i
+select -assert-count 1 @ffq0 r:INIT=1'b0 %i
+select -assert-count 1 @ffx r:INIT=1'bx %i
+select -assert-count 0 top/w:q1 %ci t:ffbb %i
+# Make sure the init values are not dropped from the wires.
+select -assert-count 1 top/w:q0 a:init=1'b0 %i
+select -assert-count 1 top/w:qq0 a:init=1'b0 %i
+select -assert-count 1 top/w:q1 a:init=1'b1 %i
+select -assert-count 0 top/w:qx a:init %i
diff --git a/tests/various/abc9.v b/tests/various/abc9.v
index a08b613a8..30ebd4e26 100644
--- a/tests/various/abc9.v
+++ b/tests/various/abc9.v
@@ -5,5 +5,7 @@ always @*
endmodule
module abc9_test028(input i, output o);
-unknown u(~i, o);
+wire w;
+unknown u(~i, w);
+unknown2 u2(w, o);
endmodule
diff --git a/tests/various/equiv_opt_multiclock.ys b/tests/various/equiv_opt_multiclock.ys
new file mode 100644
index 000000000..81e36d018
--- /dev/null
+++ b/tests/various/equiv_opt_multiclock.ys
@@ -0,0 +1,12 @@
+read_verilog <<EOT
+module top(input clk, pre, d, output reg q);
+ always @(posedge clk, posedge pre)
+ if (pre)
+ q <= 1'b1;
+ else
+ q <= d;
+endmodule
+EOT
+
+prep
+equiv_opt -assert -multiclock -map +/simcells.v synth
diff --git a/tests/various/hierarchy_defer.ys b/tests/various/hierarchy_defer.ys
new file mode 100644
index 000000000..70f5b70a3
--- /dev/null
+++ b/tests/various/hierarchy_defer.ys
@@ -0,0 +1,27 @@
+read -noverific
+read -vlog2k <<EOT
+module first;
+endmodule
+
+(* top *)
+module top(input i, output o);
+sub s0(i, o);
+endmodule
+
+(* constant_expression=1+1?2*2:3/3 *)
+module sub(input i, output o);
+assign o = ~i;
+endmodule
+EOT
+design -save read
+
+hierarchy -auto-top
+select -assert-any top
+select -assert-any sub
+select -assert-none foo
+
+design -load read
+hierarchy
+select -assert-any top
+select -assert-any sub
+select -assert-none foo
diff --git a/tests/various/mem2reg.ys b/tests/various/mem2reg.ys
new file mode 100644
index 000000000..85d6267c5
--- /dev/null
+++ b/tests/various/mem2reg.ys
@@ -0,0 +1,14 @@
+read_verilog <<EOT
+module top;
+parameter DATADEPTH=2;
+parameter DATAWIDTH=1;
+(* keep, nomem2reg *) reg [DATAWIDTH-1:0] data1 [DATADEPTH-1:0];
+(* keep, mem2reg *) reg [DATAWIDTH-1:0] data2 [DATADEPTH-1:0];
+endmodule
+EOT
+
+proc
+cd top
+select -assert-count 1 m:data1 a:src=<<EOT:4 %i
+select -assert-count 2 w:data2[*] a:src=<<EOT:5 %i
+select -assert-none a:mem2reg
diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
new file mode 100644
index 000000000..6bca62e2b
--- /dev/null
+++ b/tests/various/peepopt.ys
@@ -0,0 +1,175 @@
+read_verilog <<EOT
+module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o);
+assign o = i[s*W+:W];
+endmodule
+EOT
+
+prep -nokeepdc
+equiv_opt -assert peepopt
+design -load postopt
+clean
+select -assert-count 1 t:$shiftx
+select -assert-count 0 t:$shiftx t:* %D
+
+####################
+
+design -reset
+read_verilog <<EOT
+module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w);
+assign y = 1'b1 >> (w * (3'b110));
+endmodule
+EOT
+
+prep -nokeepdc
+equiv_opt -assert peepopt
+design -load postopt
+clean
+select -assert-count 1 t:$shr
+select -assert-count 1 t:$mul
+select -assert-count 0 t:$shr t:$mul %% t:* %D
+
+####################
+
+design -reset
+read_verilog <<EOT
+module peepopt_shiftmul_2 (input [11:0] D, input [1:0] S, output [11:0] Y);
+ assign Y = D >> (S*3);
+endmodule
+EOT
+
+prep
+design -save gold
+peepopt
+design -stash gate
+
+design -import gold -as gold peepopt_shiftmul_2
+design -import gate -as gate peepopt_shiftmul_2
+
+miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter
+sat -show-public -enable_undef -prove-asserts miter
+cd gate
+select -assert-count 1 t:$shr
+select -assert-count 1 t:$mul
+select -assert-count 0 t:$shr t:$mul %% t:* %D
+
+####################
+
+design -reset
+read_verilog <<EOT
+module peepopt_muldiv_0(input [1:0] i, output [1:0] o);
+wire [3:0] t;
+assign t = i * 3;
+assign o = t / 3;
+endmodule
+EOT
+
+prep -nokeepdc
+equiv_opt -assert peepopt
+design -load postopt
+clean
+select -assert-count 0 t:*
+
+####################
+
+design -reset
+read_verilog <<EOT
+module peepopt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0] o);
+ always @(posedge clk) if (ce) o <= i;
+endmodule
+EOT
+
+proc
+equiv_opt -assert peepopt
+design -load postopt
+clean
+select -assert-count 1 t:$dff r:WIDTH=2 %i
+select -assert-count 1 t:$mux r:WIDTH=2 %i
+select -assert-count 0 t:$dff t:$mux %% t:* %D
+
+####################
+
+design -reset
+read_verilog <<EOT
+module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o);
+ always @(posedge clk) if (ce) o <= i;
+endmodule
+EOT
+
+proc
+equiv_opt -assert peepopt
+design -load postopt
+clean
+select -assert-count 1 t:$dff r:WIDTH=2 %i
+select -assert-count 1 t:$mux r:WIDTH=2 %i
+select -assert-count 0 t:$dff t:$mux %% t:* %D
+
+###################
+
+design -reset
+read_verilog <<EOT
+module peepopt_dffmuxext_const(input clk, ce, input [1:0] i, output reg [5:0] o);
+ always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz};
+endmodule
+EOT
+
+proc
+equiv_opt -assert peepopt
+design -load postopt
+select -assert-count 1 t:$dff r:WIDTH=2 %i
+select -assert-count 1 t:$mux r:WIDTH=2 %i
+select -assert-count 0 t:$dff t:$mux %% t:* %D
+
+###################
+
+design -reset
+read_verilog <<EOT
+module peepopt_dffmuxext_const_init(input clk, ce, input [1:0] i, (* init=6'b0x00x1 *) output reg [5:0] o);
+ always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz};
+endmodule
+EOT
+
+proc
+equiv_opt -assert peepopt
+design -load postopt
+select -assert-count 1 t:$dff r:WIDTH=5 %i
+select -assert-count 1 t:$mux r:WIDTH=5 %i
+select -assert-count 0 t:$dff t:$mux %% t:* %D
+
+####################
+
+design -reset
+read_verilog <<EOT
+module peepopt_dffmuxext_unsigned_rst(input clk, ce, rst, input [1:0] i, output reg [3:0] o);
+ always @(posedge clk) if (rst) o <= 0; else if (ce) o <= i;
+endmodule
+EOT
+
+proc
+equiv_opt -assert peepopt
+design -load postopt
+wreduce
+select -assert-count 1 t:$dff r:WIDTH=2 %i
+select -assert-count 2 t:$mux
+select -assert-count 2 t:$mux r:WIDTH=2 %i
+select -assert-count 0 t:$dff t:$mux %% t:* %D
+
+####################
+
+design -reset
+read_verilog <<EOT
+module peepopt_dffmuxext_signed_rst(input clk, ce, rstn, input signed [1:0] i, output reg signed [3:0] o);
+ always @(posedge clk) begin
+ if (ce) o <= i;
+ if (!rstn) o <= 4'b1111;
+ end
+endmodule
+EOT
+
+proc
+equiv_opt -assert peepopt
+design -load postopt
+wreduce
+select -assert-count 1 t:$dff r:WIDTH=2 %i
+select -assert-count 2 t:$mux
+select -assert-count 2 t:$mux r:WIDTH=2 %i
+select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D
diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys
index 0e5fe882b..16e5f40e1 100644
--- a/tests/various/shregmap.ys
+++ b/tests/various/shregmap.ys
@@ -31,36 +31,3 @@ sat -verify -prove-asserts -show-ports -seq 5 miter
#design -load gate
#stat
-
-##########
-
-design -load read
-design -copy-to model $__XILINX_SHREG_
-hierarchy -top shregmap_variable_test
-prep
-design -save gold
-
-simplemap t:$dff t:$dffe
-shregmap -tech xilinx
-
-#stat
-# show -width
-# write_verilog -noexpr -norename
-select -assert-count 1 t:$_DFF_P_
-select -assert-count 2 t:$__XILINX_SHREG_
-
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_
-prep
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports -seq 5 miter
-
-# design -load gold
-# stat
-
-# design -load gate
-# stat
diff --git a/tests/xilinx/.gitignore b/tests/xilinx/.gitignore
new file mode 100644
index 000000000..b48f808a1
--- /dev/null
+++ b/tests/xilinx/.gitignore
@@ -0,0 +1,3 @@
+/*.log
+/*.out
+/run-test.mk
diff --git a/tests/xilinx/pmgen_xilinx_srl.ys b/tests/xilinx/pmgen_xilinx_srl.ys
new file mode 100644
index 000000000..ea2f20487
--- /dev/null
+++ b/tests/xilinx/pmgen_xilinx_srl.ys
@@ -0,0 +1,57 @@
+read_verilog -icells <<EOT
+module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);
+ parameter DEPTH = 1;
+ parameter [DEPTH-1:0] INIT = 0;
+ parameter CLKPOL = 1;
+ parameter ENPOL = 2;
+
+ wire pos_clk = C == CLKPOL;
+ reg pos_en;
+ always @(E)
+ if (ENPOL == 2) pos_en = 1'b1;
+ else pos_en = (E == ENPOL[0]);
+
+ reg [DEPTH-1:0] r;
+ always @(posedge pos_clk)
+ if (pos_en)
+ r <= {r[DEPTH-2:0], D};
+
+ assign Q = r[L];
+ assign SO = r[DEPTH-1];
+endmodule
+EOT
+read_verilog +/xilinx/cells_sim.v
+proc
+design -save model
+
+test_pmgen -generate xilinx_srl.fixed
+hierarchy -top pmtest_xilinx_srl_pm_fixed
+flatten; opt_clean
+
+design -save gold
+xilinx_srl -fixed
+techmap -autoproc -map %model
+design -stash gate
+
+design -copy-from gold -as gold pmtest_xilinx_srl_pm_fixed
+design -copy-from gate -as gate pmtest_xilinx_srl_pm_fixed
+dff2dffe -unmap # sat does not support flops-with-enable yet
+miter -equiv -flatten -make_assert gold gate miter
+sat -set-init-zero -seq 5 -verify -prove-asserts miter
+
+design -load model
+
+test_pmgen -generate xilinx_srl.variable
+hierarchy -top pmtest_xilinx_srl_pm_variable
+flatten; opt_clean
+
+design -save gold
+xilinx_srl -variable
+techmap -autoproc -map %model
+design -stash gate
+
+design -copy-from gold -as gold pmtest_xilinx_srl_pm_variable
+design -copy-from gate -as gate pmtest_xilinx_srl_pm_variable
+dff2dffe -unmap # sat does not support flops-with-enable yet
+miter -equiv -flatten -make_assert gold gate miter
+sat -set-init-zero -seq 5 -verify -prove-asserts miter
diff --git a/tests/xilinx/run-test.sh b/tests/xilinx/run-test.sh
new file mode 100755
index 000000000..ea56b70f0
--- /dev/null
+++ b/tests/xilinx/run-test.sh
@@ -0,0 +1,20 @@
+#!/usr/bin/env bash
+set -e
+{
+echo "all::"
+for x in *.ys; do
+ echo "all:: run-$x"
+ echo "run-$x:"
+ echo " @echo 'Running $x..'"
+ echo " @../../yosys -ql ${x%.ys}.log $x"
+done
+for s in *.sh; do
+ if [ "$s" != "run-test.sh" ]; then
+ echo "all:: run-$s"
+ echo "run-$s:"
+ echo " @echo 'Running $s..'"
+ echo " @bash $s"
+ fi
+done
+} > run-test.mk
+exec ${MAKE:-make} -f run-test.mk
diff --git a/tests/xilinx/xilinx_srl.v b/tests/xilinx/xilinx_srl.v
new file mode 100644
index 000000000..bc2a15ab2
--- /dev/null
+++ b/tests/xilinx/xilinx_srl.v
@@ -0,0 +1,40 @@
+module xilinx_srl_static_test(input i, clk, output [1:0] q);
+reg head = 1'b0;
+reg [3:0] shift1 = 4'b0000;
+reg [3:0] shift2 = 4'b0000;
+
+always @(posedge clk) begin
+ head <= i;
+ shift1 <= {shift1[2:0], head};
+ shift2 <= {shift2[2:0], head};
+end
+
+assign q = {shift2[3], shift1[3]};
+endmodule
+
+module xilinx_srl_variable_test(input i, clk, input [1:0] l1, l2, output [1:0] q);
+reg head = 1'b0;
+reg [3:0] shift1 = 4'b0000;
+reg [3:0] shift2 = 4'b0000;
+
+always @(posedge clk) begin
+ head <= i;
+ shift1 <= {shift1[2:0], head};
+ shift2 <= {shift2[2:0], head};
+end
+
+assign q = {shift2[l2], shift1[l1]};
+endmodule
+
+module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q);
+parameter CLKPOL = 1;
+parameter ENPOL = 1;
+parameter DEPTH = 1;
+parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
+reg [DEPTH-1:0] r = INIT;
+wire clk = C ^ CLKPOL;
+always @(posedge C)
+ if (E)
+ r <= { r[DEPTH-2:0], D };
+assign Q = r[L];
+endmodule
diff --git a/tests/xilinx/xilinx_srl.ys b/tests/xilinx/xilinx_srl.ys
new file mode 100644
index 000000000..b8df0e55a
--- /dev/null
+++ b/tests/xilinx/xilinx_srl.ys
@@ -0,0 +1,67 @@
+read_verilog xilinx_srl.v
+design -save read
+
+design -copy-to model $__XILINX_SHREG_
+hierarchy -top xilinx_srl_static_test
+prep
+design -save gold
+
+techmap
+xilinx_srl -fixed
+opt
+
+# stat
+# show -width
+select -assert-count 1 t:$_DFF_P_
+select -assert-count 2 t:$__XILINX_SHREG_
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_
+prep
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+dump gate
+sat -verify -prove-asserts -show-ports -seq 5 miter
+
+#design -load gold
+#stat
+
+#design -load gate
+#stat
+
+##########
+
+design -load read
+design -copy-to model $__XILINX_SHREG_
+hierarchy -top xilinx_srl_variable_test
+prep
+design -save gold
+
+xilinx_srl -variable
+opt
+
+#stat
+# show -width
+# write_verilog -noexpr -norename
+select -assert-count 1 t:$dff
+select -assert-count 1 t:$dff r:WIDTH=1 %i
+select -assert-count 2 t:$__XILINX_SHREG_
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_
+prep
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports -seq 5 miter
+
+# design -load gold
+# stat
+
+# design -load gate
+# stat