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This commit is contained in:
Emil J. Tywoniak 2026-06-11 13:17:54 +02:00
parent f592f2f3af
commit 8e522b08c0
206 changed files with 3081 additions and 2782 deletions
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2
techlibs/quicklogic/ql_bram_types.cc
View file

@ -155,7 +155,7 @@ struct QlBramTypesPass : public Pass {
}
cell->type = RTLIL::escape_id(type);
log_debug("Changed type of memory cell %s to %s\n", cell->name.unescape(), cell->type.unescape());
log_debug("Changed type of memory cell %s to %s\n", cell->module->design->twines.str(cell->meta_->name), cell->type.unescape());
}
}

10
techlibs/quicklogic/ql_dsp_io_regs.cc
View file

@ -84,13 +84,13 @@ struct QlDspIORegs : public Pass {
if (!cell->hasPort(cfg_port) || !sigmap(cell->getPort(cfg_port)).is_fully_const())
log_error("Missing or non-constant '%s' port on DSP cell %s\n",
cfg_port, cell);
int reg_in_i = sigmap(cell->getPort(ID(register_inputs))).as_int();
int out_sel_i = sigmap(cell->getPort(ID(output_select))).as_int();
int reg_in_i = sigmap(cell->getPort(TW::register_inputs)).as_int();
int out_sel_i = sigmap(cell->getPort(TW::output_select)).as_int();
// Get the feedback port
if (!cell->hasPort(ID(feedback)))
if (!cell->hasPort(TW(feedback)))
log_error("Missing 'feedback' port on %s", cell);
SigSpec feedback = sigmap(cell->getPort(ID(feedback)));
SigSpec feedback = sigmap(cell->getPort(TW::feedback));
// Check the top two bits on 'feedback' to be constant zero.
// That's what we are expecting from inference.
@ -132,7 +132,7 @@ struct QlDspIORegs : public Pass {
std::vector<std::string> ports2del;
if (del_clk)
cell->unsetPort(ID(clk));
cell->unsetPort(TW::clk);
switch (out_sel_i) {
case 0:

60
techlibs/quicklogic/ql_dsp_macc.cc
View file

@ -32,9 +32,9 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
auto &st = pm.st_ql_dsp_macc;
// Get port widths
size_t a_width = GetSize(st.mul->getPort(ID(A)));
size_t b_width = GetSize(st.mul->getPort(ID(B)));
size_t z_width = GetSize(st.ff->getPort(ID(Q)));
size_t a_width = GetSize(st.mul->getPort(TW::A));
size_t b_width = GetSize(st.mul->getPort(TW::B));
size_t z_width = GetSize(st.ff->getPort(TW::Q));
size_t min_width = std::min(a_width, b_width);
size_t max_width = std::max(a_width, b_width);
@ -87,9 +87,9 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
// Get input/output data signals
RTLIL::SigSpec sig_a, sig_b, sig_z;
sig_a = st.mul->getPort(ID(A));
sig_b = st.mul->getPort(ID(B));
sig_z = st.output_registered ? st.ff->getPort(ID(Q)) : st.ff->getPort(ID(D));
sig_a = st.mul->getPort(TW::A);
sig_b = st.mul->getPort(TW::B);
sig_z = st.output_registered ? st.ff->getPort(TW::Q) : st.ff->getPort(TW::D);
if (a_width < b_width)
std::swap(sig_a, sig_b);
@ -97,80 +97,80 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
// Connect input data ports, sign extend / pad with zeros
sig_a.extend_u0(tgt_a_width, ab_signed);
sig_b.extend_u0(tgt_b_width, ab_signed);
cell->setPort(ID(a_i), sig_a);
cell->setPort(ID(b_i), sig_b);
cell->setPort(TW::a_i, sig_a);
cell->setPort(TW::b_i, sig_b);
// Connect output data port, pad if needed
if ((size_t) GetSize(sig_z) < tgt_z_width) {
auto *wire = pm.module->addWire(NEW_TWINE, tgt_z_width - GetSize(sig_z));
sig_z.append(wire);
}
cell->setPort(ID(z_o), sig_z);
cell->setPort(TW::z_o, sig_z);
// Connect clock, reset and enable
cell->setPort(ID(clock_i), st.ff->getPort(ID(CLK)));
cell->setPort(TW::clock_i, st.ff->getPort(TW::CLK));
RTLIL::SigSpec rst;
RTLIL::SigSpec ena;
if (st.ff->hasPort(ID(ARST))) {
if (st.ff->hasPort(TW(ARST))) {
if (st.ff->getParam(ID(ARST_POLARITY)).as_int() != 1) {
rst = pm.module->Not(NEW_ID, st.ff->getPort(ID(ARST)));
rst = pm.module->Not(NEW_TWINE, st.ff->getPort(TW::ARST));
} else {
rst = st.ff->getPort(ID(ARST));
rst = st.ff->getPort(TW::ARST);
}
} else {
rst = RTLIL::SigSpec(RTLIL::S0);
}
if (st.ff->hasPort(ID(EN))) {
if (st.ff->hasPort(TW(EN))) {
if (st.ff->getParam(ID(EN_POLARITY)).as_int() != 1) {
ena = pm.module->Not(NEW_ID, st.ff->getPort(ID(EN)));
ena = pm.module->Not(NEW_TWINE, st.ff->getPort(TW::EN));
} else {
ena = st.ff->getPort(ID(EN));
ena = st.ff->getPort(TW::EN);
}
} else {
ena = RTLIL::SigSpec(RTLIL::S1);
}
cell->setPort(ID(reset_i), rst);
cell->setPort(ID(load_acc_i), ena);
cell->setPort(TW::reset_i, rst);
cell->setPort(TW::load_acc_i, ena);
// Insert feedback_i control logic used for clearing / loading the accumulator
if (st.mux_in_pattern) {
RTLIL::SigSpec sig_s = st.mux->getPort(ID(S));
RTLIL::SigSpec sig_s = st.mux->getPort(TW::S);
// Depending on the mux port ordering insert inverter if needed
log_assert(st.mux_ab.in(ID(A), ID(B)));
if (st.mux_ab == ID(A))
sig_s = pm.module->Not(NEW_ID, sig_s);
sig_s = pm.module->Not(NEW_TWINE, sig_s);
// Assemble the full control signal for the feedback_i port
RTLIL::SigSpec sig_f;
sig_f.append(sig_s);
sig_f.append(RTLIL::S0);
sig_f.append(RTLIL::S0);
cell->setPort(ID(feedback_i), sig_f);
cell->setPort(TW::feedback_i, sig_f);
}
// No acc clear/load
else {
cell->setPort(ID(feedback_i), RTLIL::SigSpec(RTLIL::S0, 3));
cell->setPort(TW::feedback_i, RTLIL::SigSpec(RTLIL::S0, 3));
}
// Connect control ports
cell->setPort(ID(unsigned_a_i), RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1));
cell->setPort(ID(unsigned_b_i), RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1));
cell->setPort(TW::unsigned_a_i, RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1));
cell->setPort(TW::unsigned_b_i, RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1));
// Connect config bits
cell->setPort(ID(saturate_enable_i), RTLIL::SigSpec(RTLIL::S0));
cell->setPort(ID(shift_right_i), RTLIL::SigSpec(RTLIL::S0, 6));
cell->setPort(ID(round_i), RTLIL::SigSpec(RTLIL::S0));
cell->setPort(ID(register_inputs_i), RTLIL::SigSpec(RTLIL::S0));
cell->setPort(TW::saturate_enable_i, RTLIL::SigSpec(RTLIL::S0));
cell->setPort(TW::shift_right_i, RTLIL::SigSpec(RTLIL::S0, 6));
cell->setPort(TW::round_i, RTLIL::SigSpec(RTLIL::S0));
cell->setPort(TW::register_inputs_i, RTLIL::SigSpec(RTLIL::S0));
// 3 - output post acc; 1 - output pre acc
cell->setPort(ID(output_select_i), RTLIL::Const(st.output_registered ? 1 : 3, 3));
cell->setPort(TW::output_select_i, RTLIL::Const(st.output_registered ? 1 : 3, 3));
bool subtract = (st.add->type == ID($sub));
cell->setPort(ID(subtract_i), RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0));
cell->setPort(TW::subtract_i, RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0));
// Mark the cells for removal
pm.autoremove(st.mul);

2
techlibs/quicklogic/ql_dsp_simd.cc
View file

@ -206,7 +206,7 @@ struct QlDspSimdPass : public Pass {
// Enable the fractured mode by connecting the control
// port.
simd->setPort(ID(f_mode), State::S1);
simd->setPort(TW::f_mode, State::S1);
simd->setParam(ID(MODE_BITS), mode_bits);
log_assert(mode_bits.size() == m_ModeBitsSize);