From 8e522b08c0313fa402ddb002815812117ac16762 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 11 Jun 2026 13:17:54 +0200 Subject: [PATCH] WIP --- backends/aiger/aiger.cc | 2 +- backends/aiger/xaiger.cc | 34 +-- backends/aiger2/aiger.cc | 49 ++-- backends/blif/blif.cc | 20 +- backends/btor/btor.cc | 57 +++-- backends/cxxrtl/cxxrtl_backend.cc | 77 ++++-- backends/edif/edif.cc | 33 +-- backends/firrtl/firrtl.cc | 16 +- backends/intersynth/intersynth.cc | 19 +- backends/jny/jny.cc | 14 +- backends/json/json.cc | 15 +- backends/rtlil/rtlil_backend.cc | 33 +-- backends/simplec/simplec.cc | 30 +-- backends/smt2/smt2.cc | 68 +++--- backends/smv/smv.cc | 10 +- backends/spice/spice.cc | 13 +- backends/table/table.cc | 8 +- backends/verilog/verilog_backend.cc | 49 ++-- .../source/code_examples/extensions/my_cmd.cc | 4 +- frontends/aiger/aigerparse.cc | 114 ++++----- frontends/aiger2/xaiger.cc | 32 +-- frontends/ast/ast.cc | 56 +++-- frontends/ast/genrtlil.cc | 106 ++++----- frontends/ast/simplify.cc | 6 +- frontends/blif/blifparse.cc | 79 ++++--- frontends/json/jsonparse.cc | 24 +- frontends/liberty/liberty.cc | 49 ++-- frontends/rpc/rpc_frontend.cc | 16 +- frontends/rtlil/rtlil_frontend.cc | 123 ++++++---- kernel/cellaigs.cc | 110 ++++----- kernel/cellaigs.h | 2 +- kernel/celledges.cc | 116 ++++----- kernel/celledges.h | 6 +- kernel/celltypes.h | 2 +- kernel/consteval.h | 12 +- kernel/cost.cc | 10 +- kernel/cost.h | 2 +- kernel/drivertools.cc | 6 +- kernel/drivertools.h | 16 +- kernel/ff.cc | 181 +++++++------- kernel/ffmerge.cc | 6 +- kernel/fmt.cc | 4 +- kernel/functional.cc | 115 ++++----- kernel/log.cc | 33 +++ kernel/log.h | 10 +- kernel/mem.cc | 69 +++--- kernel/newcelltypes.h | 2 +- kernel/register.cc | 20 +- kernel/rtlil.cc | 124 ++++++---- kernel/rtlil.h | 36 +-- kernel/rtlil_bufnorm.cc | 2 +- kernel/tclapi.cc | 12 +- kernel/timinginfo.h | 7 +- kernel/wallace_tree.h | 2 +- kernel/yosys.cc | 40 ++-- passes/cmds/Makefile.inc | 1 - passes/cmds/abstract.cc | 18 +- passes/cmds/add.cc | 32 +-- passes/cmds/autoname.cc | 12 +- passes/cmds/box_derive.cc | 6 +- passes/cmds/bugpoint.cc | 12 +- passes/cmds/check.cc | 46 ++-- passes/cmds/chformal.cc | 18 +- passes/cmds/chtype.cc | 5 +- passes/cmds/connect.cc | 8 +- passes/cmds/connwrappers.cc | 6 +- passes/cmds/copy.cc | 2 +- passes/cmds/delete.cc | 8 +- passes/cmds/design.cc | 6 +- passes/cmds/design_equal.cc | 74 +++--- passes/cmds/dft_tag.cc | 128 +++++----- passes/cmds/edgetypes.cc | 24 +- passes/cmds/example_dt.cc | 2 +- passes/cmds/glift.cc | 109 +++++---- passes/cmds/icell_liberty.cc | 22 +- passes/cmds/linecoverage.cc | 2 +- passes/cmds/printattrs.cc | 4 +- passes/cmds/rename.cc | 106 +++++---- passes/cmds/scatter.cc | 2 +- passes/cmds/scc.cc | 16 +- passes/cmds/select.cc | 90 +++---- passes/cmds/setattr.cc | 10 +- passes/cmds/setundef.cc | 8 +- passes/cmds/splitcells.cc | 31 +-- passes/cmds/splitnets.cc | 10 +- passes/cmds/stat.cc | 14 +- passes/cmds/test_patch.cc | 6 +- passes/cmds/test_select.cc | 9 +- passes/cmds/xprop.cc | 148 ++++++------ passes/equiv/equiv_add.cc | 12 +- passes/equiv/equiv_make.cc | 56 ++--- passes/equiv/equiv_mark.cc | 24 +- passes/equiv/equiv_miter.cc | 28 +-- passes/equiv/equiv_purge.cc | 20 +- passes/equiv/equiv_simple.cc | 2 +- passes/equiv/equiv_struct.cc | 32 ++- passes/fsm/fsm_detect.cc | 12 +- passes/fsm/fsm_expand.cc | 18 +- passes/fsm/fsm_export.cc | 6 +- passes/fsm/fsm_extract.cc | 32 +-- passes/fsm/fsm_map.cc | 4 +- passes/fsm/fsm_opt.cc | 11 +- passes/fsm/fsm_recode.cc | 8 +- passes/hierarchy/flatten.cc | 78 ++++-- passes/hierarchy/hierarchy.cc | 223 +++++++++++------- passes/hierarchy/submod.cc | 40 ++-- passes/hierarchy/uniquify.cc | 10 +- passes/memory/memory_bram.cc | 38 +-- passes/memory/memory_dff.cc | 20 +- passes/memory/memory_libmap.cc | 90 +++---- passes/memory/memory_map.cc | 61 ++--- passes/memory/memory_memx.cc | 10 +- passes/memory/memory_share.cc | 12 +- passes/opt/muxpack.cc | 2 +- passes/opt/opt_balance_tree.cc | 4 +- passes/opt/opt_clean/cells_all.cc | 10 +- passes/opt/opt_demorgan.cc | 10 +- passes/opt/opt_expr.cc | 38 +-- passes/opt/opt_ffinv.cc | 16 +- passes/opt/opt_lut_ins.cc | 80 +++---- passes/opt/opt_mem_feedback.cc | 4 +- passes/opt/opt_mem_widen.cc | 2 +- passes/opt/opt_merge.cc | 8 +- passes/opt/opt_merge_inc.cc | 4 +- passes/opt/opt_muxtree.cc | 10 +- passes/opt/opt_reduce.cc | 2 +- passes/opt/opt_share.cc | 47 ++-- passes/opt/peepopt_formal_clockgateff.pmg | 2 +- passes/opt/peepopt_shiftmul_left.pmg | 2 +- passes/opt/pmux2shiftx.cc | 8 +- passes/opt/share.cc | 54 ++--- passes/opt/wreduce.cc | 23 +- passes/pmgen/test_pmgen.cc | 14 +- passes/pmgen/test_pmgen.pmg | 14 +- passes/proc/proc_arst.cc | 10 +- passes/proc/proc_clean.cc | 4 +- passes/proc/proc_dff.cc | 32 +-- passes/proc/proc_dlatch.cc | 24 +- passes/proc/proc_init.cc | 2 +- passes/proc/proc_memwr.cc | 4 +- passes/proc/proc_mux.cc | 14 +- passes/sat/assertpmux.cc | 18 +- passes/sat/async2sync.cc | 106 ++++----- passes/sat/clk2fflogic.cc | 46 ++-- passes/sat/cutpoint.cc | 8 +- passes/sat/expose.cc | 2 +- passes/sat/fmcombine.cc | 20 +- passes/sat/fminit.cc | 18 +- passes/sat/formalff.cc | 16 +- passes/sat/freduce.cc | 2 +- passes/sat/miter.cc | 96 ++++---- passes/sat/mutate.cc | 12 +- passes/sat/qbfsat.cc | 4 +- passes/sat/sat.cc | 8 +- passes/sat/sim.cc | 54 +++-- passes/sat/supercover.cc | 6 +- passes/sat/synthprop.cc | 6 +- passes/techmap/abc9_ops.cc | 10 +- passes/techmap/aigmap.cc | 6 +- passes/techmap/alumacc.cc | 22 +- passes/techmap/arith_tree.cc | 4 +- passes/techmap/bmuxmap.cc | 6 +- passes/techmap/booth.cc | 94 ++++---- passes/techmap/bwmuxmap.cc | 8 +- passes/techmap/clockgate.cc | 2 +- passes/techmap/demuxmap.cc | 6 +- passes/techmap/dfflegalize.cc | 24 +- passes/techmap/dfflibmap.cc | 4 +- passes/techmap/extract.cc | 4 +- passes/techmap/extract_counter.cc | 26 +- passes/techmap/extract_fa.cc | 22 +- passes/techmap/extract_reduce.cc | 6 +- passes/techmap/flowmap.cc | 2 +- passes/techmap/iopadmap.cc | 4 +- passes/techmap/lut2mux.cc | 12 +- passes/techmap/maccmap.cc | 20 +- passes/techmap/muxcover.cc | 6 +- passes/techmap/pmuxtree.cc | 10 +- passes/techmap/shregmap.cc | 4 +- passes/techmap/simplemap.cc | 10 +- passes/techmap/techmap.cc | 2 +- passes/techmap/tribuf.cc | 14 +- passes/tests/test_abcloop.cc | 32 +-- passes/tests/test_autotb.cc | 44 ++-- passes/tests/test_cell.cc | 110 ++++----- techlibs/anlogic/anlogic_fixcarry.cc | 26 +- techlibs/coolrunner2/coolrunner2_fixup.cc | 46 ++-- techlibs/coolrunner2/coolrunner2_sop.cc | 32 +-- techlibs/efinix/efinix_fixcarry.cc | 12 +- techlibs/gatemate/gatemate_foldinv.cc | 2 +- techlibs/greenpak4/greenpak4_dffinv.cc | 24 +- techlibs/ice40/ice40_dsp.cc | 78 +++--- techlibs/ice40/ice40_opt.cc | 34 +-- techlibs/ice40/ice40_wrapcarry.cc | 16 +- techlibs/lattice/lattice_gsr.cc | 6 +- techlibs/microchip/microchip_dffopt.cc | 36 +-- techlibs/microchip/microchip_dsp.cc | 14 +- techlibs/nanoxplore/nx_carry.cc | 44 ++-- techlibs/quicklogic/ql_bram_types.cc | 2 +- techlibs/quicklogic/ql_dsp_io_regs.cc | 10 +- techlibs/quicklogic/ql_dsp_macc.cc | 60 ++--- techlibs/quicklogic/ql_dsp_simd.cc | 2 +- techlibs/xilinx/xilinx_dffopt.cc | 28 +-- techlibs/xilinx/xilinx_dsp.cc | 50 ++-- techlibs/xilinx/xilinx_srl.cc | 2 +- techlibs/xilinx/xilinx_srl.pmg | 16 +- 206 files changed, 3081 insertions(+), 2782 deletions(-) diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index 1c7bf3f44..1c647c447 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -776,7 +776,7 @@ struct AigerWriter if (cell->type.in(ID($_FF_), ID($_DFF_N_), ID($_DFF_P_), ID($anyinit), ID($anyconst), ID($anyseq))) { // Use sig_q to get the FF output name, but sig to lookup aiger bits - auto sig_qy = cell->getPort(cell->type.in(ID($anyconst), ID($anyseq)) ? ID::Y : ID::Q); + auto sig_qy = cell->getPort(cell->type.in(ID($anyconst), ID($anyseq)) ? TW::Y : TW::Q); SigSpec sig = sigmap(sig_qy); if (cell->get_bool_attribute(ID(clk2fflogic))) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index d316f7737..61364d2de 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -248,14 +248,16 @@ struct XAigerWriter continue; } - if (!timing.count(inst_module->name)) + auto inst_name_id = RTLIL::IdString(design->twines.str(inst_module->meta_->name)); + if (!timing.count(inst_name_id)) timing.setup_module(inst_module); - for (auto &i : timing.at(inst_module->name).arrival) { - if (!cell->hasPort(i.first.name)) + for (auto &i : timing.at(inst_name_id).arrival) { + auto port_name_ref = design->twines.add(Twine{i.first.name.str()}); + if (!cell->hasPort(port_name_ref)) continue; - auto port_wire = inst_module->wire(i.first.name); + auto port_wire = inst_module->wire(port_name_ref); log_assert(port_wire->port_output); auto d = i.second.first; @@ -263,14 +265,14 @@ struct XAigerWriter continue; auto offset = i.first.offset; - auto rhs = cell->getPort(i.first.name); + auto rhs = cell->getPort(port_name_ref); if (offset >= rhs.size()) continue; #ifndef NDEBUG if (ys_debug(1)) { static pool> seen; - if (seen.emplace(inst_module->name, i.first).second) log("%s.%s[%d] abc9_arrival = %d\n", + if (seen.emplace(inst_name_id, i.first).second) log("%s.%s[%d] abc9_arrival = %d\n", cell->type.unescape(), i.first.name.unescape(), offset, d); } #endif @@ -288,7 +290,7 @@ struct XAigerWriter auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first); auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first); if (!is_input && !is_output) - log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", c.first.unescape(), cell, cell->type.unescape()); + log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", RTLIL::IdString(design->twines.str(c.first)).unescape(), cell, cell->type.unescape()); if (is_input) for (auto b : c.second) { @@ -309,7 +311,7 @@ struct XAigerWriter //log_warning("Unsupported cell type: %s (%s)\n", cell->type.unescape(), cell); } - dict> box_ports; + dict> box_ports; for (auto cell : box_list) { log_assert(cell); @@ -321,18 +323,18 @@ struct XAigerWriter if (r.second) { // Make carry in the last PI, and carry out the last PO // since ABC requires it this way - IdString carry_in, carry_out; + TwineRef carry_in = Twine::Null, carry_out = Twine::Null; for (const auto &port_name : box_module->ports) { auto w = box_module->wire(port_name); log_assert(w); if (w->get_bool_attribute(ID::abc9_carry)) { if (w->port_input) { - if (carry_in != IdString()) + if (carry_in != Twine::Null) log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", box_module); carry_in = port_name; } if (w->port_output) { - if (carry_out != IdString()) + if (carry_out != Twine::Null) log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", box_module); carry_out = port_name; } @@ -341,11 +343,11 @@ struct XAigerWriter r.first->second.push_back(port_name); } - if (carry_in != IdString() && carry_out == IdString()) + if (carry_in != Twine::Null && carry_out == Twine::Null) log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", box_module); - if (carry_in == IdString() && carry_out != IdString()) + if (carry_in == Twine::Null && carry_out != Twine::Null) log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", box_module); - if (carry_in != IdString()) { + if (carry_in != Twine::Null) { r.first->second.push_back(carry_in); r.first->second.push_back(carry_out); } @@ -646,7 +648,7 @@ struct XAigerWriter holes_design = it->second; else holes_design = nullptr; - RTLIL::Module *holes_module = holes_design ? holes_design->module(module->name) : nullptr; + RTLIL::Module *holes_module = holes_design ? holes_design->module(module->meta_->name) : nullptr; if (holes_module) { std::stringstream a_buffer; XAigerWriter writer(holes_module, false /* dff_mode */); @@ -712,7 +714,7 @@ struct XAigerWriter int box_count = 0; for (auto cell : box_list) - f << stringf("box %d %d %s\n", box_count++, 0, cell->name.unescape()); + f << stringf("box %d %d %s\n", box_count++, 0, cell->module->design->twines.str(cell->meta_->name)); output_lines.sort(); for (auto &it : output_lines) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index bf49214f0..81abc7b1f 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -278,7 +278,7 @@ struct Index { return lits.front(); } - Lit impl_op(HierCursor &cursor, Cell *cell, IdString oport, int obit) + Lit impl_op(HierCursor &cursor, Cell *cell, TwineRef oport, int obit) { if (cell->type.in(REDUCE_OPS, LOGIC_OPS, CMP_OPS) && obit != 0) { return CFALSE; @@ -418,9 +418,9 @@ struct Index { } else if (cell->type.in(ID($fa))) { Lit c = visit(cursor, cell->getPort(TW::C)[obit]); Lit ab = XOR(a, b); - if (oport == ID::Y) { + if (oport == TW::Y) { return XOR(ab, c); - } else /* oport == ID::X */ { + } else /* oport == TW::X */ { Lit a_and_b = AND(a, b); Lit c_and_ab = AND(c, ab); return OR(a_and_b, c_and_ab); @@ -556,13 +556,14 @@ struct Index { { std::string ret; bool first = true; + Design *design = levels[0].first.module ? levels[0].first.module->design : nullptr; for (auto [minfo, cell] : levels) { if (!first) ret += "."; if (!cell) - ret += minfo.module->name.unescape(); + ret += design->twines.str(minfo.module->meta_->name); else - ret += cell->name.unescape(); + ret += design->twines.str(cell->meta_->name); first = false; } return ret; @@ -636,10 +637,10 @@ struct Index { Wire *w = def->wire(portname); if (!w) log_error("Output port %s on instance %s of %s doesn't exist\n", - portname.unescape(), driver, def); + design->twines.str(portname).c_str(), driver, def); if (bit.offset >= w->width) log_error("Bit position %d of output port %s on instance %s of %s is out of range (port has width %d)\n", - bit.offset, portname.unescape(), driver, def, w->width); + bit.offset, design->twines.str(portname).c_str(), driver, def, w->width); ret = visit(cursor, SigBit(w, bit.offset)); } cursor.exit(*this); @@ -652,14 +653,14 @@ struct Index { // step into the upper module Cell *instance = cursor.exit(*this); { - TwineRef portname = bit.wire->name; + TwineRef portname = bit.wire->meta_->name; if (!instance->hasPort(portname)) log_error("Input port %s on instance %s of %s unconnected\n", - portname.unescape(), instance, instance->type); + design->twines.str(portname).c_str(), instance, instance->type); auto &port = instance->getPort(portname); if (bit.offset >= port.size()) log_error("Bit %d of input port %s on instance %s of %s unconnected\n", - bit.offset, portname.unescape(), instance, instance->type.unescape()); + bit.offset, design->twines.str(portname).c_str(), instance, instance->type.unescape()); ret = visit(cursor, port[bit.offset]); } cursor.enter(*this, instance); @@ -905,7 +906,7 @@ struct XAigerAnalysis : Index { int max = 1; for (auto wire : mod->wires()) { if (wire->port_input && !wire->port_output) { - SigSpec port = driver->getPort(wire->name); + SigSpec port = driver->getPort(wire->meta_->name); for (int i = 0; i < std::min(wire->width, port.size()); i++) { int ilevel = visit(cursor, port[i]); max = std::max(max, ilevel + 1); @@ -999,7 +1000,7 @@ struct XAigerWriter : AigerWriter { log_assert(cursor.is_top()); // TODO driven_by_opaque_box.insert(bit); map_file << "pi " << pis.size() - 1 << " " << bit.offset - << " " << bit.wire->name.c_str() << "\n"; + << " " << design->twines.str(bit.wire->meta_->name).c_str() << "\n"; } } else { log_assert(!box_port); @@ -1034,8 +1035,8 @@ struct XAigerWriter : AigerWriter { if (map_file.is_open()) { log_assert(cursor.is_top()); map_file << "pseudopo " << proper_pos_counter << " " << bitp - << " " << box->name.c_str() - << " " << conn.first.c_str() << "\n"; + << " " << design->twines.str(box->meta_->name).c_str() + << " " << design->twines.str(conn.first).c_str() << "\n"; } proper_pos_counter++; pos.push_back(std::make_pair(bit, cursor)); @@ -1048,7 +1049,7 @@ struct XAigerWriter : AigerWriter { } else if (!is_input && !inputs) { for (auto &bit : conn.second) { if (!bit.wire || (bit.wire->port_input && !bit.wire->port_output)) - log_error("Bad connection %s/%s ~ %s\n", box, conn.first.unescape(), log_signal(conn.second)); + log_error("Bad connection %s/%s ~ %s\n", box, design->twines.str(conn.first).c_str(), log_signal(conn.second)); ensure_pi(bit, cursor); @@ -1116,7 +1117,7 @@ struct XAigerWriter : AigerWriter { for (auto [cursor, box, def] : opaque_boxes) append_opaque_box_ports(box, cursor, false); - holes_module = design->addModule(NEW_ID); + holes_module = design->addModule(design->twines.add(NEW_TWINE)); std::vector holes_pis; int boxes_ci_num = 0, boxes_co_num = 0; @@ -1133,13 +1134,13 @@ struct XAigerWriter : AigerWriter { } for (auto [cursor, box, def] : nonopaque_boxes) { - // use `def->name` not `box->type` as we want the derived type - Cell *holes_wb = holes_module->addCell(NEW_TWINE, def->name); + // use `def->meta_->name` not `box->type` as we want the derived type + Cell *holes_wb = holes_module->addCell(NEW_TWINE, IdString(design->twines.str(def->meta_->name))); int holes_pi_idx = 0; if (map_file.is_open()) { log_assert(cursor.is_top()); - map_file << "box " << box_seq << " " << box->name.c_str() << "\n"; + map_file << "box " << box_seq << " " << design->twines.str(box->meta_->name).c_str() << "\n"; } box_seq++; @@ -1158,7 +1159,7 @@ struct XAigerWriter : AigerWriter { } else { // FIXME: hierarchical path log_warning("connection on port %s[%d] of instance %s (type %s) missing, using 1'bx\n", - port_id.unescape(), i, box, box->type.unescape()); + design->twines.str(port_id).c_str(), i, box, box->type.unescape()); bit = RTLIL::Sx; } @@ -1177,7 +1178,7 @@ struct XAigerWriter : AigerWriter { while (holes_pi_idx >= (int) holes_pis.size()) { Wire *w = holes_module->addWire(NEW_TWINE, 1); w->port_input = true; - holes_module->ports.push_back(w->name); + holes_module->ports.push_back(w->meta_->name); holes_pis.push_back(w); } in_conn.append(holes_pis[holes_pi_idx]); @@ -1193,7 +1194,7 @@ struct XAigerWriter : AigerWriter { } else { // FIXME: hierarchical path log_warning("connection on port %s[%d] of instance %s (type %s) missing\n", - port_id.unescape(), i, box, box->type.unescape()); + design->twines.str(port_id).c_str(), i, box, box->type.unescape()); pad_pi(); continue; } @@ -1206,11 +1207,11 @@ struct XAigerWriter : AigerWriter { // holes Wire *w = holes_module->addWire(NEW_TWINE, port->width); w->port_output = true; - holes_module->ports.push_back(w->name); + holes_module->ports.push_back(w->meta_->name); holes_wb->setPort(port_id, w); } else { log_error("Ambiguous port direction on %s/%s\n", - box->type.unescape(), port_id.unescape()); + box->type.unescape(), design->twines.str(port_id).c_str()); } } } diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index b2e18faad..195a2676a 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -170,7 +170,7 @@ struct BlifDumper void dump() { f << stringf("\n"); - f << stringf(".model %s\n", str(module->name)); + f << stringf(".model %s\n", design->twines.str(module->meta_->name).c_str()); std::map inputs, outputs; @@ -237,8 +237,10 @@ struct BlifDumper if (config->unbuf_types.count(cell->type)) { auto portnames = config->unbuf_types.at(cell->type); + TwineRef port_in = design->twines.lookup(portnames.first.str()); + TwineRef port_out = design->twines.lookup(portnames.second.str()); f << stringf(".names %s %s\n1 1\n", - str(cell->getPort(portnames.first)).c_str(), str(cell->getPort(portnames.second)).c_str()); + str(cell->getPort(port_in)).c_str(), str(cell->getPort(port_out)).c_str()); continue; } @@ -420,7 +422,7 @@ struct BlifDumper for (auto &conn : cell->connections()) { if (conn.second.size() == 1) { - f << stringf(" %s=%s", str(conn.first), str(conn.second[0])); + f << stringf(" %s=%s", design->twines.str(conn.first).c_str(), str(conn.second[0])); continue; } @@ -429,11 +431,11 @@ struct BlifDumper if (w == nullptr) { for (int i = 0; i < GetSize(conn.second); i++) - f << stringf(" %s[%d]=%s", str(conn.first), i, str(conn.second[i])); + f << stringf(" %s[%d]=%s", design->twines.str(conn.first).c_str(), i, str(conn.second[i])); } else { for (int i = 0; i < std::min(GetSize(conn.second), GetSize(w)); i++) { SigBit sig(w, i); - f << stringf(" %s[%d]=%s", str(conn.first), sig.wire->upto ? + f << stringf(" %s[%d]=%s", design->twines.str(conn.first).c_str(), sig.wire->upto ? sig.wire->start_offset+sig.wire->width-sig.offset-1 : sig.wire->start_offset+sig.offset, str(conn.second[i]).c_str()); } @@ -665,7 +667,7 @@ struct BlifBackend : public Backend { if (top_module_name.empty()) for (auto module : design->modules()) if (module->get_bool_attribute(ID::top)) - top_module_name = module->name.str(); + top_module_name = design->twines.str(module->meta_->name); *f << stringf("# Generated by %s\n", yosys_maybe_version()); @@ -678,11 +680,11 @@ struct BlifBackend : public Backend { continue; if (module->processes.size() != 0) - log_error("Found unmapped processes in module %s: unmapped processes are not supported in BLIF backend!\n", module->name.unescape()); + log_error("Found unmapped processes in module %s: unmapped processes are not supported in BLIF backend!\n", design->twines.str(module->meta_->name).c_str()); if (module->memories.size() != 0) - log_error("Found unmapped memories in module %s: unmapped memories are not supported in BLIF backend!\n", module->name.unescape()); + log_error("Found unmapped memories in module %s: unmapped memories are not supported in BLIF backend!\n", design->twines.str(module->meta_->name).c_str()); - if (module->name == RTLIL::escape_id(top_module_name)) { + if (design->twines.str(module->meta_->name) == top_module_name) { BlifDumper::dump(*f, module, design, config); top_module_name.clear(); continue; diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index fe22fed55..eea913066 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -122,14 +122,43 @@ struct BtorWorker string infostr = obj->name.unescape(); if (!srcsym && !print_internal_names && infostr[0] == '$') return ""; if (obj->has_attribute(ID::src)) { - string raw_src = module && module->design ? module->design->get_src_attribute(obj) : std::string(); - string src = module && module->design ? module->design->resolve_src(raw_src) : raw_src; + string src = module && module->design ? module->design->get_src_attribute(obj) : std::string(); if (srcsym && infostr[0] == '$') { std::replace(src.begin(), src.end(), ' ', '_'); - if (srcsymbols.count(src) || module->count_id("\\" + src)) { + TwineRef src_ref = module->design->twines.lookup(src); + if (srcsymbols.count(src) || src_ref != Twine::Null) { for (int i = 1;; i++) { string s = stringf("%s-%d", src, i); - if (!srcsymbols.count(s) && !module->count_id("\\" + s)) { + TwineRef s_ref = module->design->twines.lookup(s); + if (!srcsymbols.count(s) && s_ref == Twine::Null) { + src = s; + break; + } + } + } + srcsymbols.insert(src); + infostr = src; + } else { + infostr += " ; " + src; + } + } + return " " + infostr; + } + + string getinfo(Mem *mem, bool srcsym = false) + { + string infostr = mem->memid.unescape(); + if (!srcsym && !print_internal_names && infostr[0] == '$') return ""; + if (mem->has_attribute(ID::src)) { + string src = module && module->design ? module->design->get_src_attribute(mem) : std::string(); + if (srcsym && infostr[0] == '$') { + std::replace(src.begin(), src.end(), ' ', '_'); + TwineRef src_ref = module->design->twines.lookup(src); + if (srcsymbols.count(src) || src_ref != Twine::Null) { + for (int i = 1;; i++) { + string s = stringf("%s-%d", src, i); + TwineRef s_ref = module->design->twines.lookup(s); + if (!srcsymbols.count(s) && s_ref == Twine::Null) { src = s; break; } @@ -249,7 +278,7 @@ struct BtorWorker } cell_recursion_guard.insert(cell); - btorf_push(cell->name.unescape()); + btorf_push(cell->module->design->twines.str(cell->meta_->name)); if (cell->type.in(ID($add), ID($sub), ID($mul), ID($and), ID($or), ID($xor), ID($xnor), ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx), ID($concat), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_))) @@ -681,7 +710,7 @@ struct BtorWorker if ((!info_filename.empty() || ywmap_json.active()) && cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_))) { - SigSpec sig_c = sigmap(cell->getPort(cell->type == ID($dff) ? ID::CLK : ID::C)); + SigSpec sig_c = sigmap(cell->getPort(cell->type == ID($dff) ? TW::CLK : TW::C)); int nid = get_sig_nid(sig_c); bool negedge = false; @@ -962,7 +991,7 @@ struct BtorWorker log_error("Unsupported cell type %s for cell %s.%s.\n", cell->type.unescape(), module, cell); okay: - btorf_pop(cell->name.unescape()); + btorf_pop(cell->module->design->twines.str(cell->meta_->name)); cell_recursion_guard.erase(cell); } @@ -1269,7 +1298,7 @@ struct BtorWorker { if (cell->type == ID($assume)) { - btorf_push(cell->name.unescape()); + btorf_push(cell->module->design->twines.str(cell->meta_->name)); int sid = get_bv_sid(1); int nid_a = get_sig_nid(cell->getPort(TW::A)); @@ -1284,12 +1313,12 @@ struct BtorWorker if (ywmap_json.active()) ywmap_assumes.emplace_back(cell); - btorf_pop(cell->name.unescape()); + btorf_pop(cell->module->design->twines.str(cell->meta_->name)); } if (cell->type == ID($assert)) { - btorf_push(cell->name.unescape()); + btorf_push(cell->module->design->twines.str(cell->meta_->name)); int sid = get_bv_sid(1); int nid_a = get_sig_nid(cell->getPort(TW::A)); @@ -1313,12 +1342,12 @@ struct BtorWorker } } - btorf_pop(cell->name.unescape()); + btorf_pop(cell->module->design->twines.str(cell->meta_->name)); } if (cell->type == ID($cover) && cover_mode) { - btorf_push(cell->name.unescape()); + btorf_push(cell->module->design->twines.str(cell->meta_->name)); int sid = get_bv_sid(1); int nid_a = get_sig_nid(cell->getPort(TW::A)); @@ -1334,7 +1363,7 @@ struct BtorWorker btorf("%d bad %d%s\n", nid, nid_en_and_a, getinfo(cell, true)); } - btorf_pop(cell->name.unescape()); + btorf_pop(cell->module->design->twines.str(cell->meta_->name)); } } @@ -1434,7 +1463,7 @@ struct BtorWorker } int nid2 = next_nid++; - btorf("%d next %d %d %d%s\n", nid2, sid, nid, nid_head, (mem->cell ? getinfo(mem->cell) : getinfo(mem->mem))); + btorf("%d next %d %d %d%s\n", nid2, sid, nid, nid_head, getinfo(mem)); btorf_pop(stringf("next %s", mem->memid.unescape())); } diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index c16d5d37c..8c5037dc5 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -642,8 +642,18 @@ std::string get_hdl_name(T *object) { if (object->has_attribute(ID::hdlname)) return object->get_string_attribute(ID::hdlname); - else - return object->name.str().substr(1); + else { + // For Wire/Cell with ->name, Module/Memory with ->meta_->name + std::string name; + if constexpr (std::is_same_v || std::is_same_v) { + name = object->name.str(); + } else if constexpr (std::is_same_v) { + name = object->design->twines.str(object->meta_->name); + } else if constexpr (std::is_same_v) { + name = object->module->design->twines.str(object->meta_->name); + } + return name.substr(1); + } } struct WireType { @@ -812,9 +822,15 @@ struct CxxrtlWorker { return mangle_name(name); } + std::string mangle_wire_name(TwineRef name, const RTLIL::Design *design) + { + // Class member namespace. + return mangle_name(RTLIL::IdString(design->twines.str(name))); + } + std::string mangle(const RTLIL::Module *module) { - return mangle_module_name(module->name, /*is_blackbox=*/module->get_bool_attribute(ID(cxxrtl_blackbox))); + return mangle_module_name(RTLIL::IdString(module->design->twines.str(module->meta_->name)), /*is_blackbox=*/module->get_bool_attribute(ID(cxxrtl_blackbox))); } std::string mangle(const Mem *mem) @@ -824,7 +840,7 @@ struct CxxrtlWorker { std::string mangle(const RTLIL::Memory *memory) { - return mangle_memory_name(memory->name); + return mangle_memory_name(RTLIL::IdString(memory->module->design->twines.str(memory->meta_->name))); } std::string mangle(const RTLIL::Cell *cell) @@ -1127,7 +1143,7 @@ struct CxxrtlWorker { if (is_cxxrtl_sync_port(cell, conn.first) && !conn.second.empty()) { f << indent; dump_sigspec_lhs(conn.second, for_debug); - f << " = " << mangle(cell) << access << mangle_wire_name(conn.first) << ".curr;\n"; + f << " = " << mangle(cell) << access << mangle_wire_name(conn.first, cell->module->design) << ".curr;\n"; } } @@ -1307,7 +1323,7 @@ struct CxxrtlWorker { dump_sigspec_rhs(arg.second); f << ";\n"; } - if (cell->hasPort(ID::A)) { + if (cell->hasPort(TW::A)) { f << indent << "bool condition = (bool)"; dump_sigspec_rhs(cell->getPort(TW::A)); f << ";\n"; @@ -1406,7 +1422,7 @@ struct CxxrtlWorker { } else if (is_ff_cell(cell->type)) { log_assert(!for_debug); // Clocks might be slices of larger signals but should only ever be single bit - if (cell->hasPort(ID::CLK) && is_valid_clock(cell->getPort(TW::CLK))) { + if (cell->hasPort(TW::CLK) && is_valid_clock(cell->getPort(TW::CLK))) { // Edge-sensitive logic RTLIL::SigBit clk_bit = cell->getPort(TW::CLK)[0]; clk_bit = sigmaps[clk_bit.wire->module](clk_bit); @@ -1417,7 +1433,7 @@ struct CxxrtlWorker { f << indent << "if (false) {\n"; } inc_indent(); - if (cell->hasPort(ID::EN)) { + if (cell->hasPort(TW::EN)) { f << indent << "if ("; dump_sigspec_rhs(cell->getPort(TW::EN)); f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n"; @@ -1428,11 +1444,11 @@ struct CxxrtlWorker { f << " = "; dump_sigspec_rhs(cell->getPort(TW::D)); f << ";\n"; - if (cell->hasPort(ID::EN) && cell->type != ID($sdffce)) { + if (cell->hasPort(TW::EN) && cell->type != ID($sdffce)) { dec_indent(); f << indent << "}\n"; } - if (cell->hasPort(ID::SRST)) { + if (cell->hasPort(TW::SRST)) { f << indent << "if ("; dump_sigspec_rhs(cell->getPort(TW::SRST)); f << " == value<1> {" << cell->getParam(ID::SRST_POLARITY).as_bool() << "u}) {\n"; @@ -1445,13 +1461,13 @@ struct CxxrtlWorker { dec_indent(); f << indent << "}\n"; } - if (cell->hasPort(ID::EN) && cell->type == ID($sdffce)) { + if (cell->hasPort(TW::EN) && cell->type == ID($sdffce)) { dec_indent(); f << indent << "}\n"; } dec_indent(); f << indent << "}\n"; - } else if (cell->hasPort(ID::EN)) { + } else if (cell->hasPort(TW::EN)) { // Level-sensitive logic f << indent << "if ("; dump_sigspec_rhs(cell->getPort(TW::EN)); @@ -1465,7 +1481,7 @@ struct CxxrtlWorker { dec_indent(); f << indent << "}\n"; } - if (cell->hasPort(ID::ARST)) { + if (cell->hasPort(TW::ARST)) { // Asynchronous reset (entire coarse cell at once) f << indent << "if ("; dump_sigspec_rhs(cell->getPort(TW::ARST)); @@ -1479,7 +1495,7 @@ struct CxxrtlWorker { dec_indent(); f << indent << "}\n"; } - if (cell->hasPort(ID::ALOAD)) { + if (cell->hasPort(TW::ALOAD)) { // Asynchronous load f << indent << "if ("; dump_sigspec_rhs(cell->getPort(TW::ALOAD)); @@ -1493,7 +1509,7 @@ struct CxxrtlWorker { dec_indent(); f << indent << "}\n"; } - if (cell->hasPort(ID::SET)) { + if (cell->hasPort(TW::SET)) { // Asynchronous set (for individual bits) f << indent; dump_sigspec_lhs(cell->getPort(TW::Q)); @@ -1505,7 +1521,7 @@ struct CxxrtlWorker { dump_sigspec_rhs(cell->getPort(TW::SET)); f << (cell->getParam(ID::SET_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n"; } - if (cell->hasPort(ID::CLR)) { + if (cell->hasPort(TW::CLR)) { // Asynchronous clear (for individual bits; priority over set) f << indent; dump_sigspec_lhs(cell->getPort(TW::Q)); @@ -1533,7 +1549,7 @@ struct CxxrtlWorker { RTLIL::Module *cell_module = cell->module->design->module(cell->type); log_assert(cell_module != nullptr && cell_module->wire(conn.first)); RTLIL::Wire *cell_module_wire = cell_module->wire(conn.first); - f << indent << mangle(cell) << access << mangle_wire_name(conn.first); + f << indent << mangle(cell) << access << mangle_wire_name(conn.first, cell->module->design); if (!is_cxxrtl_blackbox_cell(cell) && wire_types[cell_module_wire].is_buffered()) { buffered_inputs = true; f << ".next"; @@ -1565,7 +1581,7 @@ struct CxxrtlWorker { continue; // fully sync ports are handled in CELL_SYNC nodes f << indent; dump_sigspec_lhs(conn.second); - f << " = " << mangle(cell) << access << mangle_wire_name(conn.first); + f << " = " << mangle(cell) << access << mangle_wire_name(conn.first, cell->module->design); // Similarly to how there is no purpose to buffering cell inputs, there is also no purpose to buffering // combinatorial cell outputs in case the cell converges within one cycle. (To convince yourself that // this optimization is valid, consider that, since the cell converged within one cycle, it would not @@ -1699,7 +1715,7 @@ struct CxxrtlWorker { void dump_process_case(const RTLIL::Process *proc, bool for_debug = false) { dump_attrs(proc); - f << indent << "// process " << proc->name.str() << " case\n"; + f << indent << "// process " << proc->module->design->twines.str(proc->meta_->name) << " case\n"; // The case attributes (for root case) are always empty. log_assert(proc->root_case.attributes.empty()); dump_case_rule(&proc->root_case, for_debug); @@ -1708,7 +1724,7 @@ struct CxxrtlWorker { void dump_process_syncs(const RTLIL::Process *proc, bool for_debug = false) { dump_attrs(proc); - f << indent << "// process " << proc->name.str() << " syncs\n"; + f << indent << "// process " << proc->module->design->twines.str(proc->meta_->name) << " syncs\n"; for (auto sync : proc->syncs) { log_assert(!for_debug || sync->type == RTLIL::STa); @@ -1760,7 +1776,9 @@ struct CxxrtlWorker { for (auto &action : sync->actions) dump_assign(action, for_debug); for (auto &memwr : sync->mem_write_actions) { - RTLIL::Memory *memory = proc->module->memories.at(memwr.memid); + TwineRef memid_ref = proc->module->design->twines.lookup(memwr.memid.str()); + log_assert(memid_ref != Twine::Null); + RTLIL::Memory *memory = proc->module->memories[memid_ref]; std::string valid_index_temp = fresh_temporary(); f << indent << "auto " << valid_index_temp << " = memory_index("; dump_sigspec_rhs(memwr.address); @@ -2448,7 +2466,7 @@ struct CxxrtlWorker { else has_driven_comb = true; } else if (wire->port_output) { - switch (cxxrtl_port_type(module, wire->name)) { + switch (cxxrtl_port_type(module, wire->meta_->name)) { case CxxrtlPortType::SYNC: has_driven_sync = true; break; @@ -2777,8 +2795,19 @@ struct CxxrtlWorker { { RTLIL::Module *top_module = nullptr; std::vector modules; - using Order = IdString::compare_ptr_by_name; - TopoSort topo_design; + + // Custom comparator for Module* that uses new meta_->name field + struct CompareModuleByName { + bool operator()(const RTLIL::Module *a, const RTLIL::Module *b) const { + if (a == nullptr || b == nullptr) + return a < b; + auto name_a = a->design->twines.str(a->meta_->name); + auto name_b = b->design->twines.str(b->meta_->name); + return name_a < name_b; + } + }; + + TopoSort topo_design; for (auto module : design->modules()) { if (!design->selected_module(module)) continue; diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 3e9217df9..12d6953b4 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -138,7 +138,7 @@ struct EdifBackend : public Backend { bool port_rename = false; bool attr_properties = false; bool lsbidx = false; - std::map> lib_cell_ports; + std::map> lib_cell_ports; bool nogndvcc = false, gndvccy = false, keepmode = false; NewCellTypes ct(design); EdifNames edif_names; @@ -190,28 +190,29 @@ struct EdifBackend : public Backend { if (top_module_name.empty()) for (auto module : design->modules()) if (module->get_bool_attribute(ID::top)) - top_module_name = module->name.str(); + top_module_name = design->twines.str(module->meta_->name); for (auto module : design->modules()) { - lib_cell_ports[module->name]; + IdString module_type = IdString(design->twines.str(module->meta_->name)); + lib_cell_ports[module_type]; for (auto port : module->ports) { Wire *wire = module->wire(port); - lib_cell_ports[module->name][port] = std::max(lib_cell_ports[module->name][port], GetSize(wire)); + lib_cell_ports[module_type][port] = std::max(lib_cell_ports[module_type][port], GetSize(wire)); } if (module->get_blackbox_attribute()) continue; if (top_module_name.empty()) - top_module_name = module->name.str(); + top_module_name = design->twines.str(module->meta_->name); if (module->processes.size() != 0) - log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", module->name.unescape()); + log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", design->twines.str(module->meta_->name)); if (module->memories.size() != 0) - log_error("Found unmapped memories in module %s: unmapped memories are not supported in EDIF backend!\n", module->name.unescape()); + log_error("Found unmapped memories in module %s: unmapped memories are not supported in EDIF backend!\n", design->twines.str(module->meta_->name)); for (auto cell : module->cells()) { @@ -285,13 +286,14 @@ struct EdifBackend : public Backend { upto = w->upto; } } + std::string port_str = design->twines.str(port_it.first); if (width == 1) - *f << stringf(" (port %s (direction %s))\n", EDIF_DEF(port_it.first), dir); + *f << stringf(" (port %s (direction %s))\n", EDIF_DEF_STR(port_str), dir); else { int b[2]; b[upto ? 0 : 1] = start; b[upto ? 1 : 0] = start+width-1; - *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(port_it.first, port_rename, b[0], b[1]), width, dir); + *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(IdString(port_str), port_rename, b[0], b[1]), width, dir); } } *f << stringf(" )\n"); @@ -324,7 +326,7 @@ struct EdifBackend : public Backend { not_ready_yet:; } if (sorted_modules_idx == sorted_modules.size()) - log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", module_deps.begin()->first->name.unescape()); + log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", design->twines.str(module_deps.begin()->first->meta_->name)); while (sorted_modules_idx < sorted_modules.size()) module_deps.erase(sorted_modules.at(sorted_modules_idx++)); } @@ -361,7 +363,8 @@ struct EdifBackend : public Backend { SigMap sigmap(module); std::map>> net_join_db; - *f << stringf(" (cell %s\n", EDIF_DEF(module->name)); + std::string module_name_str = design->twines.str(module->meta_->name); + *f << stringf(" (cell %s\n", EDIF_DEF_STR(module_name_str)); *f << stringf(" (cellType GENERIC)\n"); *f << stringf(" (view VIEW_NETLIST\n"); *f << stringf(" (viewType NETLIST)\n"); @@ -485,10 +488,12 @@ struct EdifBackend : public Backend { *f << stringf(")\n"); for (auto &p : cell->connections()) { RTLIL::SigSpec sig = sigmap(p.second); + std::string port_name_str = design->twines.str(p.first); + std::string cell_name_str = cell->name.str(); for (int i = 0; i < GetSize(sig); i++) if (sig[i].wire == NULL && sig[i] != RTLIL::State::S0 && sig[i] != RTLIL::State::S1) log_warning("Bit %d of cell port %s.%s.%s driven by %s will be left unconnected in EDIF output.\n", - i, module, cell, p.first.unescape(), log_signal(sig[i])); + i, module, cell, port_name_str, log_signal(sig[i])); else { int member_idx = lsbidx ? i : GetSize(sig)-i-1; auto m = design->module(cell->type); @@ -501,10 +506,10 @@ struct EdifBackend : public Backend { } } if (width == 1) - net_join_db[sig[i]].insert(make_pair(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name)), cell->output(p.first))); + net_join_db[sig[i]].insert(make_pair(stringf("(portRef %s (instanceRef %s))", EDIF_REF_STR(port_name_str), EDIF_REF(cell->name)), cell->output(p.first))); else { net_join_db[sig[i]].insert(make_pair(stringf("(portRef (member %s %d) (instanceRef %s))", - EDIF_REF(p.first), member_idx, EDIF_REF(cell->name)), cell->output(p.first))); + EDIF_REF_STR(port_name_str), member_idx, EDIF_REF(cell->name)), cell->output(p.first))); } } } diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index 77003fcef..720af21f4 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -50,9 +50,9 @@ std::string getFileinfo(const RTLIL::AttrObject *design_entity, const RTLIL::Des } // Get a port direction with respect to a specific module. -FDirection getPortFDirection(IdString id, Module *module) +FDirection getPortFDirection(TwineRef ref, Module *module) { - Wire *wire = module->wire(id); + Wire *wire = module->wire(ref); FDirection direction = FD_NODIRECTION; if (wire && wire->port_id) { @@ -229,7 +229,7 @@ std::string extmodule_name(RTLIL::Cell *cell, RTLIL::Module *mod_instance) // this blackbox, we need to create a custom name for it. We just use the // name of the blackbox itself followed by the name of the cell. const std::string cell_name = std::string(make_id(cell->name)); - const std::string blackbox_name = std::string(make_id(mod_instance->name)); + const std::string blackbox_name = std::string(make_id(IdString(mod_instance->design->twines.str(mod_instance->meta_->name)))); const std::string extmodule_name = blackbox_name + "_" + cell_name; return extmodule_name; } @@ -243,7 +243,7 @@ void emit_extmodule(RTLIL::Cell *cell, RTLIL::Module *mod_instance, std::ostream { const std::string indent = " "; - const std::string blackbox_name = std::string(make_id(mod_instance->name)); + const std::string blackbox_name = std::string(make_id(IdString(mod_instance->design->twines.str(mod_instance->meta_->name)))); const std::string exported_name = extmodule_name(cell, mod_instance); // We use the cell's fileinfo for this extmodule as its parameters come from @@ -482,7 +482,7 @@ struct FirrtlWorker for (auto it = cell->connections().begin(); it != cell->connections().end(); ++it) { if (it->second.size() > 0) { const SigSpec &secondSig = it->second; - const std::string firstName = cell_name + "." + make_id(it->first); + const std::string firstName = cell_name + "." + make_id(IdString(design->twines.str(it->first))); const std::string secondExpr = make_expr(secondSig); // Find the direction for this port. FDirection dir = getPortFDirection(it->first, instModule); @@ -543,7 +543,7 @@ struct FirrtlWorker void emit_module() { std::string moduleFileinfo = getFileinfo(module); - f << stringf(" module %s: %s\n", make_id(module->name), moduleFileinfo); + f << stringf(" module %s: %s\n", make_id(IdString(module->design->twines.str(module->meta_->name))), moduleFileinfo); vector port_decls, wire_decls, mem_exprs, cell_exprs, wire_exprs; std::vector memories = Mem::get_all_memories(module); @@ -1232,7 +1232,7 @@ struct FirrtlBackend : public Backend { Module *last = nullptr; // Generate module and wire names. for (auto module : design->modules()) { - make_id(module->name); + make_id(IdString(module->design->twines.str(module->meta_->name))); last = module; if (top == nullptr && module->get_bool_attribute(ID::top)) { top = module; @@ -1249,7 +1249,7 @@ struct FirrtlBackend : public Backend { log_cmd_error("There is no top module in this design!\n"); std::string circuitFileinfo = getFileinfo(top); - *f << stringf("circuit %s: %s\n", make_id(top->name), circuitFileinfo); + *f << stringf("circuit %s: %s\n", make_id(IdString(top->design->twines.str(top->meta_->name))), circuitFileinfo); emit_elaborated_extmodules(design, *f); diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 1704ba429..1d48e49fd 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -131,20 +131,20 @@ struct IntersynthBackend : public Backend { if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells().size() == 0) continue; - if (selected && !design->selected_whole_module(module->name)) { - if (design->selected_module(module->name)) - log_cmd_error("Can't handle partially selected module %s!\n", module->name.unescape()); + if (selected && !design->selected_whole_module(module->meta_->name)) { + if (design->selected_module(module->meta_->name)) + log_cmd_error("Can't handle partially selected module %s!\n", design->twines.str(module->meta_->name).c_str()); continue; } - log("Generating netlist %s.\n", module->name.unescape()); + log("Generating netlist %s.\n", design->twines.str(module->meta_->name).c_str()); if (module->memories.size() != 0 || module->processes.size() != 0) log_error("Can't generate a netlist for a module with unprocessed memories or processes!\n"); std::set constcells_code; - netlists_code += stringf("# Netlist of module %s\n", module->name.unescape()); - netlists_code += stringf("netlist %s\n", module->name.unescape()); + netlists_code += stringf("# Netlist of module %s\n", design->twines.str(module->meta_->name).c_str()); + netlists_code += stringf("netlist %s\n", design->twines.str(module->meta_->name).c_str()); // Module Ports: "std::set celltypes_code" prevents duplicate top level ports for (auto wire : module->wires()) { @@ -166,13 +166,14 @@ struct IntersynthBackend : public Backend { log_error("Found unknown cell type %s in module!\n", cell->type.unescape()); celltype_code = stringf("celltype %s", cell->type.unescape()); - node_code = stringf("node %s %s", cell->name.unescape(), cell->type.unescape()); + node_code = stringf("node %s %s", cell->module->design->twines.str(cell->meta_->name), cell->type.unescape()); for (auto &port : cell->connections()) { RTLIL::SigSpec sig = sigmap(port.second); if (sig.size() != 0) { conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size())); - celltype_code += stringf(" b%d %s%s", sig.size(), ct.cell_output(cell->type, port.first) ? "*" : "", port.first.unescape()); - node_code += stringf(" %s %s", port.first.unescape(), netname(conntypes_code, celltypes_code, constcells_code, sig)); + std::string port_name = design->twines.str(port.first); + celltype_code += stringf(" b%d %s%s", sig.size(), ct.cell_output(cell->type, port.first) ? "*" : "", port_name.c_str()); + node_code += stringf(" %s %s", port_name.c_str(), netname(conntypes_code, celltypes_code, constcells_code, sig)); } } for (auto ¶m : cell->parameters) { diff --git a/backends/jny/jny.cc b/backends/jny/jny.cc index 00650f5d8..cd7138c46 100644 --- a/backends/jny/jny.cc +++ b/backends/jny/jny.cc @@ -211,10 +211,11 @@ struct JnyWriter f << _indent << " }"; } - void write_cell_conn(const std::pair& sig, uint16_t indent_level = 0) { + void write_cell_conn(Design* design, const std::pair& sig, uint16_t indent_level = 0) { const auto _indent = gen_indent(indent_level); + std::string port_name = design->twines.str(sig.first); f << _indent << " {\n"; - f << _indent << " \"name\": \"" << escape_string(sig.first.unescape()) << "\",\n"; + f << _indent << " \"name\": \"" << escape_string(port_name) << "\",\n"; f << _indent << " \"signals\": [\n"; write_sigspec(sig.second, indent_level + 2); @@ -232,7 +233,7 @@ struct JnyWriter const auto _indent = gen_indent(indent_level); f << _indent << "{\n"; - f << stringf(" %s\"name\": \"%s\",\n", _indent, escape_string(mod->name.unescape())); + f << stringf(" %s\"name\": \"%s\",\n", _indent, escape_string(mod->design->twines.str(mod->meta_->name))); f << _indent << " \"cell_sorts\": [\n"; bool first_sort{true}; @@ -279,8 +280,9 @@ struct JnyWriter if (!first_port) f << ",\n"; + std::string port_name = port_cell->module->design->twines.str(con.first); f << _indent << " {\n"; - f << stringf(" %s\"name\": \"%s\",\n", _indent, escape_string(con.first.unescape())); + f << stringf(" %s\"name\": \"%s\",\n", _indent, escape_string(port_name)); f << _indent << " \"direction\": \""; if (port_cell->input(con.first)) f << "i"; @@ -366,7 +368,7 @@ struct JnyWriter log_assert(cell != nullptr); f << _indent << " {\n"; - f << stringf(" %s\"name\": \"%s\"", _indent, escape_string(cell->name.unescape())); + f << stringf(" %s\"name\": \"%s\"", _indent, escape_string(cell->module->design->twines.str(cell->meta_->name))); if (_include_connections) { f << ",\n" << _indent << " \"connections\": [\n"; @@ -376,7 +378,7 @@ struct JnyWriter if (!first_conn) f << ",\n"; - write_cell_conn(conn, indent_level + 2); + write_cell_conn(cell->module->design, conn, indent_level + 2); first_conn = false; } diff --git a/backends/json/json.cc b/backends/json/json.cc index 7550b4df0..a9c2e6dac 100644 --- a/backends/json/json.cc +++ b/backends/json/json.cc @@ -79,6 +79,11 @@ struct JsonWriter return get_string(name.unescape()); } + string get_name(TwineRef name) + { + return get_string(design->twines.str(name)); + } + string get_bits(SigSpec sig) { bool first = true; @@ -162,7 +167,7 @@ struct JsonWriter log_error("Module %s contains processes, which are not supported by JSON backend (run `proc` first).\n", module); } - f << stringf(" %s: {\n", get_name(module->name)); + f << stringf(" %s: {\n", get_name(module->meta_->name)); f << stringf(" \"attributes\": {"); write_parameters(module->attributes, /*for_module=*/true, module); @@ -252,8 +257,8 @@ struct JsonWriter if (use_selection && !module->selected(it.second)) continue; f << stringf("%s\n", first ? "" : ","); - f << stringf(" %s: {\n", get_name(it.second->name)); - f << stringf(" \"hide_name\": %s,\n", it.second->name[0] == '$' ? "1" : "0"); + f << stringf(" %s: {\n", get_name(it.second->meta_->name)); + f << stringf(" \"hide_name\": %s,\n", design->twines.str(it.second->meta_->name)[0] == '$' ? "1" : "0"); f << stringf(" \"attributes\": {"); write_parameters(it.second->attributes, false, it.second); f << stringf("\n },\n"); @@ -323,13 +328,13 @@ struct JsonWriter f << stringf(" /* %3d */ [ ", node_idx); if (node.portbit >= 0) f << stringf("\"%sport\", \"%s\", %d", node.inverter ? "n" : "", - node.portname.unescape(), node.portbit); + design->twines.str(node.portname), node.portbit); else if (node.left_parent < 0 && node.right_parent < 0) f << stringf("\"%s\"", node.inverter ? "true" : "false"); else f << stringf("\"%s\", %d, %d", node.inverter ? "nand" : "and", node.left_parent, node.right_parent); for (auto &op : node.outports) - f << stringf(", \"%s\", %d", op.first.unescape(), op.second); + f << stringf(", \"%s\", %d", design->twines.str(op.first), op.second); f << stringf(" ]"); node_idx++; } diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc index be19646ee..33a552cf7 100644 --- a/backends/rtlil/rtlil_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -41,9 +41,9 @@ void RTLIL_BACKEND::dump_attributes(std::ostream &f, std::string indent, const R TwineRef id = design->obj_src_id(obj); f << stringf("%s" "attribute \\src ", indent); if (resolve_src) { - dump_const(f, RTLIL::Const(design->twines.flatten(id))); + dump_const(f, RTLIL::Const(design->twines.str(id))); } else { - dump_const(f, RTLIL::Const(design->twines.format_ref(id))); + dump_const(f, RTLIL::Const(stringf("@%zu", id))); } f << stringf("\n"); } @@ -59,22 +59,23 @@ void RTLIL_BACKEND::dump_twines(std::ostream &f, const RTLIL::Design *design) if (!design || design->twines.size() == 0) return; f << stringf("twines\n"); - design->twines.for_each_live([&](TwineRef id, const Twine &n) { + for (TwineRef id = 0; id < STATIC_TWINE_END; id++) { + const Twine &n = design->twines[id]; if (n.is_leaf()) { - f << stringf(" leaf %u ", id); + f << stringf(" leaf %zu ", id); dump_const(f, RTLIL::Const(n.leaf())); f << stringf("\n"); } else if (n.is_suffix()) { - f << stringf(" suffix %u %u ", id, n.suffix().parent); + f << stringf(" suffix %zu %zu ", id, n.suffix().prefix); dump_const(f, RTLIL::Const(n.suffix().tail)); f << stringf("\n"); - } else { - f << stringf(" concat %u", id); + } else if (n.is_concat()) { + f << stringf(" concat %zu", id); for (TwineRef c : n.children()) - f << stringf(" %u", c); + f << stringf(" %zu", c); f << stringf("\n"); } - }); + } f << stringf("end\n"); } @@ -204,7 +205,7 @@ void RTLIL_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL f << stringf("size %d ", memory->size); if (memory->start_offset != 0) f << stringf("offset %d ", memory->start_offset); - f << stringf("%s\n", memory->name); + f << stringf("%s\n", design->twines.str(memory->meta_->name).c_str()); } void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell, const RTLIL::Design *design, bool resolve_src) @@ -309,7 +310,7 @@ void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RT void RTLIL_BACKEND::dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc, const RTLIL::Design *design, bool resolve_src) { dump_attributes(f, indent, proc, design, resolve_src); - f << stringf("%s" "process %s\n", indent, proc->name); + f << stringf("%s" "process %s\n", indent, design->twines.str(proc->meta_->name).c_str()); dump_proc_case_body(f, indent + " ", &proc->root_case, design, resolve_src); for (auto* sync : proc->syncs) dump_proc_sync(f, indent + " ", sync, design, resolve_src); @@ -334,7 +335,7 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu { dump_attributes(f, indent, module, design, resolve_src); - f << stringf("%s" "module %s\n", indent, module->name); + f << stringf("%s" "module %s\n", indent, design->twines.str(module->meta_->name).c_str()); if (!module->avail_parameters.empty()) { if (only_selected) @@ -384,7 +385,7 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu bool first_conn_line = true; for (const auto& [lhs, rhs] : module->connections()) { - bool show_conn = !only_selected || design->selected_whole_module(module->name); + bool show_conn = !only_selected || design->selected_whole_module(module->meta_->name); if (!show_conn) { RTLIL::SigSpec sigs = lhs; sigs.append(rhs); @@ -414,9 +415,9 @@ void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl if (!flag_m) { int count_selected_mods = 0; for (auto* module : design->modules()) { - if (design->selected_whole_module(module->name)) + if (design->selected_whole_module(module->meta_->name)) flag_m = true; - if (design->selected(module)) + if (design->selected_module(module->meta_->name)) count_selected_mods++; } if (count_selected_mods > 1) @@ -432,7 +433,7 @@ void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl } for (const auto& [_, module] : reversed(design->modules_)) { - if (!only_selected || design->selected(module)) { + if (!only_selected || design->selected_module(module->meta_->name)) { if (only_selected) f << stringf("\n"); dump_module(f, "", module, design, only_selected, flag_m, flag_n, resolve_src); diff --git a/backends/simplec/simplec.cc b/backends/simplec/simplec.cc index b61328a70..7e5ab5f3e 100644 --- a/backends/simplec/simplec.cc +++ b/backends/simplec/simplec.cc @@ -78,7 +78,7 @@ struct HierDirtyFlags for (Cell *cell : module->cells()) { Module *mod = module->design->module(cell->type); if (mod) children[cell->name] = new HierDirtyFlags(mod, cell->name, this, - prefix + cid(cell->name) + ".", log_prefix + "." + prefix + cell->name.unescape()); + prefix + cid(cell->name) + ".", log_prefix + "." + prefix + cell->module->design->twines.str(cell->meta_->name)); } } @@ -167,7 +167,7 @@ struct SimplecWorker vector funct_declarations; - dict>>> bit2cell; + dict>>> bit2cell; dict>> bit2output; dict> driven_bits; @@ -284,10 +284,10 @@ struct SimplecWorker void create_module_struct(Module *mod) { - if (generated_structs.count(mod->name)) + if (generated_structs.count(design->twines.str(mod->meta_->name))) return; - generated_structs.insert(mod->name); + generated_structs.insert(design->twines.str(mod->meta_->name)); sigmaps[mod].set(mod); for (Wire *w : mod->wires()) @@ -309,7 +309,7 @@ struct SimplecWorker int idx = 0; for (auto bit : sigmaps.at(mod)(conn.second)) - bit2cell[mod][bit].insert(tuple(c, conn.first, idx++)); + bit2cell[mod][bit].insert(tuple(c, conn.first, idx++)); } if (design->module(c->type)) @@ -337,9 +337,9 @@ struct SimplecWorker topo.sort(); for (int i = 0; i < GetSize(topo.sorted); i++) - topoidx[mod->cell(topo.sorted[i])] = i; + topoidx[mod->cell(design->twines.lookup(topo.sorted[i].str()))] = i; - string ifdef_name = stringf("yosys_simplec_%s_state_t", cid(mod->name)); + string ifdef_name = stringf("yosys_simplec_%s_state_t", cid(RTLIL::IdString(design->twines.str(mod->meta_->name)))); for (int i = 0; i < GetSize(ifdef_name); i++) if ('a' <= ifdef_name[i] && ifdef_name[i] <= 'z') @@ -348,7 +348,7 @@ struct SimplecWorker struct_declarations.push_back(""); struct_declarations.push_back(stringf("#ifndef %s", ifdef_name)); struct_declarations.push_back(stringf("#define %s", ifdef_name)); - struct_declarations.push_back(stringf("struct %s_state_t", cid(mod->name))); + struct_declarations.push_back(stringf("struct %s_state_t", cid(RTLIL::IdString(design->twines.str(mod->meta_->name))))); struct_declarations.push_back("{"); struct_declarations.push_back(" // Input Ports"); @@ -527,9 +527,9 @@ struct SimplecWorker for (auto outbit : bit2output[work->module][bit]) { Module *parent_mod = work->parent->module; - Cell *parent_cell = parent_mod->cell(work->hiername); + Cell *parent_cell = parent_mod->cell(parent_mod->design->twines.lookup(work->hiername.str())); - IdString port_name = outbit.wire->name; + TwineRef port_name = outbit.wire->meta_->name; int port_offset = outbit.offset; SigBit parent_bit = sigmaps.at(parent_mod)(parent_cell->getPort(port_name)[port_offset]); @@ -576,7 +576,7 @@ struct SimplecWorker if (cell == nullptr || topoidx.at(cell) < topoidx.at(c)) cell = c; - string hiername = work->log_prefix + "." + cell->name.unescape(); + string hiername = work->log_prefix + "." + cell->module->design->twines.str(cell->meta_->name); if (verbose) log(" Evaluating %s (%s, best of %d).\n", hiername, cell->type.unescape(), GetSize(work->dirty_cells)); @@ -636,7 +636,7 @@ struct SimplecWorker reactivated_cells.clear(); funct_declarations.push_back(""); - funct_declarations.push_back(stringf("static void %s(struct %s_state_t *state)", func_name, cid(work->module->name))); + funct_declarations.push_back(stringf("static void %s(struct %s_state_t *state)", func_name, cid(RTLIL::IdString(work->module->design->twines.str(work->module->meta_->name))))); funct_declarations.push_back("{"); for (auto &line : preamble) funct_declarations.push_back(line); @@ -690,7 +690,7 @@ struct SimplecWorker { vector preamble; eval_init(work, preamble); - make_func(work, cid(work->module->name) + "_init", preamble); + make_func(work, cid(RTLIL::IdString(work->module->design->twines.str(work->module->meta_->name))) + "_init", preamble); } void make_eval_func(HierDirtyFlags *work) @@ -704,7 +704,7 @@ struct SimplecWorker work->set_dirty(bit); } - make_func(work, cid(work->module->name) + "_eval", preamble); + make_func(work, cid(RTLIL::IdString(work->module->design->twines.str(work->module->meta_->name))) + "_eval", preamble); } void make_tick_func(HierDirtyFlags* /* work */) @@ -716,7 +716,7 @@ struct SimplecWorker { create_module_struct(mod); - HierDirtyFlags work(mod, IdString(), nullptr, "state->", mod->name.unescape()); + HierDirtyFlags work(mod, IdString(), nullptr, "state->", mod->design->twines.str(mod->meta_->name)); make_init_func(&work); make_eval_func(&work); diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index 10a97cd1a..67b4216b9 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -207,9 +207,9 @@ struct Smt2Worker } else if (is_output || !is_input) log_error("Unsupported or unknown directionality on port %s of cell %s.%s (%s).\n", - conn.first.unescape(), module, cell, cell->type.unescape()); + module->design->twines.str(conn.first).c_str(), module, cell, cell->type.unescape()); - if (cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_)) && conn.first.in(ID::CLK, ID::C)) + if (cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_)) && (conn.first == TW::CLK || conn.first == TW::C)) { bool posedge = (cell->type == ID($_DFF_N_)) || (cell->type == ID($dff) && cell->getParam(ID::CLK_POLARITY).as_bool()); for (auto bit : sigmap(conn.second)) { @@ -220,19 +220,22 @@ struct Smt2Worker } } else - if (mod_clk_cache.count(cell->type) && mod_clk_cache.at(cell->type).count(conn.first)) { - for (auto bit : sigmap(conn.second)) { - if (mod_clk_cache.at(cell->type).at(conn.first).first) - clock_posedge.insert(bit); - if (mod_clk_cache.at(cell->type).at(conn.first).second) - clock_negedge.insert(bit); + IdString port_name = IdString(module->design->twines.str(conn.first)); + if (mod_clk_cache.count(cell->type) && mod_clk_cache.at(cell->type).count(port_name)) + { + for (auto bit : sigmap(conn.second)) { + if (mod_clk_cache.at(cell->type).at(port_name).first) + clock_posedge.insert(bit); + if (mod_clk_cache.at(cell->type).at(port_name).second) + clock_negedge.insert(bit); + } + } + else + { + for (auto bit : sigmap(conn.second)) + noclock.insert(bit); } - } - else - { - for (auto bit : sigmap(conn.second)) - noclock.insert(bit); } } @@ -257,10 +260,11 @@ struct Smt2Worker if (!wire->port_input || GetSize(wire) != 1) continue; SigBit bit = sigmap(wire); + IdString module_name = IdString(module->design->twines.str(module->meta_->name)); if (clock_posedge.count(bit)) - mod_clk_cache[module->name][wire->name].first = true; + mod_clk_cache[module_name][wire->name].first = true; if (clock_negedge.count(bit)) - mod_clk_cache[module->name][wire->name].second = true; + mod_clk_cache[module_name][wire->name].second = true; } } @@ -273,7 +277,7 @@ struct Smt2Worker const char *get_id(Module *m) { - return get_id(m->name); + return get_id(IdString(m->design->twines.str(m->meta_->name))); } const char *get_id(Cell *c) @@ -468,16 +472,16 @@ struct Smt2Worker width = GetSize(cell->getPort(TW::A)); else width = max(width, GetSize(cell->getPort(TW::A))); - if (cell->hasPort(ID::B)) + if (cell->hasPort(TW::B)) width = max(width, GetSize(cell->getPort(TW::B))); } - if (cell->hasPort(ID::A)) { + if (cell->hasPort(TW::A)) { sig_a = cell->getPort(TW::A); sig_a.extend_u0(width, is_signed); } - if (cell->hasPort(ID::B)) { + if (cell->hasPort(TW::B)) { sig_b = cell->getPort(TW::B); sig_b.extend_u0(width, (type == 'S') || (is_signed && !(type == 's'))); } @@ -520,7 +524,8 @@ struct Smt2Worker for (char ch : expr) if (ch == 'A' || ch == 'B') { - RTLIL::SigSpec sig = sigmap(cell->getPort(stringf("\\%c", ch))); + TwineRef port = (ch == 'A') ? TW::A : TW::B; + RTLIL::SigSpec sig = sigmap(cell->getPort(port)); for (auto bit : sig) processed_expr += " " + get_bool(bit); if (GetSize(sig) == 1) @@ -612,12 +617,11 @@ struct Smt2Worker if (cell->type.in(ID($anyconst), ID($anyseq), ID($anyinit), ID($allconst), ID($allseq))) { - auto QY = cell->type == ID($anyinit) ? ID::Q : ID::Y; + auto QY = cell->type == ID($anyinit) ? TW::Q : TW::Y; registers.insert(cell); string infostr; if (cell->has_attribute(ID::src)) { - string raw_src = cell->get_src_attribute(); - infostr = module && module->design ? module->design->resolve_src(raw_src) : raw_src; + infostr = cell->get_src_attribute(); } else { infostr = get_id(cell); } @@ -636,7 +640,7 @@ struct Smt2Worker bool init_only = cell->type.in(ID($anyconst), ID($anyinit), ID($allconst)); bool clk2fflogic = cell->type == ID($anyinit) && cell->get_bool_attribute(ID(clk2fflogic)); int smtoffset = 0; - for (auto chunk : cell->getPort(clk2fflogic ? ID::D : QY).chunks()) { + for (auto chunk : cell->getPort(clk2fflogic ? TW::D : QY).chunks()) { if (chunk.is_wire()) decls.push_back(witness_signal(init_only ? "init" : "seq", chunk.width, chunk.offset, "", idcounter, chunk.wire, smtoffset)); smtoffset += chunk.width; @@ -1138,8 +1142,7 @@ struct Smt2Worker if (private_name && cell->has_attribute(ID::src)) { string raw_src = cell->get_src_attribute(); - string resolved_src = module && module->design ? module->design->resolve_src(raw_src) : raw_src; - decls.push_back(stringf("; yosys-smt2-%s %d %s %s\n", cell->type.c_str() + 1, id, get_id(cell), resolved_src.c_str())); + decls.push_back(stringf("; yosys-smt2-%s %d %s %s\n", cell->type.c_str() + 1, id, get_id(cell), raw_src.c_str())); } else decls.push_back(stringf("; yosys-smt2-%s %d %s\n", cell->type.c_str() + 1, id, get_id(cell))); @@ -1478,7 +1481,8 @@ struct Smt2Worker if (statebv) { f << stringf("(define-sort |%s_s| () (_ BitVec %d))\n", get_id(module), statebv_width); - mod_stbv_width[module->name] = statebv_width; + IdString module_name = IdString(module->design->twines.str(module->meta_->name)); + mod_stbv_width[module_name] = statebv_width; } else if (statedt) { f << stringf("(declare-datatype |%s_s| ((|%s_mk|\n", get_id(module), get_id(module)); @@ -1863,9 +1867,11 @@ struct Smt2Backend : public Backend { std::map> module_deps; for (auto mod : design->modules()) { module_deps[mod] = std::set(); - for (auto cell : mod->cells()) - if (design->has(cell->type)) - module_deps[mod].insert(design->module(cell->type)); + for (auto cell : mod->cells()) { + TwineRef cell_type_ref = design->twines.lookup(cell->type.str()); + if (cell_type_ref != Twine::Null && design->has(cell_type_ref)) + module_deps[mod].insert(design->module(cell_type_ref)); + } } // simple good-enough topological sort @@ -1881,7 +1887,7 @@ struct Smt2Backend : public Backend { not_ready_yet:; } if (sorted_modules_idx == sorted_modules.size()) - log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", module_deps.begin()->first->name.unescape()); + log_error("Cyclic dependency between modules found! Cycle includes module %s.\n", module_deps.begin()->first->design->twines.str(module_deps.begin()->first->meta_->name).c_str()); while (sorted_modules_idx < sorted_modules.size()) module_deps.erase(sorted_modules.at(sorted_modules_idx++)); } diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc index 1f73993ca..b9133eeff 100644 --- a/backends/smv/smv.cc +++ b/backends/smv/smv.cc @@ -91,7 +91,7 @@ struct SmvWorker ct(module->design), sigmap(module), module(module), f(f), verbose(verbose), idcounter(0) { for (auto mod : module->design->modules()) - cid(mod->name, true); + cid(IdString(module->design->twines.str(mod->meta_->name)), true); for (auto wire : module->wires()) cid(wire->name, true); @@ -100,7 +100,7 @@ struct SmvWorker cid(cell->name, true); cid(cell->type, true); for (auto &conn : cell->connections()) - cid(conn.first, true); + cid(IdString(module->design->twines.str(conn.first)), true); } } @@ -209,7 +209,7 @@ struct SmvWorker void run() { - f << stringf("MODULE %s\n", cid(module->name)); + f << stringf("MODULE %s\n", cid(IdString(module->design->twines.str(module->meta_->name)))); for (auto wire : module->wires()) { @@ -597,9 +597,9 @@ struct SmvWorker for (auto &conn : cell->connections()) if (cell->output(conn.first)) - definitions.push_back(stringf("%s := %s.%s;", lvalue(conn.second), cid(cell->name), cid(conn.first))); + definitions.push_back(stringf("%s := %s.%s;", lvalue(conn.second), cid(cell->name), cid(IdString(module->design->twines.str(conn.first))))); else - definitions.push_back(stringf("%s.%s := %s;", cid(cell->name), cid(conn.first), rvalue(conn.second))); + definitions.push_back(stringf("%s.%s := %s;", cid(cell->name), cid(IdString(module->design->twines.str(conn.first))), rvalue(conn.second))); } for (Wire *wire : partial_assignment_wires) diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 5f14a2a66..340c72081 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -104,8 +104,9 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De for (RTLIL::Wire *wire : ports) { log_assert(wire != NULL); RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width); - if (cell->hasPort(wire->name)) { - sig = sigmap(cell->getPort(wire->name)); + TwineRef wire_name_ref = design->twines.lookup(wire->name.str()); + if (cell->hasPort(wire_name_ref)) { + sig = sigmap(cell->getPort(wire_name_ref)); sig.extend_u0(wire->width, false); } port_sigs.push_back(sig); @@ -213,7 +214,7 @@ struct SpiceBackend : public Backend { if (top_module_name.empty()) for (auto module : design->modules()) if (module->get_bool_attribute(ID::top)) - top_module_name = module->name.str(); + top_module_name = design->twines.str(module->meta_->name); *f << stringf("* SPICE netlist generated by %s\n", yosys_maybe_version()); *f << stringf("\n"); @@ -228,7 +229,7 @@ struct SpiceBackend : public Backend { if (module->memories.size() != 0) log_error("Found unmapped memories in module %s: unmapped memories are not supported in SPICE backend!\n", module); - if (module->name == RTLIL::escape_id(top_module_name)) { + if (design->twines.str(module->meta_->name) == RTLIL::escape_id(top_module_name)) { top_module = module; continue; } @@ -242,7 +243,7 @@ struct SpiceBackend : public Backend { ports.at(wire->port_id-1) = wire; } - *f << stringf(".SUBCKT %s", spice_id2str(module->name)); + *f << stringf(".SUBCKT %s", spice_id2str(IdString(design->twines.str(module->meta_->name)))); for (RTLIL::Wire *wire : ports) { log_assert(wire != NULL); if (wire->width > 1) { @@ -253,7 +254,7 @@ struct SpiceBackend : public Backend { } *f << stringf("\n"); print_spice_module(*f, module, design, neg, pos, buf, ncpf, big_endian, use_inames); - *f << stringf(".ENDS %s\n\n", spice_id2str(module->name)); + *f << stringf(".ENDS %s\n\n", spice_id2str(IdString(design->twines.str(module->meta_->name)))); } if (!top_module_name.empty()) { diff --git a/backends/table/table.cc b/backends/table/table.cc index bbb533965..546f2488a 100644 --- a/backends/table/table.cc +++ b/backends/table/table.cc @@ -77,7 +77,7 @@ struct TableBackend : public Backend { if (wire->port_id == 0) continue; - *f << module->name.unescape() << "\t"; + *f << design->twines.str(module->meta_->name) << "\t"; *f << wire->name.unescape() << "\t"; *f << "-" << "\t"; *f << "-" << "\t"; @@ -97,10 +97,10 @@ struct TableBackend : public Backend { for (auto cell : module->cells()) for (auto conn : cell->connections()) { - *f << module->name.unescape() << "\t"; - *f << cell->name.unescape() << "\t"; + *f << design->twines.str(module->meta_->name) << "\t"; + *f << cell->module->design->twines.str(cell->meta_->name) << "\t"; *f << cell->type.unescape() << "\t"; - *f << conn.first.unescape() << "\t"; + *f << design->twines.str(conn.first) << "\t"; if (cell->input(conn.first) && cell->output(conn.first)) *f << "inout" << "\t"; diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 55a27d713..6f3e199c7 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -143,7 +143,7 @@ void reset_auto_counter(RTLIL::Module *module) auto_name_counter = 0; auto_name_offset = 0; - reset_auto_counter_id(module->name, false); + reset_auto_counter_id(RTLIL::IdString(module->design->twines.flat_string(module->meta_->name)), false); for (auto w : module->wires()) reset_auto_counter_id(w->name, true); @@ -154,7 +154,7 @@ void reset_auto_counter(RTLIL::Module *module) } for (auto it = module->processes.begin(); it != module->processes.end(); ++it) - reset_auto_counter_id(it->second->name, false); + reset_auto_counter_id(RTLIL::IdString(module->design->twines.flat_string(it->first)), false); auto_name_digits = 1; for (size_t i = 10; i < auto_name_offset + auto_name_map.size(); i = i*10) @@ -417,7 +417,7 @@ void dump_attributes(std::ostream &f, std::string indent, dictsecond == State::S1 || it->second == Const(1))) f << stringf(" 1 "); else if (it->first == ID::src && (it->second.flags & RTLIL::CONST_FLAG_STRING) && active_module && active_module->design) - dump_const(f, RTLIL::Const(active_module->design->resolve_src(it->second.decode_string())), -1, 0, false, as_comment); + dump_const(f, RTLIL::Const(it->second.decode_string()), -1, 0, false, as_comment); else dump_const(f, it->second, -1, 0, false, as_comment); f << stringf(" %s%s", as_comment ? "*/" : "*)", term); @@ -981,15 +981,18 @@ void dump_cell_expr_port(std::ostream &f, RTLIL::Cell *cell, std::string port, b { if (gen_signed && cell->parameters.count("\\" + port + "_SIGNED") > 0 && cell->parameters["\\" + port + "_SIGNED"].as_bool()) { f << stringf("$signed("); - dump_sigspec(f, cell->getPort("\\" + port)); + TwineRef port_ref = cell->module->design->twines.lookup("\\" + port); + dump_sigspec(f, cell->getPort(port_ref != Twine::Null ? port_ref : cell->module->design->twines.add(Twine{"\\" + port}))); f << stringf(")"); - } else - dump_sigspec(f, cell->getPort("\\" + port)); + } else { + TwineRef port_ref = cell->module->design->twines.lookup("\\" + port); + dump_sigspec(f, cell->getPort(port_ref != Twine::Null ? port_ref : cell->module->design->twines.add(Twine{"\\" + port}))); + } } std::string cellname(RTLIL::Cell *cell) { - if (!norename && cell->name[0] == '$' && cell->is_builtin_ff() && cell->hasPort(ID::Q) && !cell->type.in(ID($ff), ID($_FF_))) + if (!norename && cell->name[0] == '$' && cell->is_builtin_ff() && cell->hasPort(TW::Q) && !cell->type.in(ID($ff), ID($_FF_))) { RTLIL::SigSpec sig = cell->getPort(TW::Q); if (GetSize(sig) != 1 || sig.is_fully_const()) @@ -1011,7 +1014,7 @@ std::string cellname(RTLIL::Cell *cell) if (wire->width != 1) cell_name += stringf("[%d]", wire->start_offset + sig[0].offset); - if (active_module && active_module->count_id(cell_name) > 0) + if (active_module && active_module->count_id(active_module->design->twines.lookup(cell_name)) > 0) goto no_special_reg_name; return id(cell_name); @@ -2006,12 +2009,15 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf(" %s (", cell_name); bool first_arg = true; - std::set numbered_ports; + std::set numbered_ports; for (int i = 1; true; i++) { char str[16]; snprintf(str, 16, "$%d", i); + std::string port_str(str); + TwineRef port_ref = cell->module->design->twines.lookup(port_str); + bool found_port = false; for (auto it = cell->connections().begin(); it != cell->connections().end(); ++it) { - if (it->first != str) + if (port_ref == Twine::Null || it->first != port_ref) continue; if (!first_arg) f << stringf(","); @@ -2019,10 +2025,11 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf("\n%s ", indent); dump_sigspec(f, it->second); numbered_ports.insert(it->first); - goto found_numbered_port; + found_port = true; + break; } - break; - found_numbered_port:; + if (!found_port) + break; } for (auto it = cell->connections().begin(); it != cell->connections().end(); ++it) { if (numbered_ports.count(it->first)) @@ -2030,7 +2037,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (!first_arg) f << stringf(","); first_arg = false; - f << stringf("\n%s .%s(", indent, id(it->first)); + f << stringf("\n%s .%s(", indent, id(cell->module->design->twines.str(it->first)).c_str()); if (it->second.size() > 0) dump_sigspec(f, it->second); f << stringf(")"); @@ -2045,7 +2052,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) } } - if (siminit && cell->is_builtin_ff() && cell->hasPort(ID::Q) && !cell->type.in(ID($ff), ID($_FF_))) { + if (siminit && cell->is_builtin_ff() && cell->hasPort(TW::Q) && !cell->type.in(ID($ff), ID($_FF_))) { std::stringstream ss; dump_reg_init(ss, cell->getPort(TW::Q)); if (!ss.str().empty()) { @@ -2406,7 +2413,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) continue; } - if (!cell->is_builtin_ff() || !cell->hasPort(ID::Q) || cell->type.in(ID($ff), ID($_FF_))) + if (!cell->is_builtin_ff() || !cell->hasPort(TW::Q) || cell->type.in(ID($ff), ID($_FF_))) continue; RTLIL::SigSpec sig = cell->getPort(TW::Q); @@ -2430,7 +2437,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) } dump_attributes(f, indent, module->attributes, "\n", /*modattr=*/true); - f << stringf("%s" "module %s(", indent, id(module->name, false)); + f << stringf("%s" "module %s(", indent, id(RTLIL::IdString(module->design->twines.str(module->meta_->name)), false)); int cnt = 0; for (auto port : module->ports) { Wire *wire = module->wire(port); @@ -2714,12 +2721,12 @@ struct VerilogBackend : public Backend { for (auto module : design->modules()) { if (module->get_blackbox_attribute() != blackboxes) continue; - if (selected && !design->selected_whole_module(module->name)) { - if (design->selected_module(module->name)) - log_cmd_error("Can't handle partially selected module %s!\n", module->name.unescape()); + if (selected && !design->selected_whole_module(module->meta_->name)) { + if (design->selected_module(module->meta_->name)) + log_cmd_error("Can't handle partially selected module %s!\n", design->twines.str(module->meta_->name).c_str()); continue; } - log("Dumping module `%s'.\n", module->name); + log("Dumping module `%s'.\n", design->twines.str(module->meta_->name).c_str()); module->sort(); dump_module(*f, "", module); } diff --git a/docs/source/code_examples/extensions/my_cmd.cc b/docs/source/code_examples/extensions/my_cmd.cc index b6aa8d54d..cbfa40ec7 100644 --- a/docs/source/code_examples/extensions/my_cmd.cc +++ b/docs/source/code_examples/extensions/my_cmd.cc @@ -39,8 +39,8 @@ struct Test1Pass : public Pass { y->port_id = 2; RTLIL::Wire *a_inv = module->addWire(NEW_TWINE, 4); - module->addNeg(NEW_ID, a, a_inv, true); - module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 3), y); + module->addNeg(NEW_TWINE, a, a_inv, true); + module->addMux(NEW_TWINE, a, a_inv, RTLIL::SigSpec(a, 3), y); module->fixup_ports(); } diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 6cc94177b..fe49814d5 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -223,9 +223,9 @@ AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString { module = new RTLIL::Module; module->design = design; - module->name = module_name; - if (design->module(module->name)) - log_error("Duplicate definition of module %s!\n", module->name.unescape()); + module->meta_->name = design->twines.add(Twine{module_name.str()}); + if (design->module(design->twines.str(module->meta_->name))) + log_error("Duplicate definition of module %s!\n", design->twines.str(module->meta_->name).c_str()); } void AigerReader::parse_aiger() @@ -269,7 +269,7 @@ end_of_header: else log_abort(); - RTLIL::Wire* n0 = module->wire(stringf("$aiger%d$0", aiger_autoidx)); + RTLIL::Wire* n0 = module->wire(design->twines.lookup(stringf("$aiger%d$0", aiger_autoidx))); if (n0) module->connect(n0, State::S0); @@ -294,7 +294,7 @@ end_of_header: log_assert(l1 < latches.size()); wire = latches[l1]; } else if (c == 'o') { - wire = module->wire(escaped_s); + wire = module->wire(design->twines.lookup(escaped_s.str())); log_assert(l1 < outputs.size()); if (wire) { // Could have been renamed by a latch @@ -307,7 +307,7 @@ end_of_header: wire = bad_properties[l1]; } else log_abort(); - module->rename(wire, escaped_s); + module->rename(wire, design->twines.add(Twine{escaped_s.str()})); } else if (c == 'j' || c == 'f') { // TODO @@ -347,25 +347,25 @@ RTLIL::Wire* AigerReader::createWireIfNotExists(RTLIL::Module *module, unsigned const unsigned variable = literal >> 1; const bool invert = literal & 1; RTLIL::IdString wire_name(stringf("$aiger%d$%d%s", aiger_autoidx, variable, invert ? "b" : "")); - RTLIL::Wire *wire = module->wire(wire_name); + RTLIL::Wire *wire = module->wire(design->twines.lookup(wire_name.str())); if (wire) return wire; log_debug2("Creating %s\n", wire_name.c_str()); - wire = module->addWire(wire_name); + wire = module->addWire(Twine{wire_name.str()}); wire->port_input = wire->port_output = false; if (!invert) return wire; RTLIL::IdString wire_inv_name(stringf("$aiger%d$%d", aiger_autoidx, variable)); - RTLIL::Wire *wire_inv = module->wire(wire_inv_name); + RTLIL::Wire *wire_inv = module->wire(design->twines.lookup(wire_inv_name.str())); if (wire_inv) { - if (module->cell(wire_inv_name)) return wire; + if (module->cell(design->twines.lookup(wire_inv_name.str()))) return wire; } else { log_debug2("Creating %s\n", wire_inv_name.c_str()); - wire_inv = module->addWire(wire_inv_name); + wire_inv = module->addWire(Twine{wire_inv_name.str()}); wire_inv->port_input = wire_inv->port_output = false; } log_debug2("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str()); - module->addNotGate(stringf("$not$aiger%d$%d", aiger_autoidx, variable), wire_inv, wire); + module->addNotGate(Twine{stringf("$not$aiger%d$%d", aiger_autoidx, variable)}, wire_inv, wire); return wire; } @@ -402,7 +402,7 @@ void AigerReader::parse_xaiger() else log_abort(); - RTLIL::Wire* n0 = module->wire(stringf("$aiger%d$0", aiger_autoidx)); + RTLIL::Wire* n0 = module->wire(design->twines.lookup(stringf("$aiger%d$0", aiger_autoidx))); if (n0) module->connect(n0, State::S0); @@ -426,7 +426,7 @@ void AigerReader::parse_xaiger() uint32_t rootNodeID = parse_xaiger_literal(f); uint32_t cutLeavesM = parse_xaiger_literal(f); log_debug2("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM); - RTLIL::Wire *output_sig = module->wire(stringf("$aiger%d$%d", aiger_autoidx, rootNodeID)); + RTLIL::Wire *output_sig = module->wire(design->twines.lookup(stringf("$aiger%d$%d", aiger_autoidx, rootNodeID))); log_assert(output_sig); uint32_t nodeID; RTLIL::SigSpec input_sig; @@ -437,7 +437,7 @@ void AigerReader::parse_xaiger() log_debug("\tLUT '$lut$aiger%d$%d' input %d is constant!\n", aiger_autoidx, rootNodeID, cutLeavesM); continue; } - RTLIL::Wire *wire = module->wire(stringf("$aiger%d$%d", aiger_autoidx, nodeID)); + RTLIL::Wire *wire = module->wire(design->twines.lookup(stringf("$aiger%d$%d", aiger_autoidx, nodeID))); log_assert(wire); input_sig.append(wire); } @@ -456,10 +456,10 @@ void AigerReader::parse_xaiger() log_assert(o.wire == nullptr); lut_mask.set(gray, o.data); } - RTLIL::Cell *output_cell = module->cell(stringf("$and$aiger%d$%d", aiger_autoidx, rootNodeID)); + RTLIL::Cell *output_cell = module->cell(design->twines.lookup(stringf("$and$aiger%d$%d", aiger_autoidx, rootNodeID))); log_assert(output_cell); module->remove(output_cell); - module->addLut(stringf("$lut$aiger%d$%d", aiger_autoidx, rootNodeID), input_sig, output_sig, std::move(lut_mask)); + module->addLut(Twine{stringf("$lut$aiger%d$%d", aiger_autoidx, rootNodeID)}, input_sig, output_sig, std::move(lut_mask)); } } else if (c == 'r') { @@ -504,9 +504,9 @@ void AigerReader::parse_xaiger() uint32_t boxUniqueId = parse_xaiger_literal(f); log_assert(boxUniqueId > 0); uint32_t oldBoxNum = parse_xaiger_literal(f); - RTLIL::Cell* cell = module->addCell(stringf("$box%u", oldBoxNum), stringf("$__boxid%u", boxUniqueId)); - cell->setPort(ID(i), SigSpec(State::S0, boxInputs)); - cell->setPort(ID(o), SigSpec(State::S0, boxOutputs)); + RTLIL::Cell* cell = module->addCell(Twine{stringf("$box%u", oldBoxNum)}, ID(stringf("$__boxid%u", boxUniqueId))); + cell->setPort(TW::I, SigSpec(State::S0, boxInputs)); + cell->setPort(TW::O, SigSpec(State::S0, boxOutputs)); cell->attributes[ID::abc9_box_seq] = oldBoxNum; boxes.emplace_back(cell); } @@ -538,7 +538,7 @@ void AigerReader::parse_aiger_ascii() log_error("Line %u cannot be interpreted as an input!\n", line_count); log_debug2("%d is an input\n", l1); log_assert(!(l1 & 1)); // Inputs can't be inverted - RTLIL::Wire *wire = module->addWire(stringf("$i%0*d", digits, l1 >> 1)); + RTLIL::Wire *wire = module->addWire(Twine{stringf("$i%0*d", digits, l1 >> 1)}); wire->port_input = true; module->connect(createWireIfNotExists(module, l1), wire); inputs.push_back(wire); @@ -547,10 +547,10 @@ void AigerReader::parse_aiger_ascii() // Parse latches RTLIL::Wire *clk_wire = nullptr; if (L > 0 && !clk_name.empty()) { - clk_wire = module->wire(clk_name); + clk_wire = module->wire(design->twines.lookup(clk_name.str())); log_assert(!clk_wire); log_debug2("Creating %s\n", clk_name.c_str()); - clk_wire = module->addWire(clk_name); + clk_wire = module->addWire(Twine{clk_name.str()}); clk_wire->port_input = true; clk_wire->port_output = false; } @@ -560,14 +560,14 @@ void AigerReader::parse_aiger_ascii() log_error("Line %u cannot be interpreted as a latch!\n", line_count); log_debug2("%d %d is a latch\n", l1, l2); log_assert(!(l1 & 1)); - RTLIL::Wire *q_wire = module->addWire(stringf("$l%0*d", digits, l1 >> 1)); + RTLIL::Wire *q_wire = module->addWire(Twine{stringf("$l%0*d", digits, l1 >> 1)}); module->connect(createWireIfNotExists(module, l1), q_wire); RTLIL::Wire *d_wire = createWireIfNotExists(module, l2); if (clk_wire) - module->addDffGate(NEW_ID, clk_wire, d_wire, q_wire); + module->addDffGate(NEW_TWINE, clk_wire, d_wire, q_wire); else - module->addFfGate(NEW_ID, d_wire, q_wire); + module->addFfGate(NEW_TWINE, d_wire, q_wire); // Reset logic is optional in AIGER 1.9 if (f.peek() == ' ') { @@ -599,7 +599,7 @@ void AigerReader::parse_aiger_ascii() std::getline(f, line); // Ignore up to start of next line log_debug2("%d is an output\n", l1); - RTLIL::Wire *wire = module->addWire(stringf("$o%0*d", digits, i)); + RTLIL::Wire *wire = module->addWire(Twine{stringf("$o%0*d", digits, i)}); wire->port_output = true; module->connect(wire, createWireIfNotExists(module, l1)); outputs.push_back(wire); @@ -640,7 +640,7 @@ void AigerReader::parse_aiger_ascii() RTLIL::Wire *o_wire = createWireIfNotExists(module, l1); RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2); RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3); - module->addAndGate("$and" + o_wire->name.str(), i1_wire, i2_wire, o_wire); + module->addAndGate(Twine{stringf("$and%s", design->twines.str(o_wire->meta_->name).c_str())}, i1_wire, i2_wire, o_wire); } } @@ -665,7 +665,7 @@ void AigerReader::parse_aiger_binary() int digits = decimal_digits(I); for (unsigned i = 1; i <= I; ++i) { log_debug2("%d is an input\n", i); - RTLIL::Wire *wire = module->addWire(stringf("$i%0*d", digits, i)); + RTLIL::Wire *wire = module->addWire(Twine{stringf("$i%0*d", digits, i)}); wire->port_input = true; module->connect(createWireIfNotExists(module, i << 1), wire); inputs.push_back(wire); @@ -674,10 +674,10 @@ void AigerReader::parse_aiger_binary() // Parse latches RTLIL::Wire *clk_wire = nullptr; if (L > 0 && !clk_name.empty()) { - clk_wire = module->wire(clk_name); + clk_wire = module->wire(design->twines.lookup(clk_name.str())); log_assert(!clk_wire); log_debug2("Creating %s\n", clk_name.c_str()); - clk_wire = module->addWire(clk_name); + clk_wire = module->addWire(Twine{clk_name.str()}); clk_wire->port_input = true; clk_wire->port_output = false; } @@ -687,14 +687,14 @@ void AigerReader::parse_aiger_binary() if (!(f >> l2)) log_error("Line %u cannot be interpreted as a latch!\n", line_count); log_debug("%d %d is a latch\n", l1, l2); - RTLIL::Wire *q_wire = module->addWire(stringf("$l%0*d", digits, l1 >> 1)); + RTLIL::Wire *q_wire = module->addWire(Twine{stringf("$l%0*d", digits, l1 >> 1)}); module->connect(createWireIfNotExists(module, l1), q_wire); RTLIL::Wire *d_wire = createWireIfNotExists(module, l2); if (clk_wire) - module->addDff(NEW_ID, clk_wire, d_wire, q_wire); + module->addDff(NEW_TWINE, clk_wire, d_wire, q_wire); else - module->addFf(NEW_ID, d_wire, q_wire); + module->addFf(NEW_TWINE, d_wire, q_wire); // Reset logic is optional in AIGER 1.9 if (f.peek() == ' ') { @@ -726,7 +726,7 @@ void AigerReader::parse_aiger_binary() std::getline(f, line); // Ignore up to start of next line log_debug2("%d is an output\n", l1); - RTLIL::Wire *wire = module->addWire(stringf("$o%0*d", digits, i)); + RTLIL::Wire *wire = module->addWire(Twine{stringf("$o%0*d", digits, i)}); wire->port_output = true; module->connect(wire, createWireIfNotExists(module, l1)); outputs.push_back(wire); @@ -767,7 +767,7 @@ void AigerReader::parse_aiger_binary() RTLIL::Wire *o_wire = createWireIfNotExists(module, l1); RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2); RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3); - module->addAndGate("$and" + o_wire->name.str(), i1_wire, i2_wire, o_wire); + module->addAndGate(Twine{stringf("$and%s", design->twines.str(o_wire->meta_->name).c_str())}, i1_wire, i2_wire, o_wire); } } @@ -775,7 +775,7 @@ void AigerReader::post_process() { unsigned ci_count = 0, co_count = 0; for (auto cell : boxes) { - for (auto &bit : cell->connections_.at(ID(i))) { + for (auto &bit : cell->connections_.at(TW::I)) { log_assert(bit == State::S0); log_assert(co_count < outputs.size()); bit = outputs[co_count++]; @@ -783,7 +783,7 @@ void AigerReader::post_process() log_assert(bit.wire->port_output); bit.wire->port_output = false; } - for (auto &bit : cell->connections_.at(ID(o))) { + for (auto &bit : cell->connections_.at(TW::O)) { log_assert(bit == State::S0); log_assert((piNum + ci_count) < inputs.size()); bit = inputs[piNum + ci_count++]; @@ -804,7 +804,7 @@ void AigerReader::post_process() log_assert(q->port_input); q->port_input = false; - Cell* ff = module->addFfGate(NEW_ID, d, q); + Cell* ff = module->addFfGate(NEW_TWINE, d, q); ff->attributes[ID::abc9_mergeability] = mergeability[i]; q->attributes[ID::init] = initial_state[i]; } @@ -829,9 +829,9 @@ void AigerReader::post_process() // Cope with the fact that a CI might be identical // to a PI (necessary due to ABC); in those cases // simply connect the latter to the former - existing = module->wire(escaped_s); + existing = module->wire(design->twines.lookup(escaped_s.str())); if (!existing) - module->rename(wire, escaped_s); + module->rename(wire, design->twines.add(Twine{escaped_s.str()})); else { wire->port_input = false; module->connect(wire, existing); @@ -840,9 +840,9 @@ void AigerReader::post_process() } else { RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index); - existing = module->wire(indexed_name); + existing = module->wire(design->twines.lookup(indexed_name.str())); if (!existing) - module->rename(wire, indexed_name); + module->rename(wire, design->twines.add(Twine{indexed_name.str()})); else { module->connect(wire, existing); wire->port_input = false; @@ -874,9 +874,9 @@ void AigerReader::post_process() // Cope with the fact that a CO might be identical // to a PO (necessary due to ABC); in those cases // simply connect the latter to the former - existing = module->wire(escaped_s); + existing = module->wire(design->twines.lookup(escaped_s.str())); if (!existing) - module->rename(wire, escaped_s); + module->rename(wire, design->twines.add(Twine{escaped_s.str()})); else { wire->port_output = false; existing->port_output = true; @@ -887,9 +887,9 @@ void AigerReader::post_process() } else { RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index); - existing = module->wire(indexed_name); + existing = module->wire(design->twines.lookup(indexed_name.str())); if (!existing) - module->rename(wire, indexed_name); + module->rename(wire, design->twines.add(Twine{indexed_name.str()})); else { wire->port_output = false; existing->port_output = true; @@ -911,11 +911,11 @@ void AigerReader::post_process() } } else if (type == "box") { - RTLIL::Cell* cell = module->cell(stringf("$box%d", variable)); + RTLIL::Cell* cell = module->cell(design->twines.lookup(stringf("$box%d", variable))); if (!cell) log_debug("Box %d (%s) no longer exists.\n", variable, escaped_s.unescape()); else - module->rename(cell, escaped_s); + module->rename(cell, design->twines.add(Twine{escaped_s.str()})); } else log_error("Symbol type '%s' not recognised.\n", type); @@ -929,30 +929,30 @@ void AigerReader::post_process() if (min == 0 && max == 0) continue; - RTLIL::Wire *wire = module->wire(name); + RTLIL::Wire *wire = module->wire(design->twines.lookup(name.str())); if (wire) - module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name, 0))); + module->rename(wire, design->twines.add(Twine{RTLIL::escape_id(stringf("%s[%d]", name.str(), 0))})); // Do not make ports with a mix of input/output into // wide ports bool port_input = false, port_output = false; for (int i = min; i <= max; i++) { RTLIL::IdString other_name = name.str() + stringf("[%d]", i); - RTLIL::Wire *other_wire = module->wire(other_name); + RTLIL::Wire *other_wire = module->wire(design->twines.lookup(other_name.str())); if (other_wire) { port_input = port_input || other_wire->port_input; port_output = port_output || other_wire->port_output; } } - wire = module->addWire(name, max-min+1); + wire = module->addWire(Twine{name.str()}, max-min+1); wire->start_offset = min; wire->port_input = port_input; wire->port_output = port_output; for (int i = min; i <= max; i++) { RTLIL::IdString other_name = stringf("%s[%d]", name, i); - RTLIL::Wire *other_wire = module->wire(other_name); + RTLIL::Wire *other_wire = module->wire(design->twines.lookup(other_name.str())); if (other_wire) { other_wire->port_input = false; other_wire->port_output = false; @@ -971,7 +971,7 @@ void AigerReader::post_process() RTLIL::Design *mapped_design = new RTLIL::Design; mapped_design->add(module); Pass::call(mapped_design, "clean"); - mapped_design->modules_.erase(module->name); + mapped_design->modules_.erase(module->meta_->name); delete mapped_design; design->add(module); @@ -980,9 +980,9 @@ void AigerReader::post_process() if (cell->type != ID($lut)) continue; auto y_port = cell->getPort(TW::Y).as_bit(); if (y_port.wire->width == 1) - module->rename(cell, stringf("$lut%s", y_port.wire->name)); + module->rename(cell, design->twines.add(Twine{stringf("$lut%s", design->twines.str(y_port.wire->meta_->name).c_str())})); else - module->rename(cell, stringf("$lut%s[%d]", y_port.wire->name, y_port.offset)); + module->rename(cell, design->twines.add(Twine{stringf("$lut%s[%d]", design->twines.str(y_port.wire->meta_->name).c_str(), y_port.offset)})); } } diff --git a/frontends/aiger2/xaiger.cc b/frontends/aiger2/xaiger.cc index 6f1db9936..412f7a180 100644 --- a/frontends/aiger2/xaiger.cc +++ b/frontends/aiger2/xaiger.cc @@ -215,17 +215,18 @@ struct Xaiger2Frontend : public Frontend { for (auto port_id : def->ports) { Wire *port = def->wire(port_id); if (port->port_output) { - if (!cell->hasPort(search.find(port_id)) || cell->getPort(port_id).size() != port->width) + if (!cell->hasPort(port_id) || cell->getPort(port_id).size() != port->width) log_error("Malformed design (1)\n"); SigSpec &conn = cell->connections_[port_id]; + std::string port_id_str = design->twines.str(port_id); for (int j = 0; j < port->width; j++) { - if (conn[j].wire && conn[j].wire->port_output) - conn[j] = module->addWire(module->uniquify( - stringf("$box$%s$%s$%d", - cell->name.isPublic() ? cell->name.c_str() + 1 : cell->name.c_str(), - port_id.isPublic() ? port_id.c_str() + 1 : port_id.c_str(), - j))); + if (conn[j].wire && conn[j].wire->port_output) { + std::string cell_name_str = cell->name.isPublic() ? cell->name.c_str() + 1 : cell->name.c_str(); + const char *port_id_str_part = RTLIL::IdString(port_id_str).isPublic() ? port_id_str.c_str() + 1 : port_id_str.c_str(); + auto new_wire_name = module->uniquify(design->twines.add(Twine{stringf("$box$%s$%s$%d", cell_name_str.c_str(), port_id_str_part, j)})); + conn[j] = module->addWire(new_wire_name); + } bits[2*(pi_num + ci_counter + box_ci_idx++) + 2] = conn[j]; } @@ -291,15 +292,15 @@ struct Xaiger2Frontend : public Frontend { log_assert(bits[out_lit] == RTLIL::Sm); log_assert(cell_id < cells.size()); auto &cell = cells[cell_id]; - Cell *instance = module->addCell(module->uniquify(stringf("$sc%d", out_lit)), cell.type); - auto out_w = module->addWire(module->uniquify(stringf("$lit%d", out_lit))); - instance->setPort(cell.out, out_w); + Cell *instance = module->addCell(module->uniquify(design->twines.add(Twine{stringf("$sc%d", out_lit)})), cell.type); + auto out_w = module->addWire(module->uniquify(design->twines.add(Twine{stringf("$lit%d", out_lit)}))); + instance->setPort(design->twines.add(Twine{cell.out.str()}), out_w); bits[out_lit] = out_w; for (auto in : cell.ins) { uint32_t in_lit = read_be32(*f); log_assert(out_lit < bits.size()); log_assert(bits[in_lit] != RTLIL::Sm); - instance->setPort(in, bits[in_lit]); + instance->setPort(design->twines.add(Twine{in.str()}), bits[in_lit]); } } } else if (c == '\n') { @@ -413,7 +414,7 @@ struct Xaiger2Frontend : public Frontend { log_error("Bad map file: primary output literal out of range\n"); if (bits[lit] == RTLIL::Sm) log_error("Bad map file: primary output literal is a marker\n"); - Wire *w = module->wire(name); + Wire *w = module->wire(design->twines.lookup(name)); if (!w || woffset < 0 || woffset >= w->width) log_error("Map file references non-existent signal bit %s[%d]\n", name.c_str(), woffset); @@ -433,11 +434,12 @@ struct Xaiger2Frontend : public Frontend { log_error("Bad map file: pseudo primary output literal out of range\n"); if (bits[lit] == RTLIL::Sm) log_error("Bad map file: pseudo primary output literal is a marker\n"); - Cell *cell = module->cell(box_name); - if (!cell || !cell->hasPort(box_port)) + Cell *cell = module->cell(design->twines.lookup(box_name)); + auto box_port_ref = design->twines.lookup(box_port); + if (!cell || !cell->hasPort(box_port_ref)) log_error("Map file references non-existent box port %s/%s\n", box_name.c_str(), box_port.c_str()); - SigSpec &port = cell->connections_[box_port]; + SigSpec &port = cell->connections_[box_port_ref]; if (poffset < 0 || poffset >= port.size()) log_error("Map file references non-existent box port bit %s/%s[%d]\n", box_name.c_str(), box_port.c_str(), poffset); diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index e3f431062..c5488fdb4 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1114,7 +1114,7 @@ void AST::set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast) return; const auto &loc = ast->location; if (!loc.begin.filename || loc.begin.filename->empty()) { - current_module->design->set_src_attribute(obj, ast->loc_string()); + current_module->design->set_src_attribute(obj, current_module->design->twines.add(Twine{ast->loc_string()})); return; } // Split filename and per-location tail so the filename interns once @@ -1123,14 +1123,12 @@ void AST::set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast) // thousands of objects in one file this collapses N copies of a long // path into 1 Leaf + N short Suffix tails. TwinePool *pool = ¤t_module->design->twines; - TwineRef file_id = pool->intern(*loc.begin.filename); + TwineRef file_id = pool->add(Twine{*loc.begin.filename}); std::string tail = stringf(":%d.%d-%d.%d", loc.begin.line, loc.begin.column, loc.end.line, loc.end.column); - TwineRef suffix_id = pool->intern_suffix(file_id, tail); - pool->release(file_id); // suffix internally holds a ref now + TwineRef suffix_id = pool->add(Twine{Twine::Suffix{file_id, tail}}); current_module->design->obj_set_src_id(obj, suffix_id); - pool->release(suffix_id); // obj_set_src_id retained on obj's behalf } static bool param_has_no_default(const AstNode* param) { @@ -1162,7 +1160,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d module->design = design; module->ast = nullptr; - module->name = ast->str; + module->meta_->name = design->twines.add(Twine{ast->str}); set_src_attr(module, ast); module->set_bool_attribute(ID::cells_not_processed); @@ -1373,12 +1371,12 @@ AST_INTERNAL::process_and_replace_module(RTLIL::Design *design, // a static counter to make sure we get a unique name. static unsigned counter; std::ostringstream new_name; - new_name << old_module->name.str() + new_name << design->twines.str(old_module->meta_->name) << "_before_process_and_replace_module_" << counter; ++counter; - design->rename(old_module, new_name.str()); + design->rename(old_module, design->twines.add(Twine{new_name.str()})); old_module->set_bool_attribute(ID::to_delete); // Check if the module was the top module. If it was, we need to remove @@ -1486,8 +1484,9 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump if (defer_local) child->str = "$abstract" + child->str; - if (design->has(child->str)) { - RTLIL::Module *existing_mod = design->module(child->str); + TwineRef mod_name = design->twines.lookup(child->str); + if (design->has(mod_name)) { + RTLIL::Module *existing_mod = design->module(mod_name); if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) { log_file_error(*child->location.begin.filename, child->location.begin.line, "Re-definition of module `%s'!\n", child->str); } else if (nooverwrite) { @@ -1612,9 +1611,11 @@ bool AstModule::reprocess_if_necessary(RTLIL::Design *design) std::string modname = cell->get_string_attribute(ID::reprocess_after); if (modname.empty()) continue; - if (design->module(modname) || design->module("$abstract" + modname)) { + TwineRef mod_ref = design->twines.lookup(modname); + TwineRef abstract_ref = design->twines.lookup("$abstract" + modname); + if (design->module(mod_ref) || design->module(abstract_ref)) { log("Reprocessing module %s because instantiated module %s has become available.\n", - name.unescape(), RTLIL::unescape_id(modname)); + design->twines.str(meta_->name).c_str(), RTLIL::unescape_id(modname)); loadconfig(); process_and_replace_module(design, this, ast.get(), NULL); return true; @@ -1709,7 +1710,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dictname.unescape(); + interf_info += design->twines.str(intf.second->meta_->name); has_interfaces = true; } @@ -1717,10 +1718,11 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dicthas(new_modname)) { + TwineRef new_modname_ref = design->twines.lookup(new_modname); + if (!design->has(new_modname_ref)) { if (!new_ast) { - auto mod = dynamic_cast(design->module(modname)); + TwineRef modname_ref = design->twines.lookup(modname); + auto mod = dynamic_cast(design->module(modname_ref)); new_ast = mod->ast->clone(); } modname = new_modname; @@ -1749,19 +1751,20 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dictwire(intf.first) != nullptr) { + TwineRef intf_name = design->twines.lookup(intf.first.str()); + if(mod->wire(intf_name) != nullptr) { // Normally, removing wires would be batched together as it's an // expensive operation, however, in this case doing so would mean // that a cell with the same name cannot be created (below)... // Since we won't expect many interfaces to exist in a module, // we can let this slide... pool to_remove; - to_remove.insert(mod->wire(intf.first)); + to_remove.insert(mod->wire(intf_name)); mod->remove(to_remove); mod->fixup_ports(); // We copy the cell of the interface to the sub-module such that it // can further be found if it is propagated down to sub-sub-modules etc. - RTLIL::Cell *new_subcell = mod->addCell(intf.first, intf.second->name); + RTLIL::Cell *new_subcell = mod->addCell(Twine{intf.first.str()}, RTLIL::IdString(design->twines.str(intf.second->meta_->name))); new_subcell->set_bool_attribute(ID::is_interface); } else { @@ -1790,10 +1793,11 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict new_ast = NULL; std::string modname = derive_common(design, parameters, &new_ast, quiet); - if (!design->has(modname) && new_ast) { + TwineRef modname_ref = design->twines.lookup(modname); + if (!design->has(modname_ref) && new_ast) { new_ast->str = modname; process_module(design, new_ast.get(), false, NULL, quiet); - design->module(modname)->check(); + design->module(modname_ref)->check(); } else if (!quiet) { log("Found cached RTLIL representation for module `%s'.\n", modname); } @@ -1832,7 +1836,7 @@ std::string AST::derived_module_name(std::string stripped_name, const std::vecto // create a new parametric module (when needed) and return the name of the generated module std::string AstModule::derive_common(RTLIL::Design *design, const dict ¶meters, std::unique_ptr* new_ast_out, bool quiet) { - std::string stripped_name = name.str(); + std::string stripped_name = design->twines.str(meta_->name); (*new_ast_out) = nullptr; if (stripped_name.compare(0, 9, "$abstract") == 0) @@ -1864,7 +1868,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dicthas(modname)) + if (design->has(design->twines.lookup(modname))) return modname; if (!quiet) @@ -1932,7 +1936,7 @@ RTLIL::Module *AstModule::clone() const { AstModule *new_mod = new AstModule; new_mod->design = design; - new_mod->name = name; + new_mod->meta_->name = meta_->name; cloneInto(new_mod); new_mod->ast = ast->clone(); @@ -1955,7 +1959,7 @@ RTLIL::Module *AstModule::clone(RTLIL::Design *dst, bool src_id_verbatim) const { AstModule *new_mod = new AstModule; new_mod->design = dst; - new_mod->name = name; + new_mod->meta_->name = dst->twines.copy_from(design->twines, meta_->name); cloneInto(new_mod, src_id_verbatim); dst->add(new_mod); @@ -1979,7 +1983,7 @@ RTLIL::Module *AstModule::clone(RTLIL::Design *dst, RTLIL::IdString target_name, { AstModule *new_mod = new AstModule; new_mod->design = dst; - new_mod->name = target_name; + new_mod->meta_->name = dst->twines.add(Twine{target_name.str()}); cloneInto(new_mod, src_id_verbatim); dst->add(new_mod); diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 123d38e23..940bcf1b2 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -46,10 +46,10 @@ using namespace AST_INTERNAL; static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true) { IdString name = stringf("%s$%s:%d$%d", type, RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++); - RTLIL::Cell *cell = current_module->addCell(name, type); + RTLIL::Cell *cell = current_module->addCell(Twine{name.str()}, type); set_src_attr(cell, that); - RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width); + RTLIL::Wire *wire = current_module->addWire(Twine{cell->name.str() + "_Y"}, result_width); set_src_attr(wire, that); wire->is_signed = that->is_signed; @@ -78,10 +78,10 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s } IdString name = stringf("$extend$%s:%d$%d", RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++); - RTLIL::Cell *cell = current_module->addCell(name, ID($pos)); + RTLIL::Cell *cell = current_module->addCell(Twine{name.str()}, ID($pos)); set_src_attr(cell, that); - RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width); + RTLIL::Wire *wire = current_module->addWire(Twine{cell->name.str() + "_Y"}, width); set_src_attr(wire, that); wire->is_signed = that->is_signed; @@ -105,10 +105,10 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right) { IdString name = stringf("%s$%s:%d$%d", type, RTLIL::encode_filename(*that->location.begin.filename), that->location.begin.line, autoidx++); - RTLIL::Cell *cell = current_module->addCell(name, type); + RTLIL::Cell *cell = current_module->addCell(Twine{name.str()}, type); set_src_attr(cell, that); - RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width); + RTLIL::Wire *wire = current_module->addWire(Twine{cell->name.str() + "_Y"}, result_width); set_src_attr(wire, that); wire->is_signed = that->is_signed; @@ -140,10 +140,10 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const std::stringstream sstr; sstr << "$ternary$" << RTLIL::encode_filename(*that->location.begin.filename) << ":" << that->location.begin.line << "$" << (autoidx++); - RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($mux)); + RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, ID($mux)); set_src_attr(cell, that); - RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size()); + RTLIL::Wire *wire = current_module->addWire(Twine{cell->name.str() + "_Y"}, left.size()); set_src_attr(wire, that); wire->is_signed = that->is_signed; @@ -177,14 +177,15 @@ static void check_unique_id(RTLIL::Module *module, RTLIL::IdString id, to_add_kind, id.c_str(), existing_kind, location_str.c_str()); }; - if (const RTLIL::Wire *wire = module->wire(id)) + TwineRef id_tw = module->design->twines.lookup(id.str()); + if (const RTLIL::Wire *wire = module->wire(id_tw)) already_exists(wire, "signal"); - if (const RTLIL::Cell *cell = module->cell(id)) + if (const RTLIL::Cell *cell = module->cell(id_tw)) already_exists(cell, "cell"); - if (module->processes.count(id)) - already_exists(module->processes.at(id), "process"); - if (module->memories.count(id)) - already_exists(module->memories.at(id), "memory"); + if (module->processes.count(id_tw)) + already_exists(module->processes.at(id_tw), "process"); + if (module->memories.count(id_tw)) + already_exists(module->memories.at(id_tw), "memory"); } // helper class for rewriting simple lookahead references in AST always blocks @@ -353,7 +354,7 @@ struct AST_INTERNAL::ProcessGenerator LookaheadRewriter la_rewriter(always.get()); // generate process and simple root case - proc = current_module->addProcess(stringf("$proc$%s:%d$%d", RTLIL::encode_filename(*always->location.begin.filename), always->location.begin.line, autoidx++)); + proc = current_module->addProcess(Twine{stringf("$proc$%s:%d$%d", RTLIL::encode_filename(*always->location.begin.filename), always->location.begin.line, autoidx++)}); set_src_attr(proc, always.get()); for (auto &attr : always->attributes) { if (attr.second->type != AST_CONSTANT) @@ -503,9 +504,9 @@ struct AST_INTERNAL::ProcessGenerator chunk.wire->name.c_str(), chunk.width+chunk.offset-1, chunk.offset);; if (chunk.wire->name.str().find('$') != std::string::npos) wire_name += stringf("$%d", autoidx++); - } while (current_module->wire(RTLIL::IdString(wire_name)) != nullptr); + } while (current_module->wire(current_module->design->twines.lookup(wire_name)) != nullptr); - RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width); + RTLIL::Wire *wire = current_module->addWire(Twine{wire_name}, chunk.width); set_src_attr(wire, always.get()); chunk.wire = wire; @@ -818,7 +819,7 @@ struct AST_INTERNAL::ProcessGenerator std::stringstream sstr; sstr << ast->str << "$" << ast->location.begin.filename << ":" << ast->location.begin.line << "$" << (autoidx++); - Wire *en = current_module->addWire(sstr.str() + "_EN", 1); + Wire *en = current_module->addWire(Twine{sstr.str() + "_EN"}, 1); set_src_attr(en, ast); proc->root_case.actions.push_back(SigSig(en, false)); current_case->actions.push_back(SigSig(en, true)); @@ -836,7 +837,7 @@ struct AST_INTERNAL::ProcessGenerator } RTLIL::Const polarity = polarity_builder.build(); - RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($print)); + RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, ID($print)); set_src_attr(cell, ast); cell->setParam(ID::TRG_WIDTH, triggers.size()); cell->setParam(ID::TRG_ENABLE, (always->type == AST_INITIAL) || !triggers.empty()); @@ -882,7 +883,7 @@ struct AST_INTERNAL::ProcessGenerator } Fmt fmt; - fmt.parse_verilog(args, /*sformat_like=*/false, default_base, /*task_name=*/ast->str, current_module->name); + fmt.parse_verilog(args, /*sformat_like=*/false, default_base, /*task_name=*/ast->str, RTLIL::IdString(current_module->design->twines.str(current_module->meta_->name))); if (ast->str.substr(0, 8) == "$display") fmt.append_literal("\n"); fmt.emit_rtlil(cell); @@ -914,9 +915,9 @@ struct AST_INTERNAL::ProcessGenerator RTLIL::SigSpec check = ast->children[0]->genWidthRTLIL(-1, false, &subst_rvalue_map.stdmap()); if (GetSize(check) != 1) - check = current_module->ReduceBool(NEW_ID, check); + check = current_module->ReduceBool(NEW_TWINE, check); - Wire *en = current_module->addWire(cellname.str() + "_EN", 1); + Wire *en = current_module->addWire(Twine{cellname.str() + "_EN"}, 1); set_src_attr(en, ast); proc->root_case.actions.push_back(SigSig(en, false)); current_case->actions.push_back(SigSig(en, true)); @@ -934,7 +935,7 @@ struct AST_INTERNAL::ProcessGenerator } RTLIL::Const polarity = polarity_builder.build(); - RTLIL::Cell *cell = current_module->addCell(cellname, ID($check)); + RTLIL::Cell *cell = current_module->addCell(Twine{cellname.str()}, ID($check)); set_src_attr(cell, ast); cell->set_bool_attribute(ID(keep)); for (auto &attr : ast->attributes) { @@ -982,7 +983,7 @@ struct AST_INTERNAL::ProcessGenerator set_src_attr(&action, child.get()); action.memid = memid; action.address = child->children[0]->genWidthRTLIL(-1, true, &subst_rvalue_map.stdmap()); - action.data = child->children[1]->genWidthRTLIL(current_module->memories[memid]->width, true, &subst_rvalue_map.stdmap()); + action.data = child->children[1]->genWidthRTLIL(current_module->memories[current_module->design->twines.lookup(memid)]->width, true, &subst_rvalue_map.stdmap()); action.enable = child->children[2]->genWidthRTLIL(-1, true, &subst_rvalue_map.stdmap()); RTLIL::Const orig_priority_mask = child->children[4]->bitsAsConst(); RTLIL::Const priority_mask = RTLIL::Const(0, cur_idx); @@ -1475,7 +1476,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // signals. RTLIL::IdString id = str; check_unique_id(current_module, id, this, "interface port"); - RTLIL::Wire *wire = current_module->addWire(id, 1); + RTLIL::Wire *wire = current_module->addWire(Twine{id.str()}, 1); set_src_attr(wire, this); wire->start_offset = 0; wire->port_id = port_id; @@ -1515,7 +1516,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::Const val = children[0]->bitsAsConst(); RTLIL::IdString id = str; check_unique_id(current_module, id, this, "pwire"); - RTLIL::Wire *wire = current_module->addWire(id, GetSize(val)); + RTLIL::Wire *wire = current_module->addWire(Twine{id.str()}, GetSize(val)); current_module->connect(wire, val); wire->is_signed = children[0]->is_signed; @@ -1540,7 +1541,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::IdString id = str; check_unique_id(current_module, id, this, "signal"); - RTLIL::Wire *wire = current_module->addWire(id, range_left - range_right + 1); + RTLIL::Wire *wire = current_module->addWire(Twine{id.str()}, range_left - range_right + 1); set_src_attr(wire, this); wire->start_offset = range_right; wire->port_id = port_id; @@ -1570,10 +1571,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (!children[0]->range_valid || !children[1]->range_valid) input_error("Memory `%s' with non-constant width or size!\n", str); - RTLIL::Memory *memory = new RTLIL::Memory; - memory->module = current_module; + check_unique_id(current_module, RTLIL::IdString(str), this, "memory"); + RTLIL::Memory *memory = current_module->addMemory(Twine{str}); set_src_attr(memory, this); - memory->name = str; memory->width = children[0]->range_left - children[0]->range_right + 1; if (children[1]->range_right < children[1]->range_left) { memory->start_offset = children[1]->range_right; @@ -1582,8 +1582,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) memory->start_offset = children[1]->range_left; memory->size = children[1]->range_right - children[1]->range_left + 1; } - check_unique_id(current_module, memory->name, this, "memory"); - current_module->memories[memory->name] = memory; for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) @@ -1629,8 +1627,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) log_assert(id2ast != nullptr); - if (id2ast->type == AST_AUTOWIRE && current_module->wire(RTLIL::IdString(str)) == nullptr) { - RTLIL::Wire *wire = current_module->addWire(str); + if (id2ast->type == AST_AUTOWIRE && current_module->wire(current_module->design->twines.lookup(str)) == nullptr) { + RTLIL::Wire *wire = current_module->addWire(Twine{str}); set_src_attr(wire, this); // If we are currently processing a bind directive which wires up @@ -1651,8 +1649,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) chunk = RTLIL::Const(id2ast->children[0]->bits); goto use_const_chunk; } - else if ((id2ast->type == AST_WIRE || id2ast->type == AST_AUTOWIRE || id2ast->type == AST_MEMORY) && current_module->wire(RTLIL::IdString(str)) != nullptr) { - RTLIL::Wire *current_wire = current_module->wire(str); + else if ((id2ast->type == AST_WIRE || id2ast->type == AST_AUTOWIRE || id2ast->type == AST_MEMORY) && current_module->wire(current_module->design->twines.lookup(str)) != nullptr) { + RTLIL::Wire *current_wire = current_module->wire(current_module->design->twines.lookup(str)); if (current_wire->get_bool_attribute(ID::is_interface)) is_interface = true; // Ignore @@ -1673,15 +1671,15 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // with the individual signals: if (is_interface) { IdString dummy_wire_name = stringf("$dummywireforinterface%s", str); - RTLIL::Wire *dummy_wire = current_module->wire(dummy_wire_name); + RTLIL::Wire *dummy_wire = current_module->wire(current_module->design->twines.lookup(dummy_wire_name.str())); if (!dummy_wire) { - dummy_wire = current_module->addWire(dummy_wire_name); + dummy_wire = current_module->addWire(Twine{dummy_wire_name.str()}); dummy_wire->set_bool_attribute(ID::is_interface); } return dummy_wire; } - wire = current_module->wire(RTLIL::IdString(str)); + wire = current_module->wire(current_module->design->twines.lookup(str)); chunk.wire = wire; chunk.width = wire->width; chunk.offset = 0; @@ -1728,11 +1726,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::SigSpec shift_val = fake_ast->children[1]->genRTLIL(fake_ast_width, fake_ast_sign); if (source_offset != 0) { - shift_val = current_module->Sub(NEW_ID, shift_val, source_offset, fake_ast_sign); + shift_val = current_module->Sub(NEW_TWINE, shift_val, source_offset, fake_ast_sign); fake_ast->children[1]->is_signed = true; } if (id2ast->range_swapped) { - shift_val = current_module->Sub(NEW_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast_sign); + shift_val = current_module->Sub(NEW_TWINE, RTLIL::SigSpec(source_width - width), shift_val, fake_ast_sign); fake_ast->children[1]->is_signed = true; } if (GetSize(shift_val) >= 32) @@ -2045,10 +2043,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) std::stringstream sstr; sstr << "$memrd$" << str << "$" << RTLIL::encode_filename(*location.begin.filename) << ":" << location.begin.line << "$" << (autoidx++); - RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($memrd)); + RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, ID($memrd)); set_src_attr(cell, this); - RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width); + RTLIL::Wire *wire = current_module->addWire(Twine{cell->name.str() + "_DATA"}, current_module->memories[current_module->design->twines.lookup(str)]->width); set_src_attr(wire, this); int mem_width, mem_size, addr_bits; @@ -2085,7 +2083,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) SigSpec en_sig = children[2]->genRTLIL(); - RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($meminit_v2)); + RTLIL::Cell *cell = current_module->addCell(Twine{sstr.str()}, ID($meminit_v2)); set_src_attr(cell, this); int mem_width, mem_size, addr_bits; @@ -2099,12 +2097,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) SigSpec addr_sig = children[0]->genRTLIL(); cell->setPort(TW::ADDR, addr_sig); - cell->setPort(TW::DATA, children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words, true)); + cell->setPort(TW::DATA, children[1]->genWidthRTLIL(current_module->memories[current_module->design->twines.lookup(str)]->width * num_words, true)); cell->setPort(TW::EN, en_sig); cell->parameters[ID::MEMID] = RTLIL::Const(str); cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig)); - cell->parameters[ID::WIDTH] = RTLIL::Const(current_module->memories[str]->width); + cell->parameters[ID::WIDTH] = RTLIL::Const(current_module->memories[current_module->design->twines.lookup(str)]->width); cell->parameters[ID::PRIORITY] = RTLIL::Const(autoidx-1); } @@ -2133,9 +2131,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::SigSpec check = children[0]->genRTLIL(); if (GetSize(check) != 1) - check = current_module->ReduceBool(NEW_ID, check); + check = current_module->ReduceBool(NEW_TWINE, check); - RTLIL::Cell *cell = current_module->addCell(cellname, ID($check)); + RTLIL::Cell *cell = current_module->addCell(Twine{cellname.str()}, ID($check)); set_src_attr(cell, this); for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) @@ -2187,7 +2185,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::IdString id = str; check_unique_id(current_module, id, this, "cell"); - RTLIL::Cell *cell = current_module->addCell(id, ""); + RTLIL::Cell *cell = current_module->addCell(Twine{id.str()}, ""); set_src_attr(cell, this); for (auto it = children.begin(); it != children.end(); it++) { @@ -2234,7 +2232,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // non-trivial signed nodes are indirected through // signed wires to enable sign extension RTLIL::IdString wire_name = NEW_ID; - RTLIL::Wire *wire = current_module->addWire(wire_name, GetSize(sig)); + RTLIL::Wire *wire = current_module->addWire(Twine{wire_name.str()}, GetSize(sig)); wire->is_signed = true; current_module->connect(wire, sig); sig = wire; @@ -2243,9 +2241,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (child->str.size() == 0) { char buf[100]; snprintf(buf, 100, "$%d", ++port_counter); - cell->setPort(buf, sig); + cell->setPort(current_module->design->twines.add(Twine{std::string(buf)}), sig); } else { - cell->setPort(child->str, sig); + cell->setPort(current_module->design->twines.add(Twine{child->str}), sig); } continue; } @@ -2357,7 +2355,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (width <= 0) input_error("Failed to detect width of %s!\n", RTLIL::unescape_id(str)); - Cell *cell = current_module->addCell(myid, str.substr(1)); + Cell *cell = current_module->addCell(Twine{myid}, str.substr(1)); set_src_attr(cell, this); cell->parameters[ID::WIDTH] = width; @@ -2368,7 +2366,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) cell->attributes[ID::reg] = attr->asAttrConst(); } - Wire *wire = current_module->addWire(myid + "_wire", width); + Wire *wire = current_module->addWire(Twine{myid + "_wire"}, width); set_src_attr(wire, this); cell->setPort(TW::Y, wire); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 806c49b97..4ece1100c 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -176,7 +176,7 @@ Fmt AstNode::processFormat(int stage, bool sformat_like, int default_base, size_ } Fmt fmt; - fmt.parse_verilog(args, sformat_like, default_base, /*task_name=*/str, current_module->name); + fmt.parse_verilog(args, sformat_like, default_base, /*task_name=*/str, RTLIL::IdString(current_module->design->twines.str(current_module->meta_->name))); return fmt; } @@ -1481,7 +1481,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin // determine the full name of port this argument is connected to TwineRef port_name; if (child->str.size()) - port_name = child->str; + port_name = module->design->twines.lookup(child->str); else { if (port_counter >= module->ports.size()) input_error("Cell instance has more ports than the module!\n"); @@ -1492,7 +1492,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin const RTLIL::Wire *ref = module->wire(port_name); if (ref == nullptr) input_error("Cell instance refers to port %s which does not exist in module %s!.\n", - port_name.unescape(), module->name.unescape()); + module->design->twines.str(port_name).c_str(), module->design->twines.str(module->meta_->name).c_str()); // select the argument, if present log_assert(child->children.size() <= 1); diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index 710c7ef21..18b742b84 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -115,11 +115,12 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool } } - IdString wire_id = RTLIL::escape_id(wire_name); - Wire *wire = module->wire(wire_id); + std::string escaped_name = RTLIL::escape_id(wire_name); + TwineRef wire_ref = design->twines.lookup(escaped_name); + Wire *wire = module->wire(wire_ref); if (wire == nullptr) - wire = module->addWire(wire_id); + wire = module->addWire(Twine{escaped_name}); return wire; }; @@ -127,7 +128,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool dict *obj_attributes = nullptr; dict *obj_parameters = nullptr; - dict> wideports_cache; + dict> wideports_cache; size_t buffer_size = 4096; char *buffer = (char*)malloc(buffer_size); @@ -172,11 +173,12 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool char *name = strtok(NULL, " \t\r\n"); if (name == nullptr) goto error; - module->name = RTLIL::escape_id(name); + std::string escaped_name = RTLIL::escape_id(name); + module->meta_->name = design->twines.add(Twine{escaped_name}); obj_attributes = &module->attributes; obj_parameters = nullptr; - if (design->module(module->name)) - log_error("Duplicate definition of module %s in line %d!\n", module->name.unescape(), line_count); + if (design->module(design->twines.lookup(escaped_name))) + log_error("Duplicate definition of module %s in line %d!\n", escaped_name.c_str(), line_count); design->add(module); continue; } @@ -198,13 +200,14 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool int width = wp.second.first; bool isinput = wp.second.second; - RTLIL::Wire *wire = module->addWire(name, width); + RTLIL::Wire *wire = module->addWire(Twine{design->twines.str(name)}, width); wire->port_input = isinput; wire->port_output = !isinput; for (int i = 0; i < width; i++) { - RTLIL::IdString other_name = name.str() + stringf("[%d]", i); - RTLIL::Wire *other_wire = module->wire(other_name); + std::string other_name = design->twines.str(name) + stringf("[%d]", i); + TwineRef other_ref = design->twines.lookup(other_name); + RTLIL::Wire *other_wire = module->wire(other_ref); if (other_wire) { other_wire->port_input = false; other_wire->port_output = false; @@ -233,18 +236,18 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool for (auto cell : remove_cells) module->remove(cell); - Wire *true_wire = module->wire(ID($true)); - Wire *false_wire = module->wire(ID($false)); - Wire *undef_wire = module->wire(ID($undef)); + Wire *true_wire = module->wire(design->twines.lookup("$true")); + Wire *false_wire = module->wire(design->twines.lookup("$false")); + Wire *undef_wire = module->wire(design->twines.lookup("$undef")); if (true_wire != nullptr) - module->rename(true_wire, stringf("$true$%d", ++blif_maxnum)); + module->rename(true_wire, design->twines.add(Twine{stringf("$true$%d", ++blif_maxnum)})); if (false_wire != nullptr) - module->rename(false_wire, stringf("$false$%d", ++blif_maxnum)); + module->rename(false_wire, design->twines.add(Twine{stringf("$false$%d", ++blif_maxnum)})); if (undef_wire != nullptr) - module->rename(undef_wire, stringf("$undef$%d", ++blif_maxnum)); + module->rename(undef_wire, design->twines.add(Twine{stringf("$undef$%d", ++blif_maxnum)})); autoidx.ensure_at_least(blif_maxnum+1); blif_maxnum = 0; @@ -272,10 +275,11 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool char *p; while ((p = strtok(NULL, " \t\r\n")) != NULL) { - RTLIL::IdString wire_name(stringf("\\%s", p)); - RTLIL::Wire *wire = module->wire(wire_name); + std::string wire_name_str = stringf("\\%s", p); + TwineRef wire_ref = design->twines.lookup(wire_name_str); + RTLIL::Wire *wire = module->wire(wire_ref); if (wire == nullptr) - wire = module->addWire(wire_name); + wire = module->addWire(Twine{wire_name_str}); if (!strcmp(cmd, ".inputs")) wire->port_input = true; else @@ -284,8 +288,9 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool if (wideports) { std::pair wp = wideports_split(p); if (!wp.first.empty() && wp.second >= 0) { - wideports_cache[wp.first].first = std::max(wideports_cache[wp.first].first, wp.second + 1); - wideports_cache[wp.first].second = !strcmp(cmd, ".inputs"); + TwineRef wp_ref = design->twines.lookup(wp.first.str()); + wideports_cache[wp_ref].first = std::max(wideports_cache[wp_ref].first, wp.second + 1); + wideports_cache[wp_ref].second = !strcmp(cmd, ".inputs"); } } } @@ -306,7 +311,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool goto error_with_reason; } - module->rename(lastcell, RTLIL::escape_id(p)); + module->rename(lastcell, design->twines.add(Twine{RTLIL::escape_id(p)})); continue; } @@ -364,17 +369,17 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool goto no_latch_clock; if (!strcmp(edge, "re")) - cell = module->addDffGate(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q)); + cell = module->addDffGate(NEW_TWINE, blif_wire(clock), blif_wire(d), blif_wire(q)); else if (!strcmp(edge, "fe")) - cell = module->addDffGate(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false); + cell = module->addDffGate(NEW_TWINE, blif_wire(clock), blif_wire(d), blif_wire(q), false); else if (!strcmp(edge, "ah")) - cell = module->addDlatchGate(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q)); + cell = module->addDlatchGate(NEW_TWINE, blif_wire(clock), blif_wire(d), blif_wire(q)); else if (!strcmp(edge, "al")) - cell = module->addDlatchGate(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false); + cell = module->addDlatchGate(NEW_TWINE, blif_wire(clock), blif_wire(d), blif_wire(q), false); else { no_latch_clock: if (dff_name.empty()) { - cell = module->addFfGate(NEW_ID, blif_wire(d), blif_wire(q)); + cell = module->addFfGate(NEW_TWINE, blif_wire(d), blif_wire(q)); } else { cell = module->addCell(NEW_TWINE, dff_name); cell->setPort(TW::D, blif_wire(d)); @@ -398,7 +403,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool RTLIL::Cell *cell = module->addCell(NEW_TWINE, celltype); RTLIL::Module *cell_mod = design->module(celltype); - dict> cell_wideports_cache; + dict> cell_wideports_cache; while ((p = strtok(NULL, " \t\r\n")) != NULL) { @@ -409,12 +414,18 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool if (wideports) { std::pair wp = wideports_split(p); - if (wp.first.empty()) - cell->setPort(RTLIL::escape_id(p), *q ? blif_wire(q) : SigSpec()); - else - cell_wideports_cache[wp.first][wp.second] = blif_wire(q); + if (wp.first.empty()) { + std::string port_name_str = RTLIL::escape_id(p); + TwineRef port_ref = design->twines.lookup(port_name_str); + cell->setPort(port_ref, *q ? blif_wire(q) : SigSpec()); + } else { + TwineRef wp_ref = design->twines.lookup(wp.first.str()); + cell_wideports_cache[wp_ref][wp.second] = blif_wire(q); + } } else { - cell->setPort(RTLIL::escape_id(p), *q ? blif_wire(q) : SigSpec()); + std::string port_name_str = RTLIL::escape_id(p); + TwineRef port_ref = design->twines.lookup(port_name_str); + cell->setPort(port_ref, *q ? blif_wire(q) : SigSpec()); } } @@ -609,7 +620,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool if (!sopmode) { SigSpec outnet = sopcell->getPort(TW::Y); SigSpec tempnet = module->addWire(NEW_TWINE); - module->addNotGate(NEW_ID, tempnet, outnet); + module->addNotGate(NEW_TWINE, tempnet, outnet); sopcell->setPort(TW::Y, tempnet); } } else diff --git a/frontends/json/jsonparse.cc b/frontends/json/jsonparse.cc index 4fbcfa5a5..64a2c8bee 100644 --- a/frontends/json/jsonparse.cc +++ b/frontends/json/jsonparse.cc @@ -300,7 +300,7 @@ void json_parse_attributes(RTLIL::Design *design, RTLIL::AttrObject *obj, JsonNo IdString key = RTLIL::escape_id(it.first.c_str()); Const value = json_parse_attr_param_value(it.second); if (key == ID::src && (value.flags & RTLIL::CONST_FLAG_STRING)) - design->set_src_attribute(obj, value.decode_string()); + design->set_src_attribute(obj, design->twines.add(Twine{value.decode_string()})); else obj->attributes[key] = value; } @@ -312,10 +312,10 @@ void json_import(Design *design, string &modname, JsonNode *node) Module *module = new RTLIL::Module; module->design = design; - module->name = RTLIL::escape_id(modname.c_str()); + module->meta_->name = design->twines.add(Twine{RTLIL::escape_id(modname)}); - if (design->module(module->name)) - log_error("Re-definition of module %s.\n", module->name.unescape()); + if (design->module(module->meta_->name)) + log_error("Re-definition of module %s.\n", design->twines.str(module->meta_->name)); design->add(module); @@ -357,10 +357,10 @@ void json_import(Design *design, string &modname, JsonNode *node) if (port_bits_node->type != 'A') log_error("JSON port node '%s' has non-array bits attribute.\n", port_name.unescape()); - Wire *port_wire = module->wire(port_name); + Wire *port_wire = module->wire(design->twines.lookup(port_name.str())); if (port_wire == nullptr) - port_wire = module->addWire(port_name, GetSize(port_bits_node->data_array)); + port_wire = module->addWire(Twine{port_name.str()}, GetSize(port_bits_node->data_array)); if (port_node->data_dict.count("upto") != 0) { JsonNode *val = port_node->data_dict.at("upto"); @@ -455,10 +455,10 @@ void json_import(Design *design, string &modname, JsonNode *node) if (bits_node->type != 'A') log_error("JSON netname node '%s' has non-array bits attribute.\n", net_name.unescape()); - Wire *wire = module->wire(net_name); + Wire *wire = module->wire(design->twines.lookup(net_name.str())); if (wire == nullptr) - wire = module->addWire(net_name, GetSize(bits_node->data_array)); + wire = module->addWire(Twine{net_name.str()}, GetSize(bits_node->data_array)); if (net_node->data_dict.count("upto") != 0) { JsonNode *val = net_node->data_dict.at("upto"); @@ -532,7 +532,7 @@ void json_import(Design *design, string &modname, JsonNode *node) IdString cell_type = RTLIL::escape_id(type_node->data_string.c_str()); - Cell *cell = module->addCell(cell_name, cell_type); + Cell *cell = module->addCell(Twine{cell_name.str()}, cell_type); if (cell_node->data_dict.count("connections") == 0) log_error("JSON cells node '%s' has no connections attribute.\n", cell_name.unescape()); @@ -580,7 +580,7 @@ void json_import(Design *design, string &modname, JsonNode *node) } - cell->setPort(conn_name, sig); + cell->setPort(design->twines.add(Twine{conn_name.str()}), sig); } if (cell_node->data_dict.count("attributes")) @@ -604,7 +604,7 @@ void json_import(Design *design, string &modname, JsonNode *node) JsonNode *memory_node = memory_node_it.second; RTLIL::Memory *mem = new RTLIL::Memory; - mem->name = memory_name; + mem->meta_->name = design->twines.add(Twine{memory_name.str()}); mem->module = module; if (memory_node->type != 'D') @@ -634,7 +634,7 @@ void json_import(Design *design, string &modname, JsonNode *node) if (memory_node->data_dict.count("attributes")) json_parse_attributes(design, mem, memory_node->data_dict.at("attributes")); - module->memories[mem->name] = mem; + module->memories[mem->meta_->name] = mem; } } diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index f21f1d3a7..3b92cf101 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -47,7 +47,8 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *& return *(expr++) == '0' ? RTLIL::State::S0 : RTLIL::State::S1; std::string id = RTLIL::escape_id(std::string(expr, id_len)); - RTLIL::Wire *w = module->wire(RTLIL::IdString(id)); + TwineRef wire_ref = module->design->twines.lookup(id); + RTLIL::Wire *w = module->wire(wire_ref); if (!w) log_error("Can't resolve wire name %s in %s.\n", RTLIL::unescape_id(id), module); @@ -60,7 +61,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector &stack int top = int(stack.size())-1; if (0 <= top-1 && stack[top].type == 0 && stack[top-1].type == '!') { - token_t t = token_t(0, module->NotGate(NEW_ID, stack[top].sig)); + token_t t = token_t(0, module->NotGate(NEW_TWINE, stack[top].sig)); stack.pop_back(); stack.pop_back(); stack.push_back(t); @@ -68,7 +69,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector &stack } if (0 <= top-1 && stack[top].type == '\'' && stack[top-1].type == 0) { - token_t t = token_t(0, module->NotGate(NEW_ID, stack[top-1].sig)); + token_t t = token_t(0, module->NotGate(NEW_TWINE, stack[top-1].sig)); stack.pop_back(); stack.pop_back(); stack.push_back(t); @@ -83,7 +84,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector &stack } if (0 <= top-2 && stack[top-2].type == 1 && stack[top-1].type == '^' && stack[top].type == 1) { - token_t t = token_t(1, module->XorGate(NEW_ID, stack[top-2].sig, stack[top].sig)); + token_t t = token_t(1, module->XorGate(NEW_TWINE, stack[top-2].sig, stack[top].sig)); stack.pop_back(); stack.pop_back(); stack.pop_back(); @@ -99,7 +100,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector &stack } if (0 <= top-1 && stack[top-1].type == 2 && stack[top].type == 2) { - token_t t = token_t(2, module->AndGate(NEW_ID, stack[top-1].sig, stack[top].sig)); + token_t t = token_t(2, module->AndGate(NEW_TWINE, stack[top-1].sig, stack[top].sig)); stack.pop_back(); stack.pop_back(); stack.push_back(t); @@ -107,7 +108,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector &stack } if (0 <= top-2 && stack[top-2].type == 2 && (stack[top-1].type == '*' || stack[top-1].type == '&') && stack[top].type == 2) { - token_t t = token_t(2, module->AndGate(NEW_ID, stack[top-2].sig, stack[top].sig)); + token_t t = token_t(2, module->AndGate(NEW_TWINE, stack[top-2].sig, stack[top].sig)); stack.pop_back(); stack.pop_back(); stack.pop_back(); @@ -123,7 +124,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector &stack } if (0 <= top-2 && stack[top-2].type == 3 && (stack[top-1].type == '+' || stack[top-1].type == '|') && stack[top].type == 3) { - token_t t = token_t(3, module->OrGate(NEW_ID, stack[top-2].sig, stack[top].sig)); + token_t t = token_t(3, module->OrGate(NEW_TWINE, stack[top-2].sig, stack[top].sig)); stack.pop_back(); stack.pop_back(); stack.pop_back(); @@ -188,21 +189,23 @@ static RTLIL::SigSpec create_tristate(RTLIL::Module *module, RTLIL::SigSpec func RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($tribuf)); cell->setParam(ID::WIDTH, GetSize(func)); cell->setPort(TW::A, func); - cell->setPort(TW::EN, module->NotGate(NEW_ID, three_state)); + cell->setPort(TW::EN, module->NotGate(NEW_TWINE, three_state)); cell->setPort(TW::Y, module->addWire(NEW_TWINE)); return cell->getPort(TW::Y); } static void create_latch_ff_wires(RTLIL::Module *module, const LibertyAst *node) { - module->addWire(RTLIL::escape_id(node->args.at(0))); - module->addWire(RTLIL::escape_id(node->args.at(1))); + module->addWire(Twine{RTLIL::escape_id(node->args.at(0))}); + module->addWire(Twine{RTLIL::escape_id(node->args.at(1))}); } static std::pair find_latch_ff_wires(RTLIL::Module *module, const LibertyAst *node) { - auto* iq_wire = module->wire(RTLIL::escape_id(node->args.at(0))); - auto* iqn_wire = module->wire(RTLIL::escape_id(node->args.at(1))); + TwineRef iq_ref = module->design->twines.lookup(RTLIL::escape_id(node->args.at(0))); + TwineRef iqn_ref = module->design->twines.lookup(RTLIL::escape_id(node->args.at(1))); + auto* iq_wire = module->wire(iq_ref); + auto* iqn_wire = module->wire(iqn_ref); log_assert(iq_wire && iqn_wire); return std::make_pair(iq_wire, iqn_wire); } @@ -212,7 +215,7 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node) auto [iq_sig, iqn_sig] = find_latch_ff_wires(module, node); RTLIL::SigSpec clk_sig, data_sig, clear_sig, preset_sig; bool clk_polarity = true, clear_polarity = true, preset_polarity = true; - const std::string name = module->name.unescape(); + const std::string name = module->design->twines.str(module->meta_->name); std::optional clear_preset_var1; std::optional clear_preset_var2; @@ -265,7 +268,7 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node) SigSpec q_sig = out_sig; if (neg) { q_sig = module->addWire(NEW_TWINE, out_sig.as_wire()); - module->addNotGate(NEW_ID, q_sig, out_sig); + module->addNotGate(NEW_TWINE, q_sig, out_sig); } RTLIL::Cell* cell = module->addCell(NEW_TWINE, ""); @@ -305,9 +308,9 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node) log_debug("cell %s variable %d cp_var %c set dominates? %d\n", name, (int)neg + 1, *cp_var, set_dominates); // S&R priority is well-defined now if (set_dominates) { - r_sig = module->AndnotGate(NEW_ID, r_sig, s_sig); + r_sig = module->AndnotGate(NEW_TWINE, r_sig, s_sig); } else { - s_sig = module->AndnotGate(NEW_ID, s_sig, r_sig); + s_sig = module->AndnotGate(NEW_TWINE, s_sig, r_sig); } } else { log_debug("cell %s variable %d undef c&p behavior\n", name, (int)neg + 1); @@ -609,7 +612,8 @@ struct LibertyFrontend : public Frontend { RTLIL::Module *module = new RTLIL::Module; module->design = design; std::string cell_name = RTLIL::escape_id(cell->args.at(0)); - module->name = cell_name; + TwineRef cell_name_ref = design->twines.lookup(cell_name); + module->meta_->name = design->twines.add(Twine{cell_name}); if (flag_lib) module->set_bool_attribute(ID::blackbox); @@ -642,7 +646,7 @@ struct LibertyFrontend : public Frontend { } } if (!flag_lib || dir->value != "internal") - module->addWire(RTLIL::escape_id(node->args.at(0))); + module->addWire(Twine{RTLIL::escape_id(node->args.at(0))}); } if (node->id == "bus" && node->args.size() == 1) @@ -682,7 +686,7 @@ struct LibertyFrontend : public Frontend { int bus_type_offset = std::get<1>(type_map.at(bus_type_node->value)); bool bus_type_upto = std::get<2>(type_map.at(bus_type_node->value)); - Wire *wire = module->addWire(RTLIL::escape_id(node->args.at(0)), bus_type_width); + Wire *wire = module->addWire(Twine{RTLIL::escape_id(node->args.at(0))}, bus_type_width); wire->start_offset = bus_type_offset; wire->upto = bus_type_upto; @@ -729,7 +733,8 @@ struct LibertyFrontend : public Frontend { if (flag_lib && dir->value == "internal") continue; - RTLIL::Wire *wire = module->wire(RTLIL::IdString(RTLIL::escape_id(node->args.at(0)))); + TwineRef wire_ref = module->design->twines.lookup(RTLIL::escape_id(node->args.at(0))); + RTLIL::Wire *wire = module->wire(wire_ref); log_assert(wire); const LibertyAst *capacitance = node->find("capacitance"); @@ -813,8 +818,8 @@ struct LibertyFrontend : public Frontend { } } - if (design->has(cell_name)) { - Module *existing_mod = design->module(cell_name); + if (design->has(cell_name_ref)) { + Module *existing_mod = design->module(cell_name_ref); if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute(ID::blackbox)) { log_error("Re-definition of cell/module %s!\n", RTLIL::unescape_id(cell_name)); } else if (flag_nooverwrite) { diff --git a/frontends/rpc/rpc_frontend.cc b/frontends/rpc/rpc_frontend.cc index 189b86697..96034bd2a 100644 --- a/frontends/rpc/rpc_frontend.cc +++ b/frontends/rpc/rpc_frontend.cc @@ -158,7 +158,7 @@ struct RpcModule : RTLIL::Module { std::shared_ptr server; RTLIL::IdString derive(RTLIL::Design *design, const dict ¶meters, bool /*mayfail*/) override { - std::string stripped_name = name.str(); + std::string stripped_name = design->twines.str(meta_->name); if (stripped_name.compare(0, 9, "$abstract") == 0) stripped_name = stripped_name.substr(9); log_assert(stripped_name[0] == '\\'); @@ -179,7 +179,7 @@ struct RpcModule : RTLIL::Module { else derived_name = "$paramod" + stripped_name + parameter_info; - if (design->has(derived_name)) { + if (design->has(design->twines.lookup(derived_name))) { log("Found cached RTLIL representation for module `%s'.\n", derived_name); } else { std::string command, input; @@ -193,12 +193,12 @@ struct RpcModule : RTLIL::Module { dict name_mangling; bool found_derived_top = false; for (auto module : derived_design->modules()) { - std::string original_name = module->name.str(); + std::string original_name = derived_design->twines.str(module->meta_->name); if (original_name == stripped_name) { found_derived_top = true; name_mangling[original_name] = derived_name; } else { - name_mangling[original_name] = derived_name + module->name.str(); + name_mangling[original_name] = derived_name + derived_design->twines.str(module->meta_->name); } } if (!found_derived_top) @@ -210,11 +210,11 @@ struct RpcModule : RTLIL::Module { cell->type = name_mangling[cell->type.str()]; for (auto module : derived_design->modules_) { - std::string mangled_name = name_mangling[module.first.str()]; + std::string mangled_name = name_mangling[derived_design->twines.str(module.first)]; - log("Importing `%s' as `%s'.\n", module.first.unescape(), mangled_name); + log("Importing `%s' as `%s'.\n", derived_design->twines.str(module.first), mangled_name); - RTLIL::IdString original_name = module.first; + RTLIL::IdString original_name = RTLIL::IdString(derived_design->twines.str(module.first)); RTLIL::Module *t = module.second->clone(design, RTLIL::IdString(mangled_name)); t->attributes.erase(ID::top); if (!t->has_attribute(ID::hdlname)) @@ -587,7 +587,7 @@ cleanup_path: log("Linking module `%s'.\n", module_name); RpcModule *module = new RpcModule; module->design = design; - module->name = "$abstract\\" + module_name; + module->meta_->name = design->twines.add(Twine{"$abstract\\" + module_name}); module->server = server; design->add(module); } diff --git a/frontends/rtlil/rtlil_frontend.cc b/frontends/rtlil/rtlil_frontend.cc index 1610d721d..aaaa1fafa 100644 --- a/frontends/rtlil/rtlil_frontend.cc +++ b/frontends/rtlil/rtlil_frontend.cc @@ -361,7 +361,7 @@ struct RTLILFrontendWorker { // We don't need to addref/release in this case. std::optional id = try_parse_id(); if (id.has_value()) { - RTLIL::Wire *wire = current_module->wire(*id); + RTLIL::Wire *wire = current_module->wire(design->twines.lookup(id->str())); if (wire == nullptr) { if (flag_legalize) wire = legalize_wire(*id); @@ -515,17 +515,7 @@ struct RTLILFrontendWorker { // is wrong and silently interning it would hide that. if (id == RTLIL::ID::src && (c.flags & RTLIL::CONST_FLAG_STRING)) { std::string raw = c.decode_string(); - // TODO error handling - auto file_id = design->twines.parse_ref(raw); - if (file_id) { - // Translate the file-local twine id to the destination - // design's pool id via twine_remap. If the file had no - // `twines` block (legacy) the remap is empty — accept the - // ref verbatim and let downstream code intern it. - auto it = twine_remap.find(*file_id); - if (it != twine_remap.end()) - c = RTLIL::Const(design->twines.format_ref(it->second)); - } else if (raw.find('|') != std::string::npos) { + if (raw.find('|') != std::string::npos) { log_warning("line %d: src attribute %s contains '|' separators. " "That convention is Yosys-internal; the producing tool " "should emit a single path:line.col per attribute and " @@ -541,12 +531,10 @@ struct RTLILFrontendWorker { // cell/wire src "@N" references (which use file-local ids) translate // to ids in design->twines. The destination pool may already be // non-empty (multi-file load) — interned/concated nodes are dedup'd - // against the existing pool by the pool itself. Each parser-side - // retain is tracked in twine_parser_holds and released at end-of-parse - // so only cell/wire references survive. + // against the existing pool by the pool itself. void parse_twines() { - TwinePoolExtender extender(design->twines, design->twines.size()); + dict file_twines; expect_eol(); while (true) { if (try_parse_keyword("end")) @@ -555,7 +543,7 @@ struct RTLILFrontendWorker { size_t file_id = parse_integer(); std::string text = parse_string(); expect_eol(); - extender.extend_leaf(text, file_id); + file_twines[file_id] = Twine{text}; continue; } if (try_parse_keyword("suffix")) { @@ -563,23 +551,30 @@ struct RTLILFrontendWorker { size_t file_parent = parse_integer(); std::string tail = parse_string(); expect_eol(); - extender.extend_suffix(file_parent, tail, file_id); + if (twine_remap.count(file_parent) == 0) + error("Unknown parent twine @%zu for suffix at line %d", file_parent, line_num); + file_twines[file_id] = Twine{Twine::Suffix{twine_remap[file_parent], tail}}; continue; } if (try_parse_keyword("concat")) { size_t file_id = parse_integer(); - std::vector children; + std::vector children; while (!try_parse_eol()) { - children.push_back(parse_integer()); + size_t child_id = parse_integer(); + if (twine_remap.count(child_id) == 0) + error("Unknown child twine @%zu for concat at line %d", child_id, line_num); + children.push_back(twine_remap[child_id]); } - extender.extend_concat(children, file_id); + file_twines[file_id] = Twine{children}; continue; } error("Expected `leaf`, `suffix` or `concat` inside twines block, got `%s'.", error_token()); } expect_eol(); - extender.finish(); + for (auto &p : file_twines) { + twine_remap[p.first] = design->twines.add(std::move(p.second)); + } } // Release the per-file parser refs gathered during parse_twines. Call @@ -587,8 +582,6 @@ struct RTLILFrontendWorker { // referred to a file_id has already adopted the corresponding local_id. void release_twine_parser_holds() { - for (TwineRef id : twine_parser_holds) - design->twines.release(id); twine_parser_holds.clear(); twine_remap.clear(); } @@ -619,15 +612,18 @@ struct RTLILFrontendWorker { { std::optional id = try_parse_id(); if (id.has_value()) { - if (current_module->wire(*id) != nullptr) { + TwineRef wire_name = design->twines.lookup(id->str()); + if (wire_name == Twine::Null) + wire_name = design->twines.add(Twine{id->str()}); + if (current_module->wire(wire_name) != nullptr) { if (flag_legalize) { log("Legalizing redefinition of wire %s.\n", *id); - pool wires = {current_module->wire(*id)}; + pool wires = {current_module->wire(wire_name)}; current_module->remove(wires); } else error("RTLIL error: redefinition of wire %s.", *id); } - wire = current_module->addWire(std::move(*id)); + wire = current_module->addWire(Twine{id->str()}); break; } if (try_parse_keyword("width")) @@ -674,18 +670,22 @@ struct RTLILFrontendWorker { int width = 1; int start_offset = 0; int size = 0; + TwineRef mem_name = Twine::Null; while (true) { std::optional id = try_parse_id(); if (id.has_value()) { - if (current_module->memories.count(*id) != 0) { + mem_name = design->twines.lookup(id->str()); + if (mem_name == Twine::Null) + mem_name = design->twines.add(Twine{id->str()}); + if (current_module->memories.count(mem_name) != 0) { if (flag_legalize) { log("Legalizing redefinition of memory %s.\n", *id); - current_module->remove(current_module->memories.at(*id)); + current_module->remove(current_module->memories.at(mem_name)); } else error("RTLIL error: redefinition of memory %s.", *id); } - memory->name = std::move(*id); + memory->meta_->name = mem_name; break; } if (try_parse_keyword("width")) @@ -702,41 +702,53 @@ struct RTLILFrontendWorker { memory->width = width; memory->start_offset = start_offset; memory->size = size; - current_module->memories.insert({memory->name, memory}); + current_module->memories.insert({mem_name, memory}); expect_eol(); } void legalize_width_parameter(RTLIL::Cell *cell, TwineRef port_name) { - std::string width_param_name = port_name.str() + "_WIDTH"; - if (cell->parameters.count(width_param_name) == 0) + std::string width_param_name = design->twines.str(port_name) + "_WIDTH"; + if (cell->parameters.count(RTLIL::IdString(width_param_name)) == 0) return; - RTLIL::Const ¶m = cell->parameters.at(width_param_name); + RTLIL::Const ¶m = cell->parameters.at(RTLIL::IdString(width_param_name)); if (param.as_int() != 0) return; - cell->parameters[width_param_name] = RTLIL::Const(cell->getPort(port_name).size()); + cell->parameters[RTLIL::IdString(width_param_name)] = RTLIL::Const(cell->getPort(port_name).size()); } void parse_cell() { RTLIL::IdString cell_type = parse_id(); - RTLIL::IdString cell_name = parse_id(); + std::string cell_name_str = parse_id(); expect_eol(); - if (current_module->cell(cell_name) != nullptr) { + TwineRef cell_name_ref = design->twines.lookup(cell_name_str); + if (cell_name_ref == Twine::Null) + cell_name_ref = design->twines.add(Twine{cell_name_str}); + + if (current_module->cell(cell_name_ref) != nullptr) { if (flag_legalize) { - RTLIL::IdString new_name; + std::string new_name_str; int suffix = 1; do { - new_name = RTLIL::IdString(cell_name.str() + "_" + std::to_string(suffix)); + new_name_str = cell_name_str + "_" + std::to_string(suffix); + TwineRef test_ref = design->twines.lookup(new_name_str); + if (test_ref == Twine::Null) + test_ref = design->twines.add(Twine{new_name_str}); ++suffix; - } while (current_module->cell(new_name) != nullptr); - log("Legalizing redefinition of cell %s by renaming to %s.\n", cell_name, new_name); - cell_name = new_name; + if (current_module->cell(test_ref) == nullptr) + break; + } while (true); + log("Legalizing redefinition of cell %s by renaming to %s.\n", cell_name_str, new_name_str); + cell_name_str = new_name_str; + cell_name_ref = design->twines.lookup(cell_name_str); + if (cell_name_ref == Twine::Null) + cell_name_ref = design->twines.add(Twine{cell_name_str}); } else - error("RTLIL error: redefinition of cell %s.", cell_name); + error("RTLIL error: redefinition of cell %s.", cell_name_str); } - RTLIL::Cell *cell = current_module->addCell(cell_name, cell_type); + RTLIL::Cell *cell = current_module->addCell(Twine{cell_name_str}, cell_type); cell->absorb_attrs(std::move(attrbuf)); while (true) @@ -763,14 +775,17 @@ struct RTLILFrontendWorker { cell->parameters.insert({std::move(param_name), std::move(val)}); expect_eol(); } else if (try_parse_keyword("connect")) { - TwineRef port_name = parse_id(); + std::string port_name_str = parse_id(); + TwineRef port_name = design->twines.lookup(port_name_str); + if (port_name == Twine::Null) + port_name = design->twines.add(Twine{port_name_str}); if (cell->hasPort(port_name)) { if (flag_legalize) - log("Legalizing redefinition of cell port %s.", port_name); + log("Legalizing redefinition of cell port %s.", port_name_str); else - error("RTLIL error: redefinition of cell port %s.", port_name); + error("RTLIL error: redefinition of cell port %s.", port_name_str); } - cell->setPort(std::move(port_name), parse_sigspec()); + cell->setPort(port_name, parse_sigspec()); if (flag_legalize) legalize_width_parameter(cell, port_name); expect_eol(); @@ -869,17 +884,21 @@ struct RTLILFrontendWorker { void parse_process() { - RTLIL::IdString proc_name = parse_id(); + std::string proc_name_str = parse_id(); expect_eol(); + TwineRef proc_name = design->twines.lookup(proc_name_str); + if (proc_name == Twine::Null) + proc_name = design->twines.add(Twine{proc_name_str}); + if (current_module->processes.count(proc_name) != 0) { if (flag_legalize) { - log("Legalizing redefinition of process %s.\n", proc_name); + log("Legalizing redefinition of process %s.\n", proc_name_str); current_module->remove(current_module->processes.at(proc_name)); } else - error("RTLIL error: redefinition of process %s.", proc_name); + error("RTLIL error: redefinition of process %s.", proc_name_str); } - RTLIL::Process *proc = current_module->addProcess(std::move(proc_name)); + RTLIL::Process *proc = current_module->addProcess(Twine{proc_name_str}); proc->absorb_attrs(std::move(attrbuf)); switch_stack.clear(); diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc index 3d6b9a184..ab8900991 100644 --- a/kernel/cellaigs.cc +++ b/kernel/cellaigs.cc @@ -94,7 +94,7 @@ struct AigMaker int inport(TwineRef portname, int portbit = 0, bool inverter = false) { if (portbit >= GetSize(cell->getPort(portname))) { - if (cell->parameters.count(portname.str() + "_SIGNED") && cell->getParam(portname.str() + "_SIGNED").as_bool()) + if (cell->parameters.count(cell->module->design->twines.str(portname) + "_SIGNED") && cell->getParam(cell->module->design->twines.str(portname) + "_SIGNED").as_bool()) return inport(portname, GetSize(cell->getPort(portname))-1, inverter); return bool_node(inverter); } @@ -247,7 +247,7 @@ struct AigMaker void outport(int node, TwineRef portname, int portbit = 0) { if (portbit < GetSize(cell->getPort(portname))) - aig->nodes.at(node).outports.push_back(pair(portname, portbit)); + aig->nodes.at(node).outports.push_back(pair(portname, portbit)); } void outport_bool(int node, TwineRef portname) @@ -305,9 +305,9 @@ Aig::Aig(Cell *cell) if (cell->type.in(ID($not), ID($_NOT_), ID($pos), ID($buf), ID($_BUF_))) { for (int i = 0; i < GetSize(cell->getPort(TW::Y)); i++) { - int A = mk.inport(ID::A, i); + int A = mk.inport(TW::A, i); int Y = cell->type.in(ID($not), ID($_NOT_)) ? mk.not_gate(A) : A; - mk.outport(Y, ID::Y, i); + mk.outport(Y, TW::Y, i); } goto optimize; } @@ -315,8 +315,8 @@ Aig::Aig(Cell *cell) if (cell->type.in(ID($and), ID($_AND_), ID($_NAND_), ID($or), ID($_OR_), ID($_NOR_), ID($xor), ID($xnor), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_))) { for (int i = 0; i < GetSize(cell->getPort(TW::Y)); i++) { - int A = mk.inport(ID::A, i); - int B = mk.inport(ID::B, i); + int A = mk.inport(TW::A, i); + int B = mk.inport(TW::B, i); int Y = cell->type.in(ID($and), ID($_AND_)) ? mk.and_gate(A, B) : cell->type.in(ID($_NAND_)) ? mk.nand_gate(A, B) : cell->type.in(ID($or), ID($_OR_)) ? mk.or_gate(A, B) : @@ -325,30 +325,30 @@ Aig::Aig(Cell *cell) cell->type.in(ID($xnor), ID($_XNOR_)) ? mk.xnor_gate(A, B) : cell->type.in(ID($_ANDNOT_)) ? mk.andnot_gate(A, B) : cell->type.in(ID($_ORNOT_)) ? mk.ornot_gate(A, B) : -1; - mk.outport(Y, ID::Y, i); + mk.outport(Y, TW::Y, i); } goto optimize; } if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_))) { - int S = mk.inport(ID::S); + int S = mk.inport(TW::S); for (int i = 0; i < GetSize(cell->getPort(TW::Y)); i++) { - int A = mk.inport(ID::A, i); - int B = mk.inport(ID::B, i); + int A = mk.inport(TW::A, i); + int B = mk.inport(TW::B, i); int Y = mk.mux_gate(A, B, S); if (cell->type == ID($_NMUX_)) Y = mk.not_gate(Y); - mk.outport(Y, ID::Y, i); + mk.outport(Y, TW::Y, i); } goto optimize; } if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) { - int Y = mk.inport(ID::A, 0); + int Y = mk.inport(TW::A, 0); for (int i = 1; i < GetSize(cell->getPort(TW::A)); i++) { - int A = mk.inport(ID::A, i); + int A = mk.inport(TW::A, i); if (cell->type == ID($reduce_and)) Y = mk.and_gate(A, Y); if (cell->type == ID($reduce_or)) Y = mk.or_gate(A, Y); if (cell->type == ID($reduce_bool)) Y = mk.or_gate(A, Y); @@ -357,35 +357,35 @@ Aig::Aig(Cell *cell) } if (cell->type == ID($reduce_xnor)) Y = mk.not_gate(Y); - mk.outport(Y, ID::Y, 0); + mk.outport(Y, TW::Y, 0); for (int i = 1; i < GetSize(cell->getPort(TW::Y)); i++) - mk.outport(mk.bool_node(false), ID::Y, i); + mk.outport(mk.bool_node(false), TW::Y, i); goto optimize; } if (cell->type.in(ID($logic_not), ID($logic_and), ID($logic_or))) { - int A = mk.inport(ID::A, 0), Y = -1; + int A = mk.inport(TW::A, 0), Y = -1; for (int i = 1; i < GetSize(cell->getPort(TW::A)); i++) - A = mk.or_gate(mk.inport(ID::A, i), A); + A = mk.or_gate(mk.inport(TW::A, i), A); if (cell->type.in(ID($logic_and), ID($logic_or))) { - int B = mk.inport(ID::B, 0); + int B = mk.inport(TW::B, 0); for (int i = 1; i < GetSize(cell->getPort(TW::B)); i++) - B = mk.or_gate(mk.inport(ID::B, i), B); + B = mk.or_gate(mk.inport(TW::B, i), B); if (cell->type == ID($logic_and)) Y = mk.and_gate(A, B); if (cell->type == ID($logic_or)) Y = mk.or_gate(A, B); } else { if (cell->type == ID($logic_not)) Y = mk.not_gate(A); } - mk.outport_bool(Y, ID::Y); + mk.outport_bool(Y, TW::Y); goto optimize; } if (cell->type.in(ID($add), ID($sub))) { int width = GetSize(cell->getPort(TW::Y)); - vector A = mk.inport_vec(ID::A, width); - vector B = mk.inport_vec(ID::B, width); + vector A = mk.inport_vec(TW::A, width); + vector B = mk.inport_vec(TW::B, width); int carry = mk.bool_node(false); if (cell->type == ID($sub)) { for (auto &n : B) @@ -393,7 +393,7 @@ Aig::Aig(Cell *cell) carry = mk.not_gate(carry); } vector Y = mk.adder(A, B, carry); - mk.outport_vec(Y, ID::Y); + mk.outport_vec(Y, TW::Y); goto optimize; } @@ -401,8 +401,8 @@ Aig::Aig(Cell *cell) { int width = std::max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::B))) + 1; - vector A = mk.inport_vec(ID::A, width); - vector B = mk.inport_vec(ID::B, width); + vector A = mk.inport_vec(TW::A, width); + vector B = mk.inport_vec(TW::B, width); if (cell->type.in(ID($gt), ID($ge))) std::swap(A, B); @@ -411,86 +411,86 @@ Aig::Aig(Cell *cell) for (auto &n : B) n = mk.not_gate(n); vector Y = mk.adder(A, B, carry); - mk.outport(Y.back(), ID::Y); + mk.outport(Y.back(), TW::Y); for (int i = 1; i < GetSize(cell->getPort(TW::Y)); i++) - mk.outport(mk.bool_node(false), ID::Y, i); + mk.outport(mk.bool_node(false), TW::Y, i); goto optimize; } if (cell->type == ID($alu)) { int width = GetSize(cell->getPort(TW::Y)); - vector A = mk.inport_vec(ID::A, width); - vector B = mk.inport_vec(ID::B, width); - int carry = mk.inport(ID::CI); - int binv = mk.inport(ID::BI); + vector A = mk.inport_vec(TW::A, width); + vector B = mk.inport_vec(TW::B, width); + int carry = mk.inport(TW::CI); + int binv = mk.inport(TW::BI); for (auto &n : B) n = mk.xor_gate(n, binv); vector X(width), CO(width); vector Y = mk.adder(A, B, carry, &X, &CO); for (int i = 0; i < width; i++) X[i] = mk.xor_gate(A[i], B[i]); - mk.outport_vec(Y, ID::Y); - mk.outport_vec(X, ID::X); - mk.outport_vec(CO, ID::CO); + mk.outport_vec(Y, TW::Y); + mk.outport_vec(X, TW::X); + mk.outport_vec(CO, TW::CO); goto optimize; } if (cell->type.in(ID($eq), ID($ne))) { int width = max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::B))); - vector A = mk.inport_vec(ID::A, width); - vector B = mk.inport_vec(ID::B, width); + vector A = mk.inport_vec(TW::A, width); + vector B = mk.inport_vec(TW::B, width); int Y = mk.bool_node(false); for (int i = 0; i < width; i++) Y = mk.or_gate(Y, mk.xor_gate(A[i], B[i])); if (cell->type == ID($eq)) Y = mk.not_gate(Y); - mk.outport_bool(Y, ID::Y); + mk.outport_bool(Y, TW::Y); goto optimize; } if (cell->type == ID($_AOI3_)) { - int A = mk.inport(ID::A); - int B = mk.inport(ID::B); - int C = mk.inport(ID::C); + int A = mk.inport(TW::A); + int B = mk.inport(TW::B); + int C = mk.inport(TW::C); int Y = mk.nor_gate(mk.and_gate(A, B), C); - mk.outport(Y, ID::Y); + mk.outport(Y, TW::Y); goto optimize; } if (cell->type == ID($_OAI3_)) { - int A = mk.inport(ID::A); - int B = mk.inport(ID::B); - int C = mk.inport(ID::C); + int A = mk.inport(TW::A); + int B = mk.inport(TW::B); + int C = mk.inport(TW::C); int Y = mk.nand_gate(mk.or_gate(A, B), C); - mk.outport(Y, ID::Y); + mk.outport(Y, TW::Y); goto optimize; } if (cell->type == ID($_AOI4_)) { - int A = mk.inport(ID::A); - int B = mk.inport(ID::B); - int C = mk.inport(ID::C); - int D = mk.inport(ID::D); + int A = mk.inport(TW::A); + int B = mk.inport(TW::B); + int C = mk.inport(TW::C); + int D = mk.inport(TW::D); int a_and_b = mk.and_gate(A, B); int Y = mk.nor_gate(a_and_b, mk.and_gate(C, D)); - mk.outport(Y, ID::Y); + mk.outport(Y, TW::Y); goto optimize; } if (cell->type == ID($_OAI4_)) { - int A = mk.inport(ID::A); - int B = mk.inport(ID::B); - int C = mk.inport(ID::C); - int D = mk.inport(ID::D); + int A = mk.inport(TW::A); + int B = mk.inport(TW::B); + int C = mk.inport(TW::C); + int D = mk.inport(TW::D); int a_or_b = mk.or_gate(A, B); int Y = mk.nand_gate(a_or_b, mk.or_gate(C, D)); - mk.outport(Y, ID::Y); + mk.outport(Y, TW::Y); goto optimize; } diff --git a/kernel/cellaigs.h b/kernel/cellaigs.h index d2ab20073..87767f584 100644 --- a/kernel/cellaigs.h +++ b/kernel/cellaigs.h @@ -30,7 +30,7 @@ struct AigNode int portbit; bool inverter; int left_parent, right_parent; - vector> outports; + vector> outports; AigNode(); bool operator==(const AigNode &other) const; diff --git a/kernel/celledges.cc b/kernel/celledges.cc index 0f7f0b0e6..488bfeb0e 100644 --- a/kernel/celledges.cc +++ b/kernel/celledges.cc @@ -31,9 +31,9 @@ void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) for (int i = 0; i < y_width; i++) { if (i < a_width) - db->add_edge(cell, ID::A, i, ID::Y, i, -1); + db->add_edge(cell, TW::A, i, TW::Y, i, -1); else if (is_signed && a_width > 0) - db->add_edge(cell, ID::A, a_width-1, ID::Y, i, -1); + db->add_edge(cell, TW::A, a_width-1, TW::Y, i, -1); } } @@ -54,14 +54,14 @@ void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) for (int i = 0; i < y_width; i++) { if (i < a_width) - db->add_edge(cell, ID::A, i, ID::Y, i, -1); + db->add_edge(cell, TW::A, i, TW::Y, i, -1); else if (is_signed && a_width > 0) - db->add_edge(cell, ID::A, a_width-1, ID::Y, i, -1); + db->add_edge(cell, TW::A, a_width-1, TW::Y, i, -1); if (i < b_width) - db->add_edge(cell, ID::B, i, ID::Y, i, -1); + db->add_edge(cell, TW::B, i, TW::Y, i, -1); else if (is_signed && b_width > 0) - db->add_edge(cell, ID::B, b_width-1, ID::Y, i, -1); + db->add_edge(cell, TW::B, b_width-1, TW::Y, i, -1); } } @@ -76,7 +76,7 @@ void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) for (int i = 0; i < y_width; i++) for (int k = 0; k <= i && k < a_width; k++) - db->add_edge(cell, ID::A, k, ID::Y, i, -1); + db->add_edge(cell, TW::A, k, TW::Y, i, -1); } void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) @@ -96,10 +96,10 @@ void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) for (int k = 0; k <= i; k++) { if (k < a_width) - db->add_edge(cell, ID::A, k, ID::Y, i, -1); + db->add_edge(cell, TW::A, k, TW::Y, i, -1); if (k < b_width) - db->add_edge(cell, ID::B, k, ID::Y, i, -1); + db->add_edge(cell, TW::B, k, TW::Y, i, -1); } } } @@ -109,7 +109,7 @@ void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) int a_width = GetSize(cell->getPort(TW::A)); for (int i = 0; i < a_width; i++) - db->add_edge(cell, ID::A, i, ID::Y, 0, -1); + db->add_edge(cell, TW::A, i, TW::Y, 0, -1); } void logic_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) @@ -118,9 +118,9 @@ void logic_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) int b_width = GetSize(cell->getPort(TW::B)); for (int i = 0; i < a_width; i++) - db->add_edge(cell, ID::A, i, ID::Y, 0, -1); + db->add_edge(cell, TW::A, i, TW::Y, 0, -1); for (int i = 0; i < b_width; i++) - db->add_edge(cell, ID::B, i, ID::Y, 0, -1); + db->add_edge(cell, TW::B, i, TW::Y, 0, -1); } void concat_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) @@ -129,9 +129,9 @@ void concat_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) int b_width = GetSize(cell->getPort(TW::B)); for (int i = 0; i < a_width; i++) - db->add_edge(cell, ID::A, i, ID::Y, i, -1); + db->add_edge(cell, TW::A, i, TW::Y, i, -1); for (int i = 0; i < b_width; i++) - db->add_edge(cell, ID::B, i, ID::Y, a_width + i, -1); + db->add_edge(cell, TW::B, i, TW::Y, a_width + i, -1); } void slice_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) @@ -143,7 +143,7 @@ void slice_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) for (int i = 0; i < y_width; i++) { int a_bit = offset + i; if (a_bit >= 0 && a_bit < a_width) - db->add_edge(cell, ID::A, a_bit, ID::Y, i, -1); + db->add_edge(cell, TW::A, a_bit, TW::Y, i, -1); } } @@ -153,10 +153,10 @@ void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) int b_width = GetSize(cell->getPort(TW::B)); for (int i = 0; i < a_width; i++) - db->add_edge(cell, ID::A, i, ID::Y, 0, -1); + db->add_edge(cell, TW::A, i, TW::Y, 0, -1); for (int i = 0; i < b_width; i++) - db->add_edge(cell, ID::B, i, ID::Y, 0, -1); + db->add_edge(cell, TW::B, i, TW::Y, 0, -1); } void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) @@ -167,13 +167,13 @@ void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) for (int i = 0; i < a_width; i++) { - db->add_edge(cell, ID::A, i, ID::Y, i, -1); + db->add_edge(cell, TW::A, i, TW::Y, i, -1); for (int k = i; k < b_width; k += a_width) - db->add_edge(cell, ID::B, k, ID::Y, i, -1); + db->add_edge(cell, TW::B, k, TW::Y, i, -1); for (int k = 0; k < s_width; k++) - db->add_edge(cell, ID::S, k, ID::Y, i, -1); + db->add_edge(cell, TW::S, k, TW::Y, i, -1); } } @@ -186,10 +186,10 @@ void bmux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) for (int i = 0; i < width; i++) { for (int k = i; k < a_width; k += width) - db->add_edge(cell, ID::A, k, ID::Y, i, -1); + db->add_edge(cell, TW::A, k, TW::Y, i, -1); for (int k = 0; k < s_width; k++) - db->add_edge(cell, ID::S, k, ID::Y, i, -1); + db->add_edge(cell, TW::S, k, TW::Y, i, -1); } } @@ -201,9 +201,9 @@ void demux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) for (int i = 0; i < width; i++) { - db->add_edge(cell, ID::A, i % a_width, ID::Y, i, -1); + db->add_edge(cell, TW::A, i % a_width, TW::Y, i, -1); for (int k = 0; k < s_width; k++) - db->add_edge(cell, ID::S, k, ID::Y, i, -1); + db->add_edge(cell, TW::S, k, TW::Y, i, -1); } } @@ -275,11 +275,11 @@ void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) if (i < b_range_upper) { for (int k = a_range_lower; k < a_range_upper; k++) - db->add_edge(cell, ID::A, k, ID::Y, i, -1); + db->add_edge(cell, TW::A, k, TW::Y, i, -1); } else { // only influence is through sign extension if (is_signed) - db->add_edge(cell, ID::A, a_width - 1, ID::Y, i, -1); + db->add_edge(cell, TW::A, a_width - 1, TW::Y, i, -1); } for (int k = 0; k < b_width_capped; k++) { @@ -289,13 +289,13 @@ void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) int skip = 1 << (k + 1); int base = skip -1; if (i % skip != base && i - a_width + 2 < 1 << b_width_capped) - db->add_edge(cell, ID::B, k, ID::Y, i, -1); + db->add_edge(cell, TW::B, k, TW::Y, i, -1); } else if (is_signed) { if (i - a_width + 2 < 1 << b_width_capped) - db->add_edge(cell, ID::B, k, ID::Y, i, -1); + db->add_edge(cell, TW::B, k, TW::Y, i, -1); } else { if (i - a_width + 1 < 1 << b_width_capped) - db->add_edge(cell, ID::B, k, ID::Y, i, -1); + db->add_edge(cell, TW::B, k, TW::Y, i, -1); } // right shifts } else if (cell->type.in(ID($shr), ID($sshr)) || (cell->type.in(ID($shift), ID($shiftx)) && !is_b_signed)) { @@ -306,10 +306,10 @@ void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) && (((y_width - i) & ~(1 << k)) < (1 << b_width_capped))); if (shift_in_bulk || (cell->type.in(ID($shr), ID($shift), ID($shiftx)) && zpad_jump)) - db->add_edge(cell, ID::B, k, ID::Y, i, -1); + db->add_edge(cell, TW::B, k, TW::Y, i, -1); } else { if (i < a_width) - db->add_edge(cell, ID::B, k, ID::Y, i, -1); + db->add_edge(cell, TW::B, k, TW::Y, i, -1); } // bidirectional shifts (positive B shifts right, negative left) } else if (cell->type.in(ID($shift), ID($shiftx)) && is_b_signed) { @@ -326,14 +326,14 @@ void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) l = l && (~(i - a_width) & ((1 << (k + 1)) - 1)) != 0; } if (r_shift_in_bulk || r_zpad_jump || l) - db->add_edge(cell, ID::B, k, ID::Y, i, -1); + db->add_edge(cell, TW::B, k, TW::Y, i, -1); } else { if (y_width - i <= b_high || a_width - 2 - i >= b_low) - db->add_edge(cell, ID::B, k, ID::Y, i, -1); + db->add_edge(cell, TW::B, k, TW::Y, i, -1); } } else { if (a_width - 1 - i >= b_low) - db->add_edge(cell, ID::B, k, ID::Y, i, -1); + db->add_edge(cell, TW::B, k, TW::Y, i, -1); } } else { log_assert(false && "unreachable"); @@ -353,14 +353,14 @@ void packed_mem_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) for (int i = 0; i < n_rd_ports; i++) { if (rd_clk_enable[i] != State::S0) { for (int k = 0; k < width; k++) - db->add_edge(cell, ID::RD_ARST, i, ID::RD_DATA, i * width + k, -1); + db->add_edge(cell, TW::RD_ARST, i, TW::RD_DATA, i * width + k, -1); continue; } for (int j = 0; j < abits; j++) for (int k = 0; k < width; k++) - db->add_edge(cell, ID::RD_ADDR, i * abits + j, - ID::RD_DATA, i * width + k, -1); + db->add_edge(cell, TW::RD_ADDR, i * abits + j, + TW::RD_DATA, i * width + k, -1); } } @@ -373,14 +373,14 @@ void memrd_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) if (cell->getParam(ID::CLK_ENABLE).as_bool()) { if (cell->type == ID($memrd_v2)) { for (int k = 0; k < width; k++) - db->add_edge(cell, ID::ARST, 0, ID::DATA, k, -1); + db->add_edge(cell, TW::ARST, 0, TW::DATA, k, -1); } return; } for (int j = 0; j < abits; j++) for (int k = 0; k < width; k++) - db->add_edge(cell, ID::ADDR, j, ID::DATA, k, -1); + db->add_edge(cell, TW::ADDR, j, TW::DATA, k, -1); } void mem_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) @@ -401,32 +401,32 @@ void ff_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) if (cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr))) { for (int k = 0; k < width; k++) { - db->add_edge(cell, ID::D, k, ID::Q, k, -1); - db->add_edge(cell, ID::EN, 0, ID::Q, k, -1); + db->add_edge(cell, TW::D, k, TW::Q, k, -1); + db->add_edge(cell, TW::EN, 0, TW::Q, k, -1); } } - if (cell->hasPort(ID::CLR)) + if (cell->hasPort(TW::CLR)) for (int k = 0; k < width; k++) - db->add_edge(cell, ID::CLR, 0, ID::Q, k, -1); - if (cell->hasPort(ID::SET)) + db->add_edge(cell, TW::CLR, 0, TW::Q, k, -1); + if (cell->hasPort(TW::SET)) for (int k = 0; k < width; k++) - db->add_edge(cell, ID::SET, 0, ID::Q, k, -1); - if (cell->hasPort(ID::ALOAD)) + db->add_edge(cell, TW::SET, 0, TW::Q, k, -1); + if (cell->hasPort(TW::ALOAD)) for (int k = 0; k < width; k++) - db->add_edge(cell, ID::ALOAD, 0, ID::Q, k, -1); - if (cell->hasPort(ID::AD)) + db->add_edge(cell, TW::ALOAD, 0, TW::Q, k, -1); + if (cell->hasPort(TW::AD)) for (int k = 0; k < width; k++) - db->add_edge(cell, ID::AD, k, ID::Q, k, -1); - if (cell->hasPort(ID::ARST)) + db->add_edge(cell, TW::AD, k, TW::Q, k, -1); + if (cell->hasPort(TW::ARST)) for (int k = 0; k < width; k++) - db->add_edge(cell, ID::ARST, 0, ID::Q, k, -1); + db->add_edge(cell, TW::ARST, 0, TW::Q, k, -1); } void full_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - std::vector input_ports; - std::vector output_ports; + std::vector input_ports; + std::vector output_ports; for (auto &conn : cell->connections()) { @@ -461,8 +461,8 @@ void bweqx_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) int max_width = std::min(width, std::min(a_width, b_width)); for (int i = 0; i < max_width; i++) { - db->add_edge(cell, ID::A, i, ID::Y, i, -1); - db->add_edge(cell, ID::B, i, ID::Y, i, -1); + db->add_edge(cell, TW::A, i, TW::Y, i, -1); + db->add_edge(cell, TW::B, i, TW::Y, i, -1); } } @@ -475,9 +475,9 @@ void bwmux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) int max_width = std::min(width, std::min(a_width, std::min(b_width, s_width))); for (int i = 0; i < max_width; i++) { - db->add_edge(cell, ID::A, i, ID::Y, i, -1); - db->add_edge(cell, ID::B, i, ID::Y, i, -1); - db->add_edge(cell, ID::S, i, ID::Y, i, -1); + db->add_edge(cell, TW::A, i, TW::Y, i, -1); + db->add_edge(cell, TW::B, i, TW::Y, i, -1); + db->add_edge(cell, TW::S, i, TW::Y, i, -1); } } diff --git a/kernel/celledges.h b/kernel/celledges.h index d5e374f05..54cdde8c2 100644 --- a/kernel/celledges.h +++ b/kernel/celledges.h @@ -28,7 +28,7 @@ YOSYS_NAMESPACE_BEGIN struct AbstractCellEdgesDatabase { virtual ~AbstractCellEdgesDatabase() { } - virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int delay) = 0; + virtual void add_edge(RTLIL::Cell *cell, TwineRef from_port, int from_bit, TwineRef to_port, int to_bit, int delay) = 0; bool add_edges_from_cell(RTLIL::Cell *cell); }; @@ -38,7 +38,7 @@ struct FwdCellEdgesDatabase : AbstractCellEdgesDatabase dict> db; FwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { } - void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override { + void add_edge(RTLIL::Cell *cell, TwineRef from_port, int from_bit, TwineRef to_port, int to_bit, int) override { SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]); SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]); db[from_sigbit].insert(to_sigbit); @@ -51,7 +51,7 @@ struct RevCellEdgesDatabase : AbstractCellEdgesDatabase dict> db; RevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { } - void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override { + void add_edge(RTLIL::Cell *cell, TwineRef from_port, int from_bit, TwineRef to_port, int to_bit, int) override { SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]); SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]); db[to_sigbit].insert(from_sigbit); diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 77b6857da..85ae31f20 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -75,7 +75,7 @@ struct CellTypes if (wire->port_output) outputs.insert(wire->meta_->name); } - setup_type(module->name, inputs, outputs); + setup_type(RTLIL::IdString(module->design->twines.str(module->meta_->name)), inputs, outputs); } void setup_design(RTLIL::Design *design) diff --git a/kernel/consteval.h b/kernel/consteval.h index 16e53929f..b748d1cef 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -132,19 +132,19 @@ struct ConstEval RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y; - log_assert(cell->hasPort(ID::Y)); + log_assert(cell->hasPort(TW::Y)); sig_y = values_map(assign_map(cell->getPort(TW::Y))); if (sig_y.is_fully_const()) return true; - if (cell->hasPort(ID::S)) { + if (cell->hasPort(TW::S)) { sig_s = cell->getPort(TW::S); } - if (cell->hasPort(ID::A)) + if (cell->hasPort(TW::A)) sig_a = cell->getPort(TW::A); - if (cell->hasPort(ID::B)) + if (cell->hasPort(TW::B)) sig_b = cell->getPort(TW::B); if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_NMUX_))) @@ -337,9 +337,9 @@ struct ConstEval RTLIL::SigSpec sig_c, sig_d; if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) { - if (cell->hasPort(ID::C)) + if (cell->hasPort(TW::C)) sig_c = cell->getPort(TW::C); - if (cell->hasPort(ID::D)) + if (cell->hasPort(TW::D)) sig_d = cell->getPort(TW::D); } diff --git a/kernel/cost.cc b/kernel/cost.cc index 7bfe95819..d4b5dc8c1 100644 --- a/kernel/cost.cc +++ b/kernel/cost.cc @@ -5,8 +5,8 @@ USING_YOSYS_NAMESPACE unsigned int CellCosts::get(RTLIL::Module *mod) { - if (mod_cost_cache_.count(mod->name)) - return mod_cost_cache_.at(mod->name); + if (mod_cost_cache_.count(mod->meta_->name)) + return mod_cost_cache_.at(mod->meta_->name); unsigned int module_cost = 1; for (auto c : mod->cells()) { @@ -14,7 +14,7 @@ unsigned int CellCosts::get(RTLIL::Module *mod) module_cost = new_cost >= module_cost ? new_cost : INT_MAX; } - mod_cost_cache_[mod->name] = module_cost; + mod_cost_cache_[mod->meta_->name] = module_cost; return module_cost; } @@ -124,7 +124,7 @@ unsigned int max_inp_width(RTLIL::Cell *cell) unsigned int port_width_sum(RTLIL::Cell *cell) { unsigned int sum = 0; - TwineRef port_width_params[] = { + IdString port_width_params[] = { ID::WIDTH, ID::A_WIDTH, ID::B_WIDTH, ID::S_WIDTH, ID::Y_WIDTH, }; @@ -146,7 +146,7 @@ unsigned int CellCosts::get(RTLIL::Cell *cell) log_debug("%s is a module, recurse\n", cell->name); return get(design_->module(cell->type)); } else if (cell->is_builtin_ff()) { - log_assert(cell->hasPort(ID::Q) && "Weird flip flop"); + log_assert(cell->hasPort(TW::Q) && "Weird flip flop"); log_debug("%s is ff\n", cell->name); return cell->getParam(ID::WIDTH).as_int(); } else if (cell->type.in(ID($mem), ID($mem_v2))) { diff --git a/kernel/cost.h b/kernel/cost.h index 15d74d7b3..3c709be30 100644 --- a/kernel/cost.h +++ b/kernel/cost.h @@ -28,7 +28,7 @@ struct CellCosts { private: - dict mod_cost_cache_; + dict mod_cost_cache_; Design *design_ = nullptr; public: diff --git a/kernel/drivertools.cc b/kernel/drivertools.cc index 55616dea1..b57c433b5 100644 --- a/kernel/drivertools.cc +++ b/kernel/drivertools.cc @@ -746,7 +746,7 @@ void DriverMap::add(SigSpec const &a, SigSpec const &b) } } -void DriverMap::add_port(Cell *cell, IdString const &port, SigSpec const &b) +void DriverMap::add_port(Cell *cell, TwineRef port, SigSpec const &b) { int offset = 0; for (auto const &chunk : b.chunks()) { @@ -877,8 +877,8 @@ std::string log_signal(DriveChunkWire const &chunk) std::string log_signal(DriveChunkPort const &chunk) { - std::string cell_id = chunk.cell->name.unescape(); - std::string port_id = chunk.port.unescape(); + std::string cell_id = chunk.cell->module->design->twines.str(cell->meta_->name); + std::string port_id = chunk.cell->module->design->twines.str(chunk.port); if (chunk.is_whole()) return stringf("%s <%s>", cell_id, port_id); if (chunk.width == 1) diff --git a/kernel/drivertools.h b/kernel/drivertools.h index 28d3be91e..ff2caeee6 100644 --- a/kernel/drivertools.h +++ b/kernel/drivertools.h @@ -87,10 +87,10 @@ struct DriveBitWire struct DriveBitPort { Cell *cell; - IdString port; + TwineRef port; int offset; - DriveBitPort(Cell *cell, IdString port, int offset) : cell(cell), port(port), offset(offset) {} + DriveBitPort(Cell *cell, TwineRef port, int offset) : cell(cell), port(port), offset(offset) {} bool operator==(const DriveBitPort &other) const { @@ -485,15 +485,15 @@ struct DriveChunkWire struct DriveChunkPort { Cell *cell; - IdString port; + TwineRef port; int offset; int width; - DriveChunkPort(Cell *cell, IdString port, int offset, int width) : + DriveChunkPort(Cell *cell, TwineRef port, int offset, int width) : cell(cell), port(port), offset(offset), width(width) { } - DriveChunkPort(Cell *cell, IdString port) : + DriveChunkPort(Cell *cell, TwineRef port) : cell(cell), port(port), offset(0), width(GetSize(cell->connections().at(port))) { } - DriveChunkPort(Cell *cell, std::pair const &conn) : + DriveChunkPort(Cell *cell, std::pair const &conn) : cell(cell), port(conn.first), offset(0), width(GetSize(conn.second)) { } DriveChunkPort(DriveBitPort const &bit) : cell(bit.cell), port(bit.port), offset(bit.offset), width(1) { } @@ -1141,7 +1141,7 @@ private: // Maps cell ports to a the first DriveBitId of the consecutive range used // for that cell port. - dict, DriveBitId> port_offsets; + dict, DriveBitId> port_offsets; // For the inverse map that maps DriveBitIds back to DriveBits we use a // sorted map containing only the first DriveBit for each wire and cell @@ -1237,7 +1237,7 @@ public: void add(SigSpec const &a, SigSpec const &b); private: - void add_port(Cell *cell, IdString const &port, SigSpec const &b); + void add_port(Cell *cell, TwineRef port, SigSpec const &b); // Only used a local variables in `orient_undirected`, always cleared, only // stored to reduce allocations. diff --git a/kernel/ff.cc b/kernel/ff.cc index 4fe2524e1..1748d1f5b 100644 --- a/kernel/ff.cc +++ b/kernel/ff.cc @@ -498,21 +498,21 @@ void FfData::aload_to_sr() { pol_clr = false; pol_set = true; if (pol_aload) { - sig_clr = patcher.Mux(NEW_ID, Const(State::S1, width), sig_ad, sig_aload); - sig_set = patcher.Mux(NEW_ID, Const(State::S0, width), sig_ad, sig_aload); + sig_clr = patcher.Mux(NEW_TWINE, Const(State::S1, width), sig_ad, sig_aload); + sig_set = patcher.Mux(NEW_TWINE, Const(State::S0, width), sig_ad, sig_aload); } else { - sig_clr = patcher.Mux(NEW_ID, sig_ad, Const(State::S1, width), sig_aload); - sig_set = patcher.Mux(NEW_ID, sig_ad, Const(State::S0, width), sig_aload); + sig_clr = patcher.Mux(NEW_TWINE, sig_ad, Const(State::S1, width), sig_aload); + sig_set = patcher.Mux(NEW_TWINE, sig_ad, Const(State::S0, width), sig_aload); } } else { pol_clr = pol_aload; pol_set = pol_aload; if (pol_aload) { - sig_clr = patcher.AndnotGate(NEW_ID, sig_aload, sig_ad); - sig_set = patcher.AndGate(NEW_ID, sig_aload, sig_ad); + sig_clr = patcher.AndnotGate(NEW_TWINE, sig_aload, sig_ad); + sig_set = patcher.AndGate(NEW_TWINE, sig_aload, sig_ad); } else { - sig_clr = patcher.OrGate(NEW_ID, sig_aload, sig_ad); - sig_set = patcher.OrnotGate(NEW_ID, sig_aload, sig_ad); + sig_clr = patcher.OrGate(NEW_TWINE, sig_aload, sig_ad); + sig_set = patcher.OrnotGate(NEW_TWINE, sig_aload, sig_ad); } } patcher.commit_inheriting_src(cell); @@ -527,31 +527,31 @@ void FfData::convert_ce_over_srst(bool val) { if (!is_fine) { if (pol_ce) { if (pol_srst) { - sig_ce = patcher.Or(NEW_ID, sig_ce, sig_srst); + sig_ce = patcher.Or(NEW_TWINE, sig_ce, sig_srst); } else { - SigSpec tmp = patcher.Not(NEW_ID, sig_srst); - sig_ce = patcher.Or(NEW_ID, sig_ce, tmp); + SigSpec tmp = patcher.Not(NEW_TWINE, sig_srst); + sig_ce = patcher.Or(NEW_TWINE, sig_ce, tmp); } } else { if (pol_srst) { - SigSpec tmp = patcher.Not(NEW_ID, sig_srst); - sig_ce = patcher.And(NEW_ID, sig_ce, tmp); + SigSpec tmp = patcher.Not(NEW_TWINE, sig_srst); + sig_ce = patcher.And(NEW_TWINE, sig_ce, tmp); } else { - sig_ce = patcher.And(NEW_ID, sig_ce, sig_srst); + sig_ce = patcher.And(NEW_TWINE, sig_ce, sig_srst); } } } else { if (pol_ce) { if (pol_srst) { - sig_ce = patcher.OrGate(NEW_ID, sig_ce, sig_srst); + sig_ce = patcher.OrGate(NEW_TWINE, sig_ce, sig_srst); } else { - sig_ce = patcher.OrnotGate(NEW_ID, sig_ce, sig_srst); + sig_ce = patcher.OrnotGate(NEW_TWINE, sig_ce, sig_srst); } } else { if (pol_srst) { - sig_ce = patcher.AndnotGate(NEW_ID, sig_ce, sig_srst); + sig_ce = patcher.AndnotGate(NEW_TWINE, sig_ce, sig_srst); } else { - sig_ce = patcher.AndGate(NEW_ID, sig_ce, sig_srst); + sig_ce = patcher.AndGate(NEW_TWINE, sig_ce, sig_srst); } } } @@ -560,31 +560,31 @@ void FfData::convert_ce_over_srst(bool val) { if (!is_fine) { if (pol_srst) { if (pol_ce) { - sig_srst = patcher.And(NEW_ID, sig_srst, sig_ce); + sig_srst = patcher.And(NEW_TWINE, sig_srst, sig_ce); } else { - SigSpec tmp = patcher.Not(NEW_ID, sig_ce); - sig_srst = patcher.And(NEW_ID, sig_srst, tmp); + SigSpec tmp = patcher.Not(NEW_TWINE, sig_ce); + sig_srst = patcher.And(NEW_TWINE, sig_srst, tmp); } } else { if (pol_ce) { - SigSpec tmp = patcher.Not(NEW_ID, sig_ce); - sig_srst = patcher.Or(NEW_ID, sig_srst, tmp); + SigSpec tmp = patcher.Not(NEW_TWINE, sig_ce); + sig_srst = patcher.Or(NEW_TWINE, sig_srst, tmp); } else { - sig_srst = patcher.Or(NEW_ID, sig_srst, sig_ce); + sig_srst = patcher.Or(NEW_TWINE, sig_srst, sig_ce); } } } else { if (pol_srst) { if (pol_ce) { - sig_srst = patcher.AndGate(NEW_ID, sig_srst, sig_ce); + sig_srst = patcher.AndGate(NEW_TWINE, sig_srst, sig_ce); } else { - sig_srst = patcher.AndnotGate(NEW_ID, sig_srst, sig_ce); + sig_srst = patcher.AndnotGate(NEW_TWINE, sig_srst, sig_ce); } } else { if (pol_ce) { - sig_srst = patcher.OrnotGate(NEW_ID, sig_srst, sig_ce); + sig_srst = patcher.OrnotGate(NEW_TWINE, sig_srst, sig_ce); } else { - sig_srst = patcher.OrGate(NEW_ID, sig_srst, sig_ce); + sig_srst = patcher.OrGate(NEW_TWINE, sig_srst, sig_ce); } } } @@ -603,14 +603,14 @@ void FfData::unmap_ce() { RTLIL::Patch patcher(module); if (!is_fine) { if (pol_ce) - sig_d = patcher.Mux(NEW_ID, sig_q, sig_d, sig_ce); + sig_d = patcher.Mux(NEW_TWINE, sig_q, sig_d, sig_ce); else - sig_d = patcher.Mux(NEW_ID, sig_d, sig_q, sig_ce); + sig_d = patcher.Mux(NEW_TWINE, sig_d, sig_q, sig_ce); } else { if (pol_ce) - sig_d = patcher.MuxGate(NEW_ID, sig_q, sig_d, sig_ce); + sig_d = patcher.MuxGate(NEW_TWINE, sig_q, sig_d, sig_ce); else - sig_d = patcher.MuxGate(NEW_ID, sig_d, sig_q, sig_ce); + sig_d = patcher.MuxGate(NEW_TWINE, sig_d, sig_q, sig_ce); } patcher.commit_inheriting_src(cell); has_ce = false; @@ -625,14 +625,14 @@ void FfData::unmap_srst() { RTLIL::Patch patcher(module); if (!is_fine) { if (pol_srst) - sig_d = patcher.Mux(NEW_ID, sig_d, val_srst, sig_srst); + sig_d = patcher.Mux(NEW_TWINE, sig_d, val_srst, sig_srst); else - sig_d = patcher.Mux(NEW_ID, val_srst, sig_d, sig_srst); + sig_d = patcher.Mux(NEW_TWINE, val_srst, sig_d, sig_srst); } else { if (pol_srst) - sig_d = patcher.MuxGate(NEW_ID, sig_d, val_srst[0], sig_srst); + sig_d = patcher.MuxGate(NEW_TWINE, sig_d, val_srst[0], sig_srst); else - sig_d = patcher.MuxGate(NEW_ID, val_srst[0], sig_d, sig_srst); + sig_d = patcher.MuxGate(NEW_TWINE, val_srst[0], sig_d, sig_srst); } patcher.commit_inheriting_src(cell); has_srst = false; @@ -664,48 +664,48 @@ Cell *FfData::emit() { cell = module->addAnyinit(name, sig_d, sig_q); log_assert(val_init.is_fully_undef()); } else { - cell = module->addFf(name, sig_d, sig_q); + cell = module->addFf(Twine{name.str()}, sig_d, sig_q); } } else if (!has_aload && !has_clk) { log_assert(has_sr); - cell = module->addSr(name, sig_set, sig_clr, sig_q, pol_set, pol_clr); + cell = module->addSr(Twine{name.str()}, sig_set, sig_clr, sig_q, pol_set, pol_clr); } else if (!has_clk) { log_assert(!has_srst); if (has_sr) - cell = module->addDlatchsr(name, sig_aload, sig_set, sig_clr, sig_ad, sig_q, pol_aload, pol_set, pol_clr); + cell = module->addDlatchsr(Twine{name.str()}, sig_aload, sig_set, sig_clr, sig_ad, sig_q, pol_aload, pol_set, pol_clr); else if (has_arst) - cell = module->addAdlatch(name, sig_aload, sig_arst, sig_ad, sig_q, val_arst, pol_aload, pol_arst); + cell = module->addAdlatch(Twine{name.str()}, sig_aload, sig_arst, sig_ad, sig_q, val_arst, pol_aload, pol_arst); else - cell = module->addDlatch(name, sig_aload, sig_ad, sig_q, pol_aload); + cell = module->addDlatch(Twine{name.str()}, sig_aload, sig_ad, sig_q, pol_aload); } else { if (has_sr) { if (has_ce) - cell = module->addDffsre(name, sig_clk, sig_ce, sig_set, sig_clr, sig_d, sig_q, pol_clk, pol_ce, pol_set, pol_clr); + cell = module->addDffsre(Twine{name.str()}, sig_clk, sig_ce, sig_set, sig_clr, sig_d, sig_q, pol_clk, pol_ce, pol_set, pol_clr); else - cell = module->addDffsr(name, sig_clk, sig_set, sig_clr, sig_d, sig_q, pol_clk, pol_set, pol_clr); + cell = module->addDffsr(Twine{name.str()}, sig_clk, sig_set, sig_clr, sig_d, sig_q, pol_clk, pol_set, pol_clr); } else if (has_arst) { if (has_ce) - cell = module->addAdffe(name, sig_clk, sig_ce, sig_arst, sig_d, sig_q, val_arst, pol_clk, pol_ce, pol_arst); + cell = module->addAdffe(Twine{name.str()}, sig_clk, sig_ce, sig_arst, sig_d, sig_q, val_arst, pol_clk, pol_ce, pol_arst); else - cell = module->addAdff(name, sig_clk, sig_arst, sig_d, sig_q, val_arst, pol_clk, pol_arst); + cell = module->addAdff(Twine{name.str()}, sig_clk, sig_arst, sig_d, sig_q, val_arst, pol_clk, pol_arst); } else if (has_aload) { if (has_ce) - cell = module->addAldffe(name, sig_clk, sig_ce, sig_aload, sig_d, sig_q, sig_ad, pol_clk, pol_ce, pol_aload); + cell = module->addAldffe(Twine{name.str()}, sig_clk, sig_ce, sig_aload, sig_d, sig_q, sig_ad, pol_clk, pol_ce, pol_aload); else - cell = module->addAldff(name, sig_clk, sig_aload, sig_d, sig_q, sig_ad, pol_clk, pol_aload); + cell = module->addAldff(Twine{name.str()}, sig_clk, sig_aload, sig_d, sig_q, sig_ad, pol_clk, pol_aload); } else if (has_srst) { if (has_ce) if (ce_over_srst) - cell = module->addSdffce(name, sig_clk, sig_ce, sig_srst, sig_d, sig_q, val_srst, pol_clk, pol_ce, pol_srst); + cell = module->addSdffce(Twine{name.str()}, sig_clk, sig_ce, sig_srst, sig_d, sig_q, val_srst, pol_clk, pol_ce, pol_srst); else - cell = module->addSdffe(name, sig_clk, sig_ce, sig_srst, sig_d, sig_q, val_srst, pol_clk, pol_ce, pol_srst); + cell = module->addSdffe(Twine{name.str()}, sig_clk, sig_ce, sig_srst, sig_d, sig_q, val_srst, pol_clk, pol_ce, pol_srst); else - cell = module->addSdff(name, sig_clk, sig_srst, sig_d, sig_q, val_srst, pol_clk, pol_srst); + cell = module->addSdff(Twine{name.str()}, sig_clk, sig_srst, sig_d, sig_q, val_srst, pol_clk, pol_srst); } else { if (has_ce) - cell = module->addDffe(name, sig_clk, sig_ce, sig_d, sig_q, pol_clk, pol_ce); + cell = module->addDffe(Twine{name.str()}, sig_clk, sig_ce, sig_d, sig_q, pol_clk, pol_ce); else - cell = module->addDff(name, sig_clk, sig_d, sig_q, pol_clk); + cell = module->addDff(Twine{name.str()}, sig_clk, sig_d, sig_q, pol_clk); } } } else { @@ -717,47 +717,47 @@ Cell *FfData::emit() { log_assert(!has_srst); log_assert(!has_sr); log_assert(!is_anyinit); - cell = module->addFfGate(name, sig_d, sig_q); + cell = module->addFfGate(Twine{name.str()}, sig_d, sig_q); } else if (!has_aload && !has_clk) { log_assert(has_sr); - cell = module->addSrGate(name, sig_set, sig_clr, sig_q, pol_set, pol_clr); + cell = module->addSrGate(Twine{name.str()}, sig_set, sig_clr, sig_q, pol_set, pol_clr); } else if (!has_clk) { log_assert(!has_srst); if (has_sr) - cell = module->addDlatchsrGate(name, sig_aload, sig_set, sig_clr, sig_ad, sig_q, pol_aload, pol_set, pol_clr); + cell = module->addDlatchsrGate(Twine{name.str()}, sig_aload, sig_set, sig_clr, sig_ad, sig_q, pol_aload, pol_set, pol_clr); else if (has_arst) - cell = module->addAdlatchGate(name, sig_aload, sig_arst, sig_ad, sig_q, val_arst.as_bool(), pol_aload, pol_arst); + cell = module->addAdlatchGate(Twine{name.str()}, sig_aload, sig_arst, sig_ad, sig_q, val_arst.as_bool(), pol_aload, pol_arst); else - cell = module->addDlatchGate(name, sig_aload, sig_ad, sig_q, pol_aload); + cell = module->addDlatchGate(Twine{name.str()}, sig_aload, sig_ad, sig_q, pol_aload); } else { if (has_sr) { if (has_ce) - cell = module->addDffsreGate(name, sig_clk, sig_ce, sig_set, sig_clr, sig_d, sig_q, pol_clk, pol_ce, pol_set, pol_clr); + cell = module->addDffsreGate(Twine{name.str()}, sig_clk, sig_ce, sig_set, sig_clr, sig_d, sig_q, pol_clk, pol_ce, pol_set, pol_clr); else - cell = module->addDffsrGate(name, sig_clk, sig_set, sig_clr, sig_d, sig_q, pol_clk, pol_set, pol_clr); + cell = module->addDffsrGate(Twine{name.str()}, sig_clk, sig_set, sig_clr, sig_d, sig_q, pol_clk, pol_set, pol_clr); } else if (has_arst) { if (has_ce) - cell = module->addAdffeGate(name, sig_clk, sig_ce, sig_arst, sig_d, sig_q, val_arst.as_bool(), pol_clk, pol_ce, pol_arst); + cell = module->addAdffeGate(Twine{name.str()}, sig_clk, sig_ce, sig_arst, sig_d, sig_q, val_arst.as_bool(), pol_clk, pol_ce, pol_arst); else - cell = module->addAdffGate(name, sig_clk, sig_arst, sig_d, sig_q, val_arst.as_bool(), pol_clk, pol_arst); + cell = module->addAdffGate(Twine{name.str()}, sig_clk, sig_arst, sig_d, sig_q, val_arst.as_bool(), pol_clk, pol_arst); } else if (has_aload) { if (has_ce) - cell = module->addAldffeGate(name, sig_clk, sig_ce, sig_aload, sig_d, sig_q, sig_ad, pol_clk, pol_ce, pol_aload); + cell = module->addAldffeGate(Twine{name.str()}, sig_clk, sig_ce, sig_aload, sig_d, sig_q, sig_ad, pol_clk, pol_ce, pol_aload); else - cell = module->addAldffGate(name, sig_clk, sig_aload, sig_d, sig_q, sig_ad, pol_clk, pol_aload); + cell = module->addAldffGate(Twine{name.str()}, sig_clk, sig_aload, sig_d, sig_q, sig_ad, pol_clk, pol_aload); } else if (has_srst) { if (has_ce) if (ce_over_srst) - cell = module->addSdffceGate(name, sig_clk, sig_ce, sig_srst, sig_d, sig_q, val_srst.as_bool(), pol_clk, pol_ce, pol_srst); + cell = module->addSdffceGate(Twine{name.str()}, sig_clk, sig_ce, sig_srst, sig_d, sig_q, val_srst.as_bool(), pol_clk, pol_ce, pol_srst); else - cell = module->addSdffeGate(name, sig_clk, sig_ce, sig_srst, sig_d, sig_q, val_srst.as_bool(), pol_clk, pol_ce, pol_srst); + cell = module->addSdffeGate(Twine{name.str()}, sig_clk, sig_ce, sig_srst, sig_d, sig_q, val_srst.as_bool(), pol_clk, pol_ce, pol_srst); else - cell = module->addSdffGate(name, sig_clk, sig_srst, sig_d, sig_q, val_srst.as_bool(), pol_clk, pol_srst); + cell = module->addSdffGate(Twine{name.str()}, sig_clk, sig_srst, sig_d, sig_q, val_srst.as_bool(), pol_clk, pol_srst); } else { if (has_ce) - cell = module->addDffeGate(name, sig_clk, sig_ce, sig_d, sig_q, pol_clk, pol_ce); + cell = module->addDffeGate(Twine{name.str()}, sig_clk, sig_ce, sig_d, sig_q, pol_clk, pol_ce); else - cell = module->addDffGate(name, sig_clk, sig_d, sig_q, pol_clk); + cell = module->addDffGate(Twine{name.str()}, sig_clk, sig_d, sig_q, pol_clk); } } } @@ -766,19 +766,8 @@ Cell *FfData::emit() { // pool, no flatten. The OwnedTwine still holds its own ref until // FfData is destroyed; set_src_id retains on the cell's behalf. cell->attributes = attributes; - if (!src_twine.empty() && cell->module && cell->module->design) { - TwinePool *dst_pool = &cell->module->design->twines; - if (src_twine.pool() == dst_pool) { - cell->set_src_id(src_twine.id()); - } else { - // Cross-pool (unusual — FfData migrated between - // designs). Rebuild the twine structure into the - // destination pool, then adopt that fresh id. - TwineRef migrated = dst_pool->copy_from(*src_twine.pool(), src_twine.id()); - cell->set_src_id(migrated); - dst_pool->release(migrated); - } - } + if (src_twine != Twine::Null && cell->module && cell->module->design) + cell->set_src_id(src_twine); if (initvals && !is_anyinit) initvals->set_init(cell->getPort(TW::Q), val_init); return cell; @@ -826,7 +815,7 @@ void FfData::flip_bits(const pool &bits) { Wire *new_q = module->addWire(NEW_TWINE, width); if (has_sr && cell) { - log_warning("Flipping D/Q/init and inserting priority fixup to legalize %s.%s [%s].\n", module->name.unescape(), cell->name.unescape(), cell->type.unescape()); + log_warning("Flipping D/Q/init and inserting priority fixup to legalize %s.%s [%s].\n", module->design->twines.str(module->meta_->name).c_str(), cell->module->design->twines.str(cell->meta_->name), cell->type.unescape()); } if (is_fine) { @@ -835,15 +824,15 @@ void FfData::flip_bits(const pool &bits) { SigSpec new_sig_clr; if (pol_set) { if (pol_clr) { - new_sig_clr = module->AndnotGate(NEW_ID, sig_set, sig_clr); + new_sig_clr = module->AndnotGate(NEW_TWINE, sig_set, sig_clr); } else { - new_sig_clr = module->AndGate(NEW_ID, sig_set, sig_clr); + new_sig_clr = module->AndGate(NEW_TWINE, sig_set, sig_clr); } } else { if (pol_clr) { - new_sig_clr = module->OrGate(NEW_ID, sig_set, sig_clr); + new_sig_clr = module->OrGate(NEW_TWINE, sig_set, sig_clr); } else { - new_sig_clr = module->OrnotGate(NEW_ID, sig_set, sig_clr); + new_sig_clr = module->OrnotGate(NEW_TWINE, sig_set, sig_clr); } } pol_set = pol_clr; @@ -852,10 +841,10 @@ void FfData::flip_bits(const pool &bits) { sig_clr = new_sig_clr; } if (has_clk || has_gclk) - sig_d = module->NotGate(NEW_ID, sig_d); + sig_d = module->NotGate(NEW_TWINE, sig_d); if (has_aload) - sig_ad = module->NotGate(NEW_ID, sig_ad); - module->addNotGate(NEW_ID, new_q, sig_q); + sig_ad = module->NotGate(NEW_TWINE, sig_ad); + module->addNotGate(NEW_TWINE, new_q, sig_q); } else { @@ -863,17 +852,17 @@ void FfData::flip_bits(const pool &bits) { SigSpec not_clr; if (!pol_clr) { not_clr = sig_clr; - sig_clr = module->Not(NEW_ID, sig_clr); + sig_clr = module->Not(NEW_TWINE, sig_clr); pol_clr = true; } else { - not_clr = module->Not(NEW_ID, sig_clr); + not_clr = module->Not(NEW_TWINE, sig_clr); } if (!pol_set) { - sig_set = module->Not(NEW_ID, sig_set); + sig_set = module->Not(NEW_TWINE, sig_set); pol_set = true; } - SigSpec masked_set = module->And(NEW_ID, sig_set, not_clr); + SigSpec masked_set = module->And(NEW_TWINE, sig_set, not_clr); for (auto bit: bits) { sig_set[bit] = sig_clr[bit]; sig_clr[bit] = masked_set[bit]; @@ -885,10 +874,10 @@ void FfData::flip_bits(const pool &bits) { mask.set(bit, State::S1); if (has_clk || has_gclk) - sig_d = module->Xor(NEW_ID, sig_d, mask); + sig_d = module->Xor(NEW_TWINE, sig_d, mask); if (has_aload) - sig_ad = module->Xor(NEW_ID, sig_ad, mask); - module->addXor(NEW_ID, new_q, mask, sig_q); + sig_ad = module->Xor(NEW_TWINE, sig_ad, mask); + module->addXor(NEW_TWINE, new_q, mask, sig_q); } sig_q = new_q; diff --git a/kernel/ffmerge.cc b/kernel/ffmerge.cc index 26f8e35df..39432b09f 100644 --- a/kernel/ffmerge.cc +++ b/kernel/ffmerge.cc @@ -301,7 +301,7 @@ void FfMergeHelper::remove_output_ff(const pool> &bits) { SigSpec q = cell->getPort(TW::Q); initvals->remove_init(q[idx]); dff_driver.erase((*sigmap)(q[idx])); - q[idx] = module->addWire(stringf("$ffmerge_disconnected$%d", autoidx++)); + q[idx] = module->addWire(Twine{stringf("$ffmerge_disconnected$%d", autoidx++)}); cell->setPort(TW::Q, q); initvals->set_init(cell->getPort(TW::Q), (*initvals)(q)); } @@ -311,7 +311,7 @@ void FfMergeHelper::mark_input_ff(const pool> &bits) { for (auto &it : bits) { Cell *cell = it.first; int idx = it.second; - if (cell->hasPort(ID::D)) { + if (cell->hasPort(TW::D)) { SigSpec d = cell->getPort(TW::D); // The user count was already at least 1 // (for the D port). Bump it as it is now connected @@ -337,7 +337,7 @@ void FfMergeHelper::set(FfInitVals *initvals_, RTLIL::Module *module_) for (auto cell : module->cells()) { if (cell->is_builtin_ff()) { - if (cell->hasPort(ID::D)) { + if (cell->hasPort(TW::D)) { SigSpec d = (*sigmap)(cell->getPort(TW::D)); for (int i = 0; i < GetSize(d); i++) dff_sink[d[i]].insert(std::make_pair(cell, i)); diff --git a/kernel/fmt.cc b/kernel/fmt.cc index 15179a75a..3d74b1da5 100644 --- a/kernel/fmt.cc +++ b/kernel/fmt.cc @@ -31,7 +31,7 @@ void Fmt::append_literal(const std::string &str) { void Fmt::parse_rtlil(const RTLIL::Cell *cell) { std::string fmt = cell->getParam(ID(FORMAT)).decode_string(); - RTLIL::SigSpec args = cell->getPort(ID(ARGS)); + RTLIL::SigSpec args = cell->getPort(TW::ARGS); parts.clear(); FmtPart part; @@ -261,7 +261,7 @@ void Fmt::emit_rtlil(RTLIL::Cell *cell) const { cell->setParam(ID(FORMAT), fmt); cell->setParam(ID(ARGS_WIDTH), args.size()); - cell->setPort(ID(ARGS), args); + cell->setPort(TW::ARGS, args); } static size_t compute_required_decimal_places(size_t size, bool signed_) diff --git a/kernel/functional.cc b/kernel/functional.cc index d04677332..535e98134 100644 --- a/kernel/functional.cc +++ b/kernel/functional.cc @@ -218,15 +218,15 @@ private: y = factory.mux(y, factory.slice(b, a.width() * i, a.width()), factory.slice(s, i, 1)); return y; } - dict handle_fa(Node a, Node b, Node c) { + dict handle_fa(Node a, Node b, Node c) { Node t1 = factory.bitwise_xor(a, b); Node t2 = factory.bitwise_and(a, b); Node t3 = factory.bitwise_and(c, t1); Node y = factory.bitwise_xor(c, t1); Node x = factory.bitwise_or(t2, t3); - return {{ID(X), x}, {ID(Y), y}}; + return {{TW::X, x}, {TW::Y, y}}; } - dict handle_alu(Node a_in, Node b_in, int y_width, bool is_signed, Node ci, Node bi) { + dict handle_alu(Node a_in, Node b_in, int y_width, bool is_signed, Node ci, Node bi) { Node a = factory.extend(a_in, y_width, is_signed); Node b_uninverted = factory.extend(b_in, y_width, is_signed); Node b = factory.mux(b_uninverted, factory.bitwise_not(b_uninverted), bi); @@ -240,13 +240,13 @@ private: Node y = factory.slice(y_extra, 0, y_width); Node carries = factory.bitwise_xor(y_extra, factory.bitwise_xor(a_extra, b_extra)); Node co = factory.slice(carries, 1, y_width); - return {{ID(X), x}, {ID(Y), y}, {ID(CO), co}}; + return {{TW::X, x}, {TW::Y, y}, {TW::CO, co}}; } Node handle_lcu(Node p, Node g, Node ci) { - return handle_alu(g, factory.bitwise_or(p, g), g.width(), false, ci, factory.constant(Const(State::S0, 1))).at(ID(CO)); + return handle_alu(g, factory.bitwise_or(p, g), g.width(), false, ci, factory.constant(Const(State::S0, 1))).at(TW::CO); } public: - std::variant, Node> handle(IdString cellName, IdString cellType, dict parameters, dict inputs) + std::variant, Node> handle(IdString cellName, IdString cellType, dict parameters, dict inputs) { int a_width = parameters.at(ID(A_WIDTH), Const(-1)).as_int(); int b_width = parameters.at(ID(B_WIDTH), Const(-1)).as_int(); @@ -255,8 +255,8 @@ public: bool b_signed = parameters.at(ID(B_SIGNED), Const(0)).as_bool(); if(cellType.in(ID($add), ID($sub), ID($and), ID($or), ID($xor), ID($xnor), ID($mul))){ bool is_signed = a_signed && b_signed; - Node a = factory.extend(inputs.at(ID(A)), y_width, is_signed); - Node b = factory.extend(inputs.at(ID(B)), y_width, is_signed); + Node a = factory.extend(inputs.at(TW::A), y_width, is_signed); + Node b = factory.extend(inputs.at(TW::B), y_width, is_signed); if(cellType == ID($add)) return factory.add(a, b); else if(cellType == ID($sub)) @@ -276,8 +276,8 @@ public: }else if(cellType.in(ID($eq), ID($ne), ID($eqx), ID($nex), ID($le), ID($lt), ID($ge), ID($gt))){ bool is_signed = a_signed && b_signed; int width = max(a_width, b_width); - Node a = factory.extend(inputs.at(ID(A)), width, is_signed); - Node b = factory.extend(inputs.at(ID(B)), width, is_signed); + Node a = factory.extend(inputs.at(TW::A), width, is_signed); + Node b = factory.extend(inputs.at(TW::B), width, is_signed); if(cellType.in(ID($eq), ID($eqx))) return factory.extend(factory.equal(a, b), y_width, false); else if(cellType.in(ID($ne), ID($nex))) @@ -293,48 +293,48 @@ public: else log_abort(); }else if(cellType.in(ID($logic_or), ID($logic_and))){ - Node a = factory.reduce_or(inputs.at(ID(A))); - Node b = factory.reduce_or(inputs.at(ID(B))); + Node a = factory.reduce_or(inputs.at(TW::A)); + Node b = factory.reduce_or(inputs.at(TW::B)); Node y = cellType == ID($logic_and) ? factory.bitwise_and(a, b) : factory.bitwise_or(a, b); return factory.extend(y, y_width, false); }else if(cellType == ID($not)){ - Node a = factory.extend(inputs.at(ID(A)), y_width, a_signed); + Node a = factory.extend(inputs.at(TW::A), y_width, a_signed); return factory.bitwise_not(a); }else if(cellType == ID($pos)){ - return factory.extend(inputs.at(ID(A)), y_width, a_signed); + return factory.extend(inputs.at(TW::A), y_width, a_signed); }else if(cellType == ID($neg)){ - Node a = factory.extend(inputs.at(ID(A)), y_width, a_signed); + Node a = factory.extend(inputs.at(TW::A), y_width, a_signed); return factory.unary_minus(a); }else if(cellType == ID($logic_not)){ - Node a = factory.reduce_or(inputs.at(ID(A))); + Node a = factory.reduce_or(inputs.at(TW::A)); Node y = factory.bitwise_not(a); return factory.extend(y, y_width, false); }else if(cellType.in(ID($reduce_or), ID($reduce_bool))){ - Node a = factory.reduce_or(inputs.at(ID(A))); + Node a = factory.reduce_or(inputs.at(TW::A)); return factory.extend(a, y_width, false); }else if(cellType == ID($reduce_and)){ - Node a = factory.reduce_and(inputs.at(ID(A))); + Node a = factory.reduce_and(inputs.at(TW::A)); return factory.extend(a, y_width, false); }else if(cellType.in(ID($reduce_xor), ID($reduce_xnor))){ - Node a = factory.reduce_xor(inputs.at(ID(A))); + Node a = factory.reduce_xor(inputs.at(TW::A)); Node y = cellType == ID($reduce_xnor) ? factory.bitwise_not(a) : a; return factory.extend(y, y_width, false); }else if(cellType == ID($shl) || cellType == ID($sshl)){ - Node a = factory.extend(inputs.at(ID(A)), y_width, a_signed); - Node b = inputs.at(ID(B)); + Node a = factory.extend(inputs.at(TW::A), y_width, a_signed); + Node b = inputs.at(TW::B); return logical_shift_left(a, b); }else if(cellType == ID($shr) || cellType == ID($sshr)){ int width = max(a_width, y_width); - Node a = factory.extend(inputs.at(ID(A)), width, a_signed); - Node b = inputs.at(ID(B)); + Node a = factory.extend(inputs.at(TW::A), width, a_signed); + Node b = inputs.at(TW::B); Node y = a_signed && cellType == ID($sshr) ? arithmetic_shift_right(a, b) : logical_shift_right(a, b); return factory.extend(y, y_width, a_signed); }else if(cellType == ID($shiftx) || cellType == ID($shift)){ int width = max(a_width, y_width); - Node a = factory.extend(inputs.at(ID(A)), width, cellType == ID($shift) && a_signed); - Node b = inputs.at(ID(B)); + Node a = factory.extend(inputs.at(TW::A), width, cellType == ID($shift) && a_signed); + Node b = inputs.at(TW::B); Node shr = logical_shift_right(a, b); if(b_signed) { Node shl = logical_shift_left(a, factory.unary_minus(b)); @@ -344,22 +344,22 @@ public: return factory.extend(shr, y_width, false); } }else if(cellType == ID($mux)){ - return factory.mux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S))); + return factory.mux(inputs.at(TW::A), inputs.at(TW::B), inputs.at(TW::S)); }else if(cellType == ID($pmux)){ - return handle_pmux(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(S))); + return handle_pmux(inputs.at(TW::A), inputs.at(TW::B), inputs.at(TW::S)); }else if(cellType == ID($concat)){ - Node a = inputs.at(ID(A)); - Node b = inputs.at(ID(B)); + Node a = inputs.at(TW::A); + Node b = inputs.at(TW::B); return factory.concat(a, b); }else if(cellType == ID($slice)){ int offset = parameters.at(ID(OFFSET)).as_int(); - Node a = inputs.at(ID(A)); + Node a = inputs.at(TW::A); return factory.slice(a, offset, y_width); }else if(cellType.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) { int width = max(a_width, b_width); bool is_signed = a_signed && b_signed; - Node a = factory.extend(inputs.at(ID(A)), width, is_signed); - Node b = factory.extend(inputs.at(ID(B)), width, is_signed); + Node a = factory.extend(inputs.at(TW::A), width, is_signed); + Node b = factory.extend(inputs.at(TW::B), width, is_signed); if(is_signed) { if(cellType == ID($div)) { // divide absolute values, then flip the sign if input signs differ @@ -403,44 +403,44 @@ public: return factory.extend(factory.unsigned_div(a, b), y_width, false); } } else if(cellType == ID($pow)) { - return handle_pow(inputs.at(ID(A)), inputs.at(ID(B)), y_width, a_signed && b_signed); + return handle_pow(inputs.at(TW::A), inputs.at(TW::B), y_width, a_signed && b_signed); } else if (cellType == ID($lut)) { int width = parameters.at(ID(WIDTH)).as_int(); Const lut_table = parameters.at(ID(LUT)); lut_table.extu(1 << width); - return handle_bmux(factory.constant(lut_table), inputs.at(ID(A)), 0, 1, width); + return handle_bmux(factory.constant(lut_table), inputs.at(TW::A), 0, 1, width); } else if (cellType == ID($bwmux)) { - Node a = inputs.at(ID(A)); - Node b = inputs.at(ID(B)); - Node s = inputs.at(ID(S)); + Node a = inputs.at(TW::A); + Node b = inputs.at(TW::B); + Node s = inputs.at(TW::S); return factory.bitwise_or( factory.bitwise_and(a, factory.bitwise_not(s)), factory.bitwise_and(b, s)); } else if (cellType == ID($bweqx)) { - Node a = inputs.at(ID(A)); - Node b = inputs.at(ID(B)); + Node a = inputs.at(TW::A); + Node b = inputs.at(TW::B); return factory.bitwise_not(factory.bitwise_xor(a, b)); } else if(cellType == ID($bmux)) { int width = parameters.at(ID(WIDTH)).as_int(); int s_width = parameters.at(ID(S_WIDTH)).as_int(); - return handle_bmux(inputs.at(ID(A)), inputs.at(ID(S)), 0, width, s_width); + return handle_bmux(inputs.at(TW::A), inputs.at(TW::S), 0, width, s_width); } else if(cellType == ID($demux)) { int width = parameters.at(ID(WIDTH)).as_int(); int s_width = parameters.at(ID(S_WIDTH)).as_int(); int y_width = width << s_width; int b_width = ceil_log2(y_width); - Node a = factory.extend(inputs.at(ID(A)), y_width, false); - Node s = factory.extend(inputs.at(ID(S)), b_width, false); + Node a = factory.extend(inputs.at(TW::A), y_width, false); + Node s = factory.extend(inputs.at(TW::S), b_width, false); Node b = factory.mul(s, factory.constant(Const(width, b_width))); return factory.logical_shift_left(a, b); } else if(cellType == ID($fa)) { - return handle_fa(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(C))); + return handle_fa(inputs.at(TW::A), inputs.at(TW::B), inputs.at(TW::C)); } else if(cellType == ID($lcu)) { - return handle_lcu(inputs.at(ID(P)), inputs.at(ID(G)), inputs.at(ID(CI))); + return handle_lcu(inputs.at(TW::P), inputs.at(TW::G), inputs.at(TW::CI)); } else if(cellType == ID($alu)) { - return handle_alu(inputs.at(ID(A)), inputs.at(ID(B)), y_width, a_signed && b_signed, inputs.at(ID(CI)), inputs.at(ID(BI))); + return handle_alu(inputs.at(TW::A), inputs.at(TW::B), y_width, a_signed && b_signed, inputs.at(TW::CI), inputs.at(TW::BI)); } else if(cellType.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) { - Node a = factory.mux(factory.constant(Const(State::S1, 1)), inputs.at(ID(A)), inputs.at(ID(EN))); + Node a = factory.mux(factory.constant(Const(State::S1, 1)), inputs.at(TW::A), inputs.at(TW::EN)); auto &output = factory.add_output(cellName, cellType, Sort(1)); output.set_value(a); return {}; @@ -468,7 +468,7 @@ public: class FunctionalIRConstruction { std::deque> queue; dict graph_nodes; - dict, Node> cell_outputs; + dict, Node> cell_outputs; DriverMap driver_map; Factory& factory; CellSimplifier simplifier; @@ -488,7 +488,7 @@ class FunctionalIRConstruction { }else return it->second; } - Node enqueue_cell(Cell *cell, IdString port_name) + Node enqueue_cell(Cell *cell, TwineRef port_name) { auto it = cell_outputs.find({cell, port_name}); if(it == cell_outputs.end()) { @@ -497,7 +497,7 @@ class FunctionalIRConstruction { for(auto const &[name, sigspec] : cell->connections()) if(driver_map.celltypes.cell_output(cell->type, name)) { auto node = factory.create_pending(sigspec.size()); - factory.suggest_name(node, cell->name.str() + "$" + name.str()); + factory.suggest_name(node, cell->name.str() + "$" + cell->module->design->twines.str(name)); cell_outputs.emplace({cell, name}, node); if(name == port_name) rv = node; @@ -539,7 +539,7 @@ private: Node concatenate_read_results(Mem *mem, vector results) { // sanity check: all read ports concatenated should equal to the RD_DATA port - const SigSpec &rd_data = mem->cell->connections().at(ID(RD_DATA)); + const SigSpec &rd_data = mem->cell->connections().at(TW::RD_DATA); int current = 0; for(size_t i = 0; i < mem->rd_ports.size(); i++) { int width = mem->width << mem->rd_ports[i].wide_log2; @@ -604,7 +604,7 @@ private: "Call memory_collect to avoid this error.\n", log_const(cell->parameters.at(ID(MEMID)))); } Node node = handle_memory(mem); - factory.update_pending(cell_outputs.at({cell, ID(RD_DATA)}), node); + factory.update_pending(cell_outputs.at({cell, TW::RD_DATA}), node); } else if (cell->is_builtin_ff()) { FfData ff(&ff_initvals, cell); if (!ff.has_gclk) @@ -613,12 +613,12 @@ private: auto &state = factory.add_state(ff.name, ID($state), Sort(ff.width)); Node q_value = factory.value(state); factory.suggest_name(q_value, ff.name); - factory.update_pending(cell_outputs.at({cell, ID(Q)}), q_value); + factory.update_pending(cell_outputs.at({cell, TW::Q}), q_value); state.set_next_value(enqueue(ff.sig_d)); state.set_initial_value(ff.val_init); } else { - dict connections; - IdString output_name; // for the single output case + dict connections; + TwineRef output_name; // for the single output case int n_outputs = 0; for(auto const &[name, sigspec] : cell->connections()) { if(driver_map.celltypes.cell_input(cell->type, name) && sigspec.size() > 0) @@ -628,12 +628,12 @@ private: n_outputs++; } } - std::variant, Node> outputs = simplifier.handle(cell->name, cell->type, cell->parameters, connections); + std::variant, Node> outputs = simplifier.handle(cell->name, cell->type, cell->parameters, connections); if(auto *nodep = std::get_if(&outputs); nodep != nullptr) { log_assert(n_outputs == 1); factory.update_pending(cell_outputs.at({cell, output_name}), *nodep); } else { - for(auto [name, node] : std::get>(outputs)) + for(auto [name, node] : std::get>(outputs)) factory.update_pending(cell_outputs.at({cell, name}), node); } } @@ -695,7 +695,8 @@ public: factory.update_pending(pending, node); } else { DriveSpec driver = driver_map(DriveSpec(port_chunk)); - check_undriven(driver, port_chunk.cell->name.unescape() + " port " + port_chunk.port.unescape()); + auto& twines = port_chunk.cell->module->design->twines; + check_undriven(driver, twines.str(port_chunk.cell->meta_->name) + " port " + twines.str(port_chunk.port)); factory.update_pending(pending, enqueue(driver)); } } else { diff --git a/kernel/log.cc b/kernel/log.cc index 272b69589..50638fdf2 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -619,6 +619,39 @@ const char *log_id(const RTLIL::IdString &str) return log_id_cache.back(); } +static const char *log_id_twine(const RTLIL::Design *design, TwineRef name) +{ + std::string unescaped = RTLIL::unescape_id(design->twines.str(name)); + log_id_cache.push_back(strdup(unescaped.c_str())); + return log_id_cache.back(); +} + +const char *log_id(const RTLIL::Module *obj, const char *nullstr) +{ + if (nullstr && obj == nullptr) return nullstr; + return log_id_twine(obj->design, obj->meta_->name); +} +const char *log_id(const RTLIL::Cell *obj, const char *nullstr) +{ + if (nullstr && obj == nullptr) return nullstr; + return log_id_twine(obj->module->design, obj->meta_->name); +} +const char *log_id(const RTLIL::Wire *obj, const char *nullstr) +{ + if (nullstr && obj == nullptr) return nullstr; + return log_id_twine(obj->module->design, obj->meta_->name); +} +const char *log_id(const RTLIL::Memory *obj, const char *nullstr) +{ + if (nullstr && obj == nullptr) return nullstr; + return log_id_twine(obj->module->design, obj->meta_->name); +} +const char *log_id(const RTLIL::Process *obj, const char *nullstr) +{ + if (nullstr && obj == nullptr) return nullstr; + return log_id_twine(obj->module->design, obj->meta_->name); +} + void log_module(RTLIL::Module *module, std::string indent) { std::stringstream buf; diff --git a/kernel/log.h b/kernel/log.h index d132ba1a0..49cee5b1a 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -259,11 +259,11 @@ std::string log_signal(const RTLIL::SigSpec &sig, bool autoint = true); std::string log_const(const RTLIL::Const &value, bool autoint = true); const char *log_id(const RTLIL::IdString &id); -template static inline const char *log_id(T *obj, const char *nullstr = nullptr) { - if (nullstr && obj == nullptr) - return nullstr; - return log_id(obj->name); -} +const char *log_id(const RTLIL::Module *obj, const char *nullstr = nullptr); +const char *log_id(const RTLIL::Cell *obj, const char *nullstr = nullptr); +const char *log_id(const RTLIL::Wire *obj, const char *nullstr = nullptr); +const char *log_id(const RTLIL::Memory *obj, const char *nullstr = nullptr); +const char *log_id(const RTLIL::Process *obj, const char *nullstr = nullptr); void log_module(RTLIL::Module *module, std::string indent = ""); void log_cell(RTLIL::Cell *cell, std::string indent = ""); diff --git a/kernel/mem.cc b/kernel/mem.cc index 2a10b92df..5905de57b 100644 --- a/kernel/mem.cc +++ b/kernel/mem.cc @@ -28,7 +28,7 @@ void Mem::remove() { cell = nullptr; } if (mem) { - module->memories.erase(mem->name); + module->memories.erase(mem->meta_->name); delete mem; mem = nullptr; } @@ -116,14 +116,14 @@ void Mem::emit() { if (packed) { if (mem) { - module->memories.erase(mem->name); + module->memories.erase(mem->meta_->name); delete mem; mem = nullptr; } if (!cell) { if (memid.empty()) memid = NEW_ID; - cell = module->addCell(memid, ID($mem_v2)); + cell = module->addCell(Twine{memid.str()}, ID($mem_v2)); } cell->type = ID($mem_v2); cell->attributes = attributes; @@ -292,10 +292,7 @@ void Mem::emit() { if (!mem) { if (memid.empty()) memid = NEW_ID; - mem = new RTLIL::Memory; - mem->name = memid; - mem->module = module; - module->memories[memid] = mem; + mem = module->addMemory(Twine{memid.str()}); } mem->width = width; mem->start_offset = start_offset; @@ -562,14 +559,14 @@ namespace { }; Mem mem_from_memory(Module *module, RTLIL::Memory *mem, const MemIndex &index) { - Mem res(module, mem->name, mem->width, mem->start_offset, mem->size); + Mem res(module, RTLIL::IdString(module->design->twines.str(mem->meta_->name)), mem->width, mem->start_offset, mem->size); res.packed = false; res.mem = mem; res.attributes = mem->attributes; std::vector rd_transparent; std::vector wr_portid; - if (index.rd_ports.count(mem->name)) { - for (auto cell : index.rd_ports.at(mem->name)) { + if (index.rd_ports.count(RTLIL::IdString(module->design->twines.str(mem->meta_->name)))) { + for (auto cell : index.rd_ports.at(RTLIL::IdString(module->design->twines.str(mem->meta_->name)))) { MemRd mrd; bool is_compat = cell->type == ID($memrd); mrd.cell = cell; @@ -611,9 +608,9 @@ namespace { rd_transparent.push_back(transparent); } } - if (index.wr_ports.count(mem->name)) { + if (index.wr_ports.count(RTLIL::IdString(module->design->twines.str(mem->meta_->name)))) { std::vector> ports; - for (auto cell : index.wr_ports.at(mem->name)) { + for (auto cell : index.wr_ports.at(RTLIL::IdString(module->design->twines.str(mem->meta_->name)))) { MemWr mwr; bool is_compat = cell->type == ID($memwr); mwr.cell = cell; @@ -656,9 +653,9 @@ namespace { } } } - if (index.inits.count(mem->name)) { + if (index.inits.count(RTLIL::IdString(module->design->twines.str(mem->meta_->name)))) { std::vector> inits; - for (auto cell : index.inits.at(mem->name)) { + for (auto cell : index.inits.at(RTLIL::IdString(module->design->twines.str(mem->meta_->name)))) { MemInit init; init.cell = cell; init.attributes = cell->attributes; @@ -933,7 +930,7 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) { if (width) { - SigSpec sig_q = module->addWire(stringf("$%s$rdreg[%d]$q", memid, idx), width); + SigSpec sig_q = module->addWire(Twine{stringf("$%s$rdreg[%d]$q", memid, idx)}, width); SigSpec sig_d; int pos = 0; @@ -943,7 +940,7 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) { port.addr[i] = sig_q[pos++]; } - c = module->addDff(stringf("$%s$rdreg[%d]", memid, idx), port.clk, sig_d, sig_q, port.clk_polarity, mem_src); + c = module->addDff(Twine{stringf("$%s$rdreg[%d]", memid, idx)}, port.clk, sig_d, sig_q, port.clk_polarity, mem_src); } else { c = nullptr; } @@ -952,7 +949,7 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) { { log_assert(port.arst == State::S0 || port.srst == State::S0); - SigSpec async_d = module->addWire(stringf("$%s$rdreg[%d]$d", memid, idx), GetSize(port.data)); + SigSpec async_d = module->addWire(Twine{stringf("$%s$rdreg[%d]$d", memid, idx)}, GetSize(port.data)); SigSpec sig_d = async_d; for (int i = 0; i < GetSize(wr_ports); i++) { @@ -975,7 +972,7 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) { raddr = port.sub_addr(sub); SigSpec addr_eq; if (raddr != waddr) - addr_eq = module->Eq(stringf("$%s$rdtransen[%d][%d][%d]$d", memid, idx, i, sub), raddr, waddr, false, mem_src); + addr_eq = module->Eq(Twine{stringf("$%s$rdtransen[%d][%d][%d]$d", memid, idx, i, sub)}, raddr, waddr, false, mem_src); int pos = 0; int ewidth = width << min_wide_log2; int wsub = wide_write ? sub : 0; @@ -988,10 +985,10 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) { SigSpec other = port.transparency_mask[i] ? wport.data.extract(pos + wsub * width, epos-pos) : Const(State::Sx, epos-pos); SigSpec cond; if (raddr != waddr) - cond = module->And(stringf("$%s$rdtransgate[%d][%d][%d][%d]$d", memid, idx, i, sub, pos), wport.en[pos + wsub * width], addr_eq, false, mem_src); + cond = module->And(Twine{stringf("$%s$rdtransgate[%d][%d][%d][%d]$d", memid, idx, i, sub, pos)}, wport.en[pos + wsub * width], addr_eq, false, mem_src); else cond = wport.en[pos + wsub * width]; - SigSpec merged = module->Mux(stringf("$%s$rdtransmux[%d][%d][%d][%d]$d", memid, idx, i, sub, pos), cur, other, cond, mem_src); + SigSpec merged = module->Mux(Twine{stringf("$%s$rdtransmux[%d][%d][%d][%d]$d", memid, idx, i, sub, pos)}, cur, other, cond, mem_src); sig_d.replace(pos + rsub * width, merged); pos = epos; } @@ -1140,7 +1137,7 @@ void Mem::emulate_priority(int idx1, int idx2, FfInitVals *initvals) addr1 = port1.sub_addr(sub); else addr2 = port2.sub_addr(sub); - SigSpec addr_eq = module->Eq(NEW_ID, addr1, addr2); + SigSpec addr_eq = module->Eq(NEW_TWINE, addr1, addr2); int ewidth = width << min_wide_log2; int sub1 = wide1 ? sub : 0; int sub2 = wide1 ? 0 : sub; @@ -1152,9 +1149,9 @@ void Mem::emulate_priority(int idx1, int idx2, FfInitVals *initvals) if (cache.count(key)) { en1 = cache[key]; } else { - SigBit active2 = module->And(NEW_ID, addr_eq, en2); - SigBit nactive2 = module->Not(NEW_ID, active2); - en1 = cache[key] = module->And(NEW_ID, en1, nactive2); + SigBit active2 = module->And(NEW_TWINE, addr_eq, en2); + SigBit nactive2 = module->Not(NEW_TWINE, active2); + en1 = cache[key] = module->And(NEW_TWINE, en1, nactive2); } } } @@ -1179,7 +1176,7 @@ void Mem::emulate_transparency(int widx, int ridx, FfInitVals *initvals) { // the mux whenever this would be relevant. It does, however, need to have the same // clock enable signal as the read port. SigSpec wdata_q = module->addWire(NEW_TWINE, GetSize(wport.data)); - module->addDffe(NEW_ID, rport.clk, rport.en, wport.data, wdata_q, rport.clk_polarity, true); + module->addDffe(NEW_TWINE, rport.clk, rport.en, wport.data, wdata_q, rport.clk_polarity, true); for (int sub = 0; sub < (1 << max_wide_log2); sub += (1 << min_wide_log2)) { SigSpec raddr = rport.addr; SigSpec waddr = wport.addr; @@ -1190,7 +1187,7 @@ void Mem::emulate_transparency(int widx, int ridx, FfInitVals *initvals) { raddr = rport.sub_addr(sub); SigSpec addr_eq; if (raddr != waddr) - addr_eq = module->Eq(NEW_ID, raddr, waddr); + addr_eq = module->Eq(NEW_TWINE, raddr, waddr); int pos = 0; int ewidth = width << min_wide_log2; int wsub = wide_write ? sub : 0; @@ -1202,7 +1199,7 @@ void Mem::emulate_transparency(int widx, int ridx, FfInitVals *initvals) { epos++; SigSpec cond; if (raddr != waddr) - cond = module->And(NEW_ID, wport.en[pos + wsub * width], addr_eq); + cond = module->And(NEW_TWINE, wport.en[pos + wsub * width], addr_eq); else cond = wport.en[pos + wsub * width]; SigSpec cond_q = module->addWire(NEW_TWINE); @@ -1243,7 +1240,7 @@ void Mem::emulate_transparency(int widx, int ridx, FfInitVals *initvals) { SigSpec cur = rdata_a.extract(pos, epos-pos); SigSpec other = wdata_q.extract(pos + wsub * width, epos-pos); SigSpec dest = rport.data.extract(pos + rsub * width, epos-pos); - module->addMux(NEW_ID, cur, other, cond_q, dest); + module->addMux(NEW_TWINE, cur, other, cond_q, dest); pos = epos; } rport.data.replace(rsub * width, rdata_a); @@ -1389,8 +1386,8 @@ void Mem::widen_wr_port(int idx, int wide_log2) { } else { // May or may not write to this subword. new_data.append(port.data); - SigSpec addr_eq = module->Eq(NEW_ID, addr_lo, cur_addr_lo); - SigSpec en = module->Mux(NEW_ID, Const(State::S0, GetSize(port.data)), port.en, addr_eq); + SigSpec addr_eq = module->Eq(NEW_TWINE, addr_lo, cur_addr_lo); + SigSpec en = module->Mux(NEW_TWINE, Const(State::S0, GetSize(port.data)), port.en, addr_eq); new_en.append(en); } } @@ -1457,7 +1454,7 @@ void Mem::emulate_rden(int idx, FfInitVals *initvals) { } ff_sel.emit(); ff_data.emit(); - module->addMux(NEW_ID, prev_data, new_data, sel, port.data); + module->addMux(NEW_TWINE, prev_data, new_data, sel, port.data); port.data = new_data; port.en = State::S1; } @@ -1506,7 +1503,7 @@ void Mem::emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, Ff } } ff_sel.emit(); - module->addMux(NEW_ID, port.init_value, new_data, sel, port.data); + module->addMux(NEW_TWINE, port.init_value, new_data, sel, port.data); port.data = new_data; port.init_value = Const(State::Sx, GetSize(port.data)); } @@ -1546,7 +1543,7 @@ void Mem::emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, Ff } } ff_sel.emit(); - module->addMux(NEW_ID, port.arst_value, new_data, sel, port.data); + module->addMux(NEW_TWINE, port.arst_value, new_data, sel, port.data); port.data = new_data; port.arst = State::S0; } @@ -1581,7 +1578,7 @@ void Mem::emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, Ff ff_sel.val_arst = State::S1; } ff_sel.emit(); - module->addMux(NEW_ID, port.srst_value, new_data, sel, port.data); + module->addMux(NEW_TWINE, port.srst_value, new_data, sel, port.data); port.data = new_data; port.srst = State::S0; } @@ -1595,7 +1592,7 @@ void Mem::emulate_rd_ce_over_srst(int idx) { return; } port.ce_over_srst = false; - port.srst = module->And(NEW_ID, port.en, port.srst); + port.srst = module->And(NEW_TWINE, port.en, port.srst); } void Mem::emulate_rd_srst_over_ce(int idx) { @@ -1606,7 +1603,7 @@ void Mem::emulate_rd_srst_over_ce(int idx) { return; } port.ce_over_srst = true; - port.en = module->Or(NEW_ID, port.en, port.srst); + port.en = module->Or(NEW_TWINE, port.en, port.srst); } bool Mem::emulate_read_first_ok() { diff --git a/kernel/newcelltypes.h b/kernel/newcelltypes.h index 5d286b978..dd170069c 100644 --- a/kernel/newcelltypes.h +++ b/kernel/newcelltypes.h @@ -590,7 +590,7 @@ struct NewCellTypes { if (wire->port_output) outputs.insert(wire->meta_->name); } - setup_type(module->name, inputs, outputs); + setup_type(RTLIL::IdString(module->design->twines.str(module->meta_->name)), inputs, outputs); } void setup_type(RTLIL::IdString type, const pool &inputs, const pool &outputs, bool is_evaluable = false, bool is_combinatorial = false, bool is_synthesizable = false) { diff --git a/kernel/register.cc b/kernel/register.cc index cba6d5f99..f3d32db12 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -305,8 +305,8 @@ void Pass::call(RTLIL::Design *design, std::vector args) void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command) { - std::string backup_selected_active_module = design->selected_active_module; - design->selected_active_module.clear(); + TwineRef backup_selected_active_module = design->selected_active_module; + design->selected_active_module = Twine::Null; design->push_selection(selection); Pass::call(design, command); @@ -317,8 +317,8 @@ void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &sele void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::vector args) { - std::string backup_selected_active_module = design->selected_active_module; - design->selected_active_module.clear(); + TwineRef backup_selected_active_module = design->selected_active_module; + design->selected_active_module = Twine::Null; design->push_selection(selection); Pass::call(design, args); @@ -329,8 +329,8 @@ void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &sele void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command) { - std::string backup_selected_active_module = design->selected_active_module; - design->selected_active_module = module->name.str(); + TwineRef backup_selected_active_module = design->selected_active_module; + design->selected_active_module = module->meta_->name; design->push_empty_selection(); design->select(module); @@ -342,8 +342,8 @@ void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::str void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vector args) { - std::string backup_selected_active_module = design->selected_active_module; - design->selected_active_module = module->name.str(); + TwineRef backup_selected_active_module = design->selected_active_module; + design->selected_active_module = module->meta_->name; design->push_empty_selection(); design->select(module); @@ -1021,10 +1021,10 @@ struct HelpPass : public Pass { json.name("code"); json.value(ch.code); vector inputs, outputs; for (auto &input : ct.inputs) - inputs.push_back(input.str()); + inputs.push_back(RTLIL::IdString((RTLIL::StaticId)input).str()); json.name("inputs"); json.value(inputs); for (auto &output : ct.outputs) - outputs.push_back(output.str()); + outputs.push_back(RTLIL::IdString((RTLIL::StaticId)output).str()); json.name("outputs"); json.value(outputs); vector properties; // CellType properties diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 71ece2876..5333ee0bb 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -196,9 +196,10 @@ struct IdStringCollector { trace(selection_var.selected_modules); trace(selection_var.selected_members); } - void trace_named(const RTLIL::NamedObject &named) { + void trace_named(const RTLIL::AttrObject &named) { trace_keys(named.attributes); - trace(named.name); + if (named.meta_) + trace(named.meta_->name); } void trace(const RTLIL::Wire &wire) { trace_named(wire); @@ -1548,6 +1549,7 @@ RTLIL::Module *RTLIL::Design::addModule(TwineRef name) RTLIL::Module *module = new RTLIL::Module; modules_[name] = module; module->design = this; + module->meta_ = alloc_obj_meta(); module->meta_->name = name; for (auto mon : monitors) @@ -1938,7 +1940,7 @@ void RTLIL::Module::makeblackbox() void RTLIL::Module::expand_interfaces(RTLIL::Design *, const dict &) { - log_error("Class doesn't support expand_interfaces (module: `%s')!\n", name.unescape()); + log_error("Class doesn't support expand_interfaces (module: `%s')!\n", design->twines.str(meta_->name).c_str()); } bool RTLIL::Module::reprocess_if_necessary(RTLIL::Design *) @@ -1950,7 +1952,7 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dicttwines.str(meta_->name).c_str()); } @@ -1958,13 +1960,12 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dicttwines.str(meta_->name).c_str()); } size_t RTLIL::Module::count_id(TwineRef id) { - IdString sid(design->twines.str(id)); - return wires_.count(id) + cells_.count(id) + memories.count(sid) + processes.count(sid); + return wires_.count(id) + cells_.count(id) + memories.count(id) + processes.count(id); } #ifndef NDEBUG @@ -1983,9 +1984,11 @@ namespace { std::stringstream buf; RTLIL_BACKEND::dump_cell(buf, " ", cell); + std::string mod_name = module ? module->design->twines.str(module->meta_->name) : std::string(); + std::string cell_name = cell->module->design->twines.str(cell->meta_->name); log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s", - module ? module->name.c_str() : "", module ? "." : "", - cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str()); + mod_name.c_str(), module ? "." : "", + cell_name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str()); } int param(IdString name) @@ -2951,8 +2954,8 @@ void RTLIL::Module::sort() wires_.sort(sort_twine_by_str); cells_.sort(sort_twine_by_str); parameter_default_values.sort(sort_by_id_str()); - memories.sort(sort_by_id_str()); - processes.sort(sort_by_id_str()); + memories.sort(sort_twine_by_str); + processes.sort(sort_twine_by_str); for (auto &it : cells_) it.second->sort(); for (auto &it : wires_) @@ -2969,13 +2972,13 @@ void check_module(RTLIL::Module *module, ParallelDispatchThreadPool &thread_pool pool memory_strings; for (auto &it : module->memories) { - log_assert(it.first == it.second->name); - log_assert(!it.first.empty()); + log_assert(it.second->meta_ && it.first == it.second->meta_->name); + log_assert(it.first != Twine::Null); log_assert(it.second->width >= 0); log_assert(it.second->size >= 0); for (auto &it2 : it.second->attributes) log_assert(!it2.first.empty()); - memory_strings.insert(it.second->name.str()); + memory_strings.insert(module->design->twines.str(it.second->meta_->name)); } std::vector ports_declared(GetSize(module->ports)); @@ -3047,8 +3050,8 @@ void check_module(RTLIL::Module *module, ParallelDispatchThreadPool &thread_pool log_assert(memids_pool.insert(memid).second); for (auto &it : module->processes) { - log_assert(it.first == it.second->name); - log_assert(!it.first.empty()); + log_assert(it.second->meta_ && it.first == it.second->meta_->name); + log_assert(it.first != Twine::Null); log_assert(it.second->root_case.compare.empty()); std::vector all_cases = {&it.second->root_case}; for (size_t i = 0; i < all_cases.size(); i++) { @@ -3172,7 +3175,8 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod, bool src_id_verbatim) cons } for (auto it = memories.rbegin(); it != memories.rend(); ++it) { const RTLIL::Memory *o = it->second; - RTLIL::Memory *m = new_mod->addMemory(it->first); + TwineRef dst_name = new_mod->design->twines.copy_from(design->twines, it->first); + RTLIL::Memory *m = new_mod->addMemory(dst_name); m->width = o->width; m->start_offset = o->start_offset; m->size = o->size; @@ -3190,8 +3194,11 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod, bool src_id_verbatim) cons } for (auto it = processes.rbegin(); it != processes.rend(); ++it) { const RTLIL::Process *o = it->second; + TwineRef dst_name = new_mod->design->twines.copy_from(design->twines, it->first); RTLIL::Process *p = o->clone(); - p->name = it->first; + if (!p->meta_) + p->meta_ = new_mod->design->alloc_obj_meta(); + p->meta_->name = dst_name; new_mod->add(p); copy_meta(o, p); std::vector> case_stack; @@ -3236,16 +3243,20 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod, bool src_id_verbatim) cons new_mod->addWire(dst_id, it->second); } - for (auto it = memories.rbegin(); it != memories.rend(); ++it) - new_mod->addMemory(it->first, it->second); + for (auto it = memories.rbegin(); it != memories.rend(); ++it) { + TwineRef dst_id = new_mod->design->twines.copy_from(design->twines, it->first); + new_mod->addMemory(dst_id, it->second); + } for (auto it = cells_.rbegin(); it != cells_.rend(); ++it) { TwineRef dst_id = new_mod->design->twines.copy_from(design->twines, it->first); new_mod->addCell(dst_id, it->second); } - for (auto it = processes.rbegin(); it != processes.rend(); ++it) - new_mod->addProcess(it->first, it->second); + for (auto it = processes.rbegin(); it != processes.rend(); ++it) { + TwineRef dst_id = new_mod->design->twines.copy_from(design->twines, it->first); + new_mod->addProcess(dst_id, it->second); + } } struct RewriteSigSpecWorker @@ -3272,7 +3283,8 @@ RTLIL::Module *RTLIL::Module::clone() const { RTLIL::Module *new_mod = new RTLIL::Module; new_mod->design = design; - new_mod->name = name; + new_mod->meta_ = design->alloc_obj_meta(); + new_mod->meta_->name = meta_->name; cloneInto(new_mod); return new_mod; } @@ -3281,7 +3293,8 @@ RTLIL::Module *RTLIL::Module::clone(RTLIL::Design *dst, bool src_id_verbatim) co { RTLIL::Module *new_mod = new RTLIL::Module; new_mod->design = dst; - new_mod->name = name; + new_mod->meta_ = dst->alloc_obj_meta(); + new_mod->meta_->name = dst->twines.copy_from(design->twines, meta_->name); cloneInto(new_mod, src_id_verbatim); dst->add(new_mod); return new_mod; @@ -3291,7 +3304,8 @@ RTLIL::Module *RTLIL::Module::clone(RTLIL::Design *dst, RTLIL::IdString target_n { RTLIL::Module *new_mod = new RTLIL::Module; new_mod->design = dst; - new_mod->name = target_name; + new_mod->meta_ = dst->alloc_obj_meta(); + new_mod->meta_->name = dst->twines.add(Twine{target_name.str()}); cloneInto(new_mod, src_id_verbatim); dst->add(new_mod); return new_mod; @@ -3371,9 +3385,9 @@ std::vector RTLIL::Module::selected_processes() const return result; } -std::vector RTLIL::Module::selected_members() const +std::vector RTLIL::Module::selected_members() const { - std::vector result; + std::vector result; auto cells = selected_cells(); auto memories = selected_memories(); auto wires = selected_wires(); @@ -3407,9 +3421,9 @@ void RTLIL::Module::add(RTLIL::Cell *cell) void RTLIL::Module::add(RTLIL::Process *process) { - log_assert(!process->name.empty()); - log_assert(count_id(design->twines.lookup(process->name.str())) == 0); - processes[process->name] = process; + log_assert(process->meta_ && process->meta_->name != Twine::Null); + log_assert(count_id(process->meta_->name) == 0); + processes[process->meta_->name] = process; process->module = this; // Propagate module back-pointer to every CaseRule/SwitchRule in the // root case tree and every MemWriteAction in the sync rules — so the @@ -3476,15 +3490,15 @@ void RTLIL::Module::remove(const pool &wires) void RTLIL::Module::remove(RTLIL::Memory *memory) { - log_assert(memories.count(memory->name) != 0); - memories.erase(memory->name); + log_assert(memory->meta_ && memories.count(memory->meta_->name) != 0); + memories.erase(memory->meta_->name); delete memory; } void RTLIL::Module::remove(RTLIL::Process *process) { - log_assert(processes.count(process->name) != 0); - processes.erase(process->name); + log_assert(process->meta_ && processes.count(process->meta_->name) != 0); + processes.erase(process->meta_->name); delete process; } @@ -3729,20 +3743,30 @@ RTLIL::Cell *RTLIL::Module::addCell(Twine &&name, const RTLIL::Cell *other) return addCell(design->twines.add(std::move(name)), other); } -RTLIL::Memory *RTLIL::Module::addMemory(IdString name) +RTLIL::Memory *RTLIL::Module::addMemory(TwineRef name) { + log_assert(design); RTLIL::Memory *mem = new RTLIL::Memory; - mem->name = std::move(name); mem->module = this; - memories[mem->name] = mem; + mem->meta_ = design->alloc_obj_meta(); + mem->meta_->name = name; + memories[name] = mem; return mem; } -RTLIL::Memory *RTLIL::Module::addMemory(IdString name, const RTLIL::Memory *other) +RTLIL::Memory *RTLIL::Module::addMemory(Twine &&name) { + log_assert(design); + return addMemory(design->twines.add(std::move(name))); +} + +RTLIL::Memory *RTLIL::Module::addMemory(TwineRef name, const RTLIL::Memory *other) +{ + log_assert(design); RTLIL::Memory *mem = new RTLIL::Memory; - mem->name = std::move(name); mem->module = this; + mem->meta_ = design->alloc_obj_meta(); + mem->meta_->name = name; mem->width = other->width; mem->start_offset = other->start_offset; mem->size = other->size; @@ -3753,18 +3777,26 @@ RTLIL::Memory *RTLIL::Module::addMemory(IdString name, const RTLIL::Memory *othe // common case. (void)other; } - memories[mem->name] = mem; + memories[name] = mem; return mem; } -RTLIL::Process *RTLIL::Module::addProcess(IdString name) +RTLIL::Process *RTLIL::Module::addProcess(TwineRef name) { + log_assert(design); RTLIL::Process *proc = new RTLIL::Process; - proc->name = std::move(name); + proc->meta_ = design->alloc_obj_meta(); + proc->meta_->name = name; add(proc); return proc; } +RTLIL::Process *RTLIL::Module::addProcess(Twine &&name) +{ + log_assert(design); + return addProcess(design->twines.add(std::move(name))); +} + namespace { // Walk two process trees in parallel and transfer src across the // design boundary for every AttrObject (CaseRule, SwitchRule, @@ -3806,10 +3838,13 @@ namespace { } } -RTLIL::Process *RTLIL::Module::addProcess(IdString name, const RTLIL::Process *other) +RTLIL::Process *RTLIL::Module::addProcess(TwineRef name, const RTLIL::Process *other) { + log_assert(design); RTLIL::Process *proc = other->clone(); - proc->name = std::move(name); + if (!proc->meta_) + proc->meta_ = design->alloc_obj_meta(); + proc->meta_->name = name; add(proc); // Migrate src across the design boundary for the inner-process tree. // Process::clone drops src on CaseRule/SwitchRule/MemWriteAction since @@ -6747,7 +6782,6 @@ RTLIL::Process *RTLIL::Process::clone() const { RTLIL::Process *new_proc = new RTLIL::Process; - new_proc->name = name; new_proc->attributes = attributes; // clone() drops src across the whole tree; the caller is responsible // for migrating src via context after the clone has a module. diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 53bb54bac..b8008e8ea 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1951,8 +1951,8 @@ struct RTLIL::Selection // add member of module to this selection template void select(T1 *module, T2 *member) { - if (!selects_all() && selected_modules.count(module->name) == 0) { - selected_members[module->name].insert(member->name); + if (!selects_all() && selected_modules.count(module->meta_->name) == 0) { + selected_members[module->meta_->name].insert(member->meta_->name); if (module->get_blackbox_attribute()) selects_boxes = true; } @@ -2921,13 +2921,13 @@ struct RTLIL::ModuleNameMasq { bool operator!=(const ModuleNameMasq &rhs) const { return RTLIL::IdString(*this) != RTLIL::IdString(rhs); } }; -struct RTLIL::Module : public RTLIL::NamedObject, public CellAdderMixin +struct RTLIL::Module : public RTLIL::AttrObject, public CellAdderMixin { friend struct RTLIL::SigNormIndex; friend struct RTLIL::Cell; friend struct RTLIL::Design; - // [[no_unique_address]] RTLIL::ModuleNameMasq name; + [[no_unique_address]] RTLIL::ModuleNameMasq name; Hasher::hash_t hashidx_; [[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; } @@ -2952,8 +2952,8 @@ public: idict avail_parameters; dict parameter_default_values; - dict memories; - dict processes; + dict memories; + dict processes; // Context-aware src helpers. Resolve Design via this->design and // route to the per-Design meta vector; assert the module is attached. @@ -3053,7 +3053,7 @@ public: std::vector selected_cells() const; std::vector selected_memories() const; std::vector selected_processes() const; - std::vector selected_members() const; + std::vector selected_members() const; template bool selected(T *member) const { return design->selected_member(meta_->name, member->meta_->name); @@ -3122,11 +3122,13 @@ public: return design->twines.add(Twine{Twine::Suffix{pref, std::to_string(autoidx++)}}); } - RTLIL::Memory *addMemory(RTLIL::IdString name); - RTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other); + RTLIL::Memory *addMemory(TwineRef name); + RTLIL::Memory *addMemory(Twine &&name); + RTLIL::Memory *addMemory(TwineRef name, const RTLIL::Memory *other); - RTLIL::Process *addProcess(RTLIL::IdString name); - RTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other); + RTLIL::Process *addProcess(TwineRef name); + RTLIL::Process *addProcess(Twine &&name); + RTLIL::Process *addProcess(TwineRef name, const RTLIL::Process *other); // The add* methods create a cell and return the created cell. All signals must exist in advance. @@ -3298,18 +3300,6 @@ inline RTLIL::CellNameMasq::operator RTLIL::IdString() const { return RTLIL::IdString(c->module->design->twines.flat_string(id)); } -inline RTLIL::ModuleNameMasq::operator RTLIL::IdString() const { - const RTLIL::Module *m = reinterpret_cast( - reinterpret_cast(this) - offsetof(RTLIL::Module, name)); - return m->design ? m->design->obj_name(m) : std::string(); -} - -inline RTLIL::ModuleNameMasq::operator TwineRef() const { - const RTLIL::Module *m = reinterpret_cast( - reinterpret_cast(this) - offsetof(RTLIL::Module, name)); - return m->design ? m->design->obj_src_id(m) : Twine::Null; -} - // inline RTLIL::ModuleNameMasq& RTLIL::ModuleNameMasq::operator=(RTLIL::IdString id) { // RTLIL::Module *m = reinterpret_cast( // reinterpret_cast(this) - offsetof(RTLIL::Module, name)); diff --git a/kernel/rtlil_bufnorm.cc b/kernel/rtlil_bufnorm.cc index 93176e244..d448a746e 100644 --- a/kernel/rtlil_bufnorm.cc +++ b/kernel/rtlil_bufnorm.cc @@ -1283,7 +1283,7 @@ void RTLIL::Cell::setPort(TwineRef portname, RTLIL::SigSpec signal) } if (yosys_xtrace) { - log("#X# Connect %s.%s.%s = %s (%d)\n", module ? module->name.unescape() : "PATCH", this, module->design->twines.str(portname), log_signal(signal), GetSize(signal)); + log("#X# Connect %s.%s.%s = %s (%d)\n", module ? log_id(module) : "PATCH", this, module->design->twines.str(portname).c_str(), log_signal(signal), GetSize(signal)); log_backtrace("-X- ", yosys_xtrace-1); } diff --git a/kernel/tclapi.cc b/kernel/tclapi.cc index ce25d10d1..e711c07b7 100644 --- a/kernel/tclapi.cc +++ b/kernel/tclapi.cc @@ -270,11 +270,11 @@ static int tcl_get_attr(ClientData, Tcl_Interp *interp, int argc, const char *ar auto obj_twine = search.find(obj_id); obj = mod->wire(obj_twine); if (!obj) - obj = mod->memories.at(obj_id, nullptr); + obj = mod->memories.at(obj_twine, nullptr); if (!obj) obj = mod->cell(obj_twine); if (!obj) - obj = mod->processes.at(obj_id, nullptr); + obj = mod->processes.at(obj_twine, nullptr); } if (!obj) @@ -335,11 +335,11 @@ static int tcl_has_attr(ClientData, Tcl_Interp *interp, int argc, const char *ar auto obj_twine = search.find(obj_id); obj = mod->wire(obj_twine); if (!obj) - obj = mod->memories.at(obj_id, nullptr); + obj = mod->memories.at(obj_twine, nullptr); if (!obj) obj = mod->cell(obj_twine); if (!obj) - obj = mod->processes.at(obj_id, nullptr); + obj = mod->processes.at(obj_twine, nullptr); } if (!obj) @@ -390,11 +390,11 @@ static int tcl_set_attr(ClientData, Tcl_Interp *interp, int objc, Tcl_Obj *const auto obj_twine = search.find(obj_id); obj = mod->wire(obj_twine); if (!obj) - obj = mod->memories.at(obj_id, nullptr); + obj = mod->memories.at(obj_twine, nullptr); if (!obj) obj = mod->cell(obj_twine); if (!obj) - obj = mod->processes.at(obj_id, nullptr); + obj = mod->processes.at(obj_twine, nullptr); } if (!obj) diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h index 1d8841832..845e9a1f2 100644 --- a/kernel/timinginfo.h +++ b/kernel/timinginfo.h @@ -37,9 +37,10 @@ struct TimingInfo bool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; } bool operator!=(const NameBit& nb) const { return !operator==(nb); } std::optional get_connection(RTLIL::Cell *cell) { - if (!cell->hasPort(name)) + TwineRef port_name = cell->module->design->twines.lookup(name.str()); + if (!cell->hasPort(port_name)) return {}; - auto &port = cell->getPort(name); + auto &port = cell->getPort(port_name); if (offset >= port.size()) return {}; return port[offset]; @@ -92,7 +93,7 @@ struct TimingInfo const ModuleTiming& setup_module(RTLIL::Module *module) { - auto r = data.insert(module->name); + auto r = data.insert(RTLIL::IdString(module->design->twines.str(module->meta_->name))); log_assert(r.second); auto &t = r.first->second; diff --git a/kernel/wallace_tree.h b/kernel/wallace_tree.h index 7da7ed04a..49c8b8ba7 100644 --- a/kernel/wallace_tree.h +++ b/kernel/wallace_tree.h @@ -24,7 +24,7 @@ inline std::pair emit_fa(Module *module, SigSpec a, SigSpec b, SigSpec sum = module->addWire(NEW_TWINE, width); SigSpec cout = module->addWire(NEW_TWINE, width); - module->addFa(NEW_ID, a, b, c, cout, sum); + module->addFa(NEW_TWINE, a, b, c, cout, sum); SigSpec carry; carry.append(State::S0); diff --git a/kernel/yosys.cc b/kernel/yosys.cc index b608a482b..4b9dce1e9 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -240,7 +240,7 @@ void yosys_setup() already_shutdown = false; IdString::ensure_prepopulated(); - Twine::ensure_prepopulated(); + twine_prepopulate(); #ifdef YOSYS_ENABLE_PYTHON // Starting Python 3.12, calling PyImport_AppendInittab on an already @@ -364,13 +364,13 @@ const char *create_prompt(RTLIL::Design *design, int recursion_counter) if (recursion_counter > 1) str += stringf("(%d) ", recursion_counter); str += "yosys"; - if (!design->selected_active_module.empty()) - str += stringf(" [%s]", RTLIL::unescape_id(design->selected_active_module)); + if (design->selected_active_module != Twine::Null) + str += stringf(" [%s]", RTLIL::unescape_id(design->twines.str(design->selected_active_module)).c_str()); if (!design->full_selection()) { - if (design->selected_active_module.empty()) + if (design->selected_active_module == Twine::Null) str += "*"; else if (design->selection().selected_modules.size() != 1 || design->selection().selected_members.size() != 0 || - design->selection().selected_modules.count(design->twines.intern(design->selected_active_module)) == 0) + design->selection().selected_modules.count(design->selected_active_module) == 0) str += "*"; } snprintf(buffer, 100, "%s> ", str.c_str()); @@ -951,11 +951,13 @@ static char *readline_obj_generator(const char *text, int state) RTLIL::Design *design = yosys_get_design(); int len = strlen(text); - if (design->selected_active_module.empty()) + if (design->selected_active_module == Twine::Null) { - for (auto mod : design->modules()) - if (mod->name.unescape().compare(0, len, text) == 0) - obj_names.push_back(strdup(mod->name.unescape().c_str())); + for (auto mod : design->modules()) { + std::string mod_name = design->twines.str(mod->meta_->name); + if (mod_name.compare(0, len, text) == 0) + obj_names.push_back(strdup(mod_name.c_str())); + } } else if (design->module(design->selected_active_module) != nullptr) { @@ -965,17 +967,21 @@ static char *readline_obj_generator(const char *text, int state) if (w->name.unescape().compare(0, len, text) == 0) obj_names.push_back(strdup(w->name.unescape().c_str())); - for (auto &it : module->memories) - if (it.first.unescape().compare(0, len, text) == 0) - obj_names.push_back(strdup(it.first.unescape().c_str())); + for (auto &it : module->memories) { + std::string mem_name = design->twines.str(it.first); + if (mem_name.compare(0, len, text) == 0) + obj_names.push_back(strdup(mem_name.c_str())); + } for (auto cell : module->cells()) - if (cell->name.unescape().compare(0, len, text) == 0) - obj_names.push_back(strdup(cell->name.unescape().c_str())); + if (cell->module->design->twines.str(cell->meta_->name).compare(0, len, text) == 0) + obj_names.push_back(strdup(cell->module->design->twines.str(cell->meta_->name).c_str())); - for (auto &it : module->processes) - if (it.first.unescape().compare(0, len, text) == 0) - obj_names.push_back(strdup(it.first.unescape().c_str())); + for (auto &it : module->processes) { + std::string proc_name = design->twines.str(it.first); + if (proc_name.compare(0, len, text) == 0) + obj_names.push_back(strdup(proc_name.c_str())); + } } std::sort(obj_names.begin(), obj_names.end()); diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index f40f19a72..587963095 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -29,7 +29,6 @@ OBJS += passes/cmds/tee.o OBJS += passes/cmds/write_file.o OBJS += passes/cmds/connwrappers.o OBJS += passes/cmds/trace.o -OBJS += passes/cmds/dump_twines.o OBJS += passes/cmds/plugin.o OBJS += passes/cmds/check.o OBJS += passes/cmds/edgetypes.o diff --git a/passes/cmds/abstract.cc b/passes/cmds/abstract.cc index 0016302b3..e344385e1 100644 --- a/passes/cmds/abstract.cc +++ b/passes/cmds/abstract.cc @@ -82,7 +82,7 @@ struct Slice { }; void emit_mux_anyseq(Module* mod, const SigSpec& mux_input, const SigSpec& mux_output, EnableLogic enable) { - auto anyseq = mod->Anyseq(NEW_ID, mux_input.size()); + auto anyseq = mod->Anyseq(mod->design->twines.add(NEW_TWINE), mux_input.size()); if (enable.bit == (enable.pol ? State::S1 : State::S0)) { mod->connect(mux_output, anyseq); } @@ -94,7 +94,7 @@ void emit_mux_anyseq(Module* mod, const SigSpec& mux_input, const SigSpec& mux_o mux_a = anyseq; mux_b = mux_input; } - (void)mod->addMux(NEW_ID, + (void)mod->addMux(NEW_TWINE, mux_a, mux_b, enable.bit, @@ -212,7 +212,7 @@ unsigned int abstract_state(Module* mod, EnableLogic enable, const std::vector offsets, IdString port_name, EnableLogic enable) { +bool abstract_value_cell_port(Module* mod, Cell* cell, std::set offsets, TwineRef port_name, EnableLogic enable) { Wire* to_abstract = mod->addWire(NEW_TWINE, offsets.size()); SigSpec mux_input; SigSpec mux_output; @@ -273,7 +273,7 @@ unsigned int abstract_value(Module* mod, EnableLogic enable, const std::vectormodule->design->twines.str(conn.first).c_str(), i, mod); explain_selections(selected_reps.at(sigmap(conn.second[i]))); offsets_to_abstract.insert(i); } @@ -496,19 +496,19 @@ struct AbstractPass : public Pass { } break; case Enable::ActiveLow: case Enable::ActiveHigh: { - Wire *enable_wire = mod->wire("\\" + enable_name); + Wire *enable_wire = mod->wire(mod->design->twines.lookup("\\" + enable_name)); if (!enable_wire) - log_cmd_error("Enable wire %s not found in module %s\n", enable_name, mod->name); + log_cmd_error("Enable wire %s not found in module %s\n", enable_name, log_id(mod)); if (GetSize(enable_wire) != 1) log_cmd_error("Enable wire %s must have width 1 but has width %d in module %s\n", - enable_name.c_str(), GetSize(enable_wire), mod->name.c_str()); + enable_name.c_str(), GetSize(enable_wire), log_id(mod)); enable_logic = { enable_wire, enable == Enable::ActiveHigh }; } break; case Enable::Initstates: { - SigBit in_init_states = mod->Initstate(NEW_ID); + SigBit in_init_states = mod->Initstate(mod->design->twines.add(NEW_TWINE)); for (int i = 1; i < initstates; i++) { Wire *in_init_states_q = mod->addWire(NEW_TWINE); - mod->addFf(NEW_ID, in_init_states, in_init_states_q); + mod->addFf(NEW_TWINE, in_init_states, in_init_states_q); in_init_states_q->attributes[ID::init] = State::S1; in_init_states = in_init_states_q; } diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 8e5165cf8..864156b1c 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -34,7 +34,8 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const { std::string escaped_name = RTLIL::escape_id(name); std::string escaped_enable_name = (enable_name != "") ? RTLIL::escape_id(enable_name) : ""; - RTLIL::Wire *wire = module->wire(escaped_name); + RTLIL::Design *design = module->design; + RTLIL::Wire *wire = module->wire(design->twines.lookup(escaped_name)); log_assert(is_formal_celltype(celltype)); if (wire == nullptr) { @@ -45,15 +46,15 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const formal_cell->setPort(TW::A, wire); if(enable_name == "") { formal_cell->setPort(TW::EN, State::S1); - log("Added $%s cell for wire \"%s.%s\"\n", celltype, module->name.str(), name); + log("Added $%s cell for wire \"%s.%s\"\n", celltype, log_id(module), name); } else { - RTLIL::Wire *enable_wire = module->wire(escaped_enable_name); + RTLIL::Wire *enable_wire = module->wire(design->twines.lookup(escaped_enable_name)); if(enable_wire == nullptr) log_error("Could not find enable wire with name \"%s\".\n", enable_name); formal_cell->setPort(TW::EN, enable_wire); - log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype, module->name.str(), name, module->name.str(), enable_name); + log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype, log_id(module), name, log_id(module), enable_name); } } } @@ -62,10 +63,11 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n { RTLIL::Wire *wire = nullptr; name = RTLIL::escape_id(name); + TwineRef name_ref = design->twines.lookup(name); - if (module->count_id(name) != 0) + if (name_ref != Twine::Null) { - wire = module->wire(name); + wire = module->wire(name_ref); if (wire != nullptr && wire->width != width) wire = nullptr; @@ -77,13 +79,13 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n wire = nullptr; if (wire == nullptr) - log_cmd_error("Found incompatible object with same name in module %s!\n", module->name); + log_cmd_error("Found incompatible object with same name in module %s!\n", log_id(module)); - log("Module %s already has such an object.\n", module->name); + log("Module %s already has such an object.\n", log_id(module)); } else { - wire = module->addWire(name, width); + wire = module->addWire(Twine{name}, width); wire->port_input = flag_input; wire->port_output = flag_output; @@ -91,7 +93,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n module->fixup_ports(); } - log("Added wire %s to module %s.\n", name, module->name); + log("Added wire %s to module %s.\n", name, log_id(module)); } if (!flag_global) @@ -106,11 +108,11 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n continue; if (mod->get_blackbox_attribute()) continue; - if (cell->hasPort(name)) + if (cell->hasPort(design->twines.add(Twine{name}))) continue; - cell->setPort(name, wire); - log("Added connection %s to cell %s.%s (%s).\n", name, module->name, cell->name, cell->type); + cell->setPort(design->twines.add(Twine{name}), wire); + log("Added connection %s to cell %s.%s (%s).\n", name, log_id(module), log_id(cell), cell->type); } } @@ -200,7 +202,7 @@ struct AddPass : public Pass { if (mod_mode) { for (; argidx < args.size(); argidx++) - design->addModule(RTLIL::escape_id(args[argidx])); + design->addModule(design->twines.add(Twine{RTLIL::escape_id(args[argidx])})); return; } @@ -210,7 +212,7 @@ struct AddPass : public Pass { for (auto module : design->modules()) { log_assert(module != nullptr); - if (!design->selected_whole_module(module->name)) + if (!design->selected_whole_module(module->meta_->name)) continue; if (module->get_bool_attribute(ID::blackbox)) continue; diff --git a/passes/cmds/autoname.cc b/passes/cmds/autoname.cc index 6994fdefd..02dbe3df4 100644 --- a/passes/cmds/autoname.cc +++ b/passes/cmds/autoname.cc @@ -48,7 +48,7 @@ int autoname_worker(Module *module, const dict& wire_score) for (auto bit : conn.second) if (bit.wire != nullptr && bit.wire->name[0] != '$') { if (suffix.empty()) - suffix = stringf("_%s_%s", cell->type.unescape(), conn.first.unescape()); + suffix = stringf("_%s_%s", cell->type.unescape(), module->design->twines.str(conn.first).c_str()); name_proposal proposed_name( bit.wire->name.str() + suffix, cell->output(conn.first) ? 0 : wire_score.at(bit.wire) @@ -66,7 +66,7 @@ int autoname_worker(Module *module, const dict& wire_score) for (auto bit : conn.second) if (bit.wire != nullptr && bit.wire->name[0] == '$' && !bit.wire->port_id) { if (suffix.empty()) - suffix = stringf("_%s", conn.first.unescape()); + suffix = stringf("_%s", module->design->twines.str(conn.first).c_str()); name_proposal proposed_name( cell->name.str() + suffix, cell->output(conn.first) ? 0 : wire_score.at(bit.wire) @@ -89,8 +89,8 @@ int autoname_worker(Module *module, const dict& wire_score) for (auto &it : proposed_cell_names) { if (best_name < it.second) continue; - IdString n = module->uniquify(IdString(it.second.name)); - log_debug("Rename cell %s in %s to %s.\n", it.first, module, n.unescape()); + TwineRef n = module->uniquify(module->design->twines.add(Twine{it.second.name})); + log_debug("Rename cell %s in %s to %s.\n", it.first, module, module->design->twines.str(n).c_str()); module->rename(it.first, n); count++; } @@ -98,8 +98,8 @@ int autoname_worker(Module *module, const dict& wire_score) for (auto &it : proposed_wire_names) { if (best_name < it.second) continue; - IdString n = module->uniquify(IdString(it.second.name)); - log_debug("Rename wire %s in %s to %s.\n", it.first, module, n.unescape()); + TwineRef n = module->uniquify(module->design->twines.add(Twine{it.second.name})); + log_debug("Rename wire %s in %s to %s.\n", it.first, module, module->design->twines.str(n).c_str()); module->rename(it.first, n); count++; } diff --git a/passes/cmds/box_derive.cc b/passes/cmds/box_derive.cc index 0a68113fd..8c3bf2a0f 100644 --- a/passes/cmds/box_derive.cc +++ b/passes/cmds/box_derive.cc @@ -94,7 +94,7 @@ struct BoxDerivePass : Pass { if (base_override) base = base_override; - auto index = std::make_pair(RTLIL::IdString(base->name), cell->parameters); + auto index = std::make_pair(RTLIL::IdString(base->design->twines.str(base->meta_->name)), cell->parameters); if (cell->parameters.empty()) continue; @@ -111,14 +111,14 @@ struct BoxDerivePass : Pass { log_error("Derived module %s cannot be renamed to private name %s.\n", derived, new_name.unescape()); derived->attributes.erase(naming_attr); - d->rename(derived, new_name); + d->rename(derived, d->twines.add(Twine{new_name.str()})); } done[index] = derived; } if (apply_mode) - cell->type = done[index]->name; + cell->type = RTLIL::IdString(done[index]->design->twines.str(done[index]->meta_->name)); } } } diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc index 085c15940..fc775bcd5 100644 --- a/passes/cmds/bugpoint.cc +++ b/passes/cmds/bugpoint.cc @@ -296,7 +296,7 @@ struct BugpointPass : public Pass { if (index++ == seed) { - log_header(design, "Trying to remove cell port %s.%s.%s.\n", mod, cell, it.first.unescape()); + log_header(design, "Trying to remove cell port %s.%s.%s.\n", mod, cell, design->twines.str(it.first).c_str()); RTLIL::SigSpec port_x(State::Sx, port.size()); cell->unsetPort(it.first); cell->setPort(it.first, port_x); @@ -305,7 +305,7 @@ struct BugpointPass : public Pass { if (!stage2 && (cell->input(it.first) || cell->output(it.first)) && index++ == seed) { - log_header(design, "Trying to expose cell port %s.%s.%s as module port.\n", mod, cell, it.first.unescape()); + log_header(design, "Trying to expose cell port %s.%s.%s as module port.\n", mod, cell, design->twines.str(it.first).c_str()); RTLIL::Wire *wire = mod->addWire(NEW_TWINE, port.size()); wire->set_bool_attribute(ID($bugpoint)); wire->port_input = cell->input(it.first); @@ -334,7 +334,7 @@ struct BugpointPass : public Pass { if (index++ == seed) { - log_header(design, "Trying to remove process %s.%s.\n", mod, process.first.unescape()); + log_header(design, "Trying to remove process %s.%s.\n", mod, design->twines.str(process.first).c_str()); removed_process = process.second; break; } @@ -363,7 +363,7 @@ struct BugpointPass : public Pass { { if (index++ == seed) { - log_header(design, "Trying to remove assign %s %s in %s.%s.\n", log_signal(it->first), log_signal(it->second), mod, pr.first.unescape()); + log_header(design, "Trying to remove assign %s %s in %s.%s.\n", log_signal(it->first), log_signal(it->second), mod, design->twines.str(pr.first).c_str()); cs->actions.erase(it); return design_copy; } @@ -389,7 +389,7 @@ struct BugpointPass : public Pass { { if (index++ == seed) { - log_header(design, "Trying to remove sync %s update %s %s in %s.%s.\n", log_signal(sy->signal), log_signal(it->first), log_signal(it->second), mod, pr.first.unescape()); + log_header(design, "Trying to remove sync %s update %s %s in %s.%s.\n", log_signal(sy->signal), log_signal(it->first), log_signal(it->second), mod, design->twines.str(pr.first).c_str()); sy->actions.erase(it); return design_copy; } @@ -399,7 +399,7 @@ struct BugpointPass : public Pass { { if (index++ == seed) { - log_header(design, "Trying to remove sync %s memwr %s %s %s %s in %s.%s.\n", log_signal(sy->signal), it->memid.unescape(), log_signal(it->address), log_signal(it->data), log_signal(it->enable), mod, pr.first.unescape()); + log_header(design, "Trying to remove sync %s memwr %s %s %s %s in %s.%s.\n", log_signal(sy->signal), it->memid.unescape(), log_signal(it->address), log_signal(it->data), log_signal(it->enable), mod, design->twines.str(pr.first).c_str()); sy->mem_write_actions.erase(it); // Remove the bit for removed action from other actions' priority masks. for (auto it2 = sy->mem_write_actions.begin(); it2 != sy->mem_write_actions.end(); ++it2) { diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index 89656abcf..759b83d5a 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -42,25 +42,25 @@ int check_bufnorm_cell(RTLIL::Module *module, RTLIL::Cell *cell) for (auto bit : conn.second) { if (bit.is_wire() && !module->fanout(bit).count(RTLIL::PortBit(cell, conn.first, i))) log_warning("sigNorm: fanout index missing entry for cell %s.%s port %s bit %d\n", - log_id(module), log_id(cell), log_id(conn.first), i), counter++; + log_id(module), log_id(cell), module->design->twines.str(conn.first).c_str(), i), counter++; ++i; } } } else if (!conn.second.empty()) { if (!conn.second.is_wire()) { log_warning("bufNorm: cell %s.%s port %s output is not a full wire: %s\n", - log_id(module), log_id(cell), log_id(conn.first), log_signal(conn.second)); + log_id(module), log_id(cell), module->design->twines.str(conn.first).c_str(), log_signal(conn.second)); counter++; } else { Wire *w = conn.second.as_wire(); if (!w->known_driver()) log_warning("bufNorm: cell %s.%s port %s drives wire %s but wire has no driverCell_ set\n", - log_id(module), log_id(cell), log_id(conn.first), log_id(w)), counter++; + log_id(module), log_id(cell), module->design->twines.str(conn.first).c_str(), log_id(w)), counter++; else if (w->driverCell() != cell || w->driverPort() != conn.first) log_warning("bufNorm: wire %s.%s driverCell_/driverPort_ mismatch: recorded driver is cell %s port %s, but cell %s port %s also drives it\n", log_id(module), log_id(w), - log_id(w->driverCell()), log_id(w->driverPort()), - log_id(cell), log_id(conn.first)), counter++; + log_id(w->driverCell()), module->design->twines.str(w->driverPort()).c_str(), + log_id(cell), module->design->twines.str(conn.first).c_str()), counter++; } } } @@ -77,16 +77,16 @@ int check_bufnorm_wire(RTLIL::Module *module, RTLIL::Wire *wire) int counter = 0; if (wire->known_driver()) { Cell *driver = wire->driverCell(); - IdString dport = wire->driverPort(); + TwineRef dport = wire->driverPort(); if (!driver->hasPort(dport)) { log_warning("bufNorm: wire %s.%s driverPort_ %s does not exist on driverCell_ %s\n", - log_id(module), log_id(wire), log_id(dport), log_id(driver)); + log_id(module), log_id(wire), module->design->twines.str(dport).c_str(), log_id(driver)); counter++; } else { const SigSpec &dsig = driver->getPort(dport); if (!dsig.is_wire() || dsig.as_wire() != wire) log_warning("bufNorm: wire %s.%s driverCell_ %s port %s does not connect back to this wire\n", - log_id(module), log_id(wire), log_id(driver), log_id(dport)), counter++; + log_id(module), log_id(wire), log_id(driver), module->design->twines.str(dport).c_str()), counter++; if (wire->port_input && !wire->port_output && driver->type != ID($input_port)) log_warning("bufNorm: module input wire %s.%s is driven by non-$input_port cell %s of type %s\n", log_id(module), log_id(wire), log_id(driver), log_id(driver->type)), counter++; @@ -109,20 +109,20 @@ int check_signorm_fanout(RTLIL::Module *module) for (auto &pb : portbits) { if (!pb.cell->hasPort(pb.port)) { log_warning("sigNorm: fanout entry for %s points to non-existent port %s on cell %s.%s\n", - log_signal(bit), log_id(pb.port), log_id(module), log_id(pb.cell)); + log_signal(bit), module->design->twines.str(pb.port).c_str(), log_id(module), log_id(pb.cell)); counter++; continue; } const SigSpec &fsig = pb.cell->getPort(pb.port); if (pb.offset < 0 || pb.offset >= fsig.size()) { log_warning("sigNorm: fanout entry for %s has out-of-bounds offset %d for cell %s.%s port %s (width %d)\n", - log_signal(bit), pb.offset, log_id(module), log_id(pb.cell), log_id(pb.port), fsig.size()); + log_signal(bit), pb.offset, log_id(module), log_id(pb.cell), module->design->twines.str(pb.port).c_str(), fsig.size()); counter++; continue; } if (fsig[pb.offset] != bit) log_warning("sigNorm: fanout entry mismatch: expected %s at offset %d of cell %s.%s port %s, found %s\n", - log_signal(bit), pb.offset, log_id(module), log_id(pb.cell), log_id(pb.port), log_signal(fsig[pb.offset])), counter++; + log_signal(bit), pb.offset, log_id(module), log_id(pb.cell), module->design->twines.str(pb.port).c_str(), log_signal(fsig[pb.offset])), counter++; } } return counter; @@ -234,7 +234,7 @@ struct CheckPass : public Pass { for (auto bit : sigmap(action.first)) wire_drivers[bit].push_back( stringf("action %s <= %s (case rule) in process %s", - log_signal(action.first), log_signal(action.second), proc_it.first.unescape())); + log_signal(action.first), log_signal(action.second), module->design->twines.str(proc_it.first).c_str())); for (auto bit : sigmap(action.second)) if (bit.wire) used_wires.insert(bit); @@ -255,7 +255,7 @@ struct CheckPass : public Pass { for (auto bit : sigmap(action.first)) wire_drivers[bit].push_back( stringf("action %s <= %s (sync rule) in process %s", - log_signal(action.first), log_signal(action.second), proc_it.first.unescape())); + log_signal(action.first), log_signal(action.second), module->design->twines.str(proc_it.first).c_str())); for (auto bit : sigmap(action.second)) if (bit.wire) used_wires.insert(bit); } @@ -278,8 +278,8 @@ struct CheckPass : public Pass { CircuitEdgesDatabase(TopoSort> &topo, SigMap &sigmap, bool force_detail) : topo(topo), sigmap(sigmap), force_detail(force_detail) {} - void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, - RTLIL::IdString to_port, int to_bit, int) override { + void add_edge(RTLIL::Cell *cell, TwineRef from_port, int from_bit, + TwineRef to_port, int to_bit, int) override { SigSpec from_portsig = cell->getPort(from_port); SigSpec to_portsig = cell->getPort(to_port); log_assert(from_bit >= 0 && from_bit < from_portsig.size()); @@ -405,7 +405,7 @@ struct CheckPass : public Pass { if (output && !input && bit.wire) wire_drivers_count[bit]++; if (output && (bit.wire || !input)) - wire_drivers[bit].push_back(stringf("port %s[%d] of cell %s (%s)", conn.first.unescape(), i, + wire_drivers[bit].push_back(stringf("port %s[%d] of cell %s (%s)", cell->module->design->twines.str(conn.first).c_str(), i, cell, cell->type.unescape())); if (output) driver_cells[bit] = cell; @@ -485,7 +485,7 @@ struct CheckPass : public Pass { SigBit prev; for (auto it = loop.rbegin(); it != loop.rend(); it++) if (it->second != -1) { // skip the fallback helper nodes - prev = SigBit(module->wire(it->first), it->second); + prev = SigBit(module->wire(module->design->twines.lookup(it->first.str())), it->second); break; } log_assert(prev != SigBit()); @@ -504,22 +504,22 @@ struct CheckPass : public Pass { MatchingEdgePrinter(std::string &message, SigMap &sigmap, SigBit from, SigBit to) : message(message), sigmap(sigmap), from(from), to(to), nhits(0) {} - void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, - RTLIL::IdString to_port, int to_bit, int) override { + void add_edge(RTLIL::Cell *cell, TwineRef from_port, int from_bit, + TwineRef to_port, int to_bit, int) override { SigBit edge_from = sigmap(cell->getPort(from_port))[from_bit]; SigBit edge_to = sigmap(cell->getPort(to_port))[to_bit]; if (edge_from == from && edge_to == to && nhits++ < HITS_LIMIT) - message += stringf(" %s[%d] --> %s[%d]\n", from_port.unescape(), from_bit, - to_port.unescape(), to_bit); + message += stringf(" %s[%d] --> %s[%d]\n", cell->module->design->twines.str(from_port).c_str(), from_bit, + cell->module->design->twines.str(to_port).c_str(), to_bit); if (nhits == HITS_LIMIT) message += " ...\n"; } }; - Wire *wire = module->wire(pair.first); + Wire *wire = module->wire(module->design->twines.lookup(pair.first.str())); log_assert(wire); - SigBit bit(module->wire(pair.first), pair.second); + SigBit bit(module->wire(module->design->twines.lookup(pair.first.str())), pair.second); log_assert(driver_cells.count(bit)); Cell *driver = driver_cells.at(bit); diff --git a/passes/cmds/chformal.cc b/passes/cmds/chformal.cc index 0239b1f69..9ad4b27ae 100644 --- a/passes/cmds/chformal.cc +++ b/passes/cmds/chformal.cc @@ -344,8 +344,8 @@ struct ChformalPass : public Pass { Wire *new_en = module->addWire(NEW_TWINE); new_en->attributes[ID::init] = State::S0; - module->addFf(NEW_ID, orig_a, new_a); - module->addFf(NEW_ID, orig_en, new_en); + module->addFf(NEW_TWINE, orig_a, new_a); + module->addFf(NEW_TWINE, orig_en, new_en); cell->setPort(TW::A, new_a); cell->setPort(TW::EN, new_en); @@ -360,12 +360,12 @@ struct ChformalPass : public Pass { for (int i = 0; i < mode_arg; i++) { Wire *w = module->addWire(NEW_TWINE); w->attributes[ID::init] = State::S0; - module->addFf(NEW_ID, en, w); + module->addFf(NEW_TWINE, en, w); en = w; } for (auto cell : constr_cells) - cell->setPort(TW::EN, module->LogicAnd(NEW_ID, en, cell->getPort(TW::EN))); + cell->setPort(TW::EN, module->LogicAnd(NEW_TWINE, en, cell->getPort(TW::EN))); } else if (mode =='p') @@ -381,13 +381,13 @@ struct ChformalPass : public Pass { cover->setParam(ID(FLAVOR), Const("cover")); for (auto const &conn : cell->connections()) - if (!conn.first.in(ID::A, ID::EN)) + if (conn.first != TW::A && conn.first != TW::EN) cover->setPort(conn.first, conn.second); cover->setPort(TW::A, cell->getPort(TW::EN)); cover->setPort(TW::EN, State::S1); } else { - module->addCover(NEW_ID_SUFFIX("coverenable"), - cell->getPort(TW::EN), State::S1, cell->get_src_attribute()); + module->addCover(NEW_TWINE_SUFFIX("coverenable"), + cell->getPort(TW::EN), State::S1, module->design->twines.add(Twine{cell->get_src_attribute()})); } } } @@ -432,9 +432,9 @@ struct ChformalPass : public Pass { plain_cell->setPort(TW::EN, sig_en); if (plain_cell->type.in(ID($assert), ID($assume))) - sig_a = module->Not(NEW_ID, sig_a); + sig_a = module->Not(NEW_TWINE, sig_a); - SigBit combined_en = module->And(NEW_ID, sig_a, sig_en); + SigBit combined_en = module->And(NEW_TWINE, sig_a, sig_en); module->swap_names(cell, plain_cell); diff --git a/passes/cmds/chtype.cc b/passes/cmds/chtype.cc index d68050519..28c55d662 100644 --- a/passes/cmds/chtype.cc +++ b/passes/cmds/chtype.cc @@ -34,10 +34,9 @@ static void publish_design(RTLIL::Design* design) { auto saved_modules = design->modules_; design->modules_.clear(); for (auto& [name, mod] : saved_modules) { - RTLIL::IdString new_name = mod->name; + RTLIL::IdString new_name = RTLIL::IdString(design->twines.str(mod->meta_->name)); publish(new_name); - mod->name = new_name; - design->modules_[mod->name] = mod; + design->modules_[mod->meta_->name] = mod; for (auto* cell : mod->cells()) { publish(cell->type); } diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index e2d4044e0..2c77ac5ac 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -136,7 +136,7 @@ struct ConnectPass : public Pass { RTLIL::Module *module = nullptr; for (auto mod : design->selected_modules()) { if (module != nullptr) - log_cmd_error("Multiple modules selected: %s, %s\n", module->name.unescape(), mod->name.unescape()); + log_cmd_error("Multiple modules selected: %s, %s\n", module->design->twines.str(module->meta_->name).c_str(), module->design->twines.str(mod->meta_->name).c_str()); module = mod; } if (module == nullptr) @@ -198,7 +198,7 @@ struct ConnectPass : public Pass { if (flag_nounset) log_cmd_error("Can't use -port together with -nounset.\n"); - if (module->cell(RTLIL::escape_id(port_cell)) == nullptr) + if (module->cell(module->design->twines.lookup(RTLIL::escape_id(port_cell))) == nullptr) log_cmd_error("Can't find cell %s.\n", port_cell); RTLIL::SigSpec sig; @@ -206,9 +206,9 @@ struct ConnectPass : public Pass { log_cmd_error("Failed to parse port expression `%s'.\n", port_expr); if (!flag_assert) { - module->cell(RTLIL::escape_id(port_cell))->setPort(RTLIL::escape_id(port_port), sigmap(sig)); + module->cell(module->design->twines.lookup(RTLIL::escape_id(port_cell)))->setPort(module->design->twines.lookup(RTLIL::escape_id(port_port)), sigmap(sig)); } else { - SigSpec cur = module->cell(RTLIL::escape_id(port_cell))->getPort(RTLIL::escape_id(port_port)); + SigSpec cur = module->cell(module->design->twines.lookup(RTLIL::escape_id(port_cell)))->getPort(module->design->twines.lookup(RTLIL::escape_id(port_port))); if (sigmap(sig) != sigmap(cur)) { log_cmd_error("Expected connection not present: expected %s, found %s.\n", log_signal(sig), log_signal(cur)); } diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc index dcc6f0004..eba84ec60 100644 --- a/passes/cmds/connwrappers.cc +++ b/passes/cmds/connwrappers.cc @@ -77,7 +77,7 @@ struct ConnwrappersWorker for (auto &conn : cell->connections()) { - std::pair key(cell->type, conn.first); + std::pair key(cell->type, RTLIL::IdString(cell->module->design->twines.str(conn.first))); if (!decls.count(key)) continue; @@ -134,8 +134,8 @@ struct ConnwrappersWorker } if (old_sig.size()) - log("Connected extended bits of %s.%s:%s: %s -> %s\n", module->name.unescape(), cell->name.unescape(), - conn.first.unescape(), log_signal(old_sig), log_signal(conn.second)); + log("Connected extended bits of %s.%s:%s: %s -> %s\n", module->design->twines.str(module->meta_->name).c_str(), cell->module->design->twines.str(cell->meta_->name), + module->design->twines.str(conn.first).c_str(), log_signal(old_sig), log_signal(conn.second)); } } } diff --git a/passes/cmds/copy.cc b/passes/cmds/copy.cc index 5a5835a43..1b2a64428 100644 --- a/passes/cmds/copy.cc +++ b/passes/cmds/copy.cc @@ -51,7 +51,7 @@ struct CopyPass : public Pass { log_cmd_error("Target module name %s already exists.\n", trg_name); RTLIL::Module *new_mod = design->module(src_name)->clone(); - new_mod->name = trg_name; + design->rename(new_mod, design->twines.add(Twine{trg_name})); design->add(new_mod); } } CopyPass; diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index e341f29d6..2f594ec75 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -68,12 +68,12 @@ struct DeletePass : public Pass { std::vector delete_mods; for (auto module : design->modules()) { - if (design->selected_whole_module(module->name) && !flag_input && !flag_output) { + if (design->selected_whole_module(module->meta_->name) && !flag_input && !flag_output) { delete_mods.push_back(module); continue; } - if (!design->selected_module(module->name)) + if (!design->selected_module(module->meta_->name)) continue; if (flag_input || flag_output) { @@ -91,7 +91,7 @@ struct DeletePass : public Pass { pool delete_wires; pool delete_cells; pool delete_procs; - pool delete_mems; + pool delete_mems; for (auto wire : module->selected_wires()) delete_wires.insert(wire); @@ -104,7 +104,7 @@ struct DeletePass : public Pass { if (design->selected(module, cell)) delete_cells.insert(cell); if (cell->has_memid() && - delete_mems.count(cell->parameters.at(ID::MEMID).decode_string()) != 0) + delete_mems.count(design->twines.lookup(cell->parameters.at(ID::MEMID).decode_string())) != 0) delete_cells.insert(cell); } diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 94172e051..a9d963b78 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -272,7 +272,7 @@ struct DesignPass : public Pass { t->attributes.erase(ID::top); queue.insert(t); - done[mod->name] = prefix; + done[RTLIL::escape_id(copy_from_design->twines.str(mod->meta_->name))] = prefix; } while (!queue.empty() && copy_from_design) @@ -316,7 +316,7 @@ struct DesignPass : public Pass { for (auto mod : copy_src_modules) { - std::string trg_name = as_name.empty() ? mod->name.str() : RTLIL::escape_id(as_name); + std::string trg_name = as_name.empty() ? copy_from_design->twines.str(mod->meta_->name) : RTLIL::escape_id(as_name); if (copy_to_design->module(trg_name) != nullptr) copy_to_design->remove(copy_to_design->module(trg_name)); @@ -358,7 +358,7 @@ struct DesignPass : public Pass { design->selection_stack.clear(); design->selection_vars.clear(); - design->selected_active_module.clear(); + design->selected_active_module = Twine::Null; design->push_full_selection(); } diff --git a/passes/cmds/design_equal.cc b/passes/cmds/design_equal.cc index 9db43c3e2..ce38d481e 100644 --- a/passes/cmds/design_equal.cc +++ b/passes/cmds/design_equal.cc @@ -38,9 +38,9 @@ public: [[noreturn]] void formatted_error(std::string err) { - log("Module A: %s\n", mod_a->name.unescape()); + log("Module A: %s\n", log_id(mod_a)); log_module(mod_a, " "); - log("Module B: %s\n", mod_b->name.unescape()); + log("Module B: %s\n", log_id(mod_b)); log_module(mod_b, " "); log_cmd_error("Designs are different: %s\n", err); } @@ -104,24 +104,22 @@ public: void check_wires() { for (const auto &it : mod_a->wires_) { - RTLIL::IdString wname(it.second->name); - RTLIL::Wire *wb = mod_b->wire(wname); + RTLIL::Wire *wb = mod_b->wire(it.first); if (!wb) - error("Module %s missing wire %s in second design.\n", mod_a->name.unescape(), wname.unescape()); + error("Module %s missing wire %s in second design.\n", log_id(mod_a), log_id(it.second)); else if (std::string mismatch = compare_wires(it.second, wb); !mismatch.empty()) - error("Module %s wire %s %s.\n", mod_a->name.unescape(), wname.unescape(), mismatch); + error("Module %s wire %s %s.\n", log_id(mod_a), log_id(it.second), mismatch); } for (const auto &it : mod_b->wires_) { - RTLIL::IdString wname(it.second->name); - if (!mod_a->wire(wname)) - error("Module %s missing wire %s in first design.\n", mod_b->name.unescape(), wname.unescape()); + if (!mod_a->wire(it.first)) + error("Module %s missing wire %s in first design.\n", log_id(mod_b), log_id(it.second)); } } std::string compare_memories(const RTLIL::Memory *a, const RTLIL::Memory *b) { - if (a->name != b->name) - return "name mismatch: " + std::string(a->name.unescape()) + " != " + b->name.unescape(); + if (a->meta_->name != b->meta_->name) + return "name mismatch: " + std::string(a->module->design->twines.str(a->meta_->name)) + " != " + b->module->design->twines.str(b->meta_->name); if (a->width != b->width) return "width mismatch: " + std::to_string(a->width) + " != " + std::to_string(b->width); if (a->start_offset != b->start_offset) @@ -154,13 +152,13 @@ public: for (const auto &it : a->connections()) { if (b->connections().count(it.first) == 0) - return "connection mismatch: missing connection " + std::string(it.first.unescape()) + " in second design"; + return "connection mismatch: missing connection " + a->module->design->twines.str(it.first) + " in second design"; if (!compare_sigspec(it.second, b->connections().at(it.first))) - return "connection " + std::string(it.first.unescape()) + " mismatch: " + log_signal(it.second) + " != " + log_signal(b->connections().at(it.first)); + return "connection " + a->module->design->twines.str(it.first) + " mismatch: " + log_signal(it.second) + " != " + log_signal(b->connections().at(it.first)); } for (const auto &it : b->connections()) if (a->connections().count(it.first) == 0) - return "connection mismatch: missing connection " + std::string(it.first.unescape()) + " in first design"; + return "connection mismatch: missing connection " + a->module->design->twines.str(it.first) + " in first design"; return ""; } @@ -168,17 +166,15 @@ public: void check_cells() { for (const auto &it : mod_a->cells_) { - RTLIL::IdString cname(it.second->name); - RTLIL::Cell *cb = mod_b->cell(cname); + RTLIL::Cell *cb = mod_b->cell(it.first); if (!cb) - error("Module %s missing cell %s in second design.\n", mod_a->name.unescape(), cname.unescape()); + error("Module %s missing cell %s in second design.\n", log_id(mod_a), log_id(it.second)); else if (std::string mismatch = compare_cells(it.second, cb); !mismatch.empty()) - error("Module %s cell %s %s.\n", mod_a->name.unescape(), cname.unescape(), mismatch); + error("Module %s cell %s %s.\n", log_id(mod_a), log_id(it.second), mismatch); } for (const auto &it : mod_b->cells_) { - RTLIL::IdString cname(it.second->name); - if (!mod_a->cell(cname)) - error("Module %s missing cell %s in first design.\n", mod_b->name.unescape(), cname.unescape()); + if (!mod_a->cell(it.first)) + error("Module %s missing cell %s in first design.\n", log_id(mod_b), log_id(it.second)); } } @@ -186,13 +182,13 @@ public: { for (const auto &it : mod_a->memories) { if (mod_b->memories.count(it.first) == 0) - error("Module %s missing memory %s in second design.\n", mod_a->name.unescape(), it.first.unescape()); + error("Module %s missing memory %s in second design.\n", log_id(mod_a), log_id(it.second)); if (std::string mismatch = compare_memories(it.second, mod_b->memories.at(it.first)); !mismatch.empty()) - error("Module %s memory %s %s.\n", mod_a->name.unescape(), it.first.unescape(), mismatch); + error("Module %s memory %s %s.\n", log_id(mod_a), log_id(it.second), mismatch); } for (const auto &it : mod_b->memories) if (mod_a->memories.count(it.first) == 0) - error("Module %s missing memory %s in first design.\n", mod_b->name.unescape(), it.first.unescape()); + error("Module %s missing memory %s in first design.\n", log_id(mod_b), log_id(it.second)); } std::string compare_case_rules(const RTLIL::CaseRule *a, const RTLIL::CaseRule *b) @@ -276,7 +272,7 @@ public: std::string compare_processes(const RTLIL::Process *a, const RTLIL::Process *b) { - if (a->name != b->name) return "name mismatch: " + std::string(a->name.unescape()) + " != " + b->name.unescape(); + if (a->meta_->name != b->meta_->name) return "name mismatch: " + std::string(a->module->design->twines.str(a->meta_->name)) + " != " + b->module->design->twines.str(b->meta_->name); if (std::string mismatch = compare_attributes(a, b); !mismatch.empty()) return mismatch; if (std::string mismatch = compare_case_rules(&a->root_case, &b->root_case); !mismatch.empty()) @@ -293,13 +289,13 @@ public: { for (auto &it : mod_a->processes) { if (mod_b->processes.count(it.first) == 0) - error("Module %s missing process %s in second design.\n", mod_a->name.unescape(), it.first.unescape()); + error("Module %s missing process %s in second design.\n", log_id(mod_a), log_id(it.second)); if (std::string mismatch = compare_processes(it.second, mod_b->processes.at(it.first)); !mismatch.empty()) - error("Module %s process %s %s.\n", mod_a->name.unescape(), it.first.unescape(), mismatch.c_str()); + error("Module %s process %s %s.\n", log_id(mod_a), log_id(it.second), mismatch.c_str()); } for (auto &it : mod_b->processes) if (mod_a->processes.count(it.first) == 0) - error("Module %s missing process %s in first design.\n", mod_b->name.unescape(), it.first.unescape()); + error("Module %s missing process %s in first design.\n", log_id(mod_b), log_id(it.second)); } void check_connections() @@ -307,23 +303,23 @@ public: const auto &conns_a = mod_a->connections(); const auto &conns_b = mod_b->connections(); if (conns_a.size() != conns_b.size()) { - error("Module %s connection count differs: %zu != %zu\n", mod_a->name.unescape(), conns_a.size(), conns_b.size()); + error("Module %s connection count differs: %zu != %zu\n", log_id(mod_a), conns_a.size(), conns_b.size()); } else { for (size_t i = 0; i < conns_a.size(); i++) { if (!compare_sigspec(conns_a[i].first, conns_b[i].first)) - error("Module %s connection %zu LHS %s != %s.\n", mod_a->name.unescape(), i, log_signal(conns_a[i].first), log_signal(conns_b[i].first)); + error("Module %s connection %zu LHS %s != %s.\n", log_id(mod_a), i, log_signal(conns_a[i].first), log_signal(conns_b[i].first)); if (!compare_sigspec(conns_a[i].second, conns_b[i].second)) - error("Module %s connection %zu RHS %s != %s.\n", mod_a->name.unescape(), i, log_signal(conns_a[i].second), log_signal(conns_b[i].second)); + error("Module %s connection %zu RHS %s != %s.\n", log_id(mod_a), i, log_signal(conns_a[i].second), log_signal(conns_b[i].second)); } } } void check() { - if (mod_a->name != mod_b->name) - error("Modules have different names: %s != %s\n", mod_a->name.unescape(), mod_b->name.unescape()); + if (mod_a->meta_->name != mod_b->meta_->name) + error("Modules have different names: %s != %s\n", log_id(mod_a), log_id(mod_b)); if (std::string mismatch = compare_attributes(mod_a, mod_b); !mismatch.empty()) - error("Module %s %s.\n", mod_a->name.unescape(), mismatch); + error("Module %s %s.\n", log_id(mod_a), mismatch); check_wires(); check_cells(); check_memories(); @@ -356,16 +352,16 @@ struct DesignEqualPass : public Pass { for (auto &it : design->modules_) { RTLIL::Module *mod = it.second; - if (!other->has(mod->name)) - log_error("Second design missing module %s.\n", mod->name.unescape()); + if (!other->has(it.first)) + log_error("Second design missing module %s.\n", log_id(mod)); - ModuleComparator cmp(mod, other->module(mod->name)); + ModuleComparator cmp(mod, other->module(it.first)); cmp.check(); } for (auto &it : other->modules_) { RTLIL::Module *mod = it.second; - if (!design->has(mod->name)) - log_error("First design missing module %s.\n", mod->name.unescape()); + if (!design->has(it.first)) + log_error("First design missing module %s.\n", log_id(mod)); } log("Designs are identical.\n"); diff --git a/passes/cmds/dft_tag.cc b/passes/cmds/dft_tag.cc index 3e8bd77ab..e0ccb2515 100644 --- a/passes/cmds/dft_tag.cc +++ b/passes/cmds/dft_tag.cc @@ -98,10 +98,10 @@ struct DftTagWorker { } for (auto cell : overwrite_cells) { - log_debug("Applying $overwrite_tag %s for signal %s\n", cell->name.unescape(), log_signal(cell->getPort(TW::A))); + log_debug("Applying $overwrite_tag %s for signal %s\n", cell->module->design->twines.str(cell->meta_->name), log_signal(cell->getPort(TW::A))); SigSpec orig_signal = cell->getPort(TW::A); SigSpec interposed_signal = divert_users(orig_signal); - auto *set_tag_cell = module->addSetTag(NEW_ID, cell->getParam(ID::TAG).decode_string(), orig_signal, cell->getPort(TW::SET), cell->getPort(TW::CLR), interposed_signal); + auto *set_tag_cell = module->addSetTag(module->design->twines.add(NEW_TWINE), cell->getParam(ID::TAG).decode_string(), orig_signal, cell->getPort(TW::SET), cell->getPort(TW::CLR), interposed_signal); modwalker.add_cell(set_tag_cell); // Make sure the next $overwrite_tag sees the new connections design_changed = true; } @@ -131,7 +131,7 @@ struct DftTagWorker { void divert_users(SigBit driver_bit, SigBit interposed_bit) { - dict, SigSpec> updated_ports; + dict, SigSpec> updated_ports; // TODO also check module outputs auto found = modwalker.signal_consumers.find(driver_bit); if (found == modwalker.signal_consumers.end()) @@ -141,7 +141,7 @@ struct DftTagWorker { continue; if (sigmap(consumer.cell->getPort(consumer.port)[consumer.offset]) != driver_bit) continue; - std::pair key = {consumer.cell, consumer.port}; + std::pair key = {consumer.cell, consumer.port}; auto found_port = updated_ports.find(key); if (found_port == updated_ports.end()) { updated_ports.emplace(key, consumer.cell->getPort(consumer.port)); @@ -318,7 +318,7 @@ struct DftTagWorker { if (!GetSize(combined)) combined = tag_sig; else - combined = autoOr(NEW_ID, combined, tag_sig); + combined = autoOr(NEW_TWINE, combined, tag_sig); } if (!GetSize(combined)) @@ -486,8 +486,8 @@ struct DftTagWorker { if (cell_tag == tag) { auto &sig_set = cell->getPort(TW::SET); auto &sig_clr = cell->getPort(TW::CLR); - tag_sig_a = autoAnd(NEW_ID, tag_sig_a, autoNot(NEW_ID, sig_clr)); - tag_sig_a = autoOr(NEW_ID, tag_sig_a, sig_set); + tag_sig_a = autoAnd(NEW_TWINE, tag_sig_a, autoNot(NEW_TWINE, sig_clr)); + tag_sig_a = autoOr(NEW_TWINE, tag_sig_a, sig_set); } emit_tag_signal(tag, sig_y, tag_sig_a); @@ -529,9 +529,9 @@ struct DftTagWorker { inv_b ^= true; if (inv_a) - sig_a = autoNot(NEW_ID, sig_a); + sig_a = autoNot(NEW_TWINE, sig_a); if (inv_b) - sig_b = autoNot(NEW_ID, sig_b); + sig_b = autoNot(NEW_TWINE, sig_b); auto group_sig_a = tag_group_signal(tag, sig_a); auto group_sig_b = tag_group_signal(tag, sig_b); @@ -541,15 +541,15 @@ struct DftTagWorker { // Does this input allow propagating (doesn't fix output or same tag group) - sig_a = autoOr(NEW_ID, sig_a, group_sig_a); - sig_b = autoOr(NEW_ID, sig_b, group_sig_b); + sig_a = autoOr(NEW_TWINE, sig_a, group_sig_a); + sig_b = autoOr(NEW_TWINE, sig_b, group_sig_b); // Mask input tags by whether the other side allows propagation - tag_sig_a = autoAnd(NEW_ID, tag_sig_a, sig_b); - tag_sig_b = autoAnd(NEW_ID, tag_sig_b, sig_a); + tag_sig_a = autoAnd(NEW_TWINE, tag_sig_a, sig_b); + tag_sig_b = autoAnd(NEW_TWINE, tag_sig_b, sig_a); - auto tag_sig = autoOr(NEW_ID, tag_sig_a, tag_sig_b); + auto tag_sig = autoOr(NEW_TWINE, tag_sig_a, tag_sig_b); emit_tag_signal(tag, sig_y, tag_sig); return; } @@ -566,7 +566,7 @@ struct DftTagWorker { auto tag_sig_a = tag_signal(tag, sig_a); auto tag_sig_b = tag_signal(tag, sig_b); - auto tag_sig = autoOr(NEW_ID, tag_sig_a, tag_sig_b); + auto tag_sig = autoOr(NEW_TWINE, tag_sig_a, tag_sig_b); emit_tag_signal(tag, sig_y, tag_sig); return; } @@ -585,23 +585,23 @@ struct DftTagWorker { auto group_sig_b = tag_group_signal(tag, sig_b); auto group_sig_s = tag_group_signal(tag, sig_s); - auto prop_s = autoOr(NEW_ID, - autoXor(NEW_ID, sig_a, sig_b), - autoOr(NEW_ID, group_sig_a, group_sig_b)); + auto prop_s = autoOr(NEW_TWINE, + autoXor(NEW_TWINE, sig_a, sig_b), + autoOr(NEW_TWINE, group_sig_a, group_sig_b)); - auto prop_a = autoOr(NEW_ID, autoNot(NEW_ID, sig_s), group_sig_s); - auto prop_b = autoOr(NEW_ID, sig_s, group_sig_s); + auto prop_a = autoOr(NEW_TWINE, autoNot(NEW_TWINE, sig_s), group_sig_s); + auto prop_b = autoOr(NEW_TWINE, sig_s, group_sig_s); auto tag_sig_a = tag_signal(tag, sig_a); auto tag_sig_b = tag_signal(tag, sig_b); auto tag_sig_s = tag_signal(tag, sig_s); - tag_sig_a = autoAnd(NEW_ID, tag_sig_a, prop_a); - tag_sig_b = autoAnd(NEW_ID, tag_sig_b, prop_b); - tag_sig_s = autoAnd(NEW_ID, tag_sig_s, prop_s); + tag_sig_a = autoAnd(NEW_TWINE, tag_sig_a, prop_a); + tag_sig_b = autoAnd(NEW_TWINE, tag_sig_b, prop_b); + tag_sig_s = autoAnd(NEW_TWINE, tag_sig_s, prop_s); - auto tag_sig = autoOr(NEW_ID, tag_sig_s, - autoOr(NEW_ID, tag_sig_a, tag_sig_b)); + auto tag_sig = autoOr(NEW_TWINE, tag_sig_s, + autoOr(NEW_TWINE, tag_sig_a, tag_sig_b)); emit_tag_signal(tag, sig_y, tag_sig); return; } @@ -620,15 +620,15 @@ struct DftTagWorker { auto tag_sig_a = tag_signal(tag, sig_a); auto tag_sig_b = tag_signal(tag, sig_b); - auto group_sig = autoOr(NEW_ID, group_sig_a, group_sig_b); + auto group_sig = autoOr(NEW_TWINE, group_sig_a, group_sig_b); // The output can only be affected by the tagged inputs if all group-untagged bits are equal - auto masked_a = autoOr(NEW_ID, sig_a, group_sig); - auto masked_b = autoOr(NEW_ID, sig_b, group_sig); + auto masked_a = autoOr(NEW_TWINE, sig_a, group_sig); + auto masked_b = autoOr(NEW_TWINE, sig_b, group_sig); - auto prop = autoEq(NEW_ID, masked_a, masked_b); + auto prop = autoEq(NEW_TWINE, masked_a, masked_b); - auto tag_sig = autoAnd(NEW_ID, prop, autoReduceOr(NEW_ID, {tag_sig_a, tag_sig_b})); + auto tag_sig = autoAnd(NEW_TWINE, prop, autoReduceOr(NEW_TWINE, {tag_sig_a, tag_sig_b})); tag_sig.extend_u0(GetSize(sig_y), false); emit_tag_signal(tag, sig_y, tag_sig); return; @@ -652,15 +652,15 @@ struct DftTagWorker { auto tag_sig_a = tag_signal(tag, sig_a); auto tag_sig_b = tag_signal(tag, sig_b); - auto group_sig = autoOr(NEW_ID, group_sig_a, group_sig_b); + auto group_sig = autoOr(NEW_TWINE, group_sig_a, group_sig_b); // The output can only be affected by the tagged inputs if the greatest possible sig_a is // greater or equal to the least possible sig_b - auto masked_a = autoOr(NEW_ID, sig_a, group_sig); - auto masked_b = autoAnd(NEW_ID, sig_b, autoNot(NEW_ID, group_sig)); + auto masked_a = autoOr(NEW_TWINE, sig_a, group_sig); + auto masked_b = autoAnd(NEW_TWINE, sig_b, autoNot(NEW_TWINE, group_sig)); - auto prop = autoGe(NEW_ID, masked_a, masked_b); + auto prop = autoGe(NEW_TWINE, masked_a, masked_b); - auto tag_sig = autoAnd(NEW_ID, prop, autoReduceOr(NEW_ID, {tag_sig_a, tag_sig_b})); + auto tag_sig = autoAnd(NEW_TWINE, prop, autoReduceOr(NEW_TWINE, {tag_sig_a, tag_sig_b})); tag_sig.extend_u0(GetSize(sig_y), false); emit_tag_signal(tag, sig_y, tag_sig); return; @@ -674,13 +674,13 @@ struct DftTagWorker { auto tag_sig_a = tag_signal(tag, sig_a); if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not))) - sig_a = autoNot(NEW_ID, sig_a); + sig_a = autoNot(NEW_TWINE, sig_a); - auto filled = autoOr(NEW_ID, sig_a, group_sig_a); + auto filled = autoOr(NEW_TWINE, sig_a, group_sig_a); - auto prop = autoReduceAnd(NEW_ID, filled); - auto tagged = autoReduceOr(NEW_ID, tag_sig_a); - auto tag_sig = autoAnd(NEW_ID, prop, tagged); + auto prop = autoReduceAnd(NEW_TWINE, filled); + auto tagged = autoReduceOr(NEW_TWINE, tag_sig_a); + auto tag_sig = autoAnd(NEW_TWINE, prop, tagged); tag_sig.extend_u0(GetSize(sig_y), false); emit_tag_signal(tag, sig_y, tag_sig); return; @@ -727,7 +727,7 @@ struct DftTagWorker { } } - SigBit any_tagged = autoReduceOr(NEW_ID, tag_input); + SigBit any_tagged = autoReduceOr(NEW_TWINE, tag_input); for (auto &conn : cell->connections()) { if (cell->output(conn.first)) { @@ -772,7 +772,7 @@ struct DftTagWorker { continue; int index = 0; - auto name = module->uniquify(stringf("%s:%s", wire->name, tag.c_str() + 1), index); + auto name = module->uniquify(module->design->twines.add(Twine{stringf("%s:%s", wire->name, tag.c_str() + 1)}), index); auto hdlname = wire->get_hdlname_attribute(); if (!hdlname.empty()) @@ -826,7 +826,7 @@ struct DftTagWorker { } - SigSpec autoAnd(IdString name, const SigSpec &sig_a, const SigSpec &sig_b) + SigSpec autoAnd(Twine &&name, const SigSpec &sig_a, const SigSpec &sig_b) { log_assert(GetSize(sig_a) == GetSize(sig_b)); if (sig_a.is_fully_zero() || sig_b.is_fully_ones() || sig_a == sig_b) @@ -834,10 +834,10 @@ struct DftTagWorker { if (sig_a.is_fully_ones() || sig_b.is_fully_zero()) return sig_b; - return module->And(name, sig_a, sig_b); + return module->And(std::move(name), sig_a, sig_b); } - SigSpec autoOr(IdString name, const SigSpec &sig_a, const SigSpec &sig_b) + SigSpec autoOr(Twine &&name, const SigSpec &sig_a, const SigSpec &sig_b) { log_assert(GetSize(sig_a) == GetSize(sig_b)); if (sig_a.is_fully_ones() || sig_b.is_fully_zero() || sig_a == sig_b) @@ -845,10 +845,10 @@ struct DftTagWorker { if (sig_a.is_fully_zero() || sig_b.is_fully_ones()) return sig_b; - return module->Or(name, sig_a, sig_b); + return module->Or(std::move(name), sig_a, sig_b); } - SigSpec autoXor(IdString name, const SigSpec &sig_a, const SigSpec &sig_b) + SigSpec autoXor(Twine &&name, const SigSpec &sig_a, const SigSpec &sig_b) { log_assert(GetSize(sig_a) == GetSize(sig_b)); if (sig_a == sig_b) @@ -858,13 +858,13 @@ struct DftTagWorker { if (sig_b.is_fully_zero()) return sig_a; if (sig_a.is_fully_ones()) - return autoNot(name, sig_b); + return autoNot(std::move(name), sig_b); if (sig_b.is_fully_ones()) - return autoNot(name, sig_a); - return module->Xor(name, sig_a, sig_b); + return autoNot(std::move(name), sig_a); + return module->Xor(std::move(name), sig_a, sig_b); } - SigSpec autoXnor(IdString name, const SigSpec &sig_a, const SigSpec &sig_b) + SigSpec autoXnor(Twine &&name, const SigSpec &sig_a, const SigSpec &sig_b) { log_assert(GetSize(sig_a) == GetSize(sig_b)); if (sig_a == sig_b) @@ -874,13 +874,13 @@ struct DftTagWorker { if (sig_b.is_fully_ones()) return sig_a; if (sig_a.is_fully_zero()) - return autoNot(name, sig_b); + return autoNot(std::move(name), sig_b); if (sig_b.is_fully_zero()) - return autoNot(name, sig_a); - return module->Xnor(name, sig_a, sig_b); + return autoNot(std::move(name), sig_a); + return module->Xnor(std::move(name), sig_a, sig_b); } - SigSpec autoNot(IdString name, const SigSpec &sig_a) + SigSpec autoNot(Twine &&name, const SigSpec &sig_a) { if (sig_a.is_fully_const()) { auto const_val = sig_a.as_const(); @@ -890,10 +890,10 @@ struct DftTagWorker { } return const_val; } - return module->Not(name, sig_a); + return module->Not(std::move(name), sig_a); } - SigSpec autoEq(IdString name, const SigSpec &sig_a, const SigSpec &sig_b) + SigSpec autoEq(Twine &&name, const SigSpec &sig_a, const SigSpec &sig_b) { log_assert(GetSize(sig_a) == GetSize(sig_b)); if (sig_a == sig_b) @@ -908,10 +908,10 @@ struct DftTagWorker { return State::S0; } - return module->Eq(name, sig_a, sig_b); + return module->Eq(std::move(name), sig_a, sig_b); } - SigSpec autoGe(IdString name, const SigSpec &sig_a, const SigSpec &sig_b) + SigSpec autoGe(Twine &&name, const SigSpec &sig_a, const SigSpec &sig_b) { log_assert(GetSize(sig_a) == GetSize(sig_b)); if (sig_a == sig_b || sig_a.is_fully_ones()) @@ -919,10 +919,10 @@ struct DftTagWorker { if (sig_b.is_fully_zero()) return State::S1; - return module->Ge(name, sig_a, sig_b); + return module->Ge(std::move(name), sig_a, sig_b); } - SigSpec autoReduceAnd(IdString name, const SigSpec &sig_a) + SigSpec autoReduceAnd(Twine &&name, const SigSpec &sig_a) { if (GetSize(sig_a) == 0) return State::S1; @@ -934,10 +934,10 @@ struct DftTagWorker { return State::S0; if (sig_a.is_fully_ones()) return State::S1; - return module->ReduceAnd(name, sig_a); + return module->ReduceAnd(std::move(name), sig_a); } - SigSpec autoReduceOr(IdString name, const SigSpec &sig_a) + SigSpec autoReduceOr(Twine &&name, const SigSpec &sig_a) { if (GetSize(sig_a) == 0) return State::S0; @@ -949,7 +949,7 @@ struct DftTagWorker { return State::S1; if (sig_a.is_fully_zero()) return State::S0; - return module->ReduceOr(name, sig_a); + return module->ReduceOr(std::move(name), sig_a); } }; diff --git a/passes/cmds/edgetypes.cc b/passes/cmds/edgetypes.cc index 2f100d724..c3f63b42a 100644 --- a/passes/cmds/edgetypes.cc +++ b/passes/cmds/edgetypes.cc @@ -58,24 +58,24 @@ struct EdgetypePass : public Pass { for (auto module : design->selected_modules()) { SigMap sigmap(module); - dict>> bit_sources, bit_sinks; - pool> multibit_ports; + dict>> bit_sources, bit_sinks; + pool> multibit_ports; for (auto cell : module->selected_cells()) for (auto conn : cell->connections()) { IdString cell_type = cell->type; - IdString port_name = conn.first; + TwineRef port_name = conn.first; SigSpec sig = sigmap(conn.second); if (GetSize(sig) > 1) - multibit_ports.insert(std::pair(cell_type, port_name)); + multibit_ports.insert(std::pair(cell_type, port_name)); for (int i = 0; i < GetSize(sig); i++) { if (cell->output(port_name)) - bit_sources[sig[i]].insert(tuple(cell_type, port_name, i)); + bit_sources[sig[i]].insert(tuple(cell_type, port_name, i)); if (cell->input(port_name)) - bit_sinks[sig[i]].insert(tuple(cell_type, port_name, i)); + bit_sinks[sig[i]].insert(tuple(cell_type, port_name, i)); } } @@ -91,13 +91,13 @@ struct EdgetypePass : public Pass { auto sink_port_name = std::get<1>(sink); auto sink_bit_index = std::get<2>(sink); - string source_str = multibit_ports.count(std::pair(source_cell_type, source_port_name)) ? - stringf("%s.%s[%d]", source_cell_type.unescape(), source_port_name.unescape(), source_bit_index) : - stringf("%s.%s", source_cell_type.unescape(), source_port_name.unescape()); + string source_str = multibit_ports.count(std::pair(source_cell_type, source_port_name)) ? + stringf("%s.%s[%d]", source_cell_type.unescape(), module->design->twines.str(source_port_name).c_str(), source_bit_index) : + stringf("%s.%s", source_cell_type.unescape(), module->design->twines.str(source_port_name).c_str()); - string sink_str = multibit_ports.count(std::pair(sink_cell_type, sink_port_name)) ? - stringf("%s.%s[%d]", sink_cell_type.unescape(), sink_port_name.unescape(), sink_bit_index) : - stringf("%s.%s", sink_cell_type.unescape(), sink_port_name.unescape()); + string sink_str = multibit_ports.count(std::pair(sink_cell_type, sink_port_name)) ? + stringf("%s.%s[%d]", sink_cell_type.unescape(), module->design->twines.str(sink_port_name).c_str(), sink_bit_index) : + stringf("%s.%s", sink_cell_type.unescape(), module->design->twines.str(sink_port_name).c_str()); edge_cache.insert(source_str + " " + sink_str); } diff --git a/passes/cmds/example_dt.cc b/passes/cmds/example_dt.cc index b18277010..17e09ca59 100644 --- a/passes/cmds/example_dt.cc +++ b/passes/cmds/example_dt.cc @@ -139,7 +139,7 @@ struct ExampleDtPass : public Pass } else { - node.set_function(ExampleFn(ID($$cell_output), {{port_chunk.port, {}}})); + node.set_function(ExampleFn(ID($$cell_output), {{RTLIL::escape_id(module->design->twines.str(port_chunk.port)), {}}})); node.append_arg(enqueue(DriveBitMarker(cells(port_chunk.cell), 0))); } } else { diff --git a/passes/cmds/glift.cc b/passes/cmds/glift.cc index f922a1b76..229d72bbd 100644 --- a/passes/cmds/glift.cc +++ b/passes/cmds/glift.cc @@ -47,8 +47,9 @@ private: //Get a SigSpec for the corresponding taint signal for the cell port, creating one if necessary: if (sig.is_wire()) { - RTLIL::Wire *w = module->wire(sig.as_wire()->name.str() + "_t"); - if (w == nullptr) w = module->addWire(sig.as_wire()->name.str() + "_t", 1); + TwineRef taint_name_ref = module->design->twines.add(Twine{sig.as_wire()->name.str() + "_t"}); + RTLIL::Wire *w = module->wire(taint_name_ref); + if (w == nullptr) w = module->addWire(Twine{sig.as_wire()->name.str() + "_t"}, 1); ret = w; } else if (sig.is_fully_const() && opt_taintconstants) @@ -70,34 +71,34 @@ private: void add_precise_GLIFT_logic(const RTLIL::Cell *cell, RTLIL::SigSpec &port_a, RTLIL::SigSpec &port_a_taint, RTLIL::SigSpec &port_b, RTLIL::SigSpec &port_b_taint, RTLIL::SigSpec &port_y_taint) { //AKA AN2_SH2 or OR2_SH2 bool is_and = cell->type.in(ID($_AND_), ID($_NAND_)); - RTLIL::SigSpec n_port_a = module->LogicNot(cell->name.str() + "_t_1_1", port_a, false, cell->src_ref()); - RTLIL::SigSpec n_port_b = module->LogicNot(cell->name.str() + "_t_1_2", port_b, false, cell->src_ref()); - auto subexpr1 = module->And(cell->name.str() + "_t_1_3", is_and? port_a : n_port_a, port_b_taint, false, cell->src_ref()); - auto subexpr2 = module->And(cell->name.str() + "_t_1_4", is_and? port_b : n_port_b, port_a_taint, false, cell->src_ref()); - auto subexpr3 = module->And(cell->name.str() + "_t_1_5", port_a_taint, port_b_taint, false, cell->src_ref()); - auto subexpr4 = module->Or(cell->name.str() + "_t_1_6", subexpr1, subexpr2, false, cell->src_ref()); - module->addOr(cell->name.str() + "_t_1_7", subexpr4, subexpr3, port_y_taint, false, cell->src_ref()); + RTLIL::SigSpec n_port_a = module->LogicNot(Twine{cell->name.str() + "_t_1_1"}, port_a, false, cell->src_ref()); + RTLIL::SigSpec n_port_b = module->LogicNot(Twine{cell->name.str() + "_t_1_2"}, port_b, false, cell->src_ref()); + auto subexpr1 = module->And(Twine{cell->name.str() + "_t_1_3"}, is_and? port_a : n_port_a, port_b_taint, false, cell->src_ref()); + auto subexpr2 = module->And(Twine{cell->name.str() + "_t_1_4"}, is_and? port_b : n_port_b, port_a_taint, false, cell->src_ref()); + auto subexpr3 = module->And(Twine{cell->name.str() + "_t_1_5"}, port_a_taint, port_b_taint, false, cell->src_ref()); + auto subexpr4 = module->Or(Twine{cell->name.str() + "_t_1_6"}, subexpr1, subexpr2, false, cell->src_ref()); + module->addOr(Twine{cell->name.str() + "_t_1_7"}, subexpr4, subexpr3, port_y_taint, false, cell->src_ref()); } void add_imprecise_GLIFT_logic_1(const RTLIL::Cell *cell, RTLIL::SigSpec &port_a, RTLIL::SigSpec &port_a_taint, RTLIL::SigSpec &port_b, RTLIL::SigSpec &port_b_taint, RTLIL::SigSpec &port_y_taint) { //AKA AN2_SH3 or OR2_SH3 bool is_and = cell->type.in(ID($_AND_), ID($_NAND_)); - RTLIL::SigSpec n_port_a = module->LogicNot(cell->name.str() + "_t_2_1", port_a, false, cell->src_ref()); - auto subexpr1 = module->And(cell->name.str() + "_t_2_2", is_and? port_b : n_port_a, is_and? port_a_taint : port_b_taint, false, cell->src_ref()); - module->addOr(cell->name.str() + "_t_2_3", is_and? port_b_taint : port_a_taint, subexpr1, port_y_taint, false, cell->src_ref()); + RTLIL::SigSpec n_port_a = module->LogicNot(Twine{cell->name.str() + "_t_2_1"}, port_a, false, cell->src_ref()); + auto subexpr1 = module->And(Twine{cell->name.str() + "_t_2_2"}, is_and? port_b : n_port_a, is_and? port_a_taint : port_b_taint, false, cell->src_ref()); + module->addOr(Twine{cell->name.str() + "_t_2_3"}, is_and? port_b_taint : port_a_taint, subexpr1, port_y_taint, false, cell->src_ref()); } void add_imprecise_GLIFT_logic_2(const RTLIL::Cell *cell, RTLIL::SigSpec &port_a, RTLIL::SigSpec &port_a_taint, RTLIL::SigSpec &port_b, RTLIL::SigSpec &port_b_taint, RTLIL::SigSpec &port_y_taint) { //AKA AN2_SH4 or OR2_SH4 bool is_and = cell->type.in(ID($_AND_), ID($_NAND_)); - RTLIL::SigSpec n_port_b = module->LogicNot(cell->name.str() + "_t_3_1", port_b, false, cell->src_ref()); - auto subexpr1 = module->And(cell->name.str() + "_t_3_2", is_and? port_a : n_port_b, is_and? port_b_taint : port_a_taint, false, cell->src_ref()); - module->addOr(cell->name.str() + "_t_3_3", is_and? port_a_taint : port_b_taint, subexpr1, port_y_taint, false, cell->src_ref()); + RTLIL::SigSpec n_port_b = module->LogicNot(Twine{cell->name.str() + "_t_3_1"}, port_b, false, cell->src_ref()); + auto subexpr1 = module->And(Twine{cell->name.str() + "_t_3_2"}, is_and? port_a : n_port_b, is_and? port_b_taint : port_a_taint, false, cell->src_ref()); + module->addOr(Twine{cell->name.str() + "_t_3_3"}, is_and? port_a_taint : port_b_taint, subexpr1, port_y_taint, false, cell->src_ref()); } void add_imprecise_GLIFT_logic_3(const RTLIL::Cell *cell, RTLIL::SigSpec &port_a_taint, RTLIL::SigSpec &port_b_taint, RTLIL::SigSpec &port_y_taint) { //AKA AN2_SH5 or OR2_SH5 or XR2_SH2 - module->addOr(cell->name.str() + "_t_4_1", port_a_taint, port_b_taint, port_y_taint, false, cell->src_ref()); + module->addOr(Twine{cell->name.str() + "_t_4_1"}, port_a_taint, port_b_taint, port_y_taint, false, cell->src_ref()); } void add_imprecise_GLIFT_logic_4(RTLIL::SigSpec &port_a_taint, RTLIL::SigSpec &port_y_taint) { @@ -118,22 +119,22 @@ private: void add_precise_GLIFT_mux(const RTLIL::Cell *cell, RTLIL::SigSpec &port_a, RTLIL::SigSpec &port_a_taint, RTLIL::SigSpec &port_b, RTLIL::SigSpec &port_b_taint, RTLIL::SigSpec &port_s, RTLIL::SigSpec &port_s_taint, RTLIL::SigSpec &port_y_taint) { //S&At | ~S&Bt | ~A&B&St | A&~B&St | At&St | Bt&St - RTLIL::SigSpec n_port_a = module->LogicNot(cell->name.str() + "_t_4_1", port_a, false, cell->src_ref()); - RTLIL::SigSpec n_port_b = module->LogicNot(cell->name.str() + "_t_4_2", port_b, false, cell->src_ref()); - RTLIL::SigSpec n_port_s = module->LogicNot(cell->name.str() + "_t_4_3", port_s, false, cell->src_ref()); - auto subexpr1 = module->And(cell->name.str() + "_t_4_4", port_s, port_a_taint, false, cell->src_ref()); - auto subexpr2 = module->And(cell->name.str() + "_t_4_5", n_port_s, port_b_taint, false, cell->src_ref()); - auto subexpr3 = module->And(cell->name.str() + "_t_4_6", n_port_a, port_b, false, cell->src_ref()); - auto subexpr4 = module->And(cell->name.str() + "_t_4_7", subexpr3, port_s_taint, false, cell->src_ref()); - auto subexpr5 = module->And(cell->name.str() + "_t_4_8", port_a, n_port_b, false, cell->src_ref()); - auto subexpr6 = module->And(cell->name.str() + "_t_4_9", subexpr5, port_s_taint, false, cell->src_ref()); - auto subexpr7 = module->And(cell->name.str() + "_t_4_10", port_a_taint, port_s_taint, false, cell->src_ref()); - auto subexpr8 = module->And(cell->name.str() + "_t_4_11", port_b_taint, port_s_taint, false, cell->src_ref()); - auto subexpr9 = module->Or(cell->name.str() + "_t_4_12", subexpr1, subexpr2, false, cell->src_ref()); - auto subexpr10 = module->Or(cell->name.str() + "_t_4_13", subexpr4, subexpr6, false, cell->src_ref()); - auto subexpr11 = module->Or(cell->name.str() + "_t_4_14", subexpr7, subexpr8, false, cell->src_ref()); - auto subexpr12 = module->Or(cell->name.str() + "_t_4_15", subexpr9, subexpr10, false, cell->src_ref()); - module->addOr(cell->name.str() + "_t_4_16", subexpr11, subexpr12, port_y_taint, false, cell->src_ref()); + RTLIL::SigSpec n_port_a = module->LogicNot(Twine{cell->name.str() + "_t_4_1"}, port_a, false, cell->src_ref()); + RTLIL::SigSpec n_port_b = module->LogicNot(Twine{cell->name.str() + "_t_4_2"}, port_b, false, cell->src_ref()); + RTLIL::SigSpec n_port_s = module->LogicNot(Twine{cell->name.str() + "_t_4_3"}, port_s, false, cell->src_ref()); + auto subexpr1 = module->And(Twine{cell->name.str() + "_t_4_4"}, port_s, port_a_taint, false, cell->src_ref()); + auto subexpr2 = module->And(Twine{cell->name.str() + "_t_4_5"}, n_port_s, port_b_taint, false, cell->src_ref()); + auto subexpr3 = module->And(Twine{cell->name.str() + "_t_4_6"}, n_port_a, port_b, false, cell->src_ref()); + auto subexpr4 = module->And(Twine{cell->name.str() + "_t_4_7"}, subexpr3, port_s_taint, false, cell->src_ref()); + auto subexpr5 = module->And(Twine{cell->name.str() + "_t_4_8"}, port_a, n_port_b, false, cell->src_ref()); + auto subexpr6 = module->And(Twine{cell->name.str() + "_t_4_9"}, subexpr5, port_s_taint, false, cell->src_ref()); + auto subexpr7 = module->And(Twine{cell->name.str() + "_t_4_10"}, port_a_taint, port_s_taint, false, cell->src_ref()); + auto subexpr8 = module->And(Twine{cell->name.str() + "_t_4_11"}, port_b_taint, port_s_taint, false, cell->src_ref()); + auto subexpr9 = module->Or(Twine{cell->name.str() + "_t_4_12"}, subexpr1, subexpr2, false, cell->src_ref()); + auto subexpr10 = module->Or(Twine{cell->name.str() + "_t_4_13"}, subexpr4, subexpr6, false, cell->src_ref()); + auto subexpr11 = module->Or(Twine{cell->name.str() + "_t_4_14"}, subexpr7, subexpr8, false, cell->src_ref()); + auto subexpr12 = module->Or(Twine{cell->name.str() + "_t_4_15"}, subexpr9, subexpr10, false, cell->src_ref()); + module->addOr(Twine{cell->name.str() + "_t_4_16"}, subexpr11, subexpr12, port_y_taint, false, cell->src_ref()); } RTLIL::SigSpec score_metamux_select(const RTLIL::SigSpec &metamux_select, const RTLIL::IdString celltype) { @@ -143,8 +144,8 @@ private: //The complex model is an area model, so a lower score should mean smaller. //In this case, a nonzero hole metamux select value means less logic. //Thus we should invert the ReduceOr over the metamux_select signal. - RTLIL::SigSpec pmux_select = module->ReduceOr(metamux_select.as_wire()->name.str() + "_nonzero", metamux_select); - return module->Pmux(NEW_ID, RTLIL::Const(1), RTLIL::Const(0), pmux_select, metamux_select.as_wire()->src_ref()); + RTLIL::SigSpec pmux_select = module->ReduceOr(Twine{metamux_select.as_wire()->name.str() + "_nonzero"}, metamux_select); + return module->Pmux(NEW_TWINE, RTLIL::Const(1), RTLIL::Const(0), pmux_select, metamux_select.as_wire()->src_ref()); } else { auto select_width = metamux_select.as_wire()->width; @@ -163,7 +164,7 @@ private: std::vector next_pmux_y_ports, pmux_y_ports(costs.begin(), costs.begin() + exp2(select_width)); for (auto i = 0; pmux_y_ports.size() > 1; ++i) { for (auto j = 0; j+1 < GetSize(pmux_y_ports); j += 2) { - next_pmux_y_ports.emplace_back(module->Pmux(stringf("%s_mux_%d_%d", metamux_select.as_wire()->name, i, j), pmux_y_ports[j], pmux_y_ports[j+1], metamux_select[GetSize(metamux_select) - 1 - i], metamux_select.as_wire()->src_ref())); + next_pmux_y_ports.emplace_back(module->Pmux(Twine{stringf("%s_mux_%d_%d", metamux_select.as_wire()->name.c_str(), i, j)}, pmux_y_ports[j], pmux_y_ports[j+1], metamux_select[GetSize(metamux_select) - 1 - i], metamux_select.as_wire()->src_ref())); } if (GetSize(pmux_y_ports) % 2 == 1) next_pmux_y_ports.push_back(pmux_y_ports[GetSize(pmux_y_ports) - 1]); @@ -206,7 +207,7 @@ private: int num_versions = opt_instrumentmore? 8 : 4; for (auto i = 1; i <= num_versions; ++i) - taint_version.emplace_back(RTLIL::SigSpec(module->addWire(stringf("%s_y%d", cell->name, i), 1))); + taint_version.emplace_back(RTLIL::SigSpec(module->addWire(Twine{stringf("%s_y%d", cell->name.c_str(), i)}, 1))); for (auto i = 0; i < num_versions; ++i) { switch(i) { @@ -232,14 +233,14 @@ private: auto select_width = log2(num_versions); log_assert(exp2(select_width) == num_versions); - RTLIL::SigSpec meta_mux_select(module->addWire(cell->name.str() + "_sel", select_width)); + RTLIL::SigSpec meta_mux_select(module->addWire(Twine{cell->name.str() + "_sel"}, select_width)); meta_mux_selects.push_back(make_pair(meta_mux_select, cell->type)); - module->connect(meta_mux_select, module->Anyconst(cell->name.str() + "_hole", select_width, cell->src_ref())); + module->connect(meta_mux_select, module->Anyconst(module->design->twines.add(Twine{cell->name.str() + "_hole"}), select_width, cell->src_ref())); std::vector next_meta_mux_y_ports, meta_mux_y_ports(taint_version); for (auto i = 0; meta_mux_y_ports.size() > 1; ++i) { for (auto j = 0; j+1 < GetSize(meta_mux_y_ports); j += 2) { - next_meta_mux_y_ports.emplace_back(module->Mux(stringf("%s_mux_%d_%d", cell->name, i, j), meta_mux_y_ports[j], meta_mux_y_ports[j+1], meta_mux_select[GetSize(meta_mux_select) - 1 - i])); + next_meta_mux_y_ports.emplace_back(module->Mux(Twine{stringf("%s_mux_%d_%d", cell->name.c_str(), i, j)}, meta_mux_y_ports[j], meta_mux_y_ports[j+1], meta_mux_select[GetSize(meta_mux_select) - 1 - i])); } if (GetSize(meta_mux_y_ports) % 2 == 1) next_meta_mux_y_ports.push_back(meta_mux_y_ports[GetSize(meta_mux_y_ports) - 1]); @@ -271,7 +272,7 @@ private: log_assert(exp2(select_width) == num_versions); for (auto i = 1; i <= num_versions; ++i) - taint_version.emplace_back(RTLIL::SigSpec(module->addWire(stringf("%s_y%d", cell->name, i), 1))); + taint_version.emplace_back(RTLIL::SigSpec(module->addWire(Twine{stringf("%s_y%d", cell->name.c_str(), i)}, 1))); for (auto i = 0; i < num_versions; ++i) { switch(i) { @@ -287,14 +288,14 @@ private: } } - RTLIL::SigSpec meta_mux_select(module->addWire(cell->name.str() + "_sel", select_width)); + RTLIL::SigSpec meta_mux_select(module->addWire(Twine{cell->name.str() + "_sel"}, select_width)); meta_mux_selects.push_back(make_pair(meta_mux_select, cell->type)); - module->connect(meta_mux_select, module->Anyconst(cell->name.str() + "_hole", select_width, cell->src_ref())); + module->connect(meta_mux_select, module->Anyconst(module->design->twines.add(Twine{cell->name.str() + "_hole"}), select_width, cell->src_ref())); std::vector next_meta_mux_y_ports, meta_mux_y_ports(taint_version); for (auto i = 0; meta_mux_y_ports.size() > 1; ++i) { for (auto j = 0; j+1 < GetSize(meta_mux_y_ports); j += 2) { - next_meta_mux_y_ports.emplace_back(module->Mux(stringf("%s_mux_%d_%d", cell->name, i, j), meta_mux_y_ports[j], meta_mux_y_ports[j+1], meta_mux_select[GetSize(meta_mux_select) - 1 - i])); + next_meta_mux_y_ports.emplace_back(module->Mux(Twine{stringf("%s_mux_%d_%d", cell->name.c_str(), i, j)}, meta_mux_y_ports[j], meta_mux_y_ports[j+1], meta_mux_select[GetSize(meta_mux_select) - 1 - i])); } if (GetSize(meta_mux_y_ports) % 2 == 1) next_meta_mux_y_ports.push_back(meta_mux_y_ports[GetSize(meta_mux_y_ports) - 1]); @@ -342,15 +343,15 @@ private: //recurse to GLIFT model the child module. However, we need to augment the ports list //with taint signals and connect the new ports to the corresponding taint signals. RTLIL::Module *cell_module_def = module->design->module(cell->type); - dict orig_ports = cell->connections(); - log("Adding cell %s\n", cell_module_def->name); + auto orig_ports = cell->connections(); + log("Adding cell %s\n", module->design->twines.str(cell_module_def->meta_->name).c_str()); for (auto &it : orig_ports) { RTLIL::SigSpec port = it.second; RTLIL::SigSpec port_taint = get_corresponding_taint_signal(port); log_assert(port_taint.is_wire()); - log_assert(std::find(cell_module_def->ports.begin(), cell_module_def->ports.end(), port_taint.as_wire()->name) != cell_module_def->ports.end()); - cell->setPort(port_taint.as_wire()->name, port_taint); + log_assert(std::find(cell_module_def->ports.begin(), cell_module_def->ports.end(), port_taint.as_wire()->meta_->name) != cell_module_def->ports.end()); + cell->setPort(module->design->twines.add(Twine{module->design->twines.str(port_taint.as_wire()->meta_->name) + "_t"}), port_taint); } } else log_cmd_error("This is a bug (4).\n"); @@ -378,7 +379,7 @@ private: for (unsigned int i = 0; meta_mux_select_sums.size() > 1; ) { meta_mux_select_sums_buf.clear(); for (i = 0; i + 1 < meta_mux_select_sums.size(); i += 2) { - meta_mux_select_sums_buf.push_back(module->Add(meta_mux_select_sums[i].as_wire()->name.str() + "_add", meta_mux_select_sums[i], meta_mux_select_sums[i+1], false)); + meta_mux_select_sums_buf.push_back(module->Add(Twine{module->design->twines.str(meta_mux_select_sums[i].as_wire()->meta_->name) + "_add"}, meta_mux_select_sums[i], meta_mux_select_sums[i+1], false)); } if (meta_mux_select_sums.size() % 2 == 1) meta_mux_select_sums_buf.push_back(meta_mux_select_sums[meta_mux_select_sums.size()-1]); @@ -387,7 +388,7 @@ private: if (meta_mux_select_sums.size() > 0) { meta_mux_select_sums[0].as_wire()->set_bool_attribute("\\minimize"); meta_mux_select_sums[0].as_wire()->set_bool_attribute("\\keep"); - module->rename(meta_mux_select_sums[0].as_wire(), cost_model_wire_name); + module->rename(meta_mux_select_sums[0].as_wire(), module->design->twines.add(Twine{cost_model_wire_name.str()})); } } @@ -576,7 +577,13 @@ struct GliftPass : public Pass { if (GetSize(design->selected_modules()) == 0) log_cmd_error("Can't operate on an empty selection!\n"); - TopoSort> topo_modules; //cribbed from passes/techmap/flatten.cc + struct ModuleNameCmp { + bool operator()(const RTLIL::Module *a, const RTLIL::Module *b) const { + if (a == nullptr || b == nullptr) return a < b; + return a->design->twines.str(a->meta_->name) < b->design->twines.str(b->meta_->name); + } + }; + TopoSort topo_modules; //cribbed from passes/techmap/flatten.cc auto worklist = design->selected_modules(); pool non_top_modules; while (!worklist.empty()) { @@ -600,7 +607,7 @@ struct GliftPass : public Pass { for (auto i = 0; i < GetSize(topo_modules.sorted); ++i) { RTLIL::Module *module = topo_modules.sorted[i]; - GliftWorker(module, !non_top_modules[module->name], opt_create_precise_model, opt_create_imprecise_model, opt_create_instrumented_model, opt_taintconstants, opt_keepoutputs, opt_simplecostmodel, opt_nocostmodel, opt_instrumentmore); + GliftWorker(module, !non_top_modules[ID(module->design->twines.str(module->meta_->name))], opt_create_precise_model, opt_create_imprecise_model, opt_create_instrumented_model, opt_taintconstants, opt_keepoutputs, opt_simplecostmodel, opt_nocostmodel, opt_instrumentmore); } } } GliftPass; diff --git a/passes/cmds/icell_liberty.cc b/passes/cmds/icell_liberty.cc index e0a73d08f..b652dc641 100644 --- a/passes/cmds/icell_liberty.cc +++ b/passes/cmds/icell_liberty.cc @@ -47,8 +47,8 @@ struct LibertyStubber { }; void liberty_flop(Module* base, Module* derived, std::ostream& f) { - auto base_name = base->name.str().substr(1); - auto derived_name = derived->name.str().substr(1); + auto base_name = base->design->twines.str(base->meta_->name).substr(1); + auto derived_name = derived->design->twines.str(derived->meta_->name).substr(1); FfTypeData ffType(base_name); LibertyItemizer i(f); @@ -67,14 +67,14 @@ struct LibertyStubber { i.indent = 3; auto sorted_ports = derived->ports; // Hack for CLK and C coming before Q does - auto cmp = [](IdString l, IdString r) { return l.str() < r.str(); }; + auto cmp = [derived](TwineRef l, TwineRef r) { return derived->design->twines.str(l) < derived->design->twines.str(r); }; std::sort(sorted_ports.begin(), sorted_ports.end(), cmp); std::string clock_pin_name = ""; for (auto x : sorted_ports) { - std::string port_name = x.unescape(); + std::string port_name = derived->design->twines.str(x); bool is_input = base_type.inputs.count(x); bool is_output = base_type.outputs.count(x); - f << "\t\tpin (" << x.unescape() << ") {\n"; + f << "\t\tpin (" << port_name << ") {\n"; if (is_input && !is_output) { i.item("direction", "input"); } else if (!is_input && is_output) { @@ -117,8 +117,8 @@ struct LibertyStubber { } void liberty_cell(Module* base, Module* derived, std::ostream& f) { - auto base_name = base->name.str().substr(1); - auto derived_name = derived->name.str().substr(1); + auto base_name = base->design->twines.str(base->meta_->name).substr(1); + auto derived_name = derived->design->twines.str(derived->meta_->name).substr(1); if (!ct.cell_types.count(base_name)) { log_debug("skip skeleton for %s\n", base_name.c_str()); return; @@ -130,9 +130,10 @@ struct LibertyStubber { auto& base_type = ct.cell_types[base_name]; f << "\tcell (\"" << derived_name << "\") {\n"; for (auto x : derived->ports) { + std::string port_name = derived->design->twines.str(x); bool is_input = base_type.inputs.count(x); bool is_output = base_type.outputs.count(x); - f << "\t\tpin (" << x.unescape() << ") {\n"; + f << "\t\tpin (" << port_name << ") {\n"; if (is_input && !is_output) { f << "\t\t\tdirection : input;\n"; } else if (!is_input && is_output) { @@ -193,9 +194,10 @@ struct IcellLiberty : Pass { if (!inst_module || !inst_module->get_blackbox_attribute()) continue; Module *base = inst_module; - if (!done.count(base->name)) { + auto base_name_id = ID(base->design->twines.str(base->meta_->name)); + if (!done.count(base_name_id)) { stubber.liberty_cell(base, base, *liberty_file); - done.insert(base->name); + done.insert(base_name_id); } } } diff --git a/passes/cmds/linecoverage.cc b/passes/cmds/linecoverage.cc index 5c25e32c5..558c59419 100644 --- a/passes/cmds/linecoverage.cc +++ b/passes/cmds/linecoverage.cc @@ -109,7 +109,7 @@ struct CoveragePass : public Pass { } } for (auto cell: module->cells()) { - log_debug("%s\t%s\t%s\n", module->selected(cell) ? "*" : " ", cell->get_src_attribute(), cell->name.unescape()); + log_debug("%s\t%s\t%s\n", module->selected(cell) ? "*" : " ", cell->get_src_attribute(), cell->module->design->twines.str(cell->meta_->name)); for (auto src: design->src_leaves(cell)) { auto filename = extract_src_filename(src); if (filename.empty()) continue; diff --git a/passes/cmds/printattrs.cc b/passes/cmds/printattrs.cc index cd91854bf..25528431e 100644 --- a/passes/cmds/printattrs.cc +++ b/passes/cmds/printattrs.cc @@ -71,7 +71,7 @@ struct PrintAttrsPass : public Pass { for (auto mod : design->selected_modules()) { if (design->selected_whole_module(mod)) { - log("%s%s\n", get_indent_str(indent), mod->name.unescape()); + log("%s%s\n", get_indent_str(indent), log_id(mod)); indent += 2; log_src(design, mod, indent); for (auto &it : mod->attributes) @@ -79,7 +79,7 @@ struct PrintAttrsPass : public Pass { } for (auto cell : mod->selected_cells()) { - log("%s%s\n", get_indent_str(indent), cell->name.unescape()); + log("%s%s\n", get_indent_str(indent), cell->module->design->twines.str(cell->meta_->name)); indent += 2; log_src(design, cell, indent); for (auto &it : cell->attributes) diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index 56d2bb830..bb36ac137 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -30,15 +30,17 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std:: from_name = RTLIL::escape_id(from_name); to_name = RTLIL::escape_id(to_name); - if (module->count_id(to_name)) - log_cmd_error("There is already an object `%s' in module `%s'.\n", RTLIL::unescape_id(to_name), module->name); + TwineRef to_ref = module->design->twines.lookup(to_name); + if (module->count_id(to_ref)) + log_cmd_error("There is already an object `%s' in module `%s'.\n", RTLIL::unescape_id(to_name), log_id(module)); - RTLIL::Wire *wire_to_rename = module->wire(from_name); - RTLIL::Cell *cell_to_rename = module->cell(from_name); + TwineRef from_ref = module->design->twines.lookup(from_name); + RTLIL::Wire *wire_to_rename = module->wire(from_ref); + RTLIL::Cell *cell_to_rename = module->cell(from_ref); if (wire_to_rename != nullptr) { - log("Renaming wire %s to %s in module %s.\n", wire_to_rename, RTLIL::unescape_id(to_name), module); - module->rename(wire_to_rename, to_name); + log("Renaming wire %s to %s in module %s.\n", log_id(wire_to_rename), RTLIL::unescape_id(to_name), log_id(module)); + module->rename(wire_to_rename, module->design->twines.add(Twine{to_name})); if (wire_to_rename->port_id || flag_output) { if (flag_output) wire_to_rename->port_output = true; @@ -50,8 +52,8 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std:: if (cell_to_rename != nullptr) { if (flag_output) log_cmd_error("Called with -output but the specified object is a cell.\n"); - log("Renaming cell %s to %s in module %s.\n", cell_to_rename, RTLIL::unescape_id(to_name), module); - module->rename(cell_to_rename, to_name); + log("Renaming cell %s to %s in module %s.\n", log_id(cell_to_rename), RTLIL::unescape_id(to_name), log_id(module)); + module->rename(cell_to_rename, module->design->twines.add(Twine{to_name})); return; } @@ -105,8 +107,11 @@ static IdString derive_name_from_cell_output_wire(const RTLIL::Cell *cell, strin RTLIL::Wire *wire; - if (move_to_cell && (!(wire = cell->module->wire(name)) || !(wire->port_input || wire->port_output))) - return name; + if (move_to_cell) { + TwineRef name_ref = cell->module->design->twines.lookup(name); + if (name_ref == Twine::Null || (!(wire = cell->module->wire(name_ref)) || !(wire->port_input || wire->port_output))) + return name; + } if (suffix.empty()) { suffix = cell->type.str(); @@ -138,7 +143,7 @@ static bool rename_witness(RTLIL::Design *design, dict &ca for (auto &c : name) if ((c < 'a' || c > 'z') && (c < 'A' || c > 'Z') && (c < '0' || c > '9') && c != '_') c = '_'; - auto new_id = module->uniquify("\\_witness_." + name); + auto new_id = ID(module->design->twines.str(module->uniquify(module->design->twines.add(Twine{"\\_witness_." + name})))); cell->set_hdlname_attribute({ "_witness_", strstr(new_id.c_str(), ".") + 1 }); renames.emplace_back(cell, new_id); } @@ -152,7 +157,7 @@ static bool rename_witness(RTLIL::Design *design, dict &ca QY = (clk2fflogic = cell->get_bool_attribute(ID(clk2fflogic))) ? ID::D : ID::Q; else QY = ID::Y; - auto sig_out = cell->getPort(QY); + auto sig_out = cell->getPort(QY == ID::D ? TW::D : (QY == ID::Q ? TW::Q : TW::Y)); for (auto chunk : sig_out.chunks()) { if (chunk.is_wire() && !chunk.wire->name.isPublic()) { @@ -160,14 +165,14 @@ static bool rename_witness(RTLIL::Design *design, dict &ca for (auto &c : name) if ((c < 'a' || c > 'z') && (c < 'A' || c > 'Z') && (c < '0' || c > '9') && c != '_') c = '_'; - auto new_id = module->uniquify("\\_witness_." + name); - auto new_wire = module->addWire(new_id, GetSize(sig_out)); + auto new_id = ID(module->design->twines.str(module->uniquify(module->design->twines.add(Twine{"\\_witness_." + name})))); + auto new_wire = module->addWire(Twine{new_id.str()}, GetSize(sig_out)); new_wire->set_hdlname_attribute({ "_witness_", strstr(new_id.c_str(), ".") + 1 }); if (clk2fflogic) module->connect({new_wire, sig_out}); else module->connect({sig_out, new_wire}); - cell->setPort(QY, new_wire); + cell->setPort(QY == ID::D ? TW::D : (QY == ID::Q ? TW::Q : TW::Y), new_wire); break; } } @@ -182,20 +187,20 @@ static bool rename_witness(RTLIL::Design *design, dict &ca for (auto &c : name) if ((c < 'a' || c > 'z') && (c < 'A' || c > 'Z') && (c < '0' || c > '9') && c != '_') c = '_'; - auto new_id = module->uniquify("\\_witness_." + name); + auto new_id = ID(module->design->twines.str(module->uniquify(module->design->twines.add(Twine{"\\_witness_." + name})))); renames.emplace_back(cell, new_id); cell->set_hdlname_attribute({ "_witness_", strstr(new_id.c_str(), ".") + 1 }); } } for (auto rename : renames) { - module->rename(rename.first, rename.second); + module->rename(rename.first, module->design->twines.add(Twine{rename.second.str()})); } cache[module] = has_witness_signals; return has_witness_signals; } -static std::string renamed_unescaped(const std::string& str) +[[maybe_unused]] static std::string renamed_unescaped(const std::string& str) { std::string new_str = ""; @@ -400,10 +405,10 @@ struct RenamePass : public Pass { new_cell_names.emplace(cell, derive_name_from_src(cell->get_src_attribute(), counter++)); for (auto &it : new_wire_names) - module->rename(it.first, it.second); + module->rename(it.first, module->design->twines.add(Twine{it.second.str()})); for (auto &it : new_cell_names) - module->rename(it.first, it.second); + module->rename(it.first, module->design->twines.add(Twine{it.second.str()})); } } else @@ -418,22 +423,23 @@ struct RenamePass : public Pass { new_cell_names[cell] = derive_name_from_cell_output_wire(cell, cell_suffix, flag_move_to_cell); for (auto &[cell, new_name] : new_cell_names) { if (flag_move_to_cell) { - RTLIL::Wire *found_wire = module->wire(new_name); + TwineRef new_name_ref = module->design->twines.lookup(new_name.str()); + RTLIL::Wire *found_wire = new_name_ref != Twine::Null ? module->wire(new_name_ref) : nullptr; if (found_wire) { std::string wire_suffix = cell_suffix; if (wire_suffix.empty()) { for (auto const &[port, _] : cell->connections()) { if (cell->output(port)) { - wire_suffix += stringf("%s.%s", cell->type, port.c_str() + 1); + wire_suffix += stringf("%s.%s", cell->type, module->design->twines.str(port).c_str() + 1); break; } } } - IdString new_wire_name = found_wire->name.str() + wire_suffix; - module->rename(found_wire, new_wire_name); + IdString new_wire_name_id = ID(found_wire->name.str() + wire_suffix); + module->rename(found_wire, module->design->twines.add(Twine{new_wire_name_id.str()})); } } - module->rename(cell, new_name); + module->rename(cell, module->design->twines.add(Twine{new_name.str()})); } } } @@ -451,24 +457,30 @@ struct RenamePass : public Pass { for (auto wire : module->selected_wires()) if (wire->name[0] == '$') { RTLIL::IdString buf; - do buf = stringf("\\%s%d%s", pattern_prefix, counter++, pattern_suffix); - while (module->wire(buf) != nullptr); + TwineRef buf_ref; + do { + buf = stringf("\\%s%d%s", pattern_prefix, counter++, pattern_suffix); + buf_ref = module->design->twines.lookup(buf.str()); + } while (buf_ref != Twine::Null && module->wire(buf_ref) != nullptr); new_wire_names[wire] = buf; } for (auto cell : module->selected_cells()) if (cell->name[0] == '$') { RTLIL::IdString buf; - do buf = stringf("\\%s%d%s", pattern_prefix, counter++, pattern_suffix); - while (module->cell(buf) != nullptr); + TwineRef buf_ref; + do { + buf = stringf("\\%s%d%s", pattern_prefix, counter++, pattern_suffix); + buf_ref = module->design->twines.lookup(buf.str()); + } while (buf_ref != Twine::Null && module->cell(buf_ref) != nullptr); new_cell_names[cell] = buf; } for (auto &it : new_wire_names) - module->rename(it.first, it.second); + module->rename(it.first, module->design->twines.add(Twine{it.second.str()})); for (auto &it : new_cell_names) - module->rename(it.first, it.second); + module->rename(it.first, module->design->twines.add(Twine{it.second.str()})); } } else @@ -503,10 +515,10 @@ struct RenamePass : public Pass { new_cell_names[cell] = NEW_ID; for (auto &it : new_wire_names) - module->rename(it.first, it.second); + module->rename(it.first, module->design->twines.add(Twine{it.second.str()})); for (auto &it : new_cell_names) - module->rename(it.first, it.second); + module->rename(it.first, module->design->twines.add(Twine{it.second.str()})); } } else @@ -521,8 +533,8 @@ struct RenamePass : public Pass { if (module == nullptr) log_cmd_error("No top module found!\n"); - log("Renaming module %s to %s.\n", module, new_name.unescape()); - design->rename(module, new_name); + log("Renaming module %s to %s.\n", log_id(module), new_name.unescape()); + design->rename(module, design->twines.add(Twine{new_name.str()})); } else if (flag_scramble_name) @@ -554,10 +566,10 @@ struct RenamePass : public Pass { } for (auto &it : new_wire_names) - module->rename(it.first, it.second); + module->rename(it.first, module->design->twines.add(Twine{it.second.str()})); for (auto &it : new_cell_names) - module->rename(it.first, it.second); + module->rename(it.first, module->design->twines.add(Twine{it.second.str()})); } } else if (flag_unescape) @@ -576,7 +588,7 @@ struct RenamePass : public Pass { name = name.substr(1); if (!VERILOG_BACKEND::id_is_verilog_escaped(name)) continue; - new_wire_names[wire] = module->uniquify("\\" + renamed_unescaped(name)); + new_wire_names[wire] = ID(module->design->twines.str(module->uniquify(module->design->twines.add(Twine{"\\" + renamed_unescaped(name)})))); auto new_name = new_wire_names[wire].str().substr(1); if (VERILOG_BACKEND::id_is_verilog_escaped(new_name)) log_error("Failed to rename wire %s -> %s\n", name, new_name); @@ -589,17 +601,17 @@ struct RenamePass : public Pass { name = name.substr(1); if (!VERILOG_BACKEND::id_is_verilog_escaped(name)) continue; - new_cell_names[cell] = module->uniquify("\\" + renamed_unescaped(name)); + new_cell_names[cell] = ID(module->design->twines.str(module->uniquify(module->design->twines.add(Twine{"\\" + renamed_unescaped(name)})))); auto new_name = new_cell_names[cell].str().substr(1); if (VERILOG_BACKEND::id_is_verilog_escaped(new_name)) log_error("Failed to rename cell %s -> %s\n", name, new_name); } for (auto &it : new_wire_names) - module->rename(it.first, it.second); + module->rename(it.first, module->design->twines.add(Twine{it.second.str()})); for (auto &it : new_cell_names) - module->rename(it.first, it.second); + module->rename(it.first, module->design->twines.add(Twine{it.second.str()})); module->fixup_ports(); } @@ -612,7 +624,7 @@ struct RenamePass : public Pass { std::string from_name = args[argidx++]; std::string to_name = args[argidx++]; - if (!design->selected_active_module.empty()) + if (design->selected_active_module != Twine::Null) { if (design->module(design->selected_active_module) != nullptr) rename_in_module(design->module(design->selected_active_module), from_name, to_name, flag_output); @@ -623,16 +635,18 @@ struct RenamePass : public Pass { log_cmd_error("Mode -output requires that there is an active module selected.\n"); RTLIL::Module *module_to_rename = nullptr; - for (auto module : design->modules()) - if (module->name == from_name || module->name.unescape() == from_name) { + for (auto module : design->modules()) { + std::string module_name_str = module->design->twines.str(module->meta_->name); + if (module_name_str == from_name || RTLIL::unescape_id(module_name_str) == from_name) { module_to_rename = module; break; } + } if (module_to_rename != nullptr) { to_name = RTLIL::escape_id(to_name); - log("Renaming module %s to %s.\n", module_to_rename->name, to_name); - design->rename(module_to_rename, to_name); + log("Renaming module %s to %s.\n", log_id(module_to_rename), to_name); + design->rename(module_to_rename, design->twines.add(Twine{to_name})); } else log_cmd_error("Object `%s' not found!\n", from_name); } diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc index 3657eb3a4..c2f99d792 100644 --- a/passes/cmds/scatter.cc +++ b/passes/cmds/scatter.cc @@ -49,7 +49,7 @@ struct ScatterPass : public Pass { for (auto module : design->selected_modules()) { for (auto cell : module->cells()) { - dict new_connections; + dict new_connections; for (auto conn : cell->connections()) new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_TWINE, GetSize(conn.second)))); for (auto &it : new_connections) { diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 2abcc857a..90a2706ea 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -101,7 +101,7 @@ struct SccWorker design(design), module(module), sigmap(module) { if (module->processes.size() > 0) { - log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name); + log("Skipping module %s as it contains processes (run 'proc' pass first).\n", log_id(module)); return; } @@ -154,16 +154,16 @@ struct SccWorker for (auto bit : subcell->getPort(TW::SRC)) { - if (!bit.wire || !cell->hasPort(bit.wire->name)) + if (!bit.wire || !cell->hasPort(bit.wire->meta_->name)) continue; - inputSignals.append(sigmap(cell->getPort(bit.wire->name))); + inputSignals.append(sigmap(cell->getPort(bit.wire->meta_->name))); } for (auto bit : subcell->getPort(TW::DST)) { - if (!bit.wire || !cell->hasPort(bit.wire->name)) + if (!bit.wire || !cell->hasPort(bit.wire->meta_->name)) continue; - outputSignals.append(sigmap(cell->getPort(bit.wire->name))); + outputSignals.append(sigmap(cell->getPort(bit.wire->meta_->name))); } } } else { @@ -221,7 +221,7 @@ struct SccWorker run(cell, 0, maxDepth); } - log("Found %d SCCs in module %s.\n", int(sccList.size()), module); + log("Found %d SCCs in module %s.\n", int(sccList.size()), log_id(module)); } void select(RTLIL::Selection &sel) @@ -232,7 +232,7 @@ struct SccWorker RTLIL::SigSpec prevsig, nextsig, sig; for (auto cell : cells) { - sel.selected_members[module->name].insert(cell->name); + sel.selected_members[module->meta_->name].insert(cell->meta_->name); prevsig.append(cellToPrevSig[cell]); nextsig.append(cellToNextSig[cell]); } @@ -243,7 +243,7 @@ struct SccWorker for (auto &chunk : sig.chunks()) if (chunk.wire != NULL) - sel.selected_members[module->name].insert(chunk.wire->name); + sel.selected_members[module->meta_->name].insert(chunk.wire->meta_->name); } } }; diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 98ae7adae..69966ecb1 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -168,7 +168,7 @@ static void select_all(RTLIL::Design *design, RTLIL::Selection &lhs) for (auto mod : design->modules()) { if (!lhs.selects_boxes && mod->get_blackbox_attribute()) continue; - lhs.selected_modules.insert(mod->name); + lhs.selected_modules.insert(mod->meta_->name); } lhs.full_selection = false; lhs.complete_selection = false; @@ -195,25 +195,25 @@ static void select_op_neg(RTLIL::Design *design, RTLIL::Selection &lhs) { if (!lhs.selects_boxes && mod->get_blackbox_attribute()) continue; - if (lhs.selected_whole_module(mod->name)) + if (lhs.selected_whole_module(mod->meta_->name)) continue; - if (!lhs.selected_module(mod->name)) { - new_sel.selected_modules.insert(mod->name); + if (!lhs.selected_module(mod->meta_->name)) { + new_sel.selected_modules.insert(mod->meta_->name); continue; } for (auto wire : mod->wires()) - if (!lhs.selected_member(mod->name, wire->name)) - new_sel.selected_members[mod->name].insert(wire->name); + if (!lhs.selected_member(mod->meta_->name, wire->meta_->name)) + new_sel.selected_members[mod->meta_->name].insert(wire->meta_->name); for (auto &it : mod->memories) - if (!lhs.selected_member(mod->name, it.first)) - new_sel.selected_members[mod->name].insert(it.first); + if (!lhs.selected_member(mod->meta_->name, it.first)) + new_sel.selected_members[mod->meta_->name].insert(it.first); for (auto cell : mod->cells()) - if (!lhs.selected_member(mod->name, cell->name)) - new_sel.selected_members[mod->name].insert(cell->name); + if (!lhs.selected_member(mod->meta_->name, cell->meta_->name)) + new_sel.selected_members[mod->meta_->name].insert(cell->meta_->name); for (auto &it : mod->processes) - if (!lhs.selected_member(mod->name, it.first)) - new_sel.selected_members[mod->name].insert(it.first); + if (!lhs.selected_member(mod->meta_->name, it.first)) + new_sel.selected_members[mod->meta_->name].insert(it.first); } lhs.selected_modules.swap(new_sel.selected_modules); @@ -230,21 +230,21 @@ static int my_xorshift32_rng() { static void select_op_random(RTLIL::Design *design, RTLIL::Selection &lhs, int count) { - vector> objects; + vector> objects; for (auto mod : design->modules()) { - if (!lhs.selected_module(mod->name)) + if (!lhs.selected_module(mod->meta_->name)) continue; for (auto cell : mod->cells()) { - if (lhs.selected_member(mod->name, cell->name)) - objects.push_back(make_pair(RTLIL::IdString(mod->name), RTLIL::IdString(cell->name))); + if (lhs.selected_member(mod->meta_->name, cell->meta_->name)) + objects.push_back(make_pair(mod->meta_->name, cell->meta_->name)); } for (auto wire : mod->wires()) { - if (lhs.selected_member(mod->name, wire->name)) - objects.push_back(make_pair(RTLIL::IdString(mod->name), RTLIL::IdString(wire->name))); + if (lhs.selected_member(mod->meta_->name, wire->meta_->name)) + objects.push_back(make_pair(mod->meta_->name, wire->meta_->name)); } } @@ -265,13 +265,13 @@ static void select_op_submod(RTLIL::Design *design, RTLIL::Selection &lhs) { for (auto mod : design->modules()) { - if (lhs.selected_whole_module(mod->name)) + if (lhs.selected_whole_module(mod->meta_->name)) { for (auto cell : mod->cells()) { if (design->module(cell->type) == nullptr) continue; - lhs.selected_modules.insert(cell->type); + lhs.selected_modules.insert(design->twines.add(Twine{cell->type.str()})); } } } @@ -281,10 +281,10 @@ static void select_op_cells_to_modules(RTLIL::Design *design, RTLIL::Selection & { RTLIL::Selection new_sel(false, lhs.selects_boxes, design); for (auto mod : design->modules()) - if (lhs.selected_module(mod->name)) + if (lhs.selected_module(mod->meta_->name)) for (auto cell : mod->cells()) - if (lhs.selected_member(mod->name, cell->name) && (design->module(cell->type) != nullptr)) - new_sel.selected_modules.insert(cell->type); + if (lhs.selected_member(mod->meta_->name, cell->meta_->name) && (design->module(cell->type) != nullptr)) + new_sel.selected_modules.insert(design->twines.add(Twine{cell->type.str()})); lhs = new_sel; } @@ -293,8 +293,8 @@ static void select_op_module_to_cells(RTLIL::Design *design, RTLIL::Selection &l RTLIL::Selection new_sel(false, lhs.selects_boxes, design); for (auto mod : design->modules()) for (auto cell : mod->cells()) - if ((design->module(cell->type) != nullptr) && lhs.selected_whole_module(cell->type)) - new_sel.selected_members[mod->name].insert(cell->name); + if ((design->module(cell->type) != nullptr) && lhs.selected_whole_module(design->twines.add(Twine{cell->type.str()}))) + new_sel.selected_members[mod->meta_->name].insert(cell->meta_->name); lhs = new_sel; } @@ -312,21 +312,21 @@ static void select_op_alias(RTLIL::Design *design, RTLIL::Selection &lhs) { if (!lhs.selects_boxes && mod->get_blackbox_attribute()) continue; - if (lhs.selected_whole_module(mod->name)) + if (lhs.selected_whole_module(mod->meta_->name)) continue; - if (!lhs.selected_module(mod->name)) + if (!lhs.selected_module(mod->meta_->name)) continue; SigMap sigmap(mod); SigPool selected_bits; for (auto wire : mod->wires()) - if (lhs.selected_member(mod->name, wire->name)) + if (lhs.selected_member(mod->meta_->name, wire->meta_->name)) selected_bits.add(sigmap(wire)); for (auto wire : mod->wires()) - if (!lhs.selected_member(mod->name, wire->name) && selected_bits.check_any(sigmap(wire))) - lhs.selected_members[mod->name].insert(wire->name); + if (!lhs.selected_member(mod->meta_->name, wire->meta_->name) && selected_bits.check_any(sigmap(wire))) + lhs.selected_members[mod->meta_->name].insert(wire->meta_->name); } } @@ -411,24 +411,24 @@ static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const R RTLIL::Module *mod = design->module(it.first); - if (lhs.selected_modules.count(mod->name) > 0) + if (lhs.selected_modules.count(mod->meta_->name) > 0) { for (auto wire : mod->wires()) - lhs.selected_members[mod->name].insert(wire->name); + lhs.selected_members[mod->meta_->name].insert(wire->meta_->name); for (auto &it : mod->memories) - lhs.selected_members[mod->name].insert(it.first); + lhs.selected_members[mod->meta_->name].insert(it.first); for (auto cell : mod->cells()) - lhs.selected_members[mod->name].insert(cell->name); + lhs.selected_members[mod->meta_->name].insert(cell->meta_->name); for (auto &it : mod->processes) - lhs.selected_members[mod->name].insert(it.first); - lhs.selected_modules.erase(mod->name); + lhs.selected_members[mod->meta_->name].insert(it.first); + lhs.selected_modules.erase(mod->meta_->name); } - if (lhs.selected_members.count(mod->name) == 0) + if (lhs.selected_members.count(mod->meta_->name) == 0) continue; for (auto &it2 : it.second) - lhs.selected_members[mod->name].erase(it2); + lhs.selected_members[mod->meta_->name].erase(it2); } } @@ -513,14 +513,14 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v bool is_input, is_output; for (auto mod : design->modules()) { - if (lhs.selected_whole_module(mod->name) || !lhs.selected_module(mod->name)) + if (lhs.selected_whole_module(mod->meta_->name) || !lhs.selected_module(mod->meta_->name)) continue; std::set selected_wires; - auto selected_members = lhs.selected_members[mod->name]; + auto selected_members = lhs.selected_members[mod->meta_->name]; for (auto wire : mod->wires()) - if (lhs.selected_member(mod->name, wire->name) && limits.count(wire->name) == 0) + if (lhs.selected_member(mod->meta_->name, wire->meta_->name) && limits.count(wire->meta_->name) == 0) selected_wires.insert(wire); for (auto &conn : mod->connections()) @@ -531,10 +531,10 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v for (size_t i = 0; i < conn_lhs.size(); i++) { if (conn_lhs[i].wire == nullptr || conn_rhs[i].wire == nullptr) continue; - if (mode != 'i' && selected_wires.count(conn_rhs[i].wire) && selected_members.count(conn_lhs[i].wire->name) == 0) - lhs.selected_members[mod->name].insert(conn_lhs[i].wire->name), sel_objects++, max_objects--; - if (mode != 'o' && selected_wires.count(conn_lhs[i].wire) && selected_members.count(conn_rhs[i].wire->name) == 0) - lhs.selected_members[mod->name].insert(conn_rhs[i].wire->name), sel_objects++, max_objects--; + if (mode != 'i' && selected_wires.count(conn_rhs[i].wire) && selected_members.count(conn_lhs[i].wire->meta_->name) == 0) + lhs.selected_members[mod->meta_->name].insert(conn_lhs[i].wire->meta_->name), sel_objects++, max_objects--; + if (mode != 'o' && selected_wires.count(conn_lhs[i].wire) && selected_members.count(conn_rhs[i].wire->meta_->name) == 0) + lhs.selected_members[mod->meta_->name].insert(conn_rhs[i].wire->meta_->name), sel_objects++, max_objects--; } } diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc index 9491ef19b..787ba4d01 100644 --- a/passes/cmds/setattr.cc +++ b/passes/cmds/setattr.cc @@ -253,10 +253,10 @@ struct ChparamPass : public Pass { return; } - pool modnames, old_modnames; + pool modnames, old_modnames; for (auto module : design->selected_whole_modules_warn()) { - modnames.insert(module->name); - old_modnames.insert(module->name); + modnames.insert(module->meta_->name); + old_modnames.insert(module->meta_->name); } modnames.sort(); @@ -265,11 +265,11 @@ struct ChparamPass : public Pass { Module *new_module = design->module(module->derive(design, new_parameters)); if (module != new_module) { Module *m = new_module->clone(); - m->name = module->name; + m->meta_->name = module->meta_->name; design->remove(module); design->add(m); } - if (old_modnames.count(new_module->name) == 0) + if (old_modnames.count(new_module->meta_->name) == 0) design->remove(new_module); } } diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 5fc72a1ae..d11455097 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -347,9 +347,9 @@ struct SetundefPass : public Pass { for (auto &c : sig.chunks()) { RTLIL::SigSpec bits; if (worker.next_bit_mode == MODE_ANYSEQ) - bits = module->Anyseq(NEW_ID, c.width); + bits = module->Anyseq(NEW_TWINE, c.width); else if (worker.next_bit_mode == MODE_ANYCONST) - bits = module->Anyconst(NEW_ID, c.width); + bits = module->Anyconst(NEW_TWINE, c.width); else for (int i = 0; i < c.width; i++) bits.append(worker.next_bit()); @@ -547,9 +547,9 @@ struct SetundefPass : public Pass { if (width > 0) { if (worker.next_bit_mode == MODE_ANYSEQ) - sig.replace(cursor, module->Anyseq(NEW_ID, width)); + sig.replace(cursor, module->Anyseq(NEW_TWINE, width)); else - sig.replace(cursor, module->Anyconst(NEW_ID, width)); + sig.replace(cursor, module->Anyconst(NEW_TWINE, width)); cursor += width; } else { cursor++; diff --git a/passes/cmds/splitcells.cc b/passes/cmds/splitcells.cc index c7515725b..b42c47061 100644 --- a/passes/cmds/splitcells.cc +++ b/passes/cmds/splitcells.cc @@ -27,8 +27,8 @@ struct SplitcellsWorker { Module *module; SigMap sigmap; - dict> bit_drivers_db; - dict>> bit_users_db; + dict> bit_drivers_db; + dict>> bit_users_db; SplitcellsWorker(Module *module) : module(module), sigmap(module) { @@ -37,7 +37,7 @@ struct SplitcellsWorker if (!cell->output(conn.first)) continue; for (int i = 0; i < GetSize(conn.second); i++) { SigBit bit(sigmap(conn.second[i])); - bit_drivers_db[bit] = tuple(cell->name, conn.first, i); + bit_drivers_db[bit] = tuple(cell->meta_->name, conn.first, i); } } } @@ -48,7 +48,7 @@ struct SplitcellsWorker for (int i = 0; i < GetSize(conn.second); i++) { SigBit bit(sigmap(conn.second[i])); if (!bit_drivers_db.count(bit)) continue; - bit_users_db[bit].insert(tuple(cell->name, + bit_users_db[bit].insert(tuple(cell->meta_->name, conn.first, i-std::get<2>(bit_drivers_db[bit]))); } } @@ -60,8 +60,8 @@ struct SplitcellsWorker for (int i = 0; i < GetSize(sig); i++) { SigBit bit(sig[i]); if (!bit_drivers_db.count(bit)) continue; - bit_users_db[bit].insert(tuple(wire->name, - IdString(), i-std::get<2>(bit_drivers_db[bit]))); + bit_users_db[bit].insert(tuple(wire->meta_->name, + Twine::Null, i-std::get<2>(bit_drivers_db[bit]))); } } } @@ -78,7 +78,7 @@ struct SplitcellsWorker int width = GetSize(outsig); width = std::min(width, GetSize(cell->getPort(TW::A))); - if (cell->hasPort(ID::B)) + if (cell->hasPort(TW::B)) width = std::min(width, GetSize(cell->getPort(TW::B))); for (int i = 1; i < width; i++) { @@ -95,9 +95,10 @@ struct SplitcellsWorker int slice_msb = slices[i]-1; int slice_lsb = slices[i-1]; - IdString slice_name = module->uniquify(cell->name.str() + (slice_msb == slice_lsb ? + std::string s = cell->name.str() + (slice_msb == slice_lsb ? stringf("%c%d%c", format[0], slice_lsb, format[1]) : - stringf("%c%d%c%d%c", format[0], slice_msb, format[2], slice_lsb, format[1]))); + stringf("%c%d%c%d%c", format[0], slice_msb, format[2], slice_lsb, format[1])); + TwineRef slice_name = module->uniquify(module->design->twines.add(Twine{s})); Cell *slice = module->addCell(slice_name, cell); @@ -114,7 +115,7 @@ struct SplitcellsWorker if (slice->hasParam(ID::A_WIDTH)) slice->setParam(ID::A_WIDTH, GetSize(slice->getPort(TW::A))); - if (slice->hasPort(ID::B)) { + if (slice->hasPort(TW::B)) { slice->setPort(TW::B, slice_signal(slice->getPort(TW::B))); if (slice->hasParam(ID::B_WIDTH)) slice->setParam(ID::B_WIDTH, GetSize(slice->getPort(TW::B))); @@ -136,7 +137,7 @@ struct SplitcellsWorker if (cell->type.in("$ff", "$dff", "$dffe", "$dffsr", "$dffsre", "$adff", "$adffe", "$aldff", "$aldffe", "$sdff", "$sdffce", "$sdffe", "$dlatch", "$dlatchsr", "$adlatch")) { - auto splitports = {ID::D, ID::Q, ID::AD, ID::SET, ID::CLR}; + auto splitports = {TW::D, TW::Q, TW::AD, TW::SET, TW::CLR}; auto splitparams = {ID::ARST_VALUE, ID::SRST_VALUE}; SigSpec outsig = sigmap(cell->getPort(TW::Q)); @@ -161,9 +162,11 @@ struct SplitcellsWorker int slice_msb = slices[i]-1; int slice_lsb = slices[i-1]; - IdString slice_name = module->uniquify(cell->name.str() + (slice_msb == slice_lsb ? + TwinePool twines = module->design->twines; + std::string s = cell->name.str() + (slice_msb == slice_lsb ? stringf("%c%d%c", format[0], slice_lsb, format[1]) : - stringf("%c%d%c%d%c", format[0], slice_msb, format[2], slice_lsb, format[1]))); + stringf("%c%d%c%d%c", format[0], slice_msb, format[2], slice_lsb, format[1])); + TwineRef slice_name = module->uniquify(twines.add(Twine{s})); Cell *slice = module->addCell(slice_name, cell); @@ -185,7 +188,7 @@ struct SplitcellsWorker slice->setParam(ID::WIDTH, GetSize(slice->getPort(TW::Q))); - log(" slice %d: %s => %s\n", i, slice_name.unescape(), log_signal(slice->getPort(TW::Q))); + log(" slice %d: %s => %s\n", i, twines.str(slice_name), log_signal(slice->getPort(TW::Q))); } module->remove(cell); diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index f943127de..dd7b3c616 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -55,7 +55,7 @@ struct SplitnetsWorker if (format.size() > 1) new_wire_name += format.substr(1, 1); - RTLIL::Wire *new_wire = module->addWire(module->uniquify(new_wire_name), width); + RTLIL::Wire *new_wire = module->addWire(module->uniquify(module->design->twines.add(Twine{new_wire_name})), width); new_wire->port_id = wire->port_id ? wire->port_id + offset : 0; new_wire->port_input = wire->port_input; new_wire->port_output = wire->port_output; @@ -149,7 +149,7 @@ struct SplitnetsPass : public Pass { design->sigNormalize(false); // module_ports_db[module_name][old_port_name] = new_port_name_list - dict>> module_ports_db; + dict>> module_ports_db; for (auto module : design->selected_modules()) { @@ -239,10 +239,10 @@ struct SplitnetsPass : public Pass { if (sig == wire) continue; - vector &new_ports = module_ports_db[module->name][wire->name]; + vector &new_ports = module_ports_db[module->design->twines.str(module->meta_->name)][wire->meta_->name]; for (SigSpec c : sig.chunks()) - new_ports.push_back(c.as_wire()->name); + new_ports.push_back(c.as_wire()->meta_->name); } } @@ -265,7 +265,7 @@ struct SplitnetsPass : public Pass { for (auto &it : module_ports_db.at(cell->type)) { - IdString port_id = it.first; + TwineRef port_id = it.first; const auto &new_port_ids = it.second; if (!cell->hasPort(port_id)) diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index 020b5ffbb..e4a915f3f 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -190,9 +190,9 @@ struct statdata_t { ID($xor), ID($xnor), ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx), ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt), ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow), ID($alu))) { - int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(TW::A)) : 0; - int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(TW::B)) : 0; - int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(TW::Y)) : 0; + int width_a = cell->hasPort(TW::A) ? GetSize(cell->getPort(TW::A)) : 0; + int width_b = cell->hasPort(TW::B) ? GetSize(cell->getPort(TW::B)) : 0; + int width_y = cell->hasPort(TW::Y) ? GetSize(cell->getPort(TW::Y)) : 0; cell_type = stringf("%s_%d", cell_type, max({width_a, width_b, width_y})); } else if (cell_type.in(ID($mux))) cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Y))); @@ -215,10 +215,10 @@ struct statdata_t { if (cell_data.single_parameter_area.size() > 0) { // assume that we just take the max of the A,B,Y ports - int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(TW::A)) : 0; - int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(TW::B)) : 0; - int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(TW::Y)) : 0; - int width_q = cell->hasPort(ID::Q) ? GetSize(cell->getPort(TW::Q)) : 0; + int width_a = cell->hasPort(TW::A) ? GetSize(cell->getPort(TW::A)) : 0; + int width_b = cell->hasPort(TW::B) ? GetSize(cell->getPort(TW::B)) : 0; + int width_y = cell->hasPort(TW::Y) ? GetSize(cell->getPort(TW::Y)) : 0; + int width_q = cell->hasPort(TW::Q) ? GetSize(cell->getPort(TW::Q)) : 0; int max_width = max({width_a, width_b, width_y, width_q}); if (!cell_area.count(cell_type)) { cell_area[cell_type] = cell_data; diff --git a/passes/cmds/test_patch.cc b/passes/cmds/test_patch.cc index d7fae5d03..874610406 100644 --- a/passes/cmds/test_patch.cc +++ b/passes/cmds/test_patch.cc @@ -25,14 +25,14 @@ struct TestPatchPass : public Pass { log_assert(neg->type == ID($not)); RTLIL::Patch patcher(module, nullptr); int width = cell->getPort(TW::A).size(); - auto sub = patcher.addSub(NEW_ID, + auto sub = patcher.addSub(NEW_TWINE, neg->getPort(TW::A), add->getPort(TW::A), patcher.addWire(NEW_TWINE, width)); auto new_out_wire = patcher.addWire(NEW_TWINE, width); - auto new_cell = patcher.addNeg(NEW_ID, sub->getPort(TW::Y), new_out_wire); + auto new_cell = patcher.addNeg(NEW_TWINE, sub->getPort(TW::Y), new_out_wire); log_cell(new_cell); - patcher.patch(add, ID::Y, new_out_wire); + patcher.patch(add, TW::Y, new_out_wire); } } } diff --git a/passes/cmds/test_select.cc b/passes/cmds/test_select.cc index 4a3bbc539..557dda002 100644 --- a/passes/cmds/test_select.cc +++ b/passes/cmds/test_select.cc @@ -1,3 +1,4 @@ +#include "kernel/rtlil.h" #include "kernel/yosys.h" USING_YOSYS_NAMESPACE @@ -139,16 +140,16 @@ struct TestSelectPass : public Pass { // get sub selection and store the results auto sub_sel = design->selected_modules(partials, (RTLIL::SelectBoxes)boxes); - pool selected_modules; - dict> selected_members; + pool selected_modules; + dict> selected_members; for (auto *mod : sub_sel) { if (mod->is_selected_whole()) { log_debug(" Adding %s.\n", mod); - selected_modules.insert(mod->name); + selected_modules.insert(mod->meta_->name); } else for (auto *memb : mod->selected_members()) { log_debug(" Adding %s.%s.\n", mod, memb); - selected_members[mod->name].insert(memb); + selected_members[mod->meta_->name].insert(memb); } } diff --git a/passes/cmds/xprop.cc b/passes/cmds/xprop.cc index 330046cf0..9f51a6ae7 100644 --- a/passes/cmds/xprop.cc +++ b/passes/cmds/xprop.cc @@ -55,18 +55,18 @@ struct XpropWorker Module *module; void invert() { std::swap(is_0, is_1); } - void auto_0() { connect_0(module->Not(NEW_ID, module->Or(NEW_ID, is_1, is_x))); } - void auto_1() { connect_1(module->Not(NEW_ID, module->Or(NEW_ID, is_0, is_x))); } - void auto_x() { connect_x(module->Not(NEW_ID, module->Or(NEW_ID, is_0, is_1))); } + void auto_0() { connect_0(module->Not(NEW_ID, module->Or(NEW_TWINE, is_1, is_x))); } + void auto_1() { connect_1(module->Not(NEW_ID, module->Or(NEW_TWINE, is_0, is_x))); } + void auto_x() { connect_x(module->Not(NEW_ID, module->Or(NEW_TWINE, is_0, is_1))); } void connect_0(SigSpec sig) { module->connect(is_0, sig); } void connect_1(SigSpec sig) { module->connect(is_1, sig); } void connect_x(SigSpec sig) { module->connect(is_x, sig); } - void connect_1_under_x(SigSpec sig) { connect_1(module->And(NEW_ID, sig, module->Not(NEW_ID, is_x))); } - void connect_0_under_x(SigSpec sig) { connect_0(module->And(NEW_ID, sig, module->Not(NEW_ID, is_x))); } + void connect_1_under_x(SigSpec sig) { connect_1(module->And(NEW_ID, sig, module->Not(NEW_TWINE, is_x))); } + void connect_0_under_x(SigSpec sig) { connect_0(module->And(NEW_ID, sig, module->Not(NEW_TWINE, is_x))); } - void connect_x_under_0(SigSpec sig) { connect_x(module->And(NEW_ID, sig, module->Not(NEW_ID, is_0))); } + void connect_x_under_0(SigSpec sig) { connect_x(module->And(NEW_ID, sig, module->Not(NEW_TWINE, is_0))); } void connect_as_bool() { int width = GetSize(is_0); @@ -198,7 +198,7 @@ struct XpropWorker } if (!invert.empty() && !driving) - invert = module->Not(NEW_ID, invert); + invert = module->Not(NEW_TWINE, invert); EncodedSig new_sigs; if (new_bits > 0) { @@ -253,7 +253,7 @@ struct XpropWorker } if (!driven_orig.empty()) { - auto decoder = module->addBwmux(NEW_ID, driven_enc.is_1, Const(State::Sx, GetSize(driven_orig)), driven_enc.is_x, driven_orig); + auto decoder = module->addBwmux(NEW_TWINE, driven_enc.is_1, Const(State::Sx, GetSize(driven_orig)), driven_enc.is_x, driven_orig); decoder->set_bool_attribute(ID::xprop_decoder); } if (!driven_never_x.first.empty()) { @@ -261,21 +261,21 @@ struct XpropWorker } if (driving && (options.assert_encoding || options.assume_encoding)) { - auto not_0 = module->Not(NEW_ID, result.is_0); - auto not_1 = module->Not(NEW_ID, result.is_1); - auto not_x = module->Not(NEW_ID, result.is_x); - auto valid = module->ReduceAnd(NEW_ID, { - module->Eq(NEW_ID, result.is_0, module->And(NEW_ID, not_1, not_x)), - module->Eq(NEW_ID, result.is_1, module->And(NEW_ID, not_0, not_x)), - module->Eq(NEW_ID, result.is_x, module->And(NEW_ID, not_0, not_1)), + auto not_0 = module->Not(NEW_TWINE, result.is_0); + auto not_1 = module->Not(NEW_TWINE, result.is_1); + auto not_x = module->Not(NEW_TWINE, result.is_x); + auto valid = module->ReduceAnd(NEW_TWINE, { + module->Eq(NEW_ID, result.is_0, module->And(NEW_TWINE, not_1, not_x)), + module->Eq(NEW_ID, result.is_1, module->And(NEW_TWINE, not_0, not_x)), + module->Eq(NEW_ID, result.is_x, module->And(NEW_TWINE, not_0, not_1)), }); if (options.assert_encoding) - module->addAssert(NEW_ID_SUFFIX("xprop_enc"), valid, State::S1); + module->addAssert(NEW_TWINE_SUFFIX("xprop_enc"), valid, State::S1); else - module->addAssume(NEW_ID_SUFFIX("xprop_enc"), valid, State::S1); + module->addAssume(NEW_TWINE_SUFFIX("xprop_enc"), valid, State::S1); if (options.debug_asserts) { - auto bad_bits = module->Bweqx(NEW_ID, {result.is_0, result.is_1, result.is_x}, Const(State::Sx, GetSize(result) * 3)); - module->addAssert(NEW_ID_SUFFIX("xprop_debug"), module->LogicNot(NEW_ID, bad_bits), State::S1); + auto bad_bits = module->Bweqx(NEW_TWINE, {result.is_0, result.is_1, result.is_x}, Const(State::Sx, GetSize(result) * 3)); + module->addAssert(NEW_TWINE_SUFFIX("xprop_debug"), module->LogicNot(NEW_TWINE, bad_bits), State::S1); } } @@ -547,8 +547,8 @@ struct XpropWorker if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_))) enc_b.invert(); - enc_y.connect_0(module->Or(NEW_ID, enc_a.is_0, enc_b.is_0)); - enc_y.connect_1(module->And(NEW_ID, enc_a.is_1, enc_b.is_1)); + enc_y.connect_0(module->Or(NEW_TWINE, enc_a.is_0, enc_b.is_0)); + enc_y.connect_1(module->And(NEW_TWINE, enc_a.is_1, enc_b.is_1)); enc_y.auto_x(); module->remove(cell); return; @@ -568,8 +568,8 @@ struct XpropWorker if (cell->type == ID($logic_not)) enc_a.invert(); - enc_y.connect_0(module->ReduceOr(NEW_ID, enc_a.is_0)); - enc_y.connect_1(module->ReduceAnd(NEW_ID, enc_a.is_1)); + enc_y.connect_0(module->ReduceOr(NEW_TWINE, enc_a.is_0)); + enc_y.connect_1(module->ReduceAnd(NEW_TWINE, enc_a.is_1)); enc_y.auto_x(); module->remove(cell); @@ -588,8 +588,8 @@ struct XpropWorker enc_y.invert(); - enc_y.connect_x(module->ReduceOr(NEW_ID, enc_a.is_x)); - enc_y.connect_1_under_x(module->ReduceXor(NEW_ID, enc_a.is_1)); + enc_y.connect_x(module->ReduceOr(NEW_TWINE, enc_a.is_x)); + enc_y.connect_1_under_x(module->ReduceXor(NEW_TWINE, enc_a.is_1)); enc_y.auto_0(); module->remove(cell); @@ -607,16 +607,16 @@ struct XpropWorker enc_y.connect_as_bool(); - auto a_is_1 = module->ReduceOr(NEW_ID, enc_a.is_1); - auto a_is_0 = module->ReduceAnd(NEW_ID, enc_a.is_0); - auto b_is_1 = module->ReduceOr(NEW_ID, enc_b.is_1); - auto b_is_0 = module->ReduceAnd(NEW_ID, enc_b.is_0); + auto a_is_1 = module->ReduceOr(NEW_TWINE, enc_a.is_1); + auto a_is_0 = module->ReduceAnd(NEW_TWINE, enc_a.is_0); + auto b_is_1 = module->ReduceOr(NEW_TWINE, enc_b.is_1); + auto b_is_0 = module->ReduceAnd(NEW_TWINE, enc_b.is_0); if (cell->type == ID($logic_or)) enc_y.invert(), std::swap(a_is_0, a_is_1), std::swap(b_is_0, b_is_1); - enc_y.connect_0(module->Or(NEW_ID, a_is_0, b_is_0)); - enc_y.connect_1(module->And(NEW_ID, a_is_1, b_is_1)); + enc_y.connect_0(module->Or(NEW_TWINE, a_is_0, b_is_0)); + enc_y.connect_1(module->And(NEW_TWINE, a_is_1, b_is_1)); enc_y.auto_x(); module->remove(cell); return; @@ -638,8 +638,8 @@ struct XpropWorker if (cell->type.in(ID($xnor), ID($_XNOR_))) enc_y.invert(); - enc_y.connect_x(module->Or(NEW_ID, enc_a.is_x, enc_b.is_x)); - enc_y.connect_1_under_x(module->Xor(NEW_ID, enc_a.is_1, enc_b.is_1)); + enc_y.connect_x(module->Or(NEW_TWINE, enc_a.is_x, enc_b.is_x)); + enc_y.connect_1_under_x(module->Xor(NEW_TWINE, enc_a.is_1, enc_b.is_1)); enc_y.auto_0(); module->remove(cell); return; @@ -661,11 +661,11 @@ struct XpropWorker if (cell->type == ID($ne)) enc_y.invert(); - auto delta = module->Xor(NEW_ID, enc_a.is_1, enc_b.is_1); - auto xpos = module->Or(NEW_ID, enc_a.is_x, enc_b.is_x); + auto delta = module->Xor(NEW_TWINE, enc_a.is_1, enc_b.is_1); + auto xpos = module->Or(NEW_TWINE, enc_a.is_x, enc_b.is_x); - enc_y.connect_0(module->ReduceOr(NEW_ID, module->And(NEW_ID, delta, module->Not(NEW_ID, xpos)))); - enc_y.connect_x_under_0(module->ReduceOr(NEW_ID, xpos)); + enc_y.connect_0(module->ReduceOr(NEW_ID, module->And(NEW_ID, delta, module->Not(NEW_TWINE, xpos)))); + enc_y.connect_x_under_0(module->ReduceOr(NEW_TWINE, xpos)); enc_y.auto_1(); module->remove(cell); return; @@ -682,12 +682,12 @@ struct XpropWorker auto enc_a = encoded(sig_a); auto enc_b = encoded(sig_b); - auto delta_0 = module->Xnor(NEW_ID, enc_a.is_0, enc_b.is_0); - auto delta_1 = module->Xnor(NEW_ID, enc_a.is_1, enc_b.is_1); + auto delta_0 = module->Xnor(NEW_TWINE, enc_a.is_0, enc_b.is_0); + auto delta_1 = module->Xnor(NEW_TWINE, enc_a.is_1, enc_b.is_1); - auto eq = module->ReduceAnd(NEW_ID, {delta_0, delta_1}); + auto eq = module->ReduceAnd(NEW_TWINE, {delta_0, delta_1}); - auto res = cell->type == ID($nex) ? module->Not(NEW_ID, eq) : eq; + auto res = cell->type == ID($nex) ? module->Not(NEW_TWINE, eq) : eq; module->connect(sig_y[0], res); if (GetSize(sig_y) > 1) @@ -704,9 +704,9 @@ struct XpropWorker auto enc_a = encoded(sig_a); auto enc_b = encoded(sig_b); - auto delta_0 = module->Xnor(NEW_ID, enc_a.is_0, enc_b.is_0); - auto delta_1 = module->Xnor(NEW_ID, enc_a.is_1, enc_b.is_1); - module->addAnd(NEW_ID, delta_0, delta_1, sig_y); + auto delta_0 = module->Xnor(NEW_TWINE, enc_a.is_0, enc_b.is_0); + auto delta_1 = module->Xnor(NEW_TWINE, enc_a.is_1, enc_b.is_1); + module->addAnd(NEW_TWINE, delta_0, delta_1, sig_y); module->remove(cell); return; } @@ -725,12 +725,12 @@ struct XpropWorker auto enc_s = encoded(sig_s); auto enc_y = encoded(sig_y, true); - enc_y.connect_1(module->And(NEW_ID, - module->Or(NEW_ID, enc_a.is_1, enc_s.is_1), - module->Or(NEW_ID, enc_b.is_1, enc_s.is_0))); - enc_y.connect_0(module->And(NEW_ID, - module->Or(NEW_ID, enc_a.is_0, enc_s.is_1), - module->Or(NEW_ID, enc_b.is_0, enc_s.is_0))); + enc_y.connect_1(module->And(NEW_TWINE, + module->Or(NEW_TWINE, enc_a.is_1, enc_s.is_1), + module->Or(NEW_TWINE, enc_b.is_1, enc_s.is_0))); + enc_y.connect_0(module->And(NEW_TWINE, + module->Or(NEW_TWINE, enc_a.is_0, enc_s.is_1), + module->Or(NEW_TWINE, enc_b.is_0, enc_s.is_0))); enc_y.auto_x(); module->remove(cell); return; @@ -749,23 +749,23 @@ struct XpropWorker int width = GetSize(enc_y); - auto all_x = module->ReduceOr(NEW_ID, { + auto all_x = module->ReduceOr(NEW_TWINE, { enc_s.is_x, - module->And(NEW_ID, enc_s.is_1, module->Sub(NEW_ID, enc_s.is_1, Const(1, width))) + module->And(NEW_ID, enc_s.is_1, module->Sub(NEW_TWINE, enc_s.is_1, Const(1, width))) }); auto selected = enc_a; for (int i = 0; i < GetSize(enc_s); i++) { auto sel_bit = enc_s.is_1[i]; - selected.is_0 = module->Mux(NEW_ID, selected.is_0, enc_b.is_0.extract(i * width, width), sel_bit); - selected.is_1 = module->Mux(NEW_ID, selected.is_1, enc_b.is_1.extract(i * width, width), sel_bit); - selected.is_x = module->Mux(NEW_ID, selected.is_x, enc_b.is_x.extract(i * width, width), sel_bit); + selected.is_0 = module->Mux(NEW_TWINE, selected.is_0, enc_b.is_0.extract(i * width, width), sel_bit); + selected.is_1 = module->Mux(NEW_TWINE, selected.is_1, enc_b.is_1.extract(i * width, width), sel_bit); + selected.is_x = module->Mux(NEW_TWINE, selected.is_x, enc_b.is_x.extract(i * width, width), sel_bit); } - enc_y.connect_0(module->Mux(NEW_ID, selected.is_0, Const(State::S0, width), all_x)); - enc_y.connect_1(module->Mux(NEW_ID, selected.is_1, Const(State::S0, width), all_x)); - enc_y.connect_x(module->Mux(NEW_ID, selected.is_x, Const(State::S1, width), all_x)); + enc_y.connect_0(module->Mux(NEW_TWINE, selected.is_0, Const(State::S0, width), all_x)); + enc_y.connect_1(module->Mux(NEW_TWINE, selected.is_1, Const(State::S0, width), all_x)); + enc_y.connect_x(module->Mux(NEW_TWINE, selected.is_x, Const(State::S1, width), all_x)); module->remove(cell); return; @@ -780,8 +780,8 @@ struct XpropWorker auto enc_b = encoded(sig_b); auto enc_y = encoded(sig_y, true); - auto all_x = module->ReduceOr(NEW_ID, enc_b.is_x)[0]; - auto not_all_x = module->Not(NEW_ID, all_x)[0]; + auto all_x = module->ReduceOr(NEW_TWINE, enc_b.is_x)[0]; + auto not_all_x = module->Not(NEW_TWINE, all_x)[0]; SigSpec y_not_0 = module->addWire(NEW_TWINE, GetSize(sig_y)); SigSpec y_1 = module->addWire(NEW_TWINE, GetSize(sig_y)); @@ -795,7 +795,7 @@ struct XpropWorker auto shift_0 = module->addCell(NEW_TWINE, encoded_type); shift_0->parameters = cell->parameters; - shift_0->setPort(TW::A, module->Not(NEW_ID, enc_a.is_0)); + shift_0->setPort(TW::A, module->Not(NEW_TWINE, enc_a.is_0)); shift_0->setPort(TW::B, enc_b.is_1); shift_0->setPort(TW::Y, y_not_0); @@ -811,14 +811,14 @@ struct XpropWorker shift_x->setPort(TW::B, enc_b.is_1); shift_x->setPort(TW::Y, y_x); - SigSpec y_0 = module->Not(NEW_ID, y_not_0); + SigSpec y_0 = module->Not(NEW_TWINE, y_not_0); if (cell->type == ID($shiftx)) std::swap(y_0, y_x); - enc_y.connect_0(module->And(NEW_ID, y_0, SigSpec(not_all_x, GetSize(sig_y)))); - enc_y.connect_1(module->And(NEW_ID, y_1, SigSpec(not_all_x, GetSize(sig_y)))); - enc_y.connect_x(module->Or(NEW_ID, y_x, SigSpec(all_x, GetSize(sig_y)))); + enc_y.connect_0(module->And(NEW_TWINE, y_0, SigSpec(not_all_x, GetSize(sig_y)))); + enc_y.connect_1(module->And(NEW_TWINE, y_1, SigSpec(not_all_x, GetSize(sig_y)))); + enc_y.connect_x(module->Or(NEW_TWINE, y_x, SigSpec(all_x, GetSize(sig_y)))); module->remove(cell); return; @@ -844,8 +844,8 @@ struct XpropWorker auto data_q = module->addWire(NEW_TWINE, GetSize(sig_q)); - module->addFf(NEW_ID, enc_d.is_1, data_q); - module->addFf(NEW_ID, enc_d.is_x, enc_q.is_x); + module->addFf(NEW_TWINE, enc_d.is_1, data_q); + module->addFf(NEW_TWINE, enc_d.is_x, enc_q.is_x); initvals.set_init(data_q, init_q_is_1); initvals.set_init(enc_q.is_x, init_q_is_x); @@ -929,13 +929,13 @@ struct XpropWorker if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) { auto sig_b = cell->getPort(TW::B); - auto invalid = module->LogicNot(NEW_ID, sig_b); + auto invalid = module->LogicNot(NEW_TWINE, sig_b); inbits_x.append(invalid); - sig_b[0] = module->Or(NEW_ID, sig_b[0], invalid); + sig_b[0] = module->Or(NEW_TWINE, sig_b[0], invalid); cell->setPort(TW::B, sig_b); } - SigBit outbits_x = (GetSize(inbits_x) == 1 ? inbits_x : module->ReduceOr(NEW_ID, inbits_x)); + SigBit outbits_x = (GetSize(inbits_x) == 1 ? inbits_x : module->ReduceOr(NEW_TWINE, inbits_x)); bool bool_out = cell->type.in(ID($le), ID($lt), ID($ge), ID($gt)); @@ -1096,9 +1096,9 @@ struct XpropWorker it->second.driven = true; } - module->addBweqx(NEW_ID, orig, Const(State::S0, GetSize(orig)), enc.is_0); - module->addBweqx(NEW_ID, orig, Const(State::S1, GetSize(orig)), enc.is_1); - module->addBweqx(NEW_ID, orig, Const(State::Sx, GetSize(orig)), enc.is_x); + module->addBweqx(NEW_TWINE, orig, Const(State::S0, GetSize(orig)), enc.is_0); + module->addBweqx(NEW_TWINE, orig, Const(State::S1, GetSize(orig)), enc.is_1); + module->addBweqx(NEW_TWINE, orig, Const(State::Sx, GetSize(orig)), enc.is_x); } } }; @@ -1234,7 +1234,7 @@ struct XpropPass : public Pass { continue; if (wire->port_input) { - module->addAssume(NEW_ID, module->Not(NEW_ID, module->ReduceOr(NEW_ID, module->Bweqx(NEW_ID, wire, Const(State::Sx, GetSize(wire))))), State::S1); + module->addAssume(NEW_ID, module->Not(NEW_TWINE, module->ReduceOr(NEW_TWINE, module->Bweqx(NEW_TWINE, wire, Const(State::Sx, GetSize(wire))))), State::S1); } } } diff --git a/passes/equiv/equiv_add.cc b/passes/equiv/equiv_add.cc index d15f6f21a..492608e81 100644 --- a/passes/equiv/equiv_add.cc +++ b/passes/equiv/equiv_add.cc @@ -43,7 +43,7 @@ struct EquivAddPass : public Pass { { bool try_mode = false; - if (design->selected_active_module.empty()) + if (design->selected_active_module == Twine::Null) log_cmd_error("This command must be executed in module context!\n"); Module *module = design->module(design->selected_active_module); @@ -56,8 +56,8 @@ struct EquivAddPass : public Pass { if (GetSize(args) == 4 && args[1] == "-cell") { - Cell *gold_cell = module->cell(RTLIL::escape_id(args[2])); - Cell *gate_cell = module->cell(RTLIL::escape_id(args[3])); + Cell *gold_cell = module->cell(design->twines.lookup(RTLIL::escape_id(args[2]))); + Cell *gate_cell = module->cell(design->twines.lookup(RTLIL::escape_id(args[3]))); if (gold_cell == nullptr) { if (try_mode) { @@ -87,7 +87,7 @@ struct EquivAddPass : public Pass { SigSpec combined_sig = module->addWire(NEW_TWINE, width); for (int i = 0; i < width; i++) { - module->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], combined_sig[i]); + module->addEquiv(NEW_TWINE, gold_sig[i], gate_sig[i], combined_sig[i]); gold_sig[i] = gate_sig[i] = combined_sig[i]; } @@ -103,7 +103,7 @@ struct EquivAddPass : public Pass { SigSig gg_conn; for (int i = 0; i < width; i++) { - module->addEquiv(NEW_ID, new_gold_wire[i], new_gold_wire[i], gold_sig[i]); + module->addEquiv(NEW_TWINE, new_gold_wire[i], new_gold_wire[i], gold_sig[i]); gg_conn.first.append(gate_sig[i]); gg_conn.second.append(gold_sig[i]); gold_sig[i] = new_gold_wire[i]; @@ -151,7 +151,7 @@ struct EquivAddPass : public Pass { pool added_equiv_cells; for (int i = 0; i < GetSize(gold_signal); i++) { - Cell *equiv_cell = module->addEquiv(NEW_ID, gold_signal[i], gate_signal[i], equiv_signal[i]); + Cell *equiv_cell = module->addEquiv(NEW_TWINE, gold_signal[i], gate_signal[i], equiv_signal[i]); equiv_cell->set_bool_attribute(ID::keep); to_equiv_bits[gold_signal[i]] = equiv_signal[i]; to_equiv_bits[gate_signal[i]] = equiv_signal[i]; diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index ad911ad87..6338db54b 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -108,13 +108,13 @@ struct EquivMakeWorker for (auto it : gold_clone->wires().to_vector()) { if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0) wire_names.insert(it->name); - gold_clone->rename(it, it->name.str() + "_gold"); + gold_clone->rename(it, gold_clone->design->twines.add(Twine{it->name.str() + "_gold"})); } for (auto it : gold_clone->cells().to_vector()) { if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0) cell_names.insert(it->name); - gold_clone->rename(it, it->name.str() + "_gold"); + gold_clone->rename(it, gold_clone->design->twines.add(Twine{it->name.str() + "_gold"})); if (it->type.in(ID($input_port), ID($output_port), ID($public))) gold_clone->remove(it); } @@ -122,13 +122,13 @@ struct EquivMakeWorker for (auto it : gate_clone->wires().to_vector()) { if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0) wire_names.insert(it->name); - gate_clone->rename(it, it->name.str() + "_gate"); + gate_clone->rename(it, gate_clone->design->twines.add(Twine{it->name.str() + "_gate"})); } for (auto it : gate_clone->cells().to_vector()) { if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0) cell_names.insert(it->name); - gate_clone->rename(it, it->name.str() + "_gate"); + gate_clone->rename(it, gate_clone->design->twines.add(Twine{it->name.str() + "_gate"})); if (it->type.in(ID($input_port), ID($output_port), ID($public))) gate_clone->remove(it); } @@ -141,8 +141,8 @@ struct EquivMakeWorker void add_eq_assertion(const SigSpec &gold_sig, const SigSpec &gate_sig) { - auto eq_wire = equiv_mod->Eqx(NEW_ID, gold_sig, gate_sig); - equiv_mod->addAssert(NEW_ID_SUFFIX("assert"), eq_wire, State::S1); + auto eq_wire = equiv_mod->Eqx(NEW_TWINE, gold_sig, gate_sig); + equiv_mod->addAssert(NEW_TWINE_SUFFIX("assert"), eq_wire, State::S1); } void find_same_wires() @@ -156,8 +156,8 @@ struct EquivMakeWorker for (auto id : wire_names) { - IdString gold_id = id.str() + "_gold"; - IdString gate_id = id.str() + "_gate"; + TwineRef gold_id = equiv_mod->design->twines.lookup(id.str() + "_gold"); + TwineRef gate_id = equiv_mod->design->twines.lookup(id.str() + "_gate"); Wire *gold_wire = equiv_mod->wire(gold_id); Wire *gate_wire = equiv_mod->wire(gate_id); @@ -166,8 +166,8 @@ struct EquivMakeWorker { log("Creating encoder/decoder for signal %s.\n", id.unescape()); - Wire *dec_wire = equiv_mod->addWire(id.str() + "_decoded", gold_wire->width); - Wire *enc_wire = equiv_mod->addWire(id.str() + "_encoded", gate_wire->width); + Wire *dec_wire = equiv_mod->addWire(Twine{id.str() + "_decoded"}, gold_wire->width); + Wire *enc_wire = equiv_mod->addWire(Twine{id.str() + "_encoded"}, gate_wire->width); SigSpec dec_a, dec_b, dec_s; SigSpec enc_a, enc_b, enc_s; @@ -213,8 +213,8 @@ struct EquivMakeWorker SigSpec dec_eq = equiv_mod->addWire(NEW_TWINE); SigSpec enc_eq = equiv_mod->addWire(NEW_TWINE); - equiv_mod->addEq(NEW_ID, reduced_dec_sig, reduced_dec_pat, dec_eq); - cells_list.push_back(equiv_mod->addEq(NEW_ID, reduced_enc_sig, reduced_enc_pat, enc_eq)); + equiv_mod->addEq(NEW_TWINE, reduced_dec_sig, reduced_dec_pat, dec_eq); + cells_list.push_back(equiv_mod->addEq(NEW_TWINE, reduced_enc_sig, reduced_enc_pat, enc_eq)); dec_s.append(dec_eq); enc_s.append(enc_eq); @@ -222,8 +222,8 @@ struct EquivMakeWorker enc_b.append(enc_result); } - equiv_mod->addPmux(NEW_ID, dec_a, dec_b, dec_s, dec_wire); - equiv_mod->addPmux(NEW_ID, enc_a, enc_b, enc_s, enc_wire); + equiv_mod->addPmux(NEW_TWINE, dec_a, dec_b, dec_s, dec_wire); + equiv_mod->addPmux(NEW_TWINE, enc_a, enc_b, enc_s, enc_wire); rd_signal_map.add(assign_map(gate_wire), enc_wire); gate_wire = dec_wire; @@ -248,7 +248,7 @@ struct EquivMakeWorker gold_wire->port_output = false; gate_wire->port_output = false; - Wire *wire = equiv_mod->addWire(id, gold_wire->width); + Wire *wire = equiv_mod->addWire(Twine{id.str()}, gold_wire->width); wire->port_output = true; if (make_assert) @@ -259,7 +259,7 @@ struct EquivMakeWorker else { for (int i = 0; i < wire->width; i++) - equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i)); + equiv_mod->addEquiv(NEW_TWINE, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i)); } rd_signal_map.add(assign_map(gold_wire), wire); @@ -268,7 +268,7 @@ struct EquivMakeWorker else if (gold_wire->port_input || gate_wire->port_input) { - Wire *wire = equiv_mod->addWire(id, gold_wire->width); + Wire *wire = equiv_mod->addWire(Twine{id.str()}, gold_wire->width); wire->port_input = true; gold_wire->port_input = false; gate_wire->port_input = false; @@ -284,7 +284,7 @@ struct EquivMakeWorker add_eq_assertion(gold_wire, gate_wire); else { - Wire *wire = equiv_mod->addWire(id, gold_wire->width); + Wire *wire = equiv_mod->addWire(Twine{id.str()}, gold_wire->width); SigSpec rdmap_gold, rdmap_gate, rdmap_equiv; for (int i = 0; i < wire->width; i++) { @@ -296,7 +296,7 @@ struct EquivMakeWorker log(" Skipping signal bit %s [%d]: undriven on gate side.\n", gate_wire, i); continue; } - equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i)); + equiv_mod->addEquiv(NEW_TWINE, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i)); rdmap_gold.append(SigBit(gold_wire, i)); rdmap_gate.append(SigBit(gate_wire, i)); rdmap_equiv.append(SigBit(wire, i)); @@ -318,7 +318,7 @@ struct EquivMakeWorker new_sig[i] = old_sig[i]; if (old_sig != new_sig) { log("Changing input %s of cell %s (%s): %s -> %s\n", - conn.first.unescape(), c, c->type.unescape(), + equiv_mod->design->twines.str(conn.first).c_str(), c, c->type.unescape(), log_signal(old_sig), log_signal(new_sig)); c->setPort(conn.first, new_sig); } @@ -333,8 +333,8 @@ struct EquivMakeWorker for (auto id : cell_names) { - IdString gold_id = id.str() + "_gold"; - IdString gate_id = id.str() + "_gate"; + TwineRef gold_id = equiv_mod->design->twines.lookup(id.str() + "_gold"); + TwineRef gate_id = equiv_mod->design->twines.lookup(id.str() + "_gate"); Cell *gold_cell = equiv_mod->cell(gold_id); Cell *gate_cell = equiv_mod->cell(gate_id); @@ -371,7 +371,7 @@ struct EquivMakeWorker for (int i = 0; i < GetSize(gold_sig); i++) if (gold_sig[i] != gate_sig[i]) { Wire *w = equiv_mod->addWire(NEW_TWINE); - equiv_mod->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], w); + equiv_mod->addEquiv(NEW_TWINE, gold_sig[i], gate_sig[i], w); gold_sig[i] = w; } } @@ -380,7 +380,7 @@ struct EquivMakeWorker } equiv_mod->remove(gate_cell); - equiv_mod->rename(gold_cell, id); + equiv_mod->rename(gold_cell, equiv_mod->design->twines.lookup(id.str())); } } @@ -492,9 +492,9 @@ struct EquivMakePass : public Pass { if (argidx+3 != args.size()) log_cmd_error("Invalid number of arguments.\n"); - worker.gold_mod = design->module(RTLIL::escape_id(args[argidx])); - worker.gate_mod = design->module(RTLIL::escape_id(args[argidx+1])); - worker.equiv_mod = design->module(RTLIL::escape_id(args[argidx+2])); + worker.gold_mod = design->module(design->twines.lookup(RTLIL::escape_id(args[argidx]))); + worker.gate_mod = design->module(design->twines.lookup(RTLIL::escape_id(args[argidx+1]))); + worker.equiv_mod = design->module(design->twines.lookup(RTLIL::escape_id(args[argidx+2]))); if (worker.gold_mod == nullptr) log_cmd_error("Can't find gold module %s.\n", args[argidx]); @@ -516,7 +516,7 @@ struct EquivMakePass : public Pass { log_header(design, "Executing EQUIV_MAKE pass (creating equiv checking module).\n"); - worker.equiv_mod = design->addModule(RTLIL::escape_id(args[argidx+2])); + worker.equiv_mod = design->addModule(design->twines.add(Twine{RTLIL::escape_id(args[argidx+2])})); worker.run(); Pass::call(design, "dump"); } diff --git a/passes/equiv/equiv_mark.cc b/passes/equiv/equiv_mark.cc index 8e67a36d6..fad66b3ab 100644 --- a/passes/equiv/equiv_mark.cc +++ b/passes/equiv/equiv_mark.cc @@ -29,15 +29,15 @@ struct EquivMarkWorker SigMap sigmap; // cache for traversing signal flow graph - dict> up_bit2cells; - dict> up_cell2bits; - pool edge_cells, equiv_cells; + dict> up_bit2cells; + dict> up_cell2bits; + pool edge_cells, equiv_cells; // graph traversal state pool queue, visited; // assigned regions - dict cell_regions; + dict cell_regions; dict bit_regions; int next_region; @@ -49,17 +49,17 @@ struct EquivMarkWorker for (auto cell : module->cells()) { if (cell->type == ID($equiv)) - equiv_cells.insert(cell->name); + equiv_cells.insert(cell->meta_->name); for (auto &port : cell->connections()) { if (cell->input(port.first)) for (auto bit : sigmap(port.second)) - up_cell2bits[cell->name].insert(bit); + up_cell2bits[cell->meta_->name].insert(bit); if (cell->output(port.first)) for (auto bit : sigmap(port.second)) - up_bit2cells[bit].insert(cell->name); + up_bit2cells[bit].insert(cell->meta_->name); } } @@ -70,7 +70,7 @@ struct EquivMarkWorker { while (!queue.empty()) { - pool cells; + pool cells; for (auto &bit : queue) { @@ -139,7 +139,7 @@ struct EquivMarkWorker for (auto cell : module->cells()) { - if (cell_regions.count(cell->name) || cell->type != ID($equiv)) + if (cell_regions.count(cell->meta_->name) || cell->type != ID($equiv)) continue; SigSpec sig_a = sigmap(cell->getPort(TW::A)); @@ -153,7 +153,7 @@ struct EquivMarkWorker for (auto bit : sig_b) queue.insert(bit); - cell_regions[cell->name] = next_region; + cell_regions[cell->meta_->name] = next_region; mark(); } @@ -174,8 +174,8 @@ struct EquivMarkWorker for (auto cell : module->cells()) { - if (cell_regions.count(cell->name)) { - int r = final_region_map.at(cell_regions.at(cell->name)); + if (cell_regions.count(cell->meta_->name)) { + int r = final_region_map.at(cell_regions.at(cell->meta_->name)); cell->attributes[ID::equiv_region] = Const(r); region_cell_count[r]++; } else diff --git a/passes/equiv/equiv_miter.cc b/passes/equiv/equiv_miter.cc index fc42e41c3..b72348822 100644 --- a/passes/equiv/equiv_miter.cc +++ b/passes/equiv/equiv_miter.cc @@ -57,7 +57,7 @@ struct EquivMiterWorker for (auto &conn : c->connections()) { if (!ct.cell_input(c->type, conn.first)) continue; - if (c->type == ID($equiv) && (conn.first == ID::A) != gold_mode) + if (c->type == ID($equiv) && (conn.first == TW::A) != gold_mode) continue; for (auto bit : sigmap(conn.second)) if (bit_to_driver.count(bit)) @@ -141,11 +141,11 @@ struct EquivMiterWorker // copy wires and cells for (auto w : miter_wires) - miter_module->addWire(w->name, w->width); + miter_module->addWire(Twine{w->name.str()}, w->width); for (auto c : miter_cells) { if (c->type.in(ID($input_port), ID($output_port), ID($public))) continue; - auto mc = miter_module->addCell(c->name, c); + auto mc = miter_module->addCell(Twine{c->name.str()}, c); for (auto &conn : mc->connections()) mc->setPort(conn.first, sigmap(conn.second)); } @@ -160,7 +160,7 @@ struct EquivMiterWorker vector chunks = sig.chunks(); for (auto &c : chunks) if (c.wire != NULL) - c.wire = mod->wire(RTLIL::IdString(c.wire->name)); + c.wire = mod->wire(mod->design->twines.lookup(c.wire->name.str())); sig = chunks; } }; @@ -220,9 +220,9 @@ struct EquivMiterWorker for (auto c : equiv_cells) { SigSpec cmp = mode_undef ? - miter_module->LogicOr(NEW_ID, miter_module->Eqx(NEW_ID, c->getPort(TW::A), State::Sx), - miter_module->Eqx(NEW_ID, c->getPort(TW::A), c->getPort(TW::B))) : - miter_module->Eq(NEW_ID, c->getPort(TW::A), c->getPort(TW::B)); + miter_module->LogicOr(NEW_TWINE, miter_module->Eqx(NEW_TWINE, c->getPort(TW::A), State::Sx), + miter_module->Eqx(NEW_TWINE, c->getPort(TW::A), c->getPort(TW::B))) : + miter_module->Eq(NEW_TWINE, c->getPort(TW::A), c->getPort(TW::B)); if (mode_cmp) { string cmp_name = stringf("\\cmp%s", log_signal(c->getPort(TW::Y))); @@ -231,21 +231,21 @@ struct EquivMiterWorker cmp_name[i] = '_'; else if (cmp_name[i] == ' ') cmp_name = cmp_name.substr(0, i) + cmp_name.substr(i+1); - auto w = miter_module->addWire(cmp_name); + auto w = miter_module->addWire(Twine{cmp_name}); w->port_output = true; miter_module->connect(w, cmp); } if (mode_assert) - miter_module->addAssert(NEW_ID, cmp, State::S1); + miter_module->addAssert(NEW_TWINE, cmp, State::S1); - trigger_signals.append(miter_module->Not(NEW_ID, cmp)); + trigger_signals.append(miter_module->Not(NEW_TWINE, cmp)); } if (mode_trigger) { - auto w = miter_module->addWire(ID(trigger)); + auto w = miter_module->addWire(Twine{"trigger"}); w->port_output = true; - miter_module->addReduceOr(NEW_ID, trigger_signals, w); + miter_module->addReduceOr(NEW_TWINE, trigger_signals, w); } miter_module->fixup_ports(); @@ -323,7 +323,7 @@ struct EquivMiterPass : public Pass { // TODO disable signorm due to rewrite_sigspecs assert design->sigNormalize(false); - if (design->module(worker.miter_name)) + if (design->module(design->twines.lookup(worker.miter_name.str()))) log_cmd_error("Miter module %s already exists.\n", worker.miter_name.unescape()); worker.source_module = nullptr; @@ -339,7 +339,7 @@ struct EquivMiterPass : public Pass { log_header(design, "Executing EQUIV_MITER pass.\n"); - worker.miter_module = design->addModule(worker.miter_name); + worker.miter_module = design->addModule(design->twines.add(Twine{worker.miter_name.str()})); worker.run(); } } EquivMiterPass; diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc index 8d0d1899e..10ce5f862 100644 --- a/passes/equiv/equiv_purge.cc +++ b/passes/equiv/equiv_purge.cc @@ -46,11 +46,11 @@ struct EquivPurgeWorker while (1) { - IdString name = stringf("\\equiv_%d", name_cnt++); - if (module->count_id(name)) + std::string name = stringf("\\equiv_%d", name_cnt++); + if (module->count_id(module->design->twines.lookup(name))) continue; - Wire *wire = module->addWire(name, GetSize(sig)); + Wire *wire = module->addWire(Twine{name}, GetSize(sig)); wire->port_output = true; module->connect(wire, sig); log(" Module output: %s (%s)\n", log_signal(wire), cellname.unescape()); @@ -73,11 +73,11 @@ struct EquivPurgeWorker while (1) { - IdString name = stringf("\\equiv_%d", name_cnt++); - if (module->count_id(name)) + std::string name = stringf("\\equiv_%d", name_cnt++); + if (module->count_id(module->design->twines.lookup(name))) continue; - Wire *wire = module->addWire(name, GetSize(sig)); + Wire *wire = module->addWire(Twine{name}, GetSize(sig)); wire->port_input = true; module->connect(sig, wire); log(" Module input: %s (%s)\n", log_signal(wire), log_signal(sig)); @@ -97,8 +97,8 @@ struct EquivPurgeWorker pool queue, visited; // cache for traversing signal flow graph - dict> up_bit2cells; - dict> up_cell2bits; + dict> up_bit2cells; + dict> up_cell2bits; for (auto cell : module->cells()) { @@ -106,10 +106,10 @@ struct EquivPurgeWorker for (auto &port : cell->connections()) { if (cell->input(port.first)) for (auto bit : sigmap(port.second)) - up_cell2bits[cell->name].insert(bit); + up_cell2bits[cell->meta_->name].insert(bit); if (cell->output(port.first)) for (auto bit : sigmap(port.second)) - up_bit2cells[bit].insert(cell->name); + up_bit2cells[bit].insert(cell->meta_->name); } continue; } diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc index 4750e1301..95c7d80b4 100644 --- a/passes/equiv/equiv_simple.cc +++ b/passes/equiv/equiv_simple.cc @@ -114,7 +114,7 @@ struct EquivSimpleWorker : public EquivWorker if (yosys_celltypes.cell_input(cell->type, conn.first)) for (auto bit : model.sigmap(conn.second)) { if (cell->is_builtin_ff()) { - if (!conn.first.in(ID::CLK, ID::C)) + if (conn.first != TW::CLK && conn.first != TW::C) next_seed.insert(bit); } else find_input_cone(bit); diff --git a/passes/equiv/equiv_struct.cc b/passes/equiv/equiv_struct.cc index eab6ac314..a58cd7832 100644 --- a/passes/equiv/equiv_struct.cc +++ b/passes/equiv/equiv_struct.cc @@ -38,8 +38,8 @@ struct EquivStructWorker { IdString type; vector> parameters; - vector> port_sizes; - vector> connections; + vector> port_sizes; + vector> connections; bool operator==(const merge_key_t &other) const { return type == other.type && connections == other.connections && @@ -55,7 +55,7 @@ struct EquivStructWorker } }; - dict> merge_cache; + dict> merge_cache; pool fwd_merge_cache, bwd_merge_cache; void merge_cell_pair(Cell *cell_a, Cell *cell_b) @@ -78,8 +78,8 @@ struct EquivStructWorker if (bits_a[i] != bits_b[i]) { inputs_a.append(bits_a[i]); inputs_b.append(bits_b[i]); - input_names.push_back(GetSize(bits_a) == 1 ? port_a.first.str() : - stringf("%s[%d]", port_a.first.unescape(), i)); + input_names.push_back(GetSize(bits_a) == 1 ? module->design->twines.str(port_a.first) : + stringf("%s[%d]", module->design->twines.str(port_a.first).c_str(), i)); } } @@ -88,12 +88,12 @@ struct EquivStructWorker SigBit bit_y = module->addWire(NEW_TWINE); log(" New $equiv for input %s: A: %s, B: %s, Y: %s\n", input_names[i].c_str(), log_signal(bit_a), log_signal(bit_b), log_signal(bit_y)); - module->addEquiv(NEW_ID, bit_a, bit_b, bit_y); + module->addEquiv(NEW_TWINE, bit_a, bit_b, bit_y); merged_map.add(bit_a, bit_y); merged_map.add(bit_b, bit_y); } - std::vector outport_names, inport_names; + std::vector outport_names, inport_names; for (auto &port_a : cell_a->connections()) if (cell_a->output(port_a.first)) @@ -110,9 +110,7 @@ struct EquivStructWorker module->connect(sig_b, sig_a); } - auto merged_attr = cell_b->get_strpool_attribute(ID::equiv_merged); - merged_attr.insert(cell_b->name.unescape()); - cell_a->add_strpool_attribute(ID::equiv_merged, merged_attr); + cell_a->set_bool_attribute(ID::equiv_merged); module->remove(cell_b); } @@ -123,7 +121,7 @@ struct EquivStructWorker log(" Starting iteration %d.\n", iter_num); pool equiv_inputs; - pool cells; + pool cells; for (auto cell : module->selected_cells()) if (cell->type == ID($equiv)) { @@ -132,10 +130,10 @@ struct EquivStructWorker equiv_bits.add(sig_b, sig_a); equiv_inputs.insert(sig_a); equiv_inputs.insert(sig_b); - cells.insert(cell->name); + cells.insert(cell->meta_->name); } else { if (mode_icells || module->design->module(cell->type)) - cells.insert(cell->name); + cells.insert(cell->meta_->name); } for (auto cell : module->selected_cells()) @@ -157,7 +155,7 @@ struct EquivStructWorker for (auto cell_name : cells) { merge_key_t key; - vector> fwd_connections; + vector> fwd_connections; Cell *cell = module->cell(cell_name); key.type = cell->type; @@ -175,14 +173,14 @@ struct EquivStructWorker if (cell->input(conn.first)) { SigSpec sig = sigmap(conn.second); for (int i = 0; i < GetSize(sig); i++) - fwd_connections.push_back(make_tuple(conn.first, i, sig[i])); + fwd_connections.push_back(std::make_tuple(conn.first, i, sig[i])); } if (cell->output(conn.first)) { SigSpec sig = equiv_bits(conn.second); for (int i = 0; i < GetSize(sig); i++) { key.connections.clear(); - key.connections.push_back(make_tuple(conn.first, i, sig[i])); + key.connections.push_back(std::make_tuple(conn.first, i, sig[i])); if (merge_cache.count(key)) bwd_merge_cache.insert(key); @@ -213,7 +211,7 @@ struct EquivStructWorker for (auto cell_name : merge_cache[key]) { Cell *c = module->cell(cell_name); if (c != nullptr) { - string n = cell_name.str(); + string n = module->design->twines.str(cell_name); cells_type = c->type; if (GetSize(n) > 5 && n.compare(GetSize(n)-5, std::string::npos, "_gold") == 0) gold_cells.push_back(c); diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 94d30ce50..cb17b0e7a 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -29,7 +29,7 @@ PRIVATE_NAMESPACE_BEGIN static RTLIL::Module *module; static SigMap assign_map; -typedef std::pair sig2driver_entry_t; +typedef std::pair sig2driver_entry_t; static SigSet sig2driver, sig2user; static std::set muxtree_cells; static SigPool sig_at_port; @@ -55,7 +55,7 @@ ret_false: sig2driver.find(sig, cellport_list); for (auto &cellport : cellport_list) { - if ((cellport.first->type != ID($mux) && cellport.first->type != ID($pmux)) || cellport.second != ID::Y) { + if ((cellport.first->type != ID($mux) && cellport.first->type != ID($pmux)) || cellport.second != TW::Y) { goto ret_false; } @@ -103,12 +103,12 @@ static bool check_state_users(RTLIL::SigSpec sig) continue; if (cell->type == ID($logic_not) && assign_map(cell->getPort(TW::A)) == sig) continue; - if (cellport.second != ID::A && cellport.second != ID::B) + if (cellport.second != TW::A && cellport.second != TW::B) return false; - if (!cell->hasPort(ID::A) || !cell->hasPort(ID::B) || !cell->hasPort(ID::Y)) + if (!cell->hasPort(TW::A) || !cell->hasPort(TW::B) || !cell->hasPort(TW::Y)) return false; for (auto &port_it : cell->connections()) - if (port_it.first != ID::A && port_it.first != ID::B && port_it.first != ID::Y) + if (port_it.first != TW::A && port_it.first != TW::B && port_it.first != TW::Y) return false; if (assign_map(cell->getPort(TW::A)) == sig && cell->getPort(TW::B).is_fully_const()) continue; @@ -145,7 +145,7 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false) for (auto &cellport : cellport_list) { - if ((cellport.first->type != ID($dff) && cellport.first->type != ID($adff)) || cellport.second != ID::Q) + if ((cellport.first->type != ID($dff) && cellport.first->type != ID($adff)) || cellport.second != TW::Q) continue; muxtree_cells.clear(); diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index dc7b3f96c..9b2e03bf6 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -57,17 +57,17 @@ struct FsmExpand int in_bits = 0; RTLIL::SigSpec new_signals; - if (cell->hasPort(ID::A)) { + if (cell->hasPort(TW::A)) { in_bits += GetSize(cell->getPort(TW::A)); new_signals.append(assign_map(cell->getPort(TW::A))); } - if (cell->hasPort(ID::B)) { + if (cell->hasPort(TW::B)) { in_bits += GetSize(cell->getPort(TW::B)); new_signals.append(assign_map(cell->getPort(TW::B))); } - if (cell->hasPort(ID::S)) { + if (cell->hasPort(TW::S)) { in_bits += GetSize(cell->getPort(TW::S)); new_signals.append(assign_map(cell->getPort(TW::S))); } @@ -75,7 +75,7 @@ struct FsmExpand if (in_bits > 8) return false; - if (cell->hasPort(ID::Y)) + if (cell->hasPort(TW::Y)) new_signals.append(assign_map(cell->getPort(TW::Y))); new_signals.sort_and_unify(); @@ -106,7 +106,7 @@ struct FsmExpand if (merged_set.count(c) > 0 || current_set.count(c) > 0 || no_candidate_set.count(c) > 0) continue; for (auto &p : c->connections()) { - if (p.first != ID::A && p.first != ID::B && p.first != ID::S && p.first != ID::Y) + if (p.first != TW::A && p.first != TW::B && p.first != TW::S && p.first != TW::Y) goto next_cell; } if (!is_cell_merge_candidate(c)) { @@ -159,11 +159,11 @@ struct FsmExpand for (int i = 0; i < (1 << input_sig.size()); i++) { RTLIL::Const in_val(i, input_sig.size()); RTLIL::SigSpec A, B, S; - if (cell->hasPort(ID::A)) + if (cell->hasPort(TW::A)) A = assign_map(cell->getPort(TW::A)); - if (cell->hasPort(ID::B)) + if (cell->hasPort(TW::B)) B = assign_map(cell->getPort(TW::B)); - if (cell->hasPort(ID::S)) + if (cell->hasPort(TW::S)) S = assign_map(cell->getPort(TW::S)); A.replace(input_sig, RTLIL::SigSpec(in_val)); B.replace(input_sig, RTLIL::SigSpec(in_val)); @@ -243,7 +243,7 @@ struct FsmExpand void execute() { log("\n"); - log("Expanding FSM `%s' from module `%s':\n", fsm_cell->name, module->name); + log("Expanding FSM `%s' from module `%s':\n", log_id(fsm_cell), log_id(module)); already_optimized = false; limit_transitions = 16 * fsm_cell->parameters[ID::TRANS_NUM].as_int(); diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc index 1b06b18c2..6fc4f0d19 100644 --- a/passes/fsm/fsm_export.cc +++ b/passes/fsm/fsm_export.cc @@ -64,13 +64,13 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st kiss_name.assign(attr_it->second.decode_string()); } else { - kiss_name.assign(module->name.unescape() + std::string("-") + cell->name.unescape() + ".kiss2"); + kiss_name.assign(module->design->twines.str(module->meta_->name) + std::string("-") + module->design->twines.str(cell->meta_->name) + ".kiss2"); } log("\n"); log("Exporting FSM `%s' from module `%s' to file `%s'.\n", - cell->name.c_str(), - module->name.c_str(), + log_id(cell), + log_id(module), kiss_name.c_str()); kiss_file.open(kiss_name, std::ios::out | std::ios::trunc); diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index af59be206..1b0943f1e 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -34,7 +34,7 @@ PRIVATE_NAMESPACE_BEGIN static RTLIL::Module *module; static SigMap assign_map; -typedef std::pair sig2driver_entry_t; +typedef std::pair sig2driver_entry_t; static SigSet sig2driver, sig2trigger; static std::map> exclusive_ctrls; @@ -70,8 +70,8 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cell(cellport.first); - if ((cell->type != ID($mux) && cell->type != ID($pmux)) || cellport.second != ID::Y) { - log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type, cell->name); + if ((cell->type != ID($mux) && cell->type != ID($pmux)) || cellport.second != TW::Y) { + log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type, log_id(cell)); return false; } @@ -255,7 +255,7 @@ undef_bit_in_next_state: static void extract_fsm(RTLIL::Wire *wire) { - log("Extracting FSM `%s' from module `%s'.\n", wire->name, module->name); + log("Extracting FSM `%s' from module `%s'.\n", log_id(wire), log_id(module)); // get input and output signals for state ff @@ -272,9 +272,9 @@ static void extract_fsm(RTLIL::Wire *wire) sig2driver.find(dff_out, cellport_list); for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cell(cellport.first); - if ((cell->type != ID($dff) && cell->type != ID($adff)) || cellport.second != ID::Q) + if ((cell->type != ID($dff) && cell->type != ID($adff)) || cellport.second != TW::Q) continue; - log(" found %s cell for state register: %s\n", cell->type, cell->name); + log(" found %s cell for state register: %s\n", cell->type, log_id(cell)); RTLIL::SigSpec sig_q = assign_map(cell->getPort(TW::Q)); RTLIL::SigSpec sig_d = assign_map(cell->getPort(TW::D)); clk = cell->getPort(TW::CLK); @@ -322,12 +322,12 @@ static void extract_fsm(RTLIL::Wire *wire) RTLIL::Cell *cell = module->cell(cellport.first); RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A)); RTLIL::SigSpec sig_b; - if (cell->hasPort(ID::B)) + if (cell->hasPort(TW::B)) sig_b = assign_map(cell->getPort(TW::B)); RTLIL::SigSpec sig_y = assign_map(cell->getPort(TW::Y)); - if (cellport.second == ID::A && !sig_b.is_fully_const()) + if (cellport.second == TW::A && !sig_b.is_fully_const()) continue; - if (cellport.second == ID::B && !sig_a.is_fully_const()) + if (cellport.second == TW::B && !sig_a.is_fully_const()) continue; log(" found ctrl output: %s\n", log_signal(sig_y)); ctrl_out.append(sig_y); @@ -368,7 +368,7 @@ static void extract_fsm(RTLIL::Wire *wire) // create fsm cell - RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name, autoidx++), ID($fsm)); + RTLIL::Cell *fsm_cell = module->addCell(Twine{stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++)}, ID($fsm)); fsm_cell->setPort(TW::CLK, clk); fsm_cell->setPort(TW::ARST, arst); fsm_cell->parameters[ID::CLK_POLARITY] = clk_polarity ? State::S1 : State::S0; @@ -389,7 +389,7 @@ static void extract_fsm(RTLIL::Wire *wire) // rename original state wire wire->attributes.erase(ID::fsm_encoding); - module->rename(wire, stringf("$fsm$oldstate%s", wire->name.c_str())); + module->rename(wire, module->design->twines.add(Twine{stringf("$fsm$oldstate%s", wire->name.c_str())})); if(wire->attributes.count(ID::hdlname)) { auto hdlname = wire->get_hdlname_attribute(); hdlname.pop_back(); @@ -406,7 +406,7 @@ static void extract_fsm(RTLIL::Wire *wire) RTLIL::Cell *cell = module->cell(cellport.first); RTLIL::SigSpec port_sig = assign_map(cell->getPort(cellport.second)); RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out); - RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%d", autoidx++), unconn_sig.size()); + RTLIL::Wire *unconn_wire = module->addWire(Twine{stringf("$fsm_unconnect$%d", autoidx++)}, unconn_sig.size()); port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]); } } @@ -449,13 +449,13 @@ struct FsmExtractPass : public Pass { if (ct.cell_output(cell->type, conn_it.first) || !ct.cell_known(cell->type)) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); - sig2driver.insert(sig, sig2driver_entry_t(cell->name, conn_it.first)); + sig2driver.insert(sig, sig2driver_entry_t(cell->meta_->name, conn_it.first)); } - if (ct.cell_input(cell->type, conn_it.first) && cell->hasPort(ID::Y) && - cell->getPort(TW::Y).size() == 1 && (conn_it.first == ID::A || conn_it.first == ID::B)) { + if (ct.cell_input(cell->type, conn_it.first) && cell->hasPort(TW::Y) && + cell->getPort(TW::Y).size() == 1 && (conn_it.first == TW::A || conn_it.first == TW::B)) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); - sig2trigger.insert(sig, sig2driver_entry_t(cell->name, conn_it.first)); + sig2trigger.insert(sig, sig2driver_entry_t(cell->meta_->name, conn_it.first)); } } if (cell->type == ID($pmux)) { diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 595cc3232..9c47b1359 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -156,7 +156,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::mapname, module->name); + log("Mapping FSM `%s' from module `%s'.\n", log_id(fsm_cell), log_id(module)); FsmData fsm_data; fsm_data.copy_from_cell(fsm_cell); @@ -166,7 +166,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) // create state register - RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters[ID::NAME].decode_string()), fsm_data.state_bits); + RTLIL::Wire *state_wire = module->addWire(module->uniquify(module->design->twines.add(Twine{fsm_cell->parameters[ID::NAME].decode_string()})), fsm_data.state_bits); RTLIL::Wire *next_state_wire = module->addWire(NEW_TWINE, fsm_data.state_bits); RTLIL::Cell *state_dff = module->addCell(NEW_TWINE, ""); diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index d66150ac2..e26b67456 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -158,7 +158,7 @@ struct FsmOpt void opt_alias_inputs() { - RTLIL::SigSpec &ctrl_in = cell->connections_[ID::CTRL_IN]; + RTLIL::SigSpec ctrl_in = cell->getPort(TW::CTRL_IN); for (int i = 0; i < ctrl_in.size(); i++) for (int j = i+1; j < ctrl_in.size(); j++) @@ -194,12 +194,13 @@ struct FsmOpt fsm_data.transition_table.swap(new_transition_table); new_transition_table.clear(); } + cell->setPort(TW::CTRL_IN, ctrl_in); } void opt_feedback_inputs() { - RTLIL::SigSpec &ctrl_in = cell->connections_[ID::CTRL_IN]; - RTLIL::SigSpec &ctrl_out = cell->connections_[ID::CTRL_OUT]; + RTLIL::SigSpec ctrl_in = cell->getPort(TW::CTRL_IN); + RTLIL::SigSpec ctrl_out = cell->getPort(TW::CTRL_OUT); for (int j = 0; j < ctrl_out.size(); j++) for (int i = 0; i < ctrl_in.size(); i++) @@ -227,6 +228,8 @@ struct FsmOpt fsm_data.transition_table.swap(new_transition_table); new_transition_table.clear(); } + cell->setPort(TW::CTRL_IN, ctrl_in); + cell->setPort(TW::CTRL_OUT, ctrl_out); } void opt_find_dont_care_worker(std::set &set, int bit, FsmData::transition_t &tr, bool &did_something) @@ -296,7 +299,7 @@ struct FsmOpt FsmOpt(RTLIL::Cell *cell, RTLIL::Module *module) { - log("Optimizing FSM `%s' from module `%s'.\n", cell->name, module->name); + log("Optimizing FSM `%s' from module `%s'.\n", log_id(cell), log_id(module)); fsm_data.copy_from_cell(cell); this->cell = cell; diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index aa96ec6de..f05e24fd9 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -39,7 +39,7 @@ static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData & for (int i = fsm_data.state_bits-1; i >= 0; i--) fprintf(f, " %s_reg[%d]", name[0] == '\\' ? name.substr(1).c_str() : name.c_str(), i); fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n", prefix, RTLIL::unescape_id(name).c_str(), - prefix, module->name.unescape().c_str()); + prefix, module->design->twines.str(module->meta_->name).c_str()); fprintf(f, "set_fsm_encoding {"); for (int i = 0; i < GetSize(fsm_data.state_table); i++) { @@ -49,14 +49,14 @@ static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData & } fprintf(f, " } -name {%s_%s} {%s:/WORK/%s}\n", prefix, RTLIL::unescape_id(name).c_str(), - prefix, module->name.unescape().c_str()); + prefix, module->design->twines.str(module->meta_->name).c_str()); } static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fsm_file, FILE *encfile, std::string default_encoding) { std::string encoding = cell->attributes.count(ID::fsm_encoding) ? cell->attributes.at(ID::fsm_encoding).decode_string() : "auto"; - log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name, module->name, encoding); + log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", log_id(cell), log_id(module), encoding); if (encoding != "none" && encoding != "user" && encoding != "one-hot" && encoding != "binary" && encoding != "auto") { log(" unknown encoding `%s': using auto instead.\n", encoding); @@ -96,7 +96,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs log_error("FSM encoding `%s' is not supported!\n", encoding); if (encfile) - fprintf(encfile, ".fsm %s %s\n", module->name.unescape().c_str(), RTLIL::unescape_id(cell->parameters[ID::NAME].decode_string()).c_str()); + fprintf(encfile, ".fsm %s %s\n", module->design->twines.str(module->meta_->name).c_str(), RTLIL::unescape_id(cell->parameters[ID::NAME].decode_string()).c_str()); int state_idx_counter = fsm_data.reset_state >= 0 ? 1 : 0; for (int i = 0; i < int(fsm_data.state_table.size()); i++) diff --git a/passes/hierarchy/flatten.cc b/passes/hierarchy/flatten.cc index 601730c88..51cd7809e 100644 --- a/passes/hierarchy/flatten.cc +++ b/passes/hierarchy/flatten.cc @@ -42,6 +42,12 @@ template return result; } +struct module_ptr_compare { + bool operator()(RTLIL::Module *a, RTLIL::Module *b) const { + return a < b; + } +}; + IdString concat_name(RTLIL::Cell *cell, IdString const &object_name, const std::string &separator = ".") { std::string_view object_name_view(object_name.c_str()); @@ -57,9 +63,31 @@ IdString concat_name(RTLIL::Cell *cell, IdString const &object_name, const std:: } template -IdString map_name(RTLIL::Cell *cell, T *object, const std::string &separator = ".") +TwineRef map_name(RTLIL::Cell *cell, T *object, const std::string &separator = ".") { - return cell->module->uniquify(concat_name(cell, object->name, separator)); + return cell->module->uniquify(cell->module->design->twines.add(Twine{concat_name(cell, object->name, separator).str()})); +} + +// Specialization for Memory +template<> +TwineRef map_name(RTLIL::Cell *cell, RTLIL::Memory *object, const std::string &separator) +{ + auto design = cell->module->design; + std::string obj_name(design->twines.str(object->meta_->name)); + IdString obj_name_id(obj_name); + std::string mapped_name = concat_name(cell, obj_name_id, separator).str(); + return cell->module->uniquify(design->twines.add(Twine{mapped_name})); +} + +// Specialization for Process +template<> +TwineRef map_name(RTLIL::Cell *cell, RTLIL::Process *object, const std::string &separator) +{ + auto design = cell->module->design; + std::string obj_name(design->twines.str(object->meta_->name)); + IdString obj_name_id(obj_name); + std::string mapped_name = concat_name(cell, obj_name_id, separator).str(); + return cell->module->uniquify(design->twines.add(Twine{mapped_name})); } void map_sigspec(const dict &map, RTLIL::SigSpec &sig, RTLIL::Module *into = nullptr) @@ -128,23 +156,24 @@ struct FlattenWorker { // Copy the contents of the flattened cell - dict memory_map; + dict memory_map; for (auto &tpl_memory_it : tpl->memories) { RTLIL::Memory *new_memory = module->addMemory(map_name(cell, tpl_memory_it.second, separator), tpl_memory_it.second); - map_attributes(cell, new_memory, tpl_memory_it.second->name); - memory_map[tpl_memory_it.first] = new_memory->name; + map_attributes(cell, new_memory, design->twines.str(tpl_memory_it.second->meta_->name)); + memory_map[tpl_memory_it.first] = new_memory->meta_->name; design->select(module, new_memory); } dict wire_map; - dict positional_ports; + dict positional_ports; for (auto tpl_wire : tpl->wires()) { if (tpl_wire->port_id > 0) - positional_ports.emplace(stringf("$%d", tpl_wire->port_id), tpl_wire->name); + positional_ports.emplace(design->twines.add(Twine{stringf("$%d", tpl_wire->port_id)}), tpl_wire->meta_->name); RTLIL::Wire *new_wire = nullptr; if (tpl_wire->name[0] == '\\') { - RTLIL::Wire *hier_wire = module->wire(concat_name(cell, tpl_wire->name, separator)); + std::string wire_name = concat_name(cell, tpl_wire->name, separator).str(); + RTLIL::Wire *hier_wire = module->wire(design->twines.lookup(wire_name)); if (hier_wire != nullptr && hier_wire->get_bool_attribute(ID::hierconn)) { hier_wire->attributes.erase(ID::hierconn); if (GetSize(hier_wire) < GetSize(tpl_wire)) { @@ -168,10 +197,12 @@ struct FlattenWorker for (auto &tpl_proc_it : tpl->processes) { RTLIL::Process *new_proc = module->addProcess(map_name(cell, tpl_proc_it.second, separator), tpl_proc_it.second); - map_attributes(cell, new_proc, tpl_proc_it.second->name); + map_attributes(cell, new_proc, design->twines.str(tpl_proc_it.second->meta_->name)); for (auto new_proc_sync : new_proc->syncs) - for (auto &memwr_action : new_proc_sync->mem_write_actions) - memwr_action.memid = memory_map.at(memwr_action.memid).str(); + for (auto &memwr_action : new_proc_sync->mem_write_actions) { + TwineRef old_memid_ref = design->twines.lookup(memwr_action.memid.str()); + memwr_action.memid = design->twines.str(memory_map.at(old_memid_ref)); + } auto rewriter = [&](RTLIL::SigSpec &sig) { map_sigspec(wire_map, sig); }; new_proc->rewrite_sigspecs(rewriter); design->select(module, new_proc); @@ -184,7 +215,8 @@ struct FlattenWorker map_attributes(cell, new_cell, tpl_cell->name); if (new_cell->has_memid()) { IdString memid = new_cell->getParam(ID::MEMID).decode_string(); - new_cell->setParam(ID::MEMID, Const(memory_map.at(memid).str())); + TwineRef memid_ref = design->twines.lookup(memid.str()); + new_cell->setParam(ID::MEMID, Const(design->twines.str(memory_map.at(memid_ref)))); } else if (new_cell->is_mem_cell()) { IdString memid = new_cell->getParam(ID::MEMID).decode_string(); new_cell->setParam(ID::MEMID, Const(concat_name(cell, memid, separator).str())); @@ -216,13 +248,14 @@ struct FlattenWorker for (auto &port_it : cell->connections()) { - IdString port_name = port_it.first; + TwineRef port_name = port_it.first; if (positional_ports.count(port_name) > 0) port_name = positional_ports.at(port_name); if (tpl->wire(port_name) == nullptr || tpl->wire(port_name)->port_id == 0) { - if (port_name.begins_with("$")) + std::string port_name_str = design->twines.str(port_name); + if (!port_name_str.empty() && port_name_str[0] == '$') log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", - port_name.c_str(), cell->name.c_str(), tpl->name.c_str()); + std::string(port_name_str).c_str(), cell->name.c_str(), design->twines.str(tpl->meta_->name).c_str()); continue; } @@ -263,7 +296,7 @@ struct FlattenWorker if (sigmap(new_conn.first).has_const()) log_error("Cell port %s.%s.%s is driving constant bits: %s <= %s\n", - module, cell, port_it.first.unescape(), log_signal(new_conn.first), log_signal(new_conn.second)); + module, cell, design->twines.str(port_it.first), log_signal(new_conn.first), log_signal(new_conn.second)); module->connect(new_conn); sigmap.add(new_conn.first, new_conn.second); @@ -296,18 +329,18 @@ struct FlattenWorker if (tpl->src_id() != Twine::Null) scopeinfo->attributes.emplace(ID(module_src), RTLIL::Const(tpl->get_src_attribute())); - scopeinfo->attributes.emplace(ID(module), tpl->name.unescape()); + scopeinfo->attributes.emplace(ID(module), RTLIL::Const(design->twines.str(tpl->meta_->name).substr(1))); } module->remove(cell); if (scopeinfo != nullptr) - module->rename(scopeinfo, cell_name); + module->rename(scopeinfo, design->twines.add(Twine{cell_name.str()})); } void flatten_module(RTLIL::Design *design, RTLIL::Module *module, pool &used_modules, const std::string &separator) { - if (!design->selected(module) || module->get_blackbox_attribute(ignore_wb)) + if (!design->selected_module(module) || module->get_blackbox_attribute(ignore_wb)) return; SigMap sigmap(module); @@ -317,10 +350,11 @@ struct FlattenWorker RTLIL::Cell *cell = worklist.back(); worklist.pop_back(); - if (!design->has(cell->type)) + TwineRef cell_type_ref = design->twines.add(Twine{cell->type.str()}); + if (!design->has(cell_type_ref)) continue; - RTLIL::Module *tpl = design->module(cell->type); + RTLIL::Module *tpl = design->module(cell_type_ref); if (tpl->get_blackbox_attribute(ignore_wb)) continue; @@ -432,7 +466,7 @@ struct FlattenPass : public Pass { else used_modules.insert(top); - TopoSort> topo_modules; + TopoSort topo_modules; pool worklist = used_modules; while (!worklist.empty()) { RTLIL::Module *module = worklist.pop(); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 7d8e2302a..036066cdd 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -56,18 +56,19 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, for (auto &celltype : found_celltypes) { - std::set portnames; + std::set portnames; std::set parameters; - std::map portwidths; + std::map portwidths; log("Generate module for cell type %s:\n", celltype); for (auto mod : design->modules()) for (auto cell : mod->cells()) if (cell->type == celltype) { for (auto &conn : cell->connections()) { - if (conn.first[0] != '$') - portnames.insert(conn.first); - portwidths[conn.first] = max(portwidths[conn.first], conn.second.size()); + std::string port_name = design->twines.str(conn.first); + if (!port_name.empty() && port_name[0] != '$') + portnames.insert(std::string(port_name)); + portwidths[std::string(port_name)] = max(portwidths[std::string(port_name)], conn.second.size()); } for (auto ¶ : cell->parameters) parameters.insert(para.first); @@ -98,11 +99,11 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, } while (portnames.size() > 0) { - TwineRef portname = *portnames.begin(); + std::string portname = *portnames.begin(); for (auto &decl : portdecls) - if (decl.index == 0 && patmatch(decl.portname.c_str(), portname.unescape().c_str())) { + if (decl.index == 0 && patmatch(decl.portname.c_str(), RTLIL::unescape_id(portname).c_str())) { generate_port_decl_t d = decl; - d.portname = portname.str(); + d.portname = portname; d.index = *indices.begin(); log_assert(!indices.empty()); indices.erase(d.index); @@ -111,21 +112,18 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, log(" port %d: %s [%d:0] %s\n", d.index, d.input ? d.output ? "inout" : "input" : "output", portwidths[d.portname]-1, RTLIL::unescape_id(d.portname)); goto found_matching_decl; } - log_error("Can't match port %s.\n", portname.unescape()); + log_error("Can't match port %s.\n", RTLIL::unescape_id(portname).c_str()); found_matching_decl:; portnames.erase(portname); } log_assert(indices.empty()); - RTLIL::Module *mod = new RTLIL::Module; - mod->design = design; - mod->name = celltype; + RTLIL::Module *mod = design->addModule(design->twines.add(Twine{celltype.str()})); mod->attributes[ID::blackbox] = RTLIL::Const(1); - design->add(mod); for (auto &decl : ports) { - RTLIL::Wire *wire = mod->addWire(decl.portname, portwidths.at(decl.portname)); + RTLIL::Wire *wire = mod->addWire(design->twines.add(Twine{decl.portname}), portwidths.at(decl.portname)); wire->port_id = decl.index; wire->port_input = decl.input; wire->port_output = decl.output; @@ -172,11 +170,24 @@ bool read_id_num(RTLIL::IdString str, int *dst) return true; } +// Overload for TwineRef +bool read_id_num(RTLIL::Design &design, TwineRef ref, int *dst) +{ + log_assert(dst); + + std::string sv = design.twines.str(ref); + if (sv.empty() || sv[0] != '$' || !('0' <= sv[1] && sv[1] <= '9')) + return false; + + *dst = atoi(std::string(sv).c_str() + 1); + return true; +} + // A helper struct for expanding a module's interface connections in expand_module struct IFExpander { IFExpander (RTLIL::Design &design, RTLIL::Module &m) - : module(m), has_interfaces_not_found(false) + : module(m), design(design), has_interfaces_not_found(false) { // Keep track of all derived interfaces available in the current // module in 'interfaces_in_module': @@ -188,15 +199,16 @@ struct IFExpander } } + RTLIL::Design &design; RTLIL::Module &module; dict interfaces_in_module; bool has_interfaces_not_found; - std::vector connections_to_remove; - std::vector connections_to_add_name; + std::vector connections_to_remove; + std::vector connections_to_add_name; std::vector connections_to_add_signal; - dict interfaces_to_add_to_submodule; - dict modports_used_in_submodule; + dict interfaces_to_add_to_submodule; + dict modports_used_in_submodule; // Reset the per-cell state void start_cell() @@ -231,7 +243,7 @@ struct IFExpander // Handle an interface connection from the module void on_interface(RTLIL::Module &submodule, - RTLIL::IdString conn_name, + TwineRef conn_name, const RTLIL::SigSpec &conn_signals) { // Check if the connected wire is a potential interface in the parent module @@ -268,16 +280,18 @@ struct IFExpander RTLIL::Module *mod_replace_ports = interfaces_in_module.at(interface_name2); // Go over all wires in interface, and add replacements to lists. + std::string conn_name_str(design.twines.str(conn_name)); for (auto mod_wire : mod_replace_ports->wires()) { - std::string signal_name1 = conn_name.str() + "." + mod_wire->name.unescape(); + std::string signal_name1 = conn_name_str + "." + mod_wire->name.unescape(); std::string signal_name2 = interface_name.str() + "." + mod_wire->name.unescape(); - connections_to_add_name.push_back(RTLIL::IdString(signal_name1)); - if(module.wire(signal_name2) == nullptr) { + connections_to_add_name.push_back(design.twines.add(Twine{signal_name1})); + TwineRef signal_name2_ref = design.twines.lookup(signal_name2); + if(module.wire(signal_name2_ref) == nullptr) { log_error("Could not find signal '%s' in '%s'\n", - signal_name2.c_str(), module.name.unescape()); + signal_name2.c_str(), design.twines.str(module.meta_->name).data()); } else { - RTLIL::Wire *wire_in_parent = module.wire(signal_name2); + RTLIL::Wire *wire_in_parent = module.wire(signal_name2_ref); connections_to_add_signal.push_back(wire_in_parent); } } @@ -296,7 +310,7 @@ struct IFExpander // Handle a single connection from the module, making a note to expand // it if it's an interface connection. void on_connection(RTLIL::Module &submodule, - RTLIL::IdString conn_name, + TwineRef conn_name, const RTLIL::SigSpec &conn_signals) { // Does the connection look like an interface @@ -310,7 +324,7 @@ struct IFExpander // Check if the connection is present as an interface in the sub-module's port list int id; - if (read_id_num(conn_name, &id)) { + if (read_id_num(design, conn_name, &id)) { /* Interface expansion is incompatible with positional arguments * during expansion, the port list gets each interface signal * inserted after the interface itself which means that the argument @@ -323,8 +337,8 @@ struct IFExpander * parent and child). */ log_error("Unable to connect `%s' to submodule `%s' with positional interface argument `%s'!\n", - module.name, - submodule.name, + design.twines.str(module.meta_->name).data(), + design.twines.str(submodule.meta_->name).data(), conn_signals[0].wire->name.str().substr(23) ); } else { @@ -414,7 +428,7 @@ RTLIL::Module *get_module(RTLIL::Design &design, // We couldn't find the module anywhere. Complain if check is set. if (check) log_error("Module `%s' referenced in module `%s' in cell `%s' is not part of the design.\n", - cell_type.c_str(), parent.name.c_str(), cell.name.c_str()); + cell_type.c_str(), parent.design->twines.str(parent.meta_->name).data(), cell.name.c_str()); return nullptr; } @@ -429,7 +443,7 @@ void check_cell_connections(const RTLIL::Module &module, RTLIL::Cell &cell, RTLI { int id; for (auto &conn : cell.connections()) { - if (read_id_num(conn.first, &id)) { + if (read_id_num(*module.design, conn.first, &id)) { if (id <= 0 || id > GetSize(mod.ports)) log_error("Module `%s' referenced in module `%s' in cell `%s' " "has only %d ports, requested port %d.\n", @@ -443,7 +457,7 @@ void check_cell_connections(const RTLIL::Module &module, RTLIL::Cell &cell, RTLI log_error("Module `%s' referenced in module `%s' in cell `%s' " "does not have a port named '%s'.\n", cell.type.unescape(), &module, &cell, - conn.first.unescape()); + module.design->twines.str(conn.first).data()); } } for (auto ¶m : cell.parameters) { @@ -503,6 +517,9 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check cell->type = cell->type.substr(pos_type + 1); } + dict interfaces_by_name; + dict modports_by_name; + RTLIL::Module *mod = design->module(cell->type); if (!mod) { @@ -530,7 +547,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check if (mod->get_blackbox_attribute()) { if (flag_simcheck || (flag_smtcheck && !mod->get_bool_attribute(ID::smtlib2_module))) log_error("Module `%s' referenced in module `%s' in cell `%s' is a blackbox/whitebox module.\n", - cell->type.c_str(), module->name.c_str(), cell->name.c_str()); + cell->type.c_str(), design->twines.str(module->meta_->name).data(), cell->name.c_str()); continue; } @@ -555,10 +572,14 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check continue; } + for (auto &p : if_expander.interfaces_to_add_to_submodule) + interfaces_by_name[RTLIL::IdString(design->twines.str(p.first))] = p.second; + for (auto &p : if_expander.modports_used_in_submodule) + modports_by_name[RTLIL::IdString(design->twines.str(p.first))] = p.second; cell->type = mod->derive(design, cell->parameters, - if_expander.interfaces_to_add_to_submodule, - if_expander.modports_used_in_submodule); + interfaces_by_name, + modports_by_name); cell->parameters.clear(); did_something = true; @@ -605,21 +626,25 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check for (auto &conn : cell->connections_) { int conn_size = conn.second.size(); TwineRef portname = conn.first; - if (portname.begins_with("$")) { - int port_id = atoi(portname.substr(1).c_str()); + std::string portname_str = module->design->twines.str(conn.first); + if (portname_str.empty() || portname_str[0] != '$') { + // Named port, use as-is + } else { + // Positional port, find by port_id + int port_id = atoi(portname_str.substr(1).data()); for (auto wire : mod->wires()) if (wire->port_id == port_id) { - portname = wire->name; + portname = wire->meta_->name; break; } } if (mod->wire(portname) == nullptr) - log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", module, cell, conn.first.unescape()); + log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", module, cell, module->design->twines.str(conn.first).data()); int port_size = mod->wire(portname)->width; if (conn_size == port_size || conn_size == 0) continue; if (conn_size != port_size*num) - log_error("Array cell `%s.%s' has invalid port vs. signal size for port `%s'.\n", module, cell, conn.first.unescape()); + log_error("Array cell `%s.%s' has invalid port vs. signal size for port `%s'.\n", module, cell, module->design->twines.str(conn.first).data()); conn.second = conn.second.extract(port_size*idx, port_size); } } @@ -627,15 +652,15 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check return did_something; } -void hierarchy_worker(RTLIL::Design *design, std::set> &used, RTLIL::Module *mod, int indent) +void hierarchy_worker(RTLIL::Design *design, std::set &used, RTLIL::Module *mod, int indent) { if (used.count(mod) > 0) return; if (indent == 0) - log("Top module: %s\n", mod->name); + log("Top module: %s\n", mod->design->twines.str(mod->meta_->name).data()); else if (!mod->get_blackbox_attribute()) - log("Used module: %*s%s\n", indent, "", mod->name); + log("Used module: %*s%s\n", indent, "", mod->design->twines.str(mod->meta_->name).data()); used.insert(mod); for (auto cell : mod->cells()) { @@ -649,7 +674,7 @@ void hierarchy_worker(RTLIL::Design *design, std::set> used; + std::set used; hierarchy_worker(design, used, top, 0); std::vector del_modules; @@ -675,7 +700,7 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib) for (auto mod : del_modules) { if (!purge_lib && mod->get_blackbox_attribute()) continue; - log("Removing unused module `%s'.\n", mod->name); + log("Removing unused module `%s'.\n", mod->design->twines.str(mod->meta_->name).data()); design->remove(mod); del_counter++; } @@ -687,7 +712,7 @@ bool set_keep_print(std::map &cache, RTLIL::Module *mod) { if (cache.count(mod) == 0) for (auto c : mod->cells()) { - if (mod->name == c->type) + if (mod->meta_->name == mod->design->twines.add(Twine{c->type.str()})) continue; RTLIL::Module *m = mod->design->module(c->type); if ((m != nullptr && set_keep_print(cache, m)) || c->type == ID($print)) @@ -700,7 +725,7 @@ bool set_keep_assert(std::map &cache, RTLIL::Module *mod) { if (cache.count(mod) == 0) for (auto c : mod->cells()) { - if (mod->name == c->type) + if (mod->meta_->name == mod->design->twines.add(Twine{c->type.str()})) continue; RTLIL::Module *m = mod->design->module(c->type); if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in(ID($check), ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) @@ -751,11 +776,18 @@ RTLIL::Wire *find_implicit_port_wire(Module *module, Cell *cell, const std::stri const std::string &cellname = cell->name.str(); size_t idx = cellname.size(); while ((idx = cellname.find_last_of('.', idx-1)) != std::string::npos) { - Wire *found = module->wire(cellname.substr(0, idx+1) + port.substr(1)); - if (found != nullptr) - return found; + std::string wire_name = cellname.substr(0, idx+1) + port.substr(1); + TwineRef ref = module->design->twines.lookup(wire_name); + if (ref != Twine::Null) { + Wire *found = module->wire(ref); + if (found != nullptr) + return found; + } } - return module->wire(port); + TwineRef ref = module->design->twines.lookup(port); + if (ref != Twine::Null) + return module->wire(ref); + return nullptr; } struct HierarchyPass : public Pass { @@ -999,10 +1031,11 @@ struct HierarchyPass : public Pass { else if (top_mod != nullptr && !top_parameters.empty()) top_mod = design->module(top_mod->derive(design, top_parameters)); - if (top_mod != nullptr && top_mod->name != top_name) { + TwineRef top_name_ref = design->twines.add(Twine{top_name.str()}); + if (top_mod != nullptr && top_mod->meta_->name != top_name_ref) { Module *m = top_mod->clone(); - m->name = top_name; - Module *old_mod = design->module(top_name); + m->meta_->name = top_name_ref; + Module *old_mod = design->module(top_name_ref); if (old_mod) design->remove(old_mod); design->add(m); @@ -1047,10 +1080,12 @@ struct HierarchyPass : public Pass { if (top_mod == nullptr) { - std::vector abstract_ids; - for (auto module : design->modules()) - if (module->name.begins_with("$abstract")) - abstract_ids.push_back(module->name); + std::vector abstract_ids; + for (auto module : design->modules()) { + std::string mod_name = design->twines.str(module->meta_->name); + if (!mod_name.empty() && mod_name[0] == '$' && mod_name.substr(0, 9) == "$abstract") + abstract_ids.push_back(module->meta_->name); + } for (auto abstract_id : abstract_ids) design->module(abstract_id)->derive(design, {}); for (auto abstract_id : abstract_ids) @@ -1070,8 +1105,9 @@ struct HierarchyPass : public Pass { log("Automatically selected %s as design top module.\n", top_mod); } - if (top_mod != nullptr && top_mod->name.begins_with("$abstract")) { - IdString top_name = top_mod->name.substr(strlen("$abstract")); + std::string top_mod_name = top_mod ? design->twines.str(top_mod->meta_->name) : std::string(""); + if (top_mod != nullptr && !top_mod_name.empty() && top_mod_name[0] == '$' && top_mod_name.substr(0, 9) == "$abstract") { + IdString top_name = IdString(top_mod_name.substr(strlen("$abstract"))); dict top_parameters; for (auto ¶ : parameters) { @@ -1083,10 +1119,11 @@ struct HierarchyPass : public Pass { top_mod = design->module(top_mod->derive(design, top_parameters)); - if (top_mod != nullptr && top_mod->name != top_name) { + TwineRef top_name_ref = design->twines.add(Twine{top_name.str()}); + if (top_mod != nullptr && top_mod->meta_->name != top_name_ref) { Module *m = top_mod->clone(); - m->name = top_name; - Module *old_mod = design->module(top_name); + m->meta_->name = top_name_ref; + Module *old_mod = design->module(top_name_ref); if (old_mod) design->remove(old_mod); design->add(m); @@ -1110,7 +1147,7 @@ struct HierarchyPass : public Pass { { did_something = false; - std::set> used_modules; + std::set used_modules; if (top_mod != NULL) { log_header(design, "Analyzing design hierarchy..\n"); hierarchy_worker(design, used_modules, top_mod, 0); @@ -1195,7 +1232,7 @@ struct HierarchyPass : public Pass { src += ": "; log_error("%sProperty `%s' in module `%s' uses unsupported SVA constructs. See frontend warnings for details, run `chformal -remove a:unsupported_sva' to ignore.\n", - src, cell->name.unescape(), mod->name.unescape()); + src, cell->module->design->twines.str(cell->meta_->name), design->twines.str(mod->meta_->name).data()); } } } @@ -1211,12 +1248,14 @@ struct HierarchyPass : public Pass { RTLIL::Module *cell_mod = design->module(cell->type); if (cell_mod == nullptr) continue; - for (auto &conn : cell->connections()) - if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') { + for (auto &conn : cell->connections()) { + std::string conn_name = design->twines.str(conn.first); + if (!conn_name.empty() && conn_name[0] == '$' && '0' <= conn_name[1] && conn_name[1] <= '9') { pos_mods.insert(design->module(cell->type)); pos_work.push_back(std::pair(mod, cell)); break; } + } pool> params_rename; for (const auto &p : cell->parameters) { @@ -1247,21 +1286,21 @@ struct HierarchyPass : public Pass { RTLIL::Cell *cell = work.second; log("Mapping positional arguments of cell %s.%s (%s).\n", module, cell, cell->type.unescape()); - dict new_connections; + dict new_connections_twine; for (auto &conn : cell->connections()) { int id; - if (read_id_num(conn.first, &id)) { + if (read_id_num(*design, conn.first, &id)) { std::pair key(design->module(cell->type), id); if (pos_map.count(key) == 0) { log(" Failed to map positional argument %d of cell %s.%s (%s).\n", id, module, cell, cell->type.unescape()); - new_connections[conn.first] = conn.second; + new_connections_twine[conn.first] = conn.second; } else - new_connections[pos_map.at(key)] = conn.second; + new_connections_twine[design->twines.add(Twine{pos_map.at(key).str()})] = conn.second; } else - new_connections[conn.first] = conn.second; + new_connections_twine[conn.first] = conn.second; } - cell->connections_ = new_connections; + cell->connections_ = new_connections_twine; } } @@ -1272,7 +1311,7 @@ struct HierarchyPass : public Pass { for (auto module : design->modules()) for (auto wire : module->wires()) if (wire->port_input && wire->attributes.count(ID::defaultvalue)) - defaults_db[module->name][wire->name] = wire->attributes.at(ID::defaultvalue); + defaults_db[RTLIL::IdString(design->twines.str(module->meta_->name))][wire->name] = wire->attributes.at(ID::defaultvalue); } // Process SV implicit wildcard port connections std::set blackbox_derivatives; @@ -1295,7 +1334,7 @@ struct HierarchyPass : public Pass { IdString new_m_name = m->derive(design, cell->parameters, true); if (new_m_name.empty()) continue; - if (new_m_name != m->name) { + if (new_m_name != RTLIL::IdString(design->twines.str(m->meta_->name))) { m = design->module(new_m_name); blackbox_derivatives.insert(m); } @@ -1306,7 +1345,7 @@ struct HierarchyPass : public Pass { // Find ports of the module that aren't explicitly connected if (!wire->port_input && !wire->port_output) continue; - if (old_connections.count(wire->name)) + if (old_connections.count(wire->meta_->name)) continue; // Make sure a wire of correct name exists in the parent Wire* parent_wire = find_implicit_port_wire(module, cell, wire->name.str()); @@ -1322,7 +1361,7 @@ struct HierarchyPass : public Pass { log_error("Width mismatch between wire (%d bits) and port (%d bits) for implicit port connection `%s' of cell %s.%s (%s).\n", parent_wire->width, wire->width, wire, module, cell, cell->type.unescape()); - cell->setPort(wire->name, parent_wire); + cell->setPort(wire->meta_->name, parent_wire); } cell->attributes.erase(ID::wildcard_port_conns); } @@ -1338,16 +1377,20 @@ struct HierarchyPass : public Pass { if (keep_positionals) { bool found_positionals = false; - for (auto &conn : cell->connections()) - if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') + for (auto &conn : cell->connections()) { + std::string conn_name = design->twines.str(conn.first); + if (!conn_name.empty() && conn_name[0] == '$' && '0' <= conn_name[1] && conn_name[1] <= '9') found_positionals = true; + } if (found_positionals) continue; } - for (auto &it : defaults_db.at(cell->type)) - if (!cell->hasPort(it.first)) - cell->setPort(it.first, it.second); + for (auto &it : defaults_db.at(cell->type)) { + TwineRef port_ref = design->twines.add(Twine{it.first.str()}); + if (!cell->hasPort(port_ref)) + cell->setPort(port_ref, it.second); + } } } @@ -1451,18 +1494,18 @@ struct HierarchyPass : public Pass { if (GetSize(w) == 1) { if (wand) - module->addReduceAnd(NEW_ID, sigs, w); + module->addReduceAnd(NEW_TWINE, sigs, w); else - module->addReduceOr(NEW_ID, sigs, w); + module->addReduceOr(NEW_TWINE, sigs, w); continue; } SigSpec s = sigs.extract(0, GetSize(w)); for (int i = GetSize(w); i < GetSize(sigs); i += GetSize(w)) { if (wand) - s = module->And(NEW_ID, s, sigs.extract(i, GetSize(w))); + s = module->And(NEW_TWINE, s, sigs.extract(i, GetSize(w))); else - s = module->Or(NEW_ID, s, sigs.extract(i, GetSize(w))); + s = module->Or(NEW_TWINE, s, sigs.extract(i, GetSize(w))); } module->connect(w, s); } @@ -1480,7 +1523,7 @@ struct HierarchyPass : public Pass { IdString new_m_name = m->derive(design, cell->parameters, true); if (new_m_name.empty()) continue; - if (new_m_name != m->name) { + if (new_m_name != RTLIL::IdString(design->twines.str(m->meta_->name))) { m = design->module(new_m_name); blackbox_derivatives.insert(m); } @@ -1504,7 +1547,7 @@ struct HierarchyPass : public Pass { bool resize_widths = !keep_portwidths && GetSize(w) != GetSize(conn.second); if (resize_widths && verific_mod && boxed_params) log_debug("Ignoring width mismatch on %s.%s.%s from verific, is port width parametrizable?\n", - module, cell, conn.first.unescape() + module, cell, design->twines.str(conn.first).data() ); else if (resize_widths) { if (GetSize(w) < GetSize(conn.second)) @@ -1529,13 +1572,13 @@ struct HierarchyPass : public Pass { if (!conn.second.is_fully_const() || !w->port_input || w->port_output) log_warning("Resizing cell port %s.%s.%s from %d bits to %d bits.\n", module, cell, - conn.first.unescape(), GetSize(conn.second), GetSize(sig)); + design->twines.str(conn.first).data(), GetSize(conn.second), GetSize(sig)); cell->setPort(conn.first, sig); } if (w->port_output && !w->port_input && sig.has_const()) log_error("Output port %s.%s.%s (%s) is connected to constants: %s\n", - module, cell, conn.first.unescape(), cell->type.unescape(), log_signal(sig)); + module, cell, design->twines.str(conn.first).data(), cell->type.unescape(), log_signal(sig)); } } } diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 7854a5ba6..9203718e5 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -87,7 +87,7 @@ struct SubmodWorker void handle_submodule(SubModule &submod) { - log("Creating submodule %s (%s) of module %s.\n", submod.name, submod.full_name, module->name); + log("Creating submodule %s (%s) of module %s.\n", submod.name, submod.full_name, design->twines.str(module->meta_->name).data()); wire_flags.clear(); for (RTLIL::Cell *cell : submod.cells) { @@ -115,10 +115,7 @@ struct SubmodWorker } } - RTLIL::Module *new_mod = new RTLIL::Module; - new_mod->design = design; - new_mod->name = submod.full_name; - design->add(new_mod); + RTLIL::Module *new_mod = design->addModule(design->twines.add(Twine{submod.full_name})); int auto_name_counter = 1; std::set all_wire_names; @@ -170,7 +167,7 @@ struct SubmodWorker new_wire_name = stringf("$submod%s", new_wire_name); } - RTLIL::Wire *new_wire = new_mod->addWire(new_wire_name, wire->width); + RTLIL::Wire *new_wire = new_mod->addWire(design->twines.add(Twine{new_wire_name}), wire->width); new_wire->port_input = new_wire_port_input; new_wire->port_output = new_wire_port_output; new_wire->start_offset = wire->start_offset; @@ -208,7 +205,7 @@ struct SubmodWorker ct.setup_module(new_mod); for (RTLIL::Cell *cell : submod.cells) { - RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell); + RTLIL::Cell *new_cell = new_mod->addCell(design->twines.add(Twine{cell->name.str()}), cell); for (auto &conn : new_cell->connections_) for (auto &bit : conn.second) if (bit.wire != nullptr) { @@ -222,7 +219,7 @@ struct SubmodWorker submod.cells.clear(); if (!copy_mode) { - RTLIL::Cell *new_cell = module->addCell(submod.full_name, submod.full_name); + RTLIL::Cell *new_cell = module->addCell(design->twines.add(Twine{submod.full_name}), ID(submod.full_name)); for (auto &it : wire_flags) { RTLIL::SigSpec old_sig = sigmap(it.first); @@ -238,7 +235,7 @@ struct SubmodWorker else if (!it.second.is_int_driven[i]) b = module->addWire(NEW_TWINE); } - new_cell->setPort(new_wire->name, old_sig); + new_cell->setPort(design->twines.add(Twine{new_wire->name.str()}), old_sig); } } } @@ -251,12 +248,12 @@ struct SubmodWorker return; if (module->processes.size() > 0) { - log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name); + log("Skipping module %s as it contains processes (run 'proc' pass first).\n", design->twines.str(module->meta_->name).data()); return; } if (module->memories.size() > 0) { - log("Skipping module %s as it contains memories (run 'memory' pass first).\n", module->name); + log("Skipping module %s as it contains memories (run 'memory' pass first).\n", design->twines.str(module->meta_->name).data()); return; } @@ -290,9 +287,10 @@ struct SubmodWorker if (submodules.count(submod_str) == 0) { submodules[submod_str].name = submod_str; - submodules[submod_str].full_name = module->name.str() + "_" + submod_str; - while (design->module(submodules[submod_str].full_name) != nullptr || - module->count_id(submodules[submod_str].full_name) != 0) + std::string module_name_str(design->twines.str(module->meta_->name)); + submodules[submod_str].full_name = module_name_str + "_" + submod_str; + while (design->module(design->twines.add(Twine{submodules[submod_str].full_name})) != nullptr || + module->count_id(design->twines.add(Twine{submodules[submod_str].full_name})) != 0) submodules[submod_str].full_name += "_"; } @@ -385,15 +383,17 @@ struct SubmodPass : public Pass { Pass::call(design, "opt_clean"); log_header(design, "Continuing SUBMOD pass.\n"); - std::set handled_modules; + std::set handled_modules; bool did_something = true; while (did_something) { did_something = false; - std::vector queued_modules; - for (auto mod : design->modules()) - if (handled_modules.count(mod->name) == 0 && design->selected_whole_module(mod->name)) - queued_modules.push_back(mod->name); + std::vector queued_modules; + for (auto mod : design->modules()) { + TwineRef mod_name = mod->meta_->name; + if (handled_modules.count(mod_name) == 0 && design->selected_whole_module(mod)) + queued_modules.push_back(mod_name); + } for (auto &modname : queued_modules) if (design->module(modname) != nullptr) { SubmodWorker worker(design, design->module(modname), copy_mode, hidden_mode); @@ -409,7 +409,7 @@ struct SubmodPass : public Pass { RTLIL::Module *module = nullptr; for (auto mod : design->selected_modules()) { if (module != nullptr) - log_cmd_error("More than one module selected: %s %s\n", module->name, mod->name); + log_cmd_error("More than one module selected: %s %s\n", design->twines.str(module->meta_->name).data(), design->twines.str(mod->meta_->name).data()); module = mod; } if (module == nullptr) diff --git a/passes/hierarchy/uniquify.cc b/passes/hierarchy/uniquify.cc index 941f4dce8..048f72134 100644 --- a/passes/hierarchy/uniquify.cc +++ b/passes/hierarchy/uniquify.cc @@ -71,7 +71,8 @@ struct UniquifyPass : public Pass { for (auto cell : module->selected_cells()) { Module *tmod = design->module(cell->type); - IdString newname = module->name.str() + "." + cell->name.unescape(); + std::string tmod_name_str(design->twines.str(tmod->meta_->name)); + IdString newname = design->twines.str(module->meta_->name).data() + std::string(".") + cell->module->design->twines.str(cell->meta_->name); if (tmod == nullptr) continue; @@ -79,17 +80,18 @@ struct UniquifyPass : public Pass { if (tmod->get_blackbox_attribute()) continue; - if (tmod->get_bool_attribute(ID::unique) && newname == tmod->name) + TwineRef newname_ref = design->twines.add(Twine{newname.str()}); + if (tmod->get_bool_attribute(ID::unique) && newname_ref == tmod->meta_->name) continue; log("Creating module %s from %s.\n", newname.unescape(), tmod); auto smod = tmod->clone(); - smod->name = newname; + smod->meta_->name = newname_ref; cell->type = newname; smod->set_bool_attribute(ID::unique); if (smod->attributes.count(ID::hdlname) == 0) - smod->attributes[ID::hdlname] = string(tmod->name.unescape()); + smod->attributes[ID::hdlname] = RTLIL::Const(tmod_name_str); design->add(smod); did_something = true; diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 094a4e637..70f5ce65f 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -157,19 +157,19 @@ struct rules_t } log_debug("setting up %s\n", name); - Module* mod = design->addModule(name); + Module* mod = design->addModule(design->twines.add(Twine{name.str()})); mod->set_bool_attribute(ID::blackbox); for (auto [name, width] : inputs) { - log_debug("input %s width %d\n", name, width); - mod->addWire(name, width)->port_input = true; + log_debug("input %s width %d\n", name.c_str(), width); + mod->addWire(design->twines.add(Twine{name.str()}), width)->port_input = true; } for (auto [name, width] : outputs) { - log_debug("output %s width %d\n", name, width); - mod->addWire(name, width)->port_output = true; + log_debug("output %s width %d\n", name.c_str(), width); + mod->addWire(design->twines.add(Twine{name.str()}), width)->port_output = true; } mod->fixup_ports(); @@ -935,7 +935,7 @@ grow_read_ports:; for (int grid_a = 0; grid_a < acells; grid_a++) for (int dupidx = 0; dupidx < dup_count; dupidx++) { - Cell *c = module->addCell(module->uniquify(stringf("%s.%d.%d.%d", mem.memid, grid_d, grid_a, dupidx)), bram.name); + Cell *c = module->addCell(module->uniquify(module->design->twines.add(Twine{stringf("%s.%d.%d.%d", mem.memid.str(), grid_d, grid_a, dupidx)})), bram.name); log(" Creating %s cell at grid position <%d %d %d>: %s\n", bram.name.unescape(), grid_d, grid_a, dupidx, c); for (auto &vp : variant_params) @@ -964,7 +964,7 @@ grow_read_ports:; const char *pf = prefix.c_str(); if (pi.clocks && clock_domains.count(pi.clocks)) - c->setPort(stringf("\\CLK%d", (pi.clocks-1) % clocks_max + 1), clock_domains.at(pi.clocks).first); + c->setPort(module->design->twines.add(Twine{stringf("\\CLK%d", (pi.clocks-1) % clocks_max + 1)}), clock_domains.at(pi.clocks).first); if (pi.clkpol > 1 && clock_polarities.count(pi.clkpol)) c->setParam(stringf("\\CLKPOL%d", (pi.clkpol-1) % clkpol_max + 1), clock_polarities.at(pi.clkpol)); if (pi.transp > 1 && read_transp.count(pi.transp)) @@ -982,23 +982,23 @@ grow_read_ports:; if (GetSize(sig_addr) > bram.abits) { SigSpec extra_addr = sig_addr.extract(bram.abits, GetSize(sig_addr) - bram.abits); SigSpec extra_addr_sel = SigSpec(grid_a, GetSize(extra_addr)); - addr_ok = module->Eq(NEW_ID, extra_addr, extra_addr_sel); + addr_ok = module->Eq(NEW_TWINE, extra_addr, extra_addr_sel); } sig_addr.extend_u0(bram.abits); - c->setPort(stringf("\\%sADDR", pf), sig_addr); + c->setPort(module->design->twines.add(Twine{stringf("\\%sADDR", pf)}), sig_addr); if (pi.wrmode == 1) { if (pi.mapped_port == -1) { if (pi.enable) - c->setPort(stringf("\\%sEN", pf), Const(State::S0, pi.enable)); + c->setPort(module->design->twines.add(Twine{stringf("\\%sEN", pf)}), Const(State::S0, pi.enable)); continue; } auto &port = mem.wr_ports[pi.mapped_port]; SigSpec sig_data = port.data.extract(grid_d * bram.dbits, bram.dbits); - c->setPort(stringf("\\%sDATA", pf), sig_data); + c->setPort(module->design->twines.add(Twine{stringf("\\%sDATA", pf)}), sig_data); if (pi.enable) { @@ -1008,28 +1008,28 @@ grow_read_ports:; sig_en.append(port.en[stride * i + grid_d * bram.dbits]); if (!addr_ok.empty()) - sig_en = module->Mux(NEW_ID, SigSpec(0, GetSize(sig_en)), sig_en, addr_ok); + sig_en = module->Mux(NEW_TWINE, SigSpec(0, GetSize(sig_en)), sig_en, addr_ok); - c->setPort(stringf("\\%sEN", pf), sig_en); + c->setPort(module->design->twines.add(Twine{stringf("\\%sEN", pf)}), sig_en); } } else { if (pi.mapped_port == -1) { if (pi.enable) - c->setPort(stringf("\\%sEN", pf), State::S0); + c->setPort(module->design->twines.add(Twine{stringf("\\%sEN", pf)}), State::S0); continue; } auto &port = mem.rd_ports[pi.mapped_port]; SigSpec sig_data = port.data.extract(grid_d * bram.dbits, bram.dbits); SigSpec bram_dout = module->addWire(NEW_TWINE, bram.dbits); - c->setPort(stringf("\\%sDATA", pf), bram_dout); + c->setPort(module->design->twines.add(Twine{stringf("\\%sDATA", pf)}), bram_dout); SigSpec addr_ok_q = addr_ok; if (port.clk_enable && !addr_ok.empty()) { addr_ok_q = module->addWire(NEW_TWINE); - module->addDffe(NEW_ID, port.clk, port.en, addr_ok, addr_ok_q, port.clk_polarity); + module->addDffe(NEW_TWINE, port.clk, port.en, addr_ok, addr_ok_q, port.clk_polarity); } dout_cache[sig_data].first.append(addr_ok_q); @@ -1038,8 +1038,8 @@ grow_read_ports:; if (pi.enable) { SigSpec sig_en = port.en; if (!addr_ok.empty()) - sig_en = module->And(NEW_ID, sig_en, addr_ok); - c->setPort(stringf("\\%sEN", pf), sig_en); + sig_en = module->And(NEW_TWINE, sig_en, addr_ok); + c->setPort(module->design->twines.add(Twine{stringf("\\%sEN", pf)}), sig_en); } } } @@ -1056,7 +1056,7 @@ grow_read_ports:; else { log_assert(GetSize(it.first)*GetSize(it.second.first) == GetSize(it.second.second)); - module->addPmux(NEW_ID, SigSpec(State::Sx, GetSize(it.first)), it.second.second, it.second.first, it.first); + module->addPmux(NEW_TWINE, SigSpec(State::Sx, GetSize(it.first)), it.second.second, it.second.first, it.first); } } diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 12b8d2ad6..e7513a67f 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -176,7 +176,7 @@ struct MemQueryCache auto driver = *drivers.begin(); if (!driver.cell->type.in(ID($mux), ID($pmux))) return false; - log_assert(driver.port == ID::Y); + log_assert(driver.port == TW::Y); SigSpec sig_s = driver.cell->getPort(TW::S); int sel_sat = qcsat.importSigBit(sel); if (neg_sel) @@ -248,15 +248,15 @@ struct MemoryDffWorker auto consumer = *consumers.begin(); bool is_b; if (consumer.cell->type == ID($mux)) { - if (consumer.port == ID::A) { + if (consumer.port == TW::A) { is_b = false; - } else if (consumer.port == ID::B) { + } else if (consumer.port == TW::B) { is_b = true; } else { continue; } } else if (consumer.cell->type == ID($pmux)) { - if (consumer.port == ID::A) { + if (consumer.port == TW::A) { is_b = false; } else { continue; @@ -281,7 +281,7 @@ struct MemoryDffWorker auto &md = res.back(); md.size++; for (int j = 0; j < GetSize(md.sig_s); j++) { - SigBit obit = consumer.cell->getPort(is_b ? ID::A : ID::B).extract(j * mux_width + consumer.offset); + SigBit obit = consumer.cell->getPort(is_b ? TW::A : TW::B).extract(j * mux_width + consumer.offset); md.sig_other[j].append(obit); } prev_idx = i; @@ -334,7 +334,7 @@ struct MemoryDffWorker void handle_rd_port(Mem &mem, QuickConeSat &qcsat, int idx) { auto &port = mem.rd_ports[idx]; - log("Checking read port `%s'[%d] in module `%s': ", mem.memid, idx, module->name); + log("Checking read port `%s'[%d] in module `%s': ", mem.memid, idx, log_id(module)); std::vector muxdata; SigSpec data = walk_muxes(port.data, muxdata); @@ -507,11 +507,11 @@ struct MemoryDffWorker merger.remove_output_ff(bits); if (ff.has_ce && !ff.pol_ce) - ff.sig_ce = module->LogicNot(NEW_ID, ff.sig_ce); + ff.sig_ce = module->LogicNot(NEW_TWINE, ff.sig_ce); if (ff.has_arst && !ff.pol_arst) - ff.sig_arst = module->LogicNot(NEW_ID, ff.sig_arst); + ff.sig_arst = module->LogicNot(NEW_TWINE, ff.sig_arst); if (ff.has_srst && !ff.pol_srst) - ff.sig_srst = module->LogicNot(NEW_ID, ff.sig_srst); + ff.sig_srst = module->LogicNot(NEW_TWINE, ff.sig_srst); port.clk = ff.sig_clk; port.clk_enable = true; port.clk_polarity = ff.pol_clk; @@ -554,7 +554,7 @@ struct MemoryDffWorker void handle_rd_port_addr(Mem &mem, int idx) { auto &port = mem.rd_ports[idx]; - log("Checking read port address `%s'[%d] in module `%s': ", mem.memid, idx, module->name); + log("Checking read port address `%s'[%d] in module `%s': ", mem.memid, idx, log_id(module)); FfData ff; pool> bits; diff --git a/passes/memory/memory_libmap.cc b/passes/memory/memory_libmap.cc index 6239c2478..d17db2769 100644 --- a/passes/memory/memory_libmap.cc +++ b/passes/memory/memory_libmap.cc @@ -204,7 +204,7 @@ struct MemMapping { if (!check_init(rdef)) continue; if (rdef.prune_rom && mem.wr_ports.empty()) { - log_debug("memory %s.%s: rejecting mapping to %s: ROM mapping disabled (prune_rom set)\n", mem.module->name.unescape(), mem.memid.unescape(), rdef.id.unescape()); + log_debug("memory %s.%s: rejecting mapping to %s: ROM mapping disabled (prune_rom set)\n", log_id(mem.module), mem.memid.unescape(), rdef.id.unescape()); continue; } MemConfig cfg; @@ -380,7 +380,7 @@ void MemMapping::dump_configs(int stage) { default: abort(); } - log_debug("Memory %s.%s mapping candidates (%s):\n", mem.module->name.unescape(), mem.memid.unescape(), stage_name); + log_debug("Memory %s.%s mapping candidates (%s):\n", log_id(mem.module), mem.memid.unescape(), stage_name); if (logic_ok) { log_debug("- logic fallback\n"); log_debug(" - cost: %f\n", logic_cost); @@ -527,7 +527,7 @@ void MemMapping::determine_style() { auto find_attr = search_for_attribute(mem, ID::lram); if (find_attr.first && find_attr.second.as_bool()) { kind = RamKind::Huge; - log("found attribute 'lram' on memory %s.%s, forced mapping to huge RAM\n", mem.module->name.unescape(), mem.memid.unescape()); + log("found attribute 'lram' on memory %s.%s, forced mapping to huge RAM\n", log_id(mem.module), mem.memid.unescape()); return; } for (auto attr: {ID::ram_block, ID::rom_block, ID::ram_style, ID::rom_style, ID::ramstyle, ID::romstyle, ID::syn_ramstyle, ID::syn_romstyle}) { @@ -536,7 +536,7 @@ void MemMapping::determine_style() { Const val = find_attr.second; if (val == 1) { kind = RamKind::NotLogic; - log("found attribute '%s = 1' on memory %s.%s, disabled mapping to FF\n", attr.unescape(), mem.module->name.unescape(), mem.memid.unescape()); + log("found attribute '%s = 1' on memory %s.%s, disabled mapping to FF\n", attr.unescape(), log_id(mem.module), mem.memid.unescape()); return; } std::string val_s = val.decode_string(); @@ -549,20 +549,20 @@ void MemMapping::determine_style() { // Nothing. } else if (val_s == "logic" || val_s == "registers") { kind = RamKind::Logic; - log("found attribute '%s = %s' on memory %s.%s, forced mapping to FF\n", attr.unescape(), val_s, mem.module->name.unescape(), mem.memid.unescape()); + log("found attribute '%s = %s' on memory %s.%s, forced mapping to FF\n", attr.unescape(), val_s, log_id(mem.module), mem.memid.unescape()); } else if (val_s == "distributed") { kind = RamKind::Distributed; - log("found attribute '%s = %s' on memory %s.%s, forced mapping to distributed RAM\n", attr.unescape(), val_s, mem.module->name.unescape(), mem.memid.unescape()); + log("found attribute '%s = %s' on memory %s.%s, forced mapping to distributed RAM\n", attr.unescape(), val_s, log_id(mem.module), mem.memid.unescape()); } else if (val_s == "block" || val_s == "block_ram" || val_s == "ebr") { kind = RamKind::Block; - log("found attribute '%s = %s' on memory %s.%s, forced mapping to block RAM\n", attr.unescape(), val_s, mem.module->name.unescape(), mem.memid.unescape()); + log("found attribute '%s = %s' on memory %s.%s, forced mapping to block RAM\n", attr.unescape(), val_s, log_id(mem.module), mem.memid.unescape()); } else if (val_s == "huge" || val_s == "ultra") { kind = RamKind::Huge; - log("found attribute '%s = %s' on memory %s.%s, forced mapping to huge RAM\n", attr.unescape(), val_s, mem.module->name.unescape(), mem.memid.unescape()); + log("found attribute '%s = %s' on memory %s.%s, forced mapping to huge RAM\n", attr.unescape(), val_s, log_id(mem.module), mem.memid.unescape()); } else { kind = RamKind::NotLogic; style = val_s; - log("found attribute '%s = %s' on memory %s.%s, forced mapping to %s RAM\n", attr.unescape(), val_s, mem.module->name.unescape(), mem.memid.unescape(), val_s); + log("found attribute '%s = %s' on memory %s.%s, forced mapping to %s RAM\n", attr.unescape(), val_s, log_id(mem.module), mem.memid.unescape(), val_s); } return; } @@ -1626,8 +1626,8 @@ std::vector generate_demux(Mem &mem, int wpidx, const Swizzle &swz) { lo = new_lo; hi = new_hi; } - SigSpec in_range = mem.module->And(NEW_ID, mem.module->Ge(NEW_ID, addr, lo), mem.module->Lt(NEW_ID, addr, hi)); - sig_a = mem.module->Mux(NEW_ID, Const(State::S0, GetSize(sig_a)), sig_a, in_range); + SigSpec in_range = mem.module->And(NEW_TWINE, mem.module->Ge(NEW_TWINE, addr, lo), mem.module->Lt(NEW_TWINE, addr, hi)); + sig_a = mem.module->Mux(NEW_TWINE, Const(State::S0, GetSize(sig_a)), sig_a, in_range); } addr.extend_u0(swz.addr_shift + hi_bits, false); SigSpec sig_s; @@ -1639,7 +1639,7 @@ std::vector generate_demux(Mem &mem, int wpidx, const Swizzle &swz) { if (GetSize(sig_s) == 0) sig_y = sig_a; else - sig_y = mem.module->Demux(NEW_ID, sig_a, sig_s); + sig_y = mem.module->Demux(NEW_TWINE, sig_a, sig_s); for (int i = 0; i < ((swz.addr_end - swz.addr_start) >> swz.addr_shift); i++) { for (int j = 0; j < (1 << GetSize(swz.addr_mux_bits)); j++) { int hi = ((swz.addr_start >> swz.addr_shift) + i) & ((1 << hi_bits) - 1); @@ -1666,7 +1666,7 @@ std::vector generate_mux(Mem &mem, int rpidx, const Swizzle &swz) { } if (port.clk_enable) { SigSpec new_sig_s = mem.module->addWire(NEW_TWINE, GetSize(sig_s)); - mem.module->addDffe(NEW_ID, port.clk, port.en, sig_s, new_sig_s, port.clk_polarity); + mem.module->addDffe(NEW_TWINE, port.clk, port.en, sig_s, new_sig_s, port.clk_polarity); sig_s = new_sig_s; } SigSpec sig_a = Const(State::Sx, GetSize(port.data) << hi_bits << GetSize(swz.addr_mux_bits)); @@ -1680,7 +1680,7 @@ std::vector generate_mux(Mem &mem, int rpidx, const Swizzle &swz) { res.push_back(sig); } } - mem.module->addBmux(NEW_ID, sig_a, sig_s, port.data); + mem.module->addBmux(NEW_TWINE, sig_a, sig_s, port.data); return res; } @@ -1710,7 +1710,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector &cells, cons if (pdef.clk_en) { if (rpcfg.rd_en_to_clk_en) { if (pdef.rdwr == RdWrKind::NoChange) { - clk_en = mem.module->Or(NEW_ID, rport.en, mem.module->ReduceOr(NEW_ID, wport.en)); + clk_en = mem.module->Or(NEW_TWINE, rport.en, mem.module->ReduceOr(NEW_TWINE, wport.en)); } else { clk_en = rport.en; } @@ -1744,20 +1744,20 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector &cells, cons switch (pdef.clk_pol) { case ClkPolKind::Posedge: if (!clk_pol) - clk = mem.module->Not(NEW_ID, clk); + clk = mem.module->Not(NEW_TWINE, clk); break; case ClkPolKind::Negedge: if (clk_pol) - clk = mem.module->Not(NEW_ID, clk); + clk = mem.module->Not(NEW_TWINE, clk); break; case ClkPolKind::Anyedge: for (auto cell: cells) cell->setParam(stringf("\\PORT_%s_CLK_POL", name), clk_pol); } for (auto cell: cells) { - cell->setPort(stringf("\\PORT_%s_CLK", name), clk); + cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_CLK", name)}), clk); if (pdef.clk_en) - cell->setPort(stringf("\\PORT_%s_CLK_EN", name), clk_en); + cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_CLK_EN", name)}), clk_en); } } @@ -1819,7 +1819,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector &cells, cons for (int i = 0; i < hw_wr_wide_log2 && i < hw_rd_wide_log2; i++) hw_addr[i] = State::S0; for (auto cell: cells) - cell->setPort(stringf("\\PORT_%s_ADDR", name), hw_addr); + cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_ADDR", name)}), hw_addr); // Write part. if (pdef.kind != PortKind::Ar && pdef.kind != PortKind::Sr) { @@ -1850,31 +1850,31 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector &cells, cons hw_wren.append(big_wren[bit.mux_idx][bit.bit]); } } - cell->setPort(stringf("\\PORT_%s_WR_DATA", name), hw_wdata); + cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_WR_DATA", name)}), hw_wdata); if (pdef.wrbe_separate) { // TODO make some use of it - SigSpec en = mem.module->ReduceOr(NEW_ID, hw_wren); - cell->setPort(stringf("\\PORT_%s_WR_EN", name), en); - cell->setPort(stringf("\\PORT_%s_WR_BE", name), hw_wren); + SigSpec en = mem.module->ReduceOr(NEW_TWINE, hw_wren); + cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_WR_EN", name)}), en); + cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_WR_BE", name)}), hw_wren); if (cfg.def->width_mode != WidthMode::Single) cell->setParam(stringf("\\PORT_%s_WR_BE_WIDTH", name), GetSize(hw_wren)); } else { - cell->setPort(stringf("\\PORT_%s_WR_EN", name), hw_wren); + cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_WR_EN", name)}), hw_wren); if (cfg.def->byte != 0 && (cfg.def->width_mode != WidthMode::Single || opts.force_params)) cell->setParam(stringf("\\PORT_%s_WR_EN_WIDTH", name), GetSize(hw_wren)); } } } else { for (auto cell: cells) { - cell->setPort(stringf("\\PORT_%s_WR_DATA", name), Const(State::Sx, width)); + cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_WR_DATA", name)}), Const(State::Sx, width)); SigSpec hw_wren = Const(State::S0, width / effective_byte); if (pdef.wrbe_separate) { - cell->setPort(stringf("\\PORT_%s_WR_EN", name), State::S0); - cell->setPort(stringf("\\PORT_%s_WR_BE", name), hw_wren); + cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_WR_EN", name)}), State::S0); + cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_WR_BE", name)}), hw_wren); if (cfg.def->width_mode != WidthMode::Single) cell->setParam(stringf("\\PORT_%s_WR_BE_WIDTH", name), GetSize(hw_wren)); } else { - cell->setPort(stringf("\\PORT_%s_WR_EN", name), hw_wren); + cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_WR_EN", name)}), hw_wren); if (cfg.def->byte != 0 && cfg.def->width_mode != WidthMode::Single) cell->setParam(stringf("\\PORT_%s_WR_EN_WIDTH", name), GetSize(hw_wren)); } @@ -1894,11 +1894,11 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector &cells, cons auto cell = cells[rd]; if (pdef.kind == PortKind::Sr || pdef.kind == PortKind::Srsw) { if (pdef.rd_en) - cell->setPort(stringf("\\PORT_%s_RD_EN", name), rpcfg.rd_en_to_clk_en ? State::S1 : rport.en); + cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_RD_EN", name)}), rpcfg.rd_en_to_clk_en ? State::S1 : rport.en); if (pdef.rdarstval != ResetValKind::None) - cell->setPort(stringf("\\PORT_%s_RD_ARST", name), rport.arst); + cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_RD_ARST", name)}), rport.arst); if (pdef.rdsrstval != ResetValKind::None) - cell->setPort(stringf("\\PORT_%s_RD_SRST", name), rport.srst); + cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_RD_SRST", name)}), rport.srst); if (pdef.rdinitval == ResetValKind::Any || pdef.rdinitval == ResetValKind::NoUndef) { Const val = rport.init_value; if (pdef.rdarstval == ResetValKind::Init && rport.arst != State::S0) { @@ -1949,7 +1949,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector &cells, cons } } SigSpec hw_rdata = mem.module->addWire(NEW_TWINE, width); - cell->setPort(stringf("\\PORT_%s_RD_DATA", name), hw_rdata); + cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_RD_DATA", name)}), hw_rdata); SigSpec lhs; SigSpec rhs; for (int i = 0; i < GetSize(hw_rdata); i++) { @@ -1965,11 +1965,11 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector &cells, cons for (auto cell: cells) { if (pdef.kind == PortKind::Sr || pdef.kind == PortKind::Srsw) { if (pdef.rd_en) - cell->setPort(stringf("\\PORT_%s_RD_EN", name), State::S0); + cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_RD_EN", name)}), State::S0); if (pdef.rdarstval != ResetValKind::None) - cell->setPort(stringf("\\PORT_%s_RD_ARST", name), State::S0); + cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_RD_ARST", name)}), State::S0); if (pdef.rdsrstval != ResetValKind::None) - cell->setPort(stringf("\\PORT_%s_RD_SRST", name), State::S0); + cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_RD_SRST", name)}), State::S0); if (pdef.rdinitval == ResetValKind::Any) cell->setParam(stringf("\\PORT_%s_RD_INIT_VALUE", name), Const(State::Sx, width)); else if (pdef.rdinitval == ResetValKind::NoUndef) @@ -1984,14 +1984,14 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector &cells, cons cell->setParam(stringf("\\PORT_%s_RD_SRST_VALUE", name), Const(State::S0, width)); } SigSpec hw_rdata = mem.module->addWire(NEW_TWINE, width); - cell->setPort(stringf("\\PORT_%s_RD_DATA", name), hw_rdata); + cell->setPort(mem.module->design->twines.add(Twine{stringf("\\PORT_%s_RD_DATA", name)}), hw_rdata); } } } } void MemMapping::emit(const MemConfig &cfg) { - log("mapping memory %s.%s via %s\n", mem.module->name.unescape(), mem.memid.unescape(), cfg.def->id.unescape()); + log("mapping memory %s.%s via %s\n", log_id(mem.module), mem.memid.unescape(), cfg.def->id.unescape()); // First, handle emulations. if (cfg.emu_read_first) mem.emulate_read_first(&worker.initvals); @@ -2068,7 +2068,7 @@ void MemMapping::emit(const MemConfig &cfg) { for (int rp = 0; rp < cfg.repl_port; rp++) { std::vector cells; for (int rd = 0; rd < cfg.repl_d; rd++) { - Cell *cell = mem.module->addCell(stringf("%s.%d.%d", mem.memid, rp, rd), cfg.def->id); + Cell *cell = mem.module->addCell(mem.module->design->twines.add(Twine{stringf("%s.%d.%d", mem.memid.str(), rp, rd)}), cfg.def->id); if (cfg.def->width_mode == WidthMode::Global || opts.force_params) cell->setParam(ID::WIDTH, cfg.def->dbits[cfg.base_width_log2]); if (opts.force_params) @@ -2086,12 +2086,12 @@ void MemMapping::emit(const MemConfig &cfg) { auto &ccfg = cfg.shared_clocks[i]; if (cdef.anyedge) { cell->setParam(stringf("\\CLK_%s_POL", cdef.name), ccfg.used ? ccfg.polarity : true); - cell->setPort(stringf("\\CLK_%s", cdef.name), ccfg.used ? ccfg.clk : State::S0); + cell->setPort(mem.module->design->twines.add(Twine{stringf("\\CLK_%s", cdef.name)}), ccfg.used ? ccfg.clk : State::S0); } else { SigSpec sig = ccfg.used ? ccfg.clk : State::S0; if (ccfg.used && ccfg.invert) - sig = mem.module->Not(NEW_ID, sig); - cell->setPort(stringf("\\CLK_%s", cdef.name), sig); + sig = mem.module->Not(NEW_TWINE, sig); + cell->setPort(mem.module->design->twines.add(Twine{stringf("\\CLK_%s", cdef.name)}), sig); } } if (cfg.def->init == MemoryInitKind::Any || cfg.def->init == MemoryInitKind::NoUndef) { @@ -2252,9 +2252,9 @@ struct MemoryLibMapPass : public Pass { int best = map.logic_cost; if (!map.logic_ok) { if (map.cfgs.empty()) { - log_debug("Rejected candidates for mapping memory %s.%s:\n", module->name.unescape(), mem.memid.unescape()); + log_debug("Rejected candidates for mapping memory %s.%s:\n", log_id(module), mem.memid.unescape()); log_debug("%s", map.rejected_cfg_debug_msgs); - log_error("no valid mapping found for memory %s.%s\n", module->name.unescape(), mem.memid.unescape()); + log_error("no valid mapping found for memory %s.%s\n", log_id(module), mem.memid.unescape()); } idx = 0; best = map.cfgs[0].cost; @@ -2266,7 +2266,7 @@ struct MemoryLibMapPass : public Pass { } } if (idx == -1) { - log("using FF mapping for memory %s.%s\n", module->name.unescape(), mem.memid.unescape()); + log("using FF mapping for memory %s.%s\n", log_id(module), mem.memid.unescape()); } else { map.emit(map.cfgs[idx]); // Rebuild indices after modifying module diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 1ef4ade28..25bdb3f53 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -91,14 +91,15 @@ struct MemoryMapWorker std::pair key(addr_sig, addr_val); log_assert(GetSize(addr_sig) == GetSize(addr_val)); + TwineRef src_ref = mem_src.empty() ? Twine::Null : design->twines.add(Twine{mem_src}); if (decoder_cache.count(key) == 0) { if (GetSize(addr_sig) < 2) { - decoder_cache[key] = module->Eq(NEW_ID, addr_sig, addr_val, false, mem_src); + decoder_cache[key] = module->Eq(NEW_TWINE, addr_sig, addr_val, false, src_ref); } else { int split_at = GetSize(addr_sig) / 2; RTLIL::SigBit left_eq = addr_decode(addr_sig.extract(0, split_at), addr_val.extract(0, split_at)); RTLIL::SigBit right_eq = addr_decode(addr_sig.extract(split_at, GetSize(addr_sig) - split_at), addr_val.extract(split_at, GetSize(addr_val) - split_at)); - decoder_cache[key] = module->And(NEW_ID, left_eq, right_eq, false, mem_src); + decoder_cache[key] = module->And(NEW_TWINE, left_eq, right_eq, false, src_ref); } } @@ -118,7 +119,7 @@ struct MemoryMapWorker // pool slot directly. { TwineRef mid = (mem.module && mem.module->design) ? mem.module->design->obj_src_id(&mem) : Twine::Null; - mem_src = (mid != Twine::Null) ? TwinePool::format_ref(mid) : std::string(); + mem_src = (mid != Twine::Null) ? design->twines.str(mid) : std::string(); } SigSpec init_data = mem.get_init_data(); @@ -132,7 +133,7 @@ struct MemoryMapWorker const auto &cell_attr = mem.attributes[attr.first]; if (attr.second.empty()) { log("Not mapping memory %s in module %s (attribute %s is set).\n", - mem.memid.c_str(), module->name.c_str(), attr.first.c_str()); + mem.memid.c_str(), log_id(module), attr.first.c_str()); return; } @@ -146,10 +147,10 @@ struct MemoryMapWorker if (!found) { if (cell_attr.flags & RTLIL::CONST_FLAG_STRING) { log("Not mapping memory %s in module %s (attribute %s is set to \"%s\").\n", - mem.memid.c_str(), module->name.c_str(), attr.first.c_str(), cell_attr.decode_string().c_str()); + mem.memid.c_str(), log_id(module), attr.first.c_str(), cell_attr.decode_string().c_str()); } else { log("Not mapping memory %s in module %s (attribute %s is set to %d).\n", - mem.memid.c_str(), module->name.c_str(), attr.first.c_str(), cell_attr.as_int()); + mem.memid.c_str(), log_id(module), attr.first.c_str(), cell_attr.as_int()); } return; } @@ -183,29 +184,29 @@ struct MemoryMapWorker static_only = false; if (GetSize(refclock) != 0) log("Not mapping memory %s in module %s (mixed clocked and async write ports).\n", - mem.memid.c_str(), module->name.c_str()); + mem.memid.c_str(), log_id(module)); if (!formal) log("Not mapping memory %s in module %s (write port %d has no clock).\n", - mem.memid.c_str(), module->name.c_str(), i); + mem.memid.c_str(), log_id(module), i); async_wr = true; continue; } static_only = false; if (async_wr) log("Not mapping memory %s in module %s (mixed clocked and async write ports).\n", - mem.memid.c_str(), module->name.c_str()); + mem.memid.c_str(), log_id(module)); if (refclock.size() == 0) { refclock = port.clk; refclock_pol = port.clk_polarity; } if (port.clk != refclock || port.clk_polarity != refclock_pol) { log("Not mapping memory %s in module %s (write clock %d is incompatible with other clocks).\n", - mem.memid.c_str(), module->name.c_str(), i); + mem.memid.c_str(), log_id(module), i); return; } } - log("Mapping memory %s in module %s:\n", mem.memid, module->name); + log("Mapping memory %s in module %s:\n", mem.memid, log_id(module)); int abits = ceil_log2(mem.size); std::vector data_reg_in(1 << abits); @@ -237,32 +238,32 @@ struct MemoryMapWorker if (static_only) { // non-static part is a ROM, we only reach this with keepdc if (formal) { - c = module->addCell(ff_id, ID($ff)); + c = module->addCell(design->twines.add(Twine{ff_id}), ID($ff)); } else { - c = module->addCell(ff_id, ID($dff)); + c = module->addCell(design->twines.add(Twine{ff_id}), ID($dff)); c->parameters[ID::CLK_POLARITY] = RTLIL::Const(RTLIL::State::S1); c->setPort(TW::CLK, RTLIL::SigSpec(RTLIL::State::S0)); } } else if (async_wr) { log_assert(formal); // General async write not implemented yet, checked against above - c = module->addCell(ff_id, ID($ff)); + c = module->addCell(design->twines.add(Twine{ff_id}), ID($ff)); } else { - c = module->addCell(ff_id, ID($dff)); + c = module->addCell(design->twines.add(Twine{ff_id}), ID($dff)); c->parameters[ID::CLK_POLARITY] = RTLIL::Const(refclock_pol); c->setPort(TW::CLK, refclock); } - c->set_src_attribute(mem_src); + c->set_src_attribute(mem_src.empty() ? Twine::Null : design->twines.add(Twine{mem_src})); c->parameters[ID::WIDTH] = mem.width; - RTLIL::Wire *w_in = module->addWire(genid(mem.memid, "", addr, "$d"), mem.width); + RTLIL::Wire *w_in = module->addWire(design->twines.add(Twine{genid(mem.memid, "", addr, "$d")}), mem.width); data_reg_in[idx] = w_in; c->setPort(TW::D, w_in); - std::string w_out_name = stringf("%s[%d]", mem.memid, addr); - if (module->wire(RTLIL::IdString(w_out_name)) != nullptr) + std::string w_out_name = stringf("%s[%d]", mem.memid.str(), addr); + if (module->wire(design->twines.lookup(w_out_name)) != nullptr) w_out_name = genid(mem.memid, "", addr, "$q"); - RTLIL::Wire *w_out = module->addWire(w_out_name, mem.width); + RTLIL::Wire *w_out = module->addWire(design->twines.add(Twine{w_out_name}), mem.width); if (formal && mem.packed && mem.cell->name.c_str()[0] == '\\') { auto hdlname = mem.cell->get_hdlname_attribute(); @@ -305,15 +306,15 @@ struct MemoryMapWorker for (size_t k = 0; k < rd_signals.size(); k++) { - RTLIL::Cell *c = module->addCell(genid(mem.memid, "$rdmux", i, "", j, "", k), ID($mux)); - c->set_src_attribute(mem_src); + RTLIL::Cell *c = module->addCell(design->twines.add(Twine{genid(mem.memid, "$rdmux", i, "", j, "", k)}), ID($mux)); + c->set_src_attribute(mem_src.empty() ? Twine::Null : design->twines.add(Twine{mem_src})); c->parameters[ID::WIDTH] = GetSize(port.data); c->setPort(TW::Y, rd_signals[k]); c->setPort(TW::S, rd_addr.extract(abits-j-1, 1)); count_mux++; - c->setPort(TW::A, module->addWire(genid(mem.memid, "$rdmux", i, "", j, "", k, "$a"), GetSize(port.data))); - c->setPort(TW::B, module->addWire(genid(mem.memid, "$rdmux", i, "", j, "", k, "$b"), GetSize(port.data))); + c->setPort(TW::A, module->addWire(design->twines.add(Twine{genid(mem.memid, "$rdmux", i, "", j, "", k, "$a")}), GetSize(port.data))); + c->setPort(TW::B, module->addWire(design->twines.add(Twine{genid(mem.memid, "$rdmux", i, "", j, "", k, "$b")}), GetSize(port.data))); next_rd_signals.push_back(c->getPort(TW::A)); next_rd_signals.push_back(c->getPort(TW::B)); @@ -365,8 +366,8 @@ struct MemoryMapWorker if (wr_bit != State::S1) { - RTLIL::Cell *c = module->addCell(genid(mem.memid, "$wren", addr, "", j, "", wr_offset), ID($and)); - c->set_src_attribute(mem_src); + RTLIL::Cell *c = module->addCell(design->twines.add(Twine{genid(mem.memid, "$wren", addr, "", j, "", wr_offset)}), ID($and)); + c->set_src_attribute(mem_src.empty() ? Twine::Null : design->twines.add(Twine{mem_src})); c->parameters[ID::A_SIGNED] = RTLIL::Const(0); c->parameters[ID::B_SIGNED] = RTLIL::Const(0); c->parameters[ID::A_WIDTH] = RTLIL::Const(1); @@ -375,18 +376,18 @@ struct MemoryMapWorker c->setPort(TW::A, w); c->setPort(TW::B, wr_bit); - w = module->addWire(genid(mem.memid, "$wren", addr, "", j, "", wr_offset, "$y")); + w = module->addWire(design->twines.add(Twine{genid(mem.memid, "$wren", addr, "", j, "", wr_offset, "$y")})); c->setPort(TW::Y, RTLIL::SigSpec(w)); } - RTLIL::Cell *c = module->addCell(genid(mem.memid, "$wrmux", addr, "", j, "", wr_offset), ID($mux)); - c->set_src_attribute(mem_src); + RTLIL::Cell *c = module->addCell(design->twines.add(Twine{genid(mem.memid, "$wrmux", addr, "", j, "", wr_offset)}), ID($mux)); + c->set_src_attribute(mem_src.empty() ? Twine::Null : design->twines.add(Twine{mem_src})); c->parameters[ID::WIDTH] = wr_width; c->setPort(TW::A, sig.extract(wr_offset, wr_width)); c->setPort(TW::B, port.data.extract(wr_offset + sub * mem.width, wr_width)); c->setPort(TW::S, RTLIL::SigSpec(w)); - w = module->addWire(genid(mem.memid, "$wrmux", addr, "", j, "", wr_offset, "$y"), wr_width); + w = module->addWire(design->twines.add(Twine{genid(mem.memid, "$wrmux", addr, "", j, "", wr_offset, "$y")}), wr_width); c->setPort(TW::Y, w); sig.replace(wr_offset, w); diff --git a/passes/memory/memory_memx.cc b/passes/memory/memory_memx.cc index 29ccbe61f..680e2e6bf 100644 --- a/passes/memory/memory_memx.cc +++ b/passes/memory/memory_memx.cc @@ -42,10 +42,10 @@ struct MemoryMemxPass : public Pass { addr.extend_u0(32); - SigSpec res = mem.module->Nex(NEW_ID, mem.module->ReduceXor(NEW_ID, addr), mem.module->ReduceXor(NEW_ID, {addr, State::S1})); + SigSpec res = mem.module->Nex(NEW_TWINE, mem.module->ReduceXor(NEW_TWINE, addr), mem.module->ReduceXor(NEW_TWINE, {addr, State::S1})); if (start_addr != 0) - res = mem.module->LogicAnd(NEW_ID, res, mem.module->Ge(NEW_ID, addr, start_addr)); - res = mem.module->LogicAnd(NEW_ID, res, mem.module->Lt(NEW_ID, addr, end_addr)); + res = mem.module->LogicAnd(NEW_TWINE, res, mem.module->Ge(NEW_TWINE, addr, start_addr)); + res = mem.module->LogicAnd(NEW_TWINE, res, mem.module->Lt(NEW_TWINE, addr, end_addr)); return res; } @@ -64,13 +64,13 @@ struct MemoryMemxPass : public Pass { SigSpec addr_ok = make_addr_check(mem, port.addr); Wire *raw_rdata = module->addWire(NEW_TWINE, GetSize(port.data)); - module->addMux(NEW_ID, SigSpec(State::Sx, GetSize(port.data)), raw_rdata, addr_ok, port.data); + module->addMux(NEW_TWINE, SigSpec(State::Sx, GetSize(port.data)), raw_rdata, addr_ok, port.data); port.data = raw_rdata; } for (auto &port : mem.wr_ports) { SigSpec addr_ok = make_addr_check(mem, port.addr); - port.en = module->And(NEW_ID, port.en, addr_ok.repeat(GetSize(port.en))); + port.en = module->And(NEW_TWINE, port.en, addr_ok.repeat(GetSize(port.en))); } mem.emit(); diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index adfe6ddaa..5fb187095 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -271,8 +271,8 @@ struct MemoryShareWorker port1.data.replace(pos, port2.data.extract(pos, width)); new_en = port2.en[pos]; } else { - port1.data.replace(pos, module->Mux(NEW_ID, port1.data.extract(pos, width), port2.data.extract(pos, width), port2.en[pos])); - new_en = module->Or(NEW_ID, port1.en[pos], port2.en[pos]); + port1.data.replace(pos, module->Mux(NEW_TWINE, port1.data.extract(pos, width), port2.data.extract(pos, width), port2.en[pos])); + new_en = module->Or(NEW_TWINE, port1.en[pos], port2.en[pos]); } for (int k = pos; k < epos; k++) port1.en[k] = new_en; @@ -424,17 +424,17 @@ struct MemoryShareWorker RTLIL::SigSpec this_data = port2.data; std::vector this_en = modwalker.sigmap(port2.en); - RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en); + RTLIL::SigBit this_en_active = module->ReduceOr(NEW_TWINE, this_en); if (GetSize(last_addr) < GetSize(this_addr)) last_addr.extend_u0(GetSize(this_addr)); else this_addr.extend_u0(GetSize(last_addr)); - SigSpec new_addr = module->Mux(NEW_ID, last_addr.extract_end(port1.wide_log2), this_addr.extract_end(port1.wide_log2), this_en_active); + SigSpec new_addr = module->Mux(NEW_TWINE, last_addr.extract_end(port1.wide_log2), this_addr.extract_end(port1.wide_log2), this_en_active); port1.addr = SigSpec({new_addr, port1.addr.extract(0, port1.wide_log2)}); - port1.data = module->Mux(NEW_ID, last_data, this_data, this_en_active); + port1.data = module->Mux(NEW_TWINE, last_data, this_data, this_en_active); std::map, int> groups_en; RTLIL::SigSpec grouped_last_en, grouped_this_en, en; @@ -451,7 +451,7 @@ struct MemoryShareWorker en.append(RTLIL::SigSpec(grouped_en, groups_en[key])); } - module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en); + module->addMux(NEW_TWINE, grouped_last_en, grouped_this_en, this_en_active, grouped_en); port1.en = en; port2.removed = true; diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc index 86417b748..63eba0f01 100644 --- a/passes/opt/muxpack.cc +++ b/passes/opt/muxpack.cc @@ -291,7 +291,7 @@ struct MuxpackWorker else { log_assert(cursor_cell->type == ID($mux)); b_sig.append(cursor_cell->getPort(TW::A)); - s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(TW::S))); + s_sig.append(module->LogicNot(NEW_TWINE, cursor_cell->getPort(TW::S))); } remove_cells.insert(cursor_cell); } diff --git a/passes/opt/opt_balance_tree.cc b/passes/opt/opt_balance_tree.cc index bdf603837..f839606fb 100644 --- a/passes/opt/opt_balance_tree.cc +++ b/passes/opt/opt_balance_tree.cc @@ -256,7 +256,7 @@ struct OptBalanceTreeWorker { Cell* x = bfs_queue.front(); bfs_queue.pop_front(); - for (IdString port: {ID::A, ID::B}) { + for (TwineRef port: {TW::A, TW::B}) { auto sig = sigmap(x->getPort(port)); Cell* drv = sig_to_driver[sig]; bool drv_ok = drv && is_right_type(drv, cell_type); @@ -271,7 +271,7 @@ struct OptBalanceTreeWorker { bfs_queue.push_back(drv); } else { sources[sig]++; - signeds[sig] = x->getParam(port == ID::A ? ID::A_SIGNED : ID::B_SIGNED).as_bool(); + signeds[sig] = x->getParam(port == TW::A ? ID::A_SIGNED : ID::B_SIGNED).as_bool(); } } } diff --git a/passes/opt/opt_clean/cells_all.cc b/passes/opt/opt_clean/cells_all.cc index d9d3f8b61..c1125f5ca 100644 --- a/passes/opt/opt_clean/cells_all.cc +++ b/passes/opt/opt_clean/cells_all.cc @@ -200,9 +200,10 @@ ConflictLogs explore(CellAnalysis& analysis, CellTraversal& traversal, const Sig continue; auto bit = actx.assign_map(raw_bit); if (bit.wire == nullptr && clean_ctx.ct_all.cell_known(cell->type)) { + auto twines = cell->module->design->twines; std::string msg = stringf("Driver-driver conflict " "for %s between cell %s.%s and constant %s in %s: Resolved using constant.", - log_signal(raw_bit), cell->name.unescape(), actx.mod->design->twines.str(it2.first), log_signal(bit), actx.mod->name); + log_signal(raw_bit), twines.str(cell->meta_->name), twines.str(it2.first), log_signal(bit), twines.str(actx.mod->meta_->name)); logs.logs.insert(ctx, {wire_map(raw_bit), msg}); } if (bit.wire != nullptr) @@ -237,7 +238,7 @@ struct MemAnalysis { dict indices; MemAnalysis(const RTLIL::Module* mod) : unused(mod->memories.size()), indices() { for (int i = 0; i < GetSize(mod->memories); ++i) { - indices[mod->memories.element(i)->first.str()] = i; + indices[mod->design->twines.str(mod->memories.element(i)->first)] = i; unused[i].store(true, std::memory_order_relaxed); } } @@ -324,9 +325,10 @@ void remove_mems(RTLIL::Module* mod, const MemAnalysis& mem_analysis, bool verbo for (const auto &it : mem_analysis.indices) { if (!mem_analysis.unused[it.second].load(std::memory_order_relaxed)) continue; - RTLIL::IdString id(it.first); + std::string id_s = it.first; + TwineRef id = mod->design->twines.add(Twine{it.first}); if (verbose) - log_debug(" removing unused memory `%s'.\n", id.unescape()); + log_debug(" removing unused memory `%s'.\n", id_s); delete mod->memories.at(id); mod->memories.erase(id); } diff --git a/passes/opt/opt_demorgan.cc b/passes/opt/opt_demorgan.cc index b1d938134..b32cd33b4 100644 --- a/passes/opt/opt_demorgan.cc +++ b/passes/opt/opt_demorgan.cc @@ -43,7 +43,7 @@ void demorgan_worker( if (GetSize(insig) < 1) return; - log("Inspecting %s cell %s (%d inputs)\n", cell->type.unescape(), cell->name.unescape(), GetSize(insig)); + log("Inspecting %s cell %s (%d inputs)\n", cell->type.unescape(), cell->module->design->twines.str(cell->meta_->name), GetSize(insig)); int num_inverted = 0; for(int i=0; itype == ID($_NOT_)) + if(x.port == TW::Y && x.cell->type == ID($_NOT_)) { inverted = true; break; @@ -89,7 +89,7 @@ void demorgan_worker( RTLIL::Cell* srcinv = NULL; for(auto x : ports) { - if(x.port == ID::Y && x.cell->type == ID($_NOT_)) + if(x.port == TW::Y && x.cell->type == ID($_NOT_)) { srcinv = x.cell; break; @@ -100,7 +100,7 @@ void demorgan_worker( if(!srcinv) { auto inverted_b = m->addWire(NEW_TWINE); - m->addNot(NEW_ID, RTLIL::SigSpec(b), RTLIL::SigSpec(inverted_b)); + m->addNot(NEW_TWINE, RTLIL::SigSpec(b), RTLIL::SigSpec(inverted_b)); insig[i] = inverted_b; } @@ -167,7 +167,7 @@ void demorgan_worker( //Add an inverter to the output auto inverted_output = cell->getPort(TW::Y); auto uninverted_output = m->addWire(NEW_TWINE); - m->addNot(NEW_ID, RTLIL::SigSpec(uninverted_output), inverted_output); + m->addNot(NEW_TWINE, RTLIL::SigSpec(uninverted_output), inverted_output); cell->setPort(TW::Y, uninverted_output); } diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 2a28e04a4..17a117ea8 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -124,7 +124,7 @@ void log_replace_sig(RTLIL::Module *module, RTLIL::Cell *cell, { log_debug("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n", cell->type.c_str(), cell->name.c_str(), info.c_str(), - module->name.c_str(), log_signal(old_sig), log_signal(new_sig)); + module->design->twines.str(module->meta_->name).c_str(), log_signal(old_sig), log_signal(new_sig)); } void log_replace_port(RTLIL::Module *module, RTLIL::Cell *cell, @@ -714,7 +714,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons { if (cell->type == ID($reduce_xnor)) { log_debug("Replacing %s cell `%s' in module `%s' with $not cell.\n", - cell->type.unescape(), cell->name.unescape(), module); + cell->type.unescape(), cell->module->design->twines.str(cell->meta_->name), module); cell->type = ID($not); did_something = true; } else { @@ -735,7 +735,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (a_fully_const != b_fully_const) { log_debug("Replacing %s cell `%s' in module `%s' having one fully constant input\n", - cell->type.unescape(), cell->name.unescape(), module); + cell->type.unescape(), cell->module->design->twines.str(cell->meta_->name), module); RTLIL::SigSpec sig_y = assign_map(cell->getPort(TW::Y)); int width = GetSize(cell->getPort(TW::Y)); @@ -885,7 +885,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (GetSize(new_sig_a) < GetSize(sig_a)) { log_debug("Replacing port A of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n", - cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_sig_a)); + cell->type.c_str(), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str(), log_signal(sig_a), log_signal(new_sig_a)); cell->setPort(TW::A, new_sig_a); cell->parameters.at(ID::A_WIDTH) = GetSize(new_sig_a); did_something = true; @@ -907,7 +907,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (GetSize(new_sig_b) < GetSize(sig_b)) { log_debug("Replacing port B of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n", - cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_sig_b)); + cell->type.c_str(), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str(), log_signal(sig_b), log_signal(new_sig_b)); cell->setPort(TW::B, new_sig_b); cell->parameters.at(ID::B_WIDTH) = GetSize(new_sig_b); did_something = true; @@ -932,7 +932,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (new_a != RTLIL::State::Sm && RTLIL::SigSpec(new_a) != sig_a) { log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", - cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); + cell->type.c_str(), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str(), log_signal(sig_a), log_signal(new_a)); cell->setPort(TW::A, sig_a = new_a); cell->parameters.at(ID::A_WIDTH) = 1; did_something = true; @@ -957,7 +957,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (new_a != RTLIL::State::Sm && RTLIL::SigSpec(new_a) != sig_a) { log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", - cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); + cell->type.c_str(), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str(), log_signal(sig_a), log_signal(new_a)); cell->setPort(TW::A, sig_a = new_a); cell->parameters.at(ID::A_WIDTH) = 1; did_something = true; @@ -982,7 +982,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (new_b != RTLIL::State::Sm && RTLIL::SigSpec(new_b) != sig_b) { log_debug("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", - cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b)); + cell->type.c_str(), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str(), log_signal(sig_b), log_signal(new_b)); cell->setPort(TW::B, sig_b = new_b); cell->parameters.at(ID::B_WIDTH) = 1; did_something = true; @@ -1259,7 +1259,7 @@ skip_fine_alu: ACTION_DO(TW::Y, cell->getPort(TW::A)); if (input == State::S0 && !a.is_fully_undef()) { log_debug("Replacing data input of %s cell `%s' in module `%s' with constant undef.\n", - cell->type.c_str(), cell->name.c_str(), module->name.c_str()); + cell->type.c_str(), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str()); cell->setPort(TW::A, SigSpec(State::Sx, GetSize(a))); did_something = true; goto next_cell; @@ -1468,7 +1468,7 @@ skip_fine_alu: if (identity_wrt_a || identity_wrt_b) { log_debug("Replacing %s cell `%s' in module `%s' with identity for port %c.\n", - cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B'); + cell->type.c_str(), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str(), identity_wrt_a ? 'A' : 'B'); if (cell->type == ID($alu)) { bool a_signed = cell->parameters[ID::A_SIGNED].as_bool(); @@ -1794,14 +1794,14 @@ skip_identity: // 2^B = 1<name.c_str(), module->name.c_str()); + cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str()); cell->type = ID($shl); cell->parameters[ID::A_WIDTH] = 1; cell->setPort(TW::A, Const(State::S1, 1)); } else { log_debug("Replacing pow cell `%s' in module `%s' with multiply and left-shift\n", - cell->name.c_str(), module->name.c_str()); + cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str()); OptExprPatcher patcher(module, &assign_map); int a_width = cell->parameters[ID::A_WIDTH].as_int(); @@ -1844,7 +1844,7 @@ skip_identity: if (sig_a.is_fully_zero()) { log_debug("Replacing multiply-by-zero cell `%s' in module `%s' with zero-driver.\n", - cell->name.c_str(), module->name.c_str()); + cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str()); OptExprPatcher patcher(module, &assign_map); patcher.patch(cell, TW::Y, RTLIL::SigSpec(0, sig_y.size()), "mul_zero"); @@ -1855,7 +1855,7 @@ skip_identity: if (sig_a.is_onehot(&exp) && !(a_signed && exp == GetSize(sig_a) - 1)) { log_debug("Replacing multiply-by-%s cell `%s' in module `%s' with shift-by-%d.\n", - log_signal(sig_a), cell->name.c_str(), module->name.c_str(), exp); + log_signal(sig_a), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str(), exp); if (!swapped_ab) { cell->setPort(TW::A, cell->getPort(TW::B)); @@ -1888,7 +1888,7 @@ skip_identity: if (a_zeros || b_zeros) { int y_zeros = a_zeros + b_zeros; log_debug("Removing low %d A and %d B bits from cell `%s' in module `%s'.\n", - a_zeros, b_zeros, cell->name.c_str(), module->name.c_str()); + a_zeros, b_zeros, cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str()); if (y_zeros >= GetSize(sig_y)) { OptExprPatcher patcher(module, &assign_map); @@ -1927,7 +1927,7 @@ skip_identity: if (sig_b.is_fully_zero()) { log_debug("Replacing divide-by-zero cell `%s' in module `%s' with undef-driver.\n", - cell->name.c_str(), module->name.c_str()); + cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str()); OptExprPatcher patcher(module, &assign_map); patcher.patch(cell, TW::Y, RTLIL::SigSpec(State::Sx, sig_y.size()), "div_zero"); @@ -1942,7 +1942,7 @@ skip_identity: bool is_truncating = cell->type == ID($div); log_debug("Replacing %s-divide-by-%s cell `%s' in module `%s' with shift-by-%d.\n", is_truncating ? "truncating" : "flooring", - log_signal(sig_b), cell->name.c_str(), module->name.c_str(), exp); + log_signal(sig_b), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str(), exp); Const new_b = exp; @@ -1970,7 +1970,7 @@ skip_identity: bool is_truncating = cell->type == ID($mod); log_debug("Replacing %s-modulo-by-%s cell `%s' in module `%s' with bitmask.\n", is_truncating ? "truncating" : "flooring", - log_signal(sig_b), cell->name.c_str(), module->name.c_str()); + log_signal(sig_b), cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str()); // truncating modulo has the same masked bits as flooring modulo, but // the sign bits are those of A (except when R=0) @@ -2055,7 +2055,7 @@ skip_identity: for (auto &p : split_points) log_debug("Splitting $alu cell `%s' in module `%s' at const-carry point %d.\n", - cell->name.c_str(), module->name.c_str(), p.first); + cell->name.c_str(), module->design->twines.str(module->meta_->name).c_str(), p.first); if (split_points.back().first != GetSize(sig_y)) split_points.push_back(std::make_pair(GetSize(sig_y), State::Sx)); diff --git a/passes/opt/opt_ffinv.cc b/passes/opt/opt_ffinv.cc index 216ebce4d..c74ad2a72 100644 --- a/passes/opt/opt_ffinv.cc +++ b/passes/opt/opt_ffinv.cc @@ -48,9 +48,9 @@ struct OptFfInvWorker return false; Cell *d_inv = nullptr; for (auto &port: d_ports) { - if (port.cell == ff.cell && port.port == ID::D) + if (port.cell == ff.cell && port.port == TW::D) continue; - if (port.port != ID::Y) + if (port.port != TW::Y) return false; if (port.cell->type.in(ID($not), ID($_NOT_))) { // OK @@ -72,11 +72,11 @@ struct OptFfInvWorker auto q_ports = index.query_ports(ff.sig_q); pool q_luts; for (auto &port: q_ports) { - if (port.cell == ff.cell && port.port == ID::Q) + if (port.cell == ff.cell && port.port == TW::Q) continue; if (port.cell == d_inv) return false; - if (port.port != ID::A) + if (port.port != TW::A) return false; if (!port.cell->type.in(ID($not), ID($_NOT_), ID($lut))) return false; @@ -133,9 +133,9 @@ struct OptFfInvWorker if (d_ports.size() != 2) return false; for (auto &port: d_ports) { - if (port.cell == ff.cell && port.port == ID::D) + if (port.cell == ff.cell && port.port == TW::D) continue; - if (port.port != ID::Y) + if (port.port != TW::Y) return false; if (!port.cell->type.in(ID($not), ID($_NOT_), ID($lut))) return false; @@ -151,11 +151,11 @@ struct OptFfInvWorker return false; Cell *q_inv = nullptr; for (auto &port: q_ports) { - if (port.cell == ff.cell && port.port == ID::Q) + if (port.cell == ff.cell && port.port == TW::Q) continue; if (port.cell == d_lut) return false; - if (port.port != ID::A) + if (port.port != TW::A) return false; if (port.cell->type.in(ID($not), ID($_NOT_))) { // OK diff --git a/passes/opt/opt_lut_ins.cc b/passes/opt/opt_lut_ins.cc index 7881b5d75..a7cdb27a1 100644 --- a/passes/opt/opt_lut_ins.cc +++ b/passes/opt/opt_lut_ins.cc @@ -83,44 +83,44 @@ struct OptLutInsPass : public Pass { output = cell->getPort(TW::Y); lut = cell->getParam(ID::LUT); } else if (techname == "xilinx" || techname == "gowin" || techname == "analogdevices") { - if (cell->type == ID(LUT1)) { + if (cell->type == ID::LUT1) { inputs = { - cell->getPort(ID(I0)), + cell->getPort(TW::I0), }; - } else if (cell->type == ID(LUT2)) { + } else if (cell->type == ID::LUT2) { inputs = { - cell->getPort(ID(I0)), - cell->getPort(ID(I1)), + cell->getPort(TW::I0), + cell->getPort(TW::I1), }; - } else if (cell->type == ID(LUT3)) { + } else if (cell->type == ID::LUT3) { inputs = { - cell->getPort(ID(I0)), - cell->getPort(ID(I1)), - cell->getPort(ID(I2)), + cell->getPort(TW::I0), + cell->getPort(TW::I1), + cell->getPort(TW::I2), }; - } else if (cell->type == ID(LUT4)) { + } else if (cell->type == ID::LUT4) { inputs = { - cell->getPort(ID(I0)), - cell->getPort(ID(I1)), - cell->getPort(ID(I2)), - cell->getPort(ID(I3)), + cell->getPort(TW::I0), + cell->getPort(TW::I1), + cell->getPort(TW::I2), + cell->getPort(TW::I3), }; - } else if (cell->type == ID(LUT5)) { + } else if (cell->type == ID::LUT5) { inputs = { - cell->getPort(ID(I0)), - cell->getPort(ID(I1)), - cell->getPort(ID(I2)), - cell->getPort(ID(I3)), - cell->getPort(ID(I4)), + cell->getPort(TW::I0), + cell->getPort(TW::I1), + cell->getPort(TW::I2), + cell->getPort(TW::I3), + cell->getPort(TW::I4), }; - } else if (cell->type == ID(LUT6)) { + } else if (cell->type == ID::LUT6) { inputs = { - cell->getPort(ID(I0)), - cell->getPort(ID(I1)), - cell->getPort(ID(I2)), - cell->getPort(ID(I3)), - cell->getPort(ID(I4)), - cell->getPort(ID(I5)), + cell->getPort(TW::I0), + cell->getPort(TW::I1), + cell->getPort(TW::I2), + cell->getPort(TW::I3), + cell->getPort(TW::I4), + cell->getPort(TW::I5), }; } else { // Not a LUT. @@ -140,7 +140,7 @@ struct OptLutInsPass : public Pass { cell->getPort(TW::D), }; lut = cell->getParam(ID::INIT); - output = cell->getPort(ID(Z)); + output = cell->getPort(TW::Z); ignore_const = true; } else { // Not a LUT. @@ -255,23 +255,23 @@ struct OptLutInsPass : public Pass { cell->type = ID(LUT6); else log_assert(0); - cell->unsetPort(ID(I0)); - cell->unsetPort(ID(I1)); - cell->unsetPort(ID(I2)); - cell->unsetPort(ID(I3)); - cell->unsetPort(ID(I4)); - cell->unsetPort(ID(I5)); - cell->setPort(ID(I0), new_inputs[0]); + cell->unsetPort(TW::I0); + cell->unsetPort(TW::I1); + cell->unsetPort(TW::I2); + cell->unsetPort(TW::I3); + cell->unsetPort(TW::I4); + cell->unsetPort(TW::I5); + cell->setPort(TW::I0, new_inputs[0]); if (GetSize(new_inputs) >= 2) - cell->setPort(ID(I1), new_inputs[1]); + cell->setPort(TW::I1, new_inputs[1]); if (GetSize(new_inputs) >= 3) - cell->setPort(ID(I2), new_inputs[2]); + cell->setPort(TW::I2, new_inputs[2]); if (GetSize(new_inputs) >= 4) - cell->setPort(ID(I3), new_inputs[3]); + cell->setPort(TW::I3, new_inputs[3]); if (GetSize(new_inputs) >= 5) - cell->setPort(ID(I4), new_inputs[4]); + cell->setPort(TW::I4, new_inputs[4]); if (GetSize(new_inputs) >= 6) - cell->setPort(ID(I5), new_inputs[5]); + cell->setPort(TW::I5, new_inputs[5]); } } } diff --git a/passes/opt/opt_mem_feedback.cc b/passes/opt/opt_mem_feedback.cc index f7648be0b..a41f7e2e5 100644 --- a/passes/opt/opt_mem_feedback.cc +++ b/passes/opt/opt_mem_feedback.cc @@ -120,7 +120,7 @@ struct OptMemFeedbackWorker sig1.append(it.first); sig2.append(it.second ? RTLIL::State::S1 : RTLIL::State::S0); } - terms.append(module->Ne(NEW_ID, sig1, sig2)); + terms.append(module->Ne(NEW_TWINE, sig1, sig2)); } if (olden != State::S1) @@ -130,7 +130,7 @@ struct OptMemFeedbackWorker terms = State::S1; if (GetSize(terms) > 1) - terms = module->ReduceAnd(NEW_ID, terms); + terms = module->ReduceAnd(NEW_TWINE, terms); return conditions_logic_cache[key] = terms; } diff --git a/passes/opt/opt_mem_widen.cc b/passes/opt/opt_mem_widen.cc index f642666db..b7bc748c4 100644 --- a/passes/opt/opt_mem_widen.cc +++ b/passes/opt/opt_mem_widen.cc @@ -65,7 +65,7 @@ struct OptMemWidenPass : public Pass { factor_log2 = port.wide_log2; if (factor_log2 == 0) continue; - log("Widening base width of memory %s in module %s by factor %d.\n", mem.memid.unescape(), module->name.unescape(), 1 << factor_log2); + log("Widening base width of memory %s in module %s by factor %d.\n", mem.memid.unescape(), design->twines.str(module->meta_->name).c_str(), 1 << factor_log2); total_count++; // The inits are too messy to expand one-by-one, for they may // collide with one another after expansion. Just hit it with diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index de8278bc5..da123d5ca 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -207,7 +207,7 @@ struct OptMergeWorker FfInitVals initvals; initvals.set(&assign_map, module); - log("Finding identical cells in module `%s'.\n", module->name); + log("Finding identical cells in module `%s'.\n", module->design->twines.str(module->meta_->name).c_str()); // Use no more than one worker per thousand cells, rounded down, so // we only start multithreading with at least 2000 cells. @@ -242,7 +242,7 @@ struct OptMergeWorker while (did_something) { int cells_size = module->cells_size(); - log("Computing hashes of %d cells of `%s'.\n", cells_size, module->name); + log("Computing hashes of %d cells of `%s'.\n", cells_size, module->design->twines.str(module->meta_->name).c_str()); std::vector>> sharded_bucketed_cell_hashes(workers); int cell_index = 0; @@ -264,7 +264,7 @@ struct OptMergeWorker sharded_bucketed_cell_hashes[i] = std::move(cell_hashes_queues[i].pop_front()->bucketed_cell_hashes); } - log("Finding duplicate cells in `%s'.\n", module->name); + log("Finding duplicate cells in `%s'.\n", module->design->twines.str(module->meta_->name).c_str()); std::vector merged_duplicates; { Multithreading multithreading; @@ -311,7 +311,7 @@ struct OptMergeWorker port_replacements.emplace_back(it.first, keep_sig); } } - log_debug(" Removing %s cell `%s' from module `%s'.\n", remove_cell->type, remove_cell->name, module->name); + log_debug(" Removing %s cell `%s' from module `%s'.\n", remove_cell->type, log_id(remove_cell->name), module->design->twines.str(module->meta_->name).c_str()); RTLIL::Patch patcher(module, &assign_map); // Single-output cell types take the compatible Patch::patch // path; multi-output types (e.g. $alu) use patch_ports, diff --git a/passes/opt/opt_merge_inc.cc b/passes/opt/opt_merge_inc.cc index fa4d16ae7..932b88dc9 100644 --- a/passes/opt/opt_merge_inc.cc +++ b/passes/opt/opt_merge_inc.cc @@ -83,7 +83,7 @@ struct OptMergeIncWorker { total_count = 0; - log("Finding identical cells in module `%s'.\n", module->name); + log("Finding identical cells in module `%s'.\n", module->design->twines.str(module->meta_->name).c_str()); assign_map.set(module); initvals.set(&assign_map, module); @@ -281,7 +281,7 @@ struct OptMergeIncWorker } } - log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type, cell->name, module->name); + log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type, log_id(cell->name), module->design->twines.str(module->meta_->name).c_str()); RTLIL::Patch patcher(module, &assign_map); if (port_replacements.size() == 1) { patcher.patch(cell, port_replacements[0].first, port_replacements[0].second, diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 85d1fbf7f..bce8f551b 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -226,7 +226,7 @@ struct OptMuxtreeWorker OptMuxtreeWorker(RTLIL::Design *design, RTLIL::Module *module) : design(design), module(module), assign_map(module), removed_count(0) { - log("Running muxtree optimizer on module %s..\n", module->name); + log("Running muxtree optimizer on module %s..\n", module->design->twines.str(module->meta_->name).c_str()); log(" Creating internal representation of mux trees.\n"); @@ -472,7 +472,7 @@ struct OptMuxtreeWorker int width_if_b = 0; idict ctrl_bits; - if (portname == ID::B) + if (portname == TW::B) width_if_b = GetSize(muxinfo.cell->getPort(TW::A)); for (int bit : sig2bits(muxinfo.cell->getPort(TW::S), false)) ctrl_bits(bit); @@ -519,7 +519,7 @@ struct OptMuxtreeWorker } if (did_something) { - log(" Replacing known input bits on port %s of cell %s: %s -> %s\n", portname.unescape(), + log(" Replacing known input bits on port %s of cell %s: %s -> %s\n", design->twines.str(portname).c_str(), muxinfo.cell, log_signal(muxinfo.cell->getPort(portname)), log_signal(sig)); muxinfo.cell->setPort(portname, sig); } @@ -536,8 +536,8 @@ struct OptMuxtreeWorker // set input ports to constants if we find known active or inactive signals if (limits.do_replace_known) { - replace_known(knowledge, muxinfo, ID::A); - replace_known(knowledge, muxinfo, ID::B); + replace_known(knowledge, muxinfo, TW::A); + replace_known(knowledge, muxinfo, TW::B); } // if there is a constant activated port we just use it diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 4c073c0a5..c57bd3883 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -512,7 +512,7 @@ struct OptReduceWorker OptReduceWorker(RTLIL::Design *design, RTLIL::Module *module, bool do_fine) : design(design), module(module), assign_map(module) { - log(" Optimizing cells in module %s.\n", module->name); + log(" Optimizing cells in module %s.\n", module->design->twines.str(module->meta_->name).c_str()); total_count = 0; did_something = true; diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index c485c807c..af5eb9844 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -55,11 +55,11 @@ struct ExtSigSpec { RTLIL::SigSpec sig; RTLIL::SigSpec sign; bool is_signed; - RTLIL::IdString semantics; + TwineRef semantics; ExtSigSpec() {} - ExtSigSpec(RTLIL::SigSpec s, RTLIL::SigSpec sign = RTLIL::Const(0, 1), bool is_signed = false, RTLIL::IdString semantics = RTLIL::IdString()) : sig(s), sign(sign), is_signed(is_signed), semantics(semantics) {} + ExtSigSpec(RTLIL::SigSpec s, RTLIL::SigSpec sign = RTLIL::Const(0, 1), bool is_signed = false, TwineRef semantics = Twine::Null) : sig(s), sign(sign), is_signed(is_signed), semantics(semantics) {} bool empty() const { return sig.empty(); } @@ -126,22 +126,22 @@ bool mergeable(RTLIL::Cell *a, RTLIL::Cell *b) return a_type == b_type; } -RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, TwineRef port_name) +TwineRef decode_port_semantics(RTLIL::Cell *cell, TwineRef port_name) { - if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($concat), SHIFT_OPS) && port_name == ID::B) + if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($concat), SHIFT_OPS) && port_name == TW::B) return port_name; if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_))) return port_name; - return ""; + return Twine::Null; } RTLIL::SigSpec decode_port_sign(RTLIL::Cell *cell, TwineRef port_name) { - if (cell->type == ID($alu) && port_name == ID::B) + if (cell->type == ID($alu) && port_name == TW::B) return cell->getPort(TW::BI); - else if (cell->type == ID($sub) && port_name == ID::B) + else if (cell->type == ID($sub) && port_name == TW::B) return RTLIL::Const(1, 1); return RTLIL::Const(0, 1); @@ -152,8 +152,9 @@ bool decode_port_signed(RTLIL::Cell *cell, TwineRef port_name) if (cell->type.in(BITWISE_OPS, LOGICAL_OPS)) return false; - if (cell->hasParam(port_name.str() + "_SIGNED")) - return cell->getParam(port_name.str() + "_SIGNED").as_bool(); + auto param_signed = cell->module->design->twines.str(port_name) + "_SIGNED"; + if (cell->hasParam(param_signed)) + return cell->getParam(param_signed).as_bool(); return false; } @@ -163,7 +164,7 @@ ExtSigSpec decode_port(RTLIL::Cell *cell, TwineRef port_name, const SigMap &sigm auto sig = sigmap(cell->getPort(port_name)); RTLIL::SigSpec sign = decode_port_sign(cell, port_name); - RTLIL::IdString semantics = decode_port_semantics(cell, port_name); + TwineRef semantics = decode_port_semantics(cell, port_name); bool is_signed = decode_port_signed(cell, port_name); @@ -177,9 +178,9 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< for (const auto& p : ports) { auto op = p.op; - RTLIL::IdString muxed_port_name = ID::A; - if (decode_port(op, ID::A, sigmap) == operand) - muxed_port_name = ID::B; + TwineRef muxed_port_name = TW::A; + if (decode_port(op, TW::A, sigmap) == operand) + muxed_port_name = TW::B; auto operand = decode_port(op, muxed_port_name, sigmap); if (operand.sig.size() > max_width) @@ -196,7 +197,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< for (auto &operand : muxed_operands) { operand.sig.extend_u0(max_width, operand.is_signed); if (operand.sign != muxed_operands[0].sign) - operand = ExtSigSpec(module->Neg(NEW_ID, operand.sig, operand.is_signed)); + operand = ExtSigSpec(module->Neg(NEW_TWINE, operand.sig, operand.is_signed)); } for (const auto& p : ports) { @@ -241,9 +242,9 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< SigSpec mux_to_oper; if (GetSize(shared_pmux_s) == 1) { - mux_to_oper = module->Mux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s); + mux_to_oper = module->Mux(NEW_TWINE, shared_pmux_a, shared_pmux_b, shared_pmux_s); } else { - mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s); + mux_to_oper = module->Pmux(NEW_TWINE, shared_pmux_a, shared_pmux_b, shared_pmux_s); } if (shared_op->type.in(ID($alu))) { @@ -257,7 +258,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< if (!is_fine) shared_op->setParam(ID::Y_WIDTH, GetSize(new_out)); - if (decode_port(shared_op, ID::A, sigmap) == operand) { + if (decode_port(shared_op, TW::A, sigmap) == operand) { shared_op->setPort(TW::B, mux_to_oper); if (!is_fine) shared_op->setParam(ID::B_WIDTH, max_width); @@ -284,9 +285,9 @@ void check_muxed_operands(std::vector &ports, const ExtSigSpe auto p = *it; auto op = p->op; - RTLIL::IdString muxed_port_name = ID::A; - if (decode_port(op, ID::A, sigmap) == shared_operand) { - muxed_port_name = ID::B; + TwineRef muxed_port_name = TW::A; + if (decode_port(op, TW::A, sigmap) == shared_operand) { + muxed_port_name = TW::B; } auto operand = decode_port(op, muxed_port_name, sigmap); @@ -313,7 +314,7 @@ ExtSigSpec find_shared_operand(const OpMuxConn* seed, std::vectorop; - for (TwineRef port_name : {ID::A, ID::B}) { + for (TwineRef port_name : {TW::A, TW::B}) { oper = decode_port(op_a, port_name, sigmap); auto operand_users = operand_to_users.at(oper); @@ -386,7 +387,7 @@ struct OptSharePass : public Pass { bool skip = false; if (cell->type == ID($alu)) { - for (TwineRef port_name : {ID::X, ID::CO}) { + for (TwineRef port_name : {TW::X, TW::CO}) { for (auto outbit : sigmap(cell->getPort(port_name))) if (bit_users[outbit] > 1) skip = true; @@ -400,7 +401,7 @@ struct OptSharePass : public Pass { for (int i = 0; i < GetSize(mux_insig); i++) op_outbit_to_outsig[mux_insig[i]] = std::make_pair(cell, i); - for (TwineRef port_name : {ID::A, ID::B}) { + for (TwineRef port_name : {TW::A, TW::B}) { auto op_insig = decode_port(cell, port_name, sigmap); operand_to_users[op_insig].insert(cell); if (operand_to_users[op_insig].size() > 1) diff --git a/passes/opt/peepopt_formal_clockgateff.pmg b/passes/opt/peepopt_formal_clockgateff.pmg index 8b4ad28ff..0ac378870 100644 --- a/passes/opt/peepopt_formal_clockgateff.pmg +++ b/passes/opt/peepopt_formal_clockgateff.pmg @@ -51,7 +51,7 @@ code // used to drive other nodes. If it isn't, it will be trivially removed by // clean SigSpec flopped_en = module->addWire(NEW_TWINE); - module->addDff(NEW_ID, clk, en, flopped_en, true, latch->src_ref()); + module->addDff(NEW_TWINE, clk, en, flopped_en, true, latch->src_ref()); and_gate->setPort(latched_en_port_name, flopped_en); did_something = true; diff --git a/passes/opt/peepopt_shiftmul_left.pmg b/passes/opt/peepopt_shiftmul_left.pmg index 4778be874..4e08b2dd2 100644 --- a/passes/opt/peepopt_shiftmul_left.pmg +++ b/passes/opt/peepopt_shiftmul_left.pmg @@ -149,7 +149,7 @@ code shift->setParam(\B_WIDTH, GetSize(new_b)); } else { SigSpec b_neg = module->addWire(NEW_TWINE, GetSize(new_b) + 1); - module->addNeg(NEW_ID, new_b, b_neg); + module->addNeg(NEW_TWINE, new_b, b_neg); shift->setPort(\B, b_neg); shift->setParam(\B_WIDTH, GetSize(b_neg)); } diff --git a/passes/opt/pmux2shiftx.cc b/passes/opt/pmux2shiftx.cc index 97e09851c..b4b1724ae 100644 --- a/passes/opt/pmux2shiftx.cc +++ b/passes/opt/pmux2shiftx.cc @@ -681,9 +681,9 @@ struct Pmux2ShiftxPass : public Pass { // creat cmp signal SigSpec cmp = perm_sig; if (perm_xormask.as_bool()) - cmp = module->Xor(NEW_ID, cmp, perm_xormask, false, src); + cmp = module->Xor(NEW_TWINE, cmp, perm_xormask, false, src); if (offset.as_bool()) - cmp = module->Sub(NEW_ID, cmp, offset, false, src); + cmp = module->Sub(NEW_TWINE, cmp, offset, false, src); // create enable signal SigBit en = State::S1; @@ -692,7 +692,7 @@ struct Pmux2ShiftxPass : public Pass { for (auto &it : perm_choices) enable_mask.set(it.first.as_int(), State::S1); en = module->addWire(NEW_TWINE); - module->addShift(NEW_ID, enable_mask, cmp, en, false, src); + module->addShift(NEW_TWINE, enable_mask, cmp, en, false, src); } // create data signal @@ -712,7 +712,7 @@ struct Pmux2ShiftxPass : public Pass { // create shiftx cell SigSpec shifted_cmp = {cmp, SigSpec(State::S0, width_bits)}; SigSpec outsig = module->addWire(NEW_TWINE, width); - Cell *c = module->addShiftx(NEW_ID, data, shifted_cmp, outsig, false, src); + Cell *c = module->addShiftx(NEW_TWINE, data, shifted_cmp, outsig, false, src); updated_S.append(en); updated_B.append(outsig); log(" created $shiftx cell %s.\n", c); diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 69bac1dcb..fc39ea6d8 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -207,12 +207,12 @@ struct ShareWorker if (supercell_aux && GetSize(sig_a)) { sig_a = module->addWire(NEW_TWINE, GetSize(sig_a)); - supercell_aux->insert(module->addMux(NEW_ID, sig_a2, sig_a1, act, sig_a)); + supercell_aux->insert(module->addMux(NEW_TWINE, sig_a2, sig_a1, act, sig_a)); } if (supercell_aux && GetSize(sig_b)) { sig_b = module->addWire(NEW_TWINE, GetSize(sig_b)); - supercell_aux->insert(module->addMux(NEW_ID, sig_b2, sig_b1, act, sig_b)); + supercell_aux->insert(module->addMux(NEW_TWINE, sig_b2, sig_b1, act, sig_b)); } Macc::term_t p; @@ -284,12 +284,12 @@ struct ShareWorker if (supercell_aux && GetSize(sig_a)) { sig_a = module->addWire(NEW_TWINE, GetSize(sig_a)); - supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_a)), m1.terms[i].in_a, act, sig_a)); + supercell_aux->insert(module->addMux(NEW_TWINE, RTLIL::SigSpec(0, GetSize(sig_a)), m1.terms[i].in_a, act, sig_a)); } if (supercell_aux && GetSize(sig_b)) { sig_b = module->addWire(NEW_TWINE, GetSize(sig_b)); - supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_b)), m1.terms[i].in_b, act, sig_b)); + supercell_aux->insert(module->addMux(NEW_TWINE, RTLIL::SigSpec(0, GetSize(sig_b)), m1.terms[i].in_b, act, sig_b)); } Macc::term_t p; @@ -307,12 +307,12 @@ struct ShareWorker if (supercell_aux && GetSize(sig_a)) { sig_a = module->addWire(NEW_TWINE, GetSize(sig_a)); - supercell_aux->insert(module->addMux(NEW_ID, m2.terms[i].in_a, RTLIL::SigSpec(0, GetSize(sig_a)), act, sig_a)); + supercell_aux->insert(module->addMux(NEW_TWINE, m2.terms[i].in_a, RTLIL::SigSpec(0, GetSize(sig_a)), act, sig_a)); } if (supercell_aux && GetSize(sig_b)) { sig_b = module->addWire(NEW_TWINE, GetSize(sig_b)); - supercell_aux->insert(module->addMux(NEW_ID, m2.terms[i].in_b, RTLIL::SigSpec(0, GetSize(sig_b)), act, sig_b)); + supercell_aux->insert(module->addMux(NEW_TWINE, m2.terms[i].in_b, RTLIL::SigSpec(0, GetSize(sig_b)), act, sig_b)); } Macc::term_t p; @@ -327,8 +327,8 @@ struct ShareWorker { RTLIL::SigSpec sig_y = module->addWire(NEW_TWINE, width); - supercell_aux->insert(module->addPos(NEW_ID, sig_y, c1->getPort(TW::Y))); - supercell_aux->insert(module->addPos(NEW_ID, sig_y, c2->getPort(TW::Y))); + supercell_aux->insert(module->addPos(NEW_TWINE, sig_y, c1->getPort(TW::Y))); + supercell_aux->insert(module->addPos(NEW_TWINE, sig_y, c2->getPort(TW::Y))); supercell->setParam(ID::Y_WIDTH, width); supercell->setPort(TW::Y, sig_y); @@ -536,7 +536,7 @@ struct ShareWorker a2.extend_u0(a_width, a_signed); RTLIL::SigSpec a = module->addWire(NEW_TWINE, a_width); - supercell_aux.insert(module->addMux(NEW_ID, a2, a1, act, a)); + supercell_aux.insert(module->addMux(NEW_TWINE, a2, a1, act, a)); RTLIL::Wire *y = module->addWire(NEW_TWINE, y_width); @@ -547,8 +547,8 @@ struct ShareWorker supercell->setPort(TW::A, a); supercell->setPort(TW::Y, y); - supercell_aux.insert(module->addPos(NEW_ID, y, y1)); - supercell_aux.insert(module->addPos(NEW_ID, y, y2)); + supercell_aux.insert(module->addPos(NEW_TWINE, y, y1)); + supercell_aux.insert(module->addPos(NEW_TWINE, y, y2)); supercell_aux.insert(supercell); return supercell; @@ -653,8 +653,8 @@ struct ShareWorker RTLIL::SigSpec a = module->addWire(NEW_TWINE, a_width); RTLIL::SigSpec b = module->addWire(NEW_TWINE, b_width); - supercell_aux.insert(module->addMux(NEW_ID, a2, a1, act, a)); - supercell_aux.insert(module->addMux(NEW_ID, b2, b1, act, b)); + supercell_aux.insert(module->addMux(NEW_TWINE, a2, a1, act, a)); + supercell_aux.insert(module->addMux(NEW_TWINE, b2, b1, act, b)); RTLIL::Wire *y = module->addWire(NEW_TWINE, y_width); RTLIL::Wire *x = c1->type == ID($alu) ? module->addWire(NEW_TWINE, y_width) : nullptr; @@ -671,8 +671,8 @@ struct ShareWorker supercell->setPort(TW::Y, y); if (c1->type == ID($alu)) { RTLIL::Wire *ci = module->addWire(NEW_TWINE), *bi = module->addWire(NEW_TWINE); - supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(TW::CI), c1->getPort(TW::CI), act, ci)); - supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(TW::BI), c1->getPort(TW::BI), act, bi)); + supercell_aux.insert(module->addMux(NEW_TWINE, c2->getPort(TW::CI), c1->getPort(TW::CI), act, ci)); + supercell_aux.insert(module->addMux(NEW_TWINE, c2->getPort(TW::BI), c1->getPort(TW::BI), act, bi)); supercell->setPort(TW::CI, ci); supercell->setPort(TW::BI, bi); supercell->setPort(TW::CO, co); @@ -680,13 +680,13 @@ struct ShareWorker } supercell->check(); - supercell_aux.insert(module->addPos(NEW_ID, y, y1)); - supercell_aux.insert(module->addPos(NEW_ID, y, y2)); + supercell_aux.insert(module->addPos(NEW_TWINE, y, y1)); + supercell_aux.insert(module->addPos(NEW_TWINE, y, y2)); if (c1->type == ID($alu)) { - supercell_aux.insert(module->addPos(NEW_ID, co, c1->getPort(TW::CO))); - supercell_aux.insert(module->addPos(NEW_ID, co, c2->getPort(TW::CO))); - supercell_aux.insert(module->addPos(NEW_ID, x, c1->getPort(TW::X))); - supercell_aux.insert(module->addPos(NEW_ID, x, c2->getPort(TW::X))); + supercell_aux.insert(module->addPos(NEW_TWINE, co, c1->getPort(TW::CO))); + supercell_aux.insert(module->addPos(NEW_TWINE, co, c2->getPort(TW::CO))); + supercell_aux.insert(module->addPos(NEW_TWINE, x, c1->getPort(TW::X))); + supercell_aux.insert(module->addPos(NEW_TWINE, x, c2->getPort(TW::X))); } supercell_aux.insert(supercell); @@ -711,9 +711,9 @@ struct ShareWorker addr1.extend_u0(GetSize(addr2)); else addr2.extend_u0(GetSize(addr1)); - supercell->setPort(TW::ADDR, addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1); + supercell->setPort(TW::ADDR, addr1 != addr2 ? module->Mux(NEW_TWINE, addr2, addr1, act) : addr1); supercell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr1)); - supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort(TW::DATA), c2->getPort(TW::DATA))); + supercell_aux.insert(module->addPos(NEW_TWINE, supercell->getPort(TW::DATA), c2->getPort(TW::DATA))); supercell_aux.insert(supercell); return supercell; } @@ -744,7 +744,7 @@ struct ShareWorker modwalker.get_consumers(pbits, modwalker.cell_outputs[cell]); for (auto &bit : pbits) { - if ((bit.cell->type == ID($mux) || bit.cell->type == ID($pmux)) && bit.port == ID::S) + if ((bit.cell->type == ID($mux) || bit.cell->type == ID($pmux)) && bit.port == TW::S) forbidden_controls_cache[cell].insert(bit.cell->getPort(TW::S).extract(bit.offset, 1)); consumer_cells.insert(bit.cell); } @@ -892,7 +892,7 @@ struct ShareWorker } for (auto &pbit : modwalker.signal_consumers[bit]) { log_assert(StaticCellTypes::Compat::internals_nomem_noff(pbit.cell->type)); - if ((pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) && (pbit.port == ID::A || pbit.port == ID::B)) + if ((pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) && (pbit.port == TW::A || pbit.port == TW::B)) driven_data_muxes.insert(pbit.cell); else driven_cells.insert(pbit.cell); @@ -1063,14 +1063,14 @@ struct ShareWorker for (auto &p : activation_patterns) { all_cases_wire->width++; - supercell_aux.insert(module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, all_cases_wire->width - 1))); + supercell_aux.insert(module->addEq(NEW_TWINE, p.first, p.second, RTLIL::SigSpec(all_cases_wire, all_cases_wire->width - 1))); } if (all_cases_wire->width == 1) return all_cases_wire; RTLIL::Wire *result_wire = module->addWire(NEW_TWINE); - supercell_aux.insert(module->addReduceOr(NEW_ID, all_cases_wire, result_wire)); + supercell_aux.insert(module->addReduceOr(NEW_TWINE, all_cases_wire, result_wire)); return result_wire; } diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 0a8fab2dc..766a2d20b 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -243,7 +243,8 @@ struct WreduceWorker void run_reduce_inport(Cell *cell, char port, int max_port_size, bool &port_signed, bool &did_something) { port_signed = cell->getParam(stringf("\\%c_SIGNED", port)).as_bool(); - SigSpec sig = mi.sigmap(cell->getPort(stringf("\\%c", port))); + auto twines = cell->module->design->twines; + SigSpec sig = mi.sigmap(cell->getPort(twines.add(Twine{stringf("\\%c", twines.str(port))}))); if (port == 'B' && cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) port_signed = false; @@ -267,7 +268,8 @@ struct WreduceWorker if (bits_removed) { log("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n", bits_removed, GetSize(sig) + bits_removed, port, module, cell, cell->type.unescape()); - cell->setPort(stringf("\\%c", port), sig); + // SigSpec sig = mi.sigmap(cell->getPort(twines.add(Twine{stringf("\\%c", twines.str(port))}))); + cell->setPort(twines.add(Twine{stringf("\\%c", twines.str(port))}), sig); did_something = true; } } @@ -306,8 +308,8 @@ struct WreduceWorker // Reduce size of ports A and B based on constant input bits and size of output port - int max_port_a_size = cell->hasPort(ID::A) ? GetSize(cell->getPort(TW::A)) : -1; - int max_port_b_size = cell->hasPort(ID::B) ? GetSize(cell->getPort(TW::B)) : -1; + int max_port_a_size = cell->hasPort(TW::A) ? GetSize(cell->getPort(TW::A)) : -1; + int max_port_b_size = cell->hasPort(TW::B) ? GetSize(cell->getPort(TW::B)) : -1; if (cell->type.in(ID($not), ID($pos), ID($neg), ID($and), ID($or), ID($xor), ID($add), ID($sub))) { max_port_a_size = min(max_port_a_size, GetSize(sig)); @@ -362,7 +364,7 @@ struct WreduceWorker if (max_port_b_size >= 0) run_reduce_inport(cell, 'B', max_port_b_size, port_b_signed, did_something); - if (cell->hasPort(ID::A) && cell->hasPort(ID::B) && port_a_signed && port_b_signed) { + if (cell->hasPort(TW::A) && cell->hasPort(TW::B) && port_a_signed && port_b_signed) { SigSpec sig_a = mi.sigmap(cell->getPort(TW::A)), sig_b = mi.sigmap(cell->getPort(TW::B)); if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0 && GetSize(sig_b) > 0 && sig_b[GetSize(sig_b)-1] == State::S0) { @@ -376,7 +378,7 @@ struct WreduceWorker } } - if (cell->hasPort(ID::A) && !cell->hasPort(ID::B) && port_a_signed) { + if (cell->hasPort(TW::A) && !cell->hasPort(TW::B) && port_a_signed) { SigSpec sig_a = mi.sigmap(cell->getPort(TW::A)); if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0) { log("Converting cell %s.%s (%s) from signed to unsigned.\n", @@ -414,8 +416,8 @@ struct WreduceWorker bool is_signed = cell->getParam(ID::A_SIGNED).as_bool() || cell->type == ID($sub); int a_size = 0, b_size = 0; - if (cell->hasPort(ID::A)) a_size = GetSize(cell->getPort(TW::A)); - if (cell->hasPort(ID::B)) b_size = GetSize(cell->getPort(TW::B)); + if (cell->hasPort(TW::A)) a_size = GetSize(cell->getPort(TW::A)); + if (cell->hasPort(TW::B)) b_size = GetSize(cell->getPort(TW::B)); int max_y_size = max(a_size, b_size); @@ -637,7 +639,8 @@ struct WreducePass : public Pass { } if (!opt_memx && c->type.in(ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2), ID($meminit), ID($meminit_v2))) { - IdString memid = c->getParam(ID::MEMID).decode_string(); + std::string memid_s = c->getParam(ID::MEMID).decode_string(); + TwineRef memid = design->twines.add(Twine{memid_s}); RTLIL::Memory *mem = module->memories.at(memid); if (mem->start_offset >= 0) { int cur_addrbits = c->getParam(ID::ABITS).as_int(); @@ -646,7 +649,7 @@ struct WreducePass : public Pass { log("Removed top %d address bits (of %d) from memory %s port %s.%s (%s).\n", cur_addrbits-max_addrbits, cur_addrbits, c->type == ID($memrd) ? "read" : c->type == ID($memwr) ? "write" : "init", - module, c, memid.unescape()); + module, c, memid_s); c->setParam(ID::ABITS, max_addrbits); c->setPort(TW::ADDR, c->getPort(TW::ADDR).extract(0, max_addrbits)); } diff --git a/passes/pmgen/test_pmgen.cc b/passes/pmgen/test_pmgen.cc index e11341f4e..8d24a874a 100644 --- a/passes/pmgen/test_pmgen.cc +++ b/passes/pmgen/test_pmgen.cc @@ -58,11 +58,11 @@ void reduce_chain(test_pmgen_pm &pm) Cell *c; if (last_cell->type == ID($_AND_)) - c = pm.module->addReduceAnd(NEW_ID, A, Y); + c = pm.module->addReduceAnd(NEW_TWINE, A, Y); else if (last_cell->type == ID($_OR_)) - c = pm.module->addReduceOr(NEW_ID, A, Y); + c = pm.module->addReduceOr(NEW_TWINE, A, Y); else if (last_cell->type == ID($_XOR_)) - c = pm.module->addReduceXor(NEW_ID, A, Y); + c = pm.module->addReduceXor(NEW_TWINE, A, Y); else log_abort(); @@ -87,11 +87,11 @@ void reduce_tree(test_pmgen_pm &pm) Cell *c; if (st.first->type == ID($_AND_)) - c = pm.module->addReduceAnd(NEW_ID, A, Y); + c = pm.module->addReduceAnd(NEW_TWINE, A, Y); else if (st.first->type == ID($_OR_)) - c = pm.module->addReduceOr(NEW_ID, A, Y); + c = pm.module->addReduceOr(NEW_TWINE, A, Y); else if (st.first->type == ID($_XOR_)) - c = pm.module->addReduceXor(NEW_ID, A, Y); + c = pm.module->addReduceXor(NEW_TWINE, A, Y); else log_abort(); @@ -112,7 +112,7 @@ void opt_eqpmux(test_pmgen_pm &pm) log_signal(Y), st.eq, st.ne, st.pmux); pm.autoremove(st.pmux); - Cell *c = pm.module->addMux(NEW_ID, NE, EQ, st.eq->getPort(TW::Y), Y); + Cell *c = pm.module->addMux(NEW_TWINE, NE, EQ, st.eq->getPort(TW::Y), Y); log(" -> %s (%s)\n", c, c->type.unescape()); } diff --git a/passes/pmgen/test_pmgen.pmg b/passes/pmgen/test_pmgen.pmg index e7f16644b..c7b5ce539 100644 --- a/passes/pmgen/test_pmgen.pmg +++ b/passes/pmgen/test_pmgen.pmg @@ -20,13 +20,13 @@ generate switch (rng(3)) { case 0: - module->addAndGate(NEW_ID, A, B, Y); + module->addAndGate(NEW_TWINE, A, B, Y); break; case 1: - module->addOrGate(NEW_ID, A, B, Y); + module->addOrGate(NEW_TWINE, A, B, Y); break; case 2: - module->addXorGate(NEW_ID, A, B, Y); + module->addXorGate(NEW_TWINE, A, B, Y); break; } endmatch @@ -85,7 +85,7 @@ generate 10 SigSpec A = module->addWire(NEW_TWINE); SigSpec B = module->addWire(NEW_TWINE); SigSpec Y = port(chain.back().first, chain.back().second); - Cell *c = module->addAndGate(NEW_ID, A, B, Y); + Cell *c = module->addAndGate(NEW_TWINE, A, B, Y); c->type = chain.back().first->type; endmatch @@ -124,7 +124,7 @@ generate 100 10 SigSpec A = module->addWire(NEW_TWINE, rng(7)+1); SigSpec B = module->addWire(NEW_TWINE, rng(7)+1); SigSpec Y = module->addWire(NEW_TWINE); - module->addEq(NEW_ID, A, B, Y, rng(2)); + module->addEq(NEW_TWINE, A, B, Y, rng(2)); endmatch match pmux @@ -146,7 +146,7 @@ generate 100 10 S.append(i == idx ? port(eq, \Y) : module->addWire(NEW_TWINE)); } - module->addPmux(NEW_ID, A, B, S, Y); + module->addPmux(NEW_TWINE, A, B, S, Y); endmatch match ne @@ -173,7 +173,7 @@ generate 100 10 } else { Y = module->addWire(NEW_TWINE); } - module->addNe(NEW_ID, A, B, Y, rng(2)); + module->addNe(NEW_TWINE, A, B, Y, rng(2)); endmatch match pmux2 diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 7963a68a3..15e79e583 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -204,7 +204,7 @@ void proc_arst(RTLIL::Module *mod, RTLIL::Process *proc, SigMap &assign_map) bool polarity = sync->type == RTLIL::SyncType::STp; if (check_signal(mod, root_sig, sync->signal, polarity)) { if (edge_syncs.size() > 1) { - log("Found async reset %s in `%s.%s'.\n", log_signal(sync->signal), mod->name, proc->name); + log("Found async reset %s in `%s.%s'.\n", log_signal(sync->signal), log_id(mod), log_id(proc)); sync->type = sync->type == RTLIL::SyncType::STp ? RTLIL::SyncType::ST1 : RTLIL::SyncType::ST0; arst_syncs.push_back(sync); edge_syncs.erase(it); @@ -223,7 +223,7 @@ void proc_arst(RTLIL::Module *mod, RTLIL::Process *proc, SigMap &assign_map) sync->mem_write_actions.clear(); eliminate_const(mod, &proc->root_case, root_sig, polarity); } else { - log("Found VHDL-style edge-trigger %s in `%s.%s'.\n", log_signal(sync->signal), mod->name, proc->name); + log("Found VHDL-style edge-trigger %s in `%s.%s'.\n", log_signal(sync->signal), log_id(mod), log_id(proc)); eliminate_const(mod, &proc->root_case, root_sig, !polarity); } did_something = true; @@ -292,7 +292,7 @@ struct ProcArstPass : public Pass { SigMap assign_map(mod); for (auto proc : mod->selected_processes()) { proc_arst(mod, proc, assign_map); - if (global_arst.empty() || mod->wire(global_arst) == nullptr) + if (global_arst.empty() || mod->wire(design->twines.lookup(global_arst)) == nullptr) continue; std::vector arst_actions; for (auto sync : proc->syncs) @@ -309,14 +309,14 @@ struct ProcArstPass : public Pass { } if (arst_sig.size()) { log("Added global reset to process %s: %s <- %s\n", - proc->name.c_str(), log_signal(arst_sig), log_signal(arst_val)); + log_id(proc), log_signal(arst_sig), log_signal(arst_val)); arst_actions.push_back(RTLIL::SigSig(arst_sig, arst_val)); } } if (!arst_actions.empty()) { RTLIL::SyncRule *sync = new RTLIL::SyncRule; sync->type = global_arst_neg ? RTLIL::SyncType::ST0 : RTLIL::SyncType::ST1; - sync->signal = mod->wire(global_arst); + sync->signal = mod->wire(design->twines.lookup(global_arst)); sync->actions = arst_actions; proc->syncs.push_back(sync); } diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 0df9fc0b2..bbdff6dbb 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -172,7 +172,7 @@ void proc_clean(RTLIL::Module *mod, RTLIL::Process *proc, int &total_count, bool proc_clean_case(&proc->root_case, did_something, count, -1); } if (count > 0 && !quiet) - log("Found and cleaned up %d empty switch%s in `%s.%s'.\n", count, count == 1 ? "" : "es", mod->name, proc->name); + log("Found and cleaned up %d empty switch%s in `%s.%s'.\n", count, count == 1 ? "" : "es", log_id(mod), log_id(proc)); total_count += count; } @@ -216,7 +216,7 @@ struct ProcCleanPass : public Pass { if (proc->syncs.size() == 0 && proc->root_case.switches.size() == 0 && proc->root_case.actions.size() == 0) { if (!quiet) - log("Removing empty process `%s.%s'.\n", mod, proc->name); + log("Removing empty process `%s.%s'.\n", log_id(mod), log_id(proc)); delme.push_back(proc); } } diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index d6ffb3eec..e2ca54544 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -66,26 +66,26 @@ void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec for (auto it = async_rules.crbegin(); it != async_rules.crend(); it++) { const auto& [sync_value, rule] = *it; - const auto pos_trig = rule->type == RTLIL::SyncType::ST1 ? rule->signal : mod->Not(NEW_ID, rule->signal); + const auto pos_trig = rule->type == RTLIL::SyncType::ST1 ? rule->signal : mod->Not(NEW_TWINE, rule->signal); // If pos_trig is true, we have priority at this point in the tree so // set a bit if sync_value has a set bit. Otherwise, defer to the rest // of the priority tree - sig_sr_set = mod->Mux(NEW_ID, sig_sr_set, sync_value, pos_trig); + sig_sr_set = mod->Mux(NEW_TWINE, sig_sr_set, sync_value, pos_trig); // Same deal with clear bit - const auto sync_value_inv = mod->Not(NEW_ID, sync_value); - sig_sr_clr = mod->Mux(NEW_ID, sig_sr_clr, sync_value_inv, pos_trig); + const auto sync_value_inv = mod->Not(NEW_TWINE, sync_value); + sig_sr_clr = mod->Mux(NEW_TWINE, sig_sr_clr, sync_value_inv, pos_trig); } std::stringstream sstr; sstr << "$procdff$" << (autoidx++); - RTLIL::Cell *cell = mod->addDffsr(sstr.str(), clk, sig_sr_set, sig_sr_clr, sig_d, sig_q, clk_polarity); + RTLIL::Cell *cell = mod->addDffsr(Twine{sstr.str()}, clk, sig_sr_set, sig_sr_clr, sig_d, sig_q, clk_polarity); cell->attributes = proc->attributes; log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n", - cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative"); + log_id(cell->type), log_id(cell), clk_polarity ? "positive" : "negative"); } void gen_aldff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_out, @@ -94,7 +94,7 @@ void gen_aldff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set std::stringstream sstr; sstr << "$procdff$" << (autoidx++); - RTLIL::Cell *cell = mod->addCell(sstr.str(), ID($aldff)); + RTLIL::Cell *cell = mod->addCell(Twine{sstr.str()}, ID($aldff)); cell->attributes = proc->attributes; cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size()); @@ -106,7 +106,7 @@ void gen_aldff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set cell->setPort(TW::CLK, clk); cell->setPort(TW::ALOAD, set); - log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type, cell->name, + log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", log_id(cell->type), log_id(cell), clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative"); } @@ -116,7 +116,7 @@ void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RT std::stringstream sstr; sstr << "$procdff$" << (autoidx++); - RTLIL::Cell *cell = mod->addCell(sstr.str(), clk.empty() ? ID($ff) : arst ? ID($adff) : ID($dff)); + RTLIL::Cell *cell = mod->addCell(Twine{sstr.str()}, clk.empty() ? ID($ff) : arst ? ID($adff) : ID($dff)); cell->attributes = proc->attributes; cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size()); @@ -136,9 +136,9 @@ void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RT cell->setPort(TW::CLK, clk); if (!clk.empty()) - log(" created %s cell `%s' with %s edge clock", cell->type, cell->name, clk_polarity ? "positive" : "negative"); + log(" created %s cell `%s' with %s edge clock", log_id(cell->type), log_id(cell), clk_polarity ? "positive" : "negative"); else - log(" created %s cell `%s' with global clock", cell->type, cell->name); + log(" created %s cell `%s' with global clock", log_id(cell->type), log_id(cell)); if (arst) log(" and %s level reset", arst_polarity ? "positive" : "negative"); log(".\n"); @@ -154,7 +154,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) break; log("Creating register for signal `%s.%s' using process `%s.%s'.\n", - mod->name.c_str(), log_signal(sig), mod->name.c_str(), proc->name.c_str()); + log_id(mod), log_signal(sig), log_id(mod), log_id(proc)); RTLIL::SigSpec insig = RTLIL::SigSpec(RTLIL::State::Sz, sig.size()); RTLIL::SyncRule *sync_edge = NULL; @@ -217,12 +217,12 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) // (with appropriate negation) RTLIL::SigSpec triggers; for (const auto &[_, it] : async_rules) - triggers.append(it->type == RTLIL::SyncType::ST1 ? it->signal : mod->Not(NEW_ID, it->signal)); + triggers.append(it->type == RTLIL::SyncType::ST1 ? it->signal : mod->Not(NEW_TWINE, it->signal)); // Put this into the dummy sync rule so it can be treated the same // as ones coming from the module single_async_rule.type = RTLIL::SyncType::ST1; - single_async_rule.signal = mod->ReduceOr(NEW_ID, triggers); + single_async_rule.signal = mod->ReduceOr(NEW_TWINE, triggers); single_async_rule.actions.push_back(RTLIL::SigSig(sig, rstval)); // Replace existing rules with this new rule @@ -239,9 +239,9 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) if (async_rules.size() == 1 && async_rules.front().first == sig) { const auto& [_, rule] = async_rules.front(); if (rule->type == RTLIL::SyncType::ST1) - insig = mod->Mux(NEW_ID, insig, sig, rule->signal); + insig = mod->Mux(NEW_TWINE, insig, sig, rule->signal); else - insig = mod->Mux(NEW_ID, sig, insig, rule->signal); + insig = mod->Mux(NEW_TWINE, sig, insig, rule->signal); async_rules.clear(); } diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc index c759bec1b..6f84a6d67 100644 --- a/passes/proc/proc_dlatch.cc +++ b/passes/proc/proc_dlatch.cc @@ -246,20 +246,20 @@ struct proc_dlatch_db_t if (rule.match == State::S1) and_bits.append(rule.signal); else if (rule.match == State::S0) - and_bits.append(module->Not(NEW_ID, rule.signal, false, src)); + and_bits.append(module->Not(NEW_TWINE, rule.signal, false)); else - and_bits.append(module->Eq(NEW_ID, rule.signal, rule.match, false, src)); + and_bits.append(module->Eq(NEW_TWINE, rule.signal, rule.match, false)); } if (!rule.children.empty()) { SigSpec or_bits; for (int k : rule.children) or_bits.append(make_hold(k, src)); - and_bits.append(module->ReduceOr(NEW_ID, or_bits, false, src)); + and_bits.append(module->ReduceOr(NEW_TWINE, or_bits, false)); } if (GetSize(and_bits) == 2) - and_bits = module->And(NEW_ID, and_bits[0], and_bits[1], false, src); + and_bits = module->And(NEW_TWINE, and_bits[0], and_bits[1], false); log_assert(GetSize(and_bits) == 1); rules_sig[n] = and_bits[0]; @@ -360,7 +360,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) if (proc->get_bool_attribute(ID::always_ff)) log_error("Found non edge/level sensitive event in always_ff process `%s.%s'.\n", - db.module->name.c_str(), proc->name.c_str()); + db.module->design->twines.str(db.module->meta_->name).c_str(), db.module->design->twines.str(proc->meta_->name).c_str()); for (auto ss : sr->actions) { @@ -397,14 +397,14 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) SigSpec lhs = chunk, rhs = nolatches_bits.second.extract(offset, chunk.width); if (proc->get_bool_attribute(ID::always_latch)) log_error("No latch inferred for signal `%s.%s' from always_latch process `%s.%s'.\n", - db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str()); + db.module->design->twines.str(db.module->meta_->name).c_str(), log_signal(lhs), db.module->design->twines.str(db.module->meta_->name).c_str(), db.module->design->twines.str(proc->meta_->name).c_str()); else log("No latch inferred for signal `%s.%s' from process `%s.%s'.\n", - db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str()); + db.module->design->twines.str(db.module->meta_->name).c_str(), log_signal(lhs), db.module->design->twines.str(db.module->meta_->name).c_str(), db.module->design->twines.str(proc->meta_->name).c_str()); for (auto &bit : lhs) { State val = db.initvals(bit); if (db.initvals(bit) != State::Sx) { - log("Removing init bit %s for non-memory siginal `%s.%s` in process `%s.%s`.\n", log_signal(val), db.module->name, log_signal(bit), db.module->name, proc->name); + log("Removing init bit %s for non-memory siginal `%s.%s` in process `%s.%s`.\n", log_signal(val), db.module->design->twines.str(db.module->meta_->name), log_signal(bit), db.module->design->twines.str(db.module->meta_->name), db.module->design->twines.str(proc->meta_->name)); } db.initvals.remove_init(bit); } @@ -429,16 +429,16 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) SigSpec lhs = latches_bits.first.extract(offset, width); SigSpec rhs = latches_bits.second.extract(offset, width); - Cell *cell = db.module->addDlatch(NEW_ID, db.module->Not(NEW_ID, db.make_hold(n, src)), rhs, lhs); - cell->set_src_attribute(src); + Cell *cell = db.module->addDlatch(NEW_TWINE, db.module->Not(NEW_TWINE, db.make_hold(n, src)), rhs, lhs); + cell->set_src_attribute(db.module->design->twines.add(Twine{src})); db.generated_dlatches.insert(cell); if (proc->get_bool_attribute(ID::always_comb)) log_error("Latch inferred for signal `%s.%s' from always_comb process `%s.%s'.\n", - db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str()); + db.module->design->twines.str(db.module->meta_->name).c_str(), log_signal(lhs), db.module->design->twines.str(db.module->meta_->name).c_str(), db.module->design->twines.str(proc->meta_->name).c_str()); else log("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n", - db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell); + db.module->design->twines.str(db.module->meta_->name).c_str(), log_signal(lhs), db.module->design->twines.str(db.module->meta_->name).c_str(), db.module->design->twines.str(proc->meta_->name).c_str(), cell); } offset += width; diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 3d27eaa9a..50649a99a 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -31,7 +31,7 @@ void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc) for (auto &sync : proc->syncs) if (sync->type == RTLIL::SyncType::STi) { - log("Found init rule in `%s.%s'.\n", mod->name, proc->name); + log("Found init rule in `%s.%s'.\n", log_id(mod), log_id(proc)); for (auto &action : sync->actions) { diff --git a/passes/proc/proc_memwr.cc b/passes/proc/proc_memwr.cc index a39db73fe..aab451606 100644 --- a/passes/proc/proc_memwr.cc +++ b/passes/proc/proc_memwr.cc @@ -55,10 +55,10 @@ void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict &n for (auto sr2 : proc->syncs) { if (sr2->type == RTLIL::SyncType::ST0) { log_assert(sr2->mem_write_actions.empty()); - enable = mod->Mux(NEW_ID, Const(State::S0, GetSize(enable)), enable, sr2->signal); + enable = mod->Mux(NEW_TWINE, Const(State::S0, GetSize(enable)), enable, sr2->signal); } else if (sr2->type == RTLIL::SyncType::ST1) { log_assert(sr2->mem_write_actions.empty()); - enable = mod->Mux(NEW_ID, enable, Const(State::S0, GetSize(enable)), sr2->signal); + enable = mod->Mux(NEW_TWINE, enable, Const(State::S0, GetSize(enable)), sr2->signal); } } cell->setPort(TW::EN, enable); diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 2ace54222..b7719adfa 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -155,7 +155,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s std::stringstream sstr; sstr << "$procmux$" << (autoidx++); - RTLIL::Wire *cmp_wire = mod->addWire(sstr.str() + "_CMP", 0); + RTLIL::Wire *cmp_wire = mod->addWire(Twine{sstr.str() + "_CMP"}, 0); for (auto comp : compare) { @@ -178,7 +178,7 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s else { // create compare cell - RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str(), cmp_wire->width), ifxmode ? ID($eqx) : ID($eq)); + RTLIL::Cell *eq_cell = mod->addCell(Twine{stringf("%s_CMP%d", sstr.str(), cmp_wire->width)}, ifxmode ? ID($eqx) : ID($eq)); apply_attrs(eq_cell, sw, cs); eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0); @@ -201,10 +201,10 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s } else { - ctrl_wire = mod->addWire(sstr.str() + "_CTRL"); + ctrl_wire = mod->addWire(Twine{sstr.str() + "_CTRL"}); // reduce cmp vector to one logic signal - RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", ID($reduce_or)); + RTLIL::Cell *any_cell = mod->addCell(Twine{sstr.str() + "_ANY"}, ID($reduce_or)); apply_attrs(any_cell, sw, cs); any_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0); @@ -236,10 +236,10 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s log_assert(ctrl_sig.size() == 1); // prepare multiplexer output signal - RTLIL::Wire *result_wire = mod->addWire(sstr.str() + "_Y", when_signal.size()); + RTLIL::Wire *result_wire = mod->addWire(Twine{sstr.str() + "_Y"}, when_signal.size()); // create the multiplexer itself - RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), ID($mux)); + RTLIL::Cell *mux_cell = mod->addCell(Twine{sstr.str()}, ID($mux)); apply_attrs(mux_cell, sw, cs); mux_cell->parameters[ID::WIDTH] = RTLIL::Const(when_signal.size()); @@ -412,7 +412,7 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc, bool ifxmode) { - log("Creating decoders for process `%s.%s'.\n", mod->name, proc->name); + log("Creating decoders for process `%s.%s'.\n", log_id(mod), log_id(proc)); SigSnippets sigsnip; sigsnip.insert(&proc->root_case); diff --git a/passes/sat/assertpmux.cc b/passes/sat/assertpmux.cc index c352027e3..0325c9508 100644 --- a/passes/sat/assertpmux.cc +++ b/passes/sat/assertpmux.cc @@ -100,12 +100,12 @@ struct AssertpmuxWorker if (muxport_actsignal.count(muxport) == 0) { if (portidx == 0) - muxport_actsignal[muxport] = module->LogicNot(NEW_ID, cell->getPort(TW::S)); + muxport_actsignal[muxport] = module->LogicNot(NEW_TWINE, cell->getPort(TW::S)); else muxport_actsignal[muxport] = cell->getPort(TW::S)[portidx-1]; } - output.append(module->LogicAnd(NEW_ID, muxport_actsignal.at(muxport), get_bit_activation(cell->getPort(TW::Y)[bitidx]))); + output.append(module->LogicAnd(NEW_TWINE, muxport_actsignal.at(muxport), get_bit_activation(cell->getPort(TW::Y)[bitidx]))); } output.sort_and_unify(); @@ -113,7 +113,7 @@ struct AssertpmuxWorker if (GetSize(output) == 0) output = State::S0; else if (GetSize(output) > 1) - output = module->ReduceOr(NEW_ID, output); + output = module->ReduceOr(NEW_TWINE, output); sigbit_actsignals[bit] = output.as_bit(); } @@ -138,7 +138,7 @@ struct AssertpmuxWorker if (GetSize(output) == 0) output = State::S0; else if (GetSize(output) > 1) - output = module->ReduceOr(NEW_ID, output); + output = module->ReduceOr(NEW_TWINE, output); sigspec_actsignals[sig] = output.as_bit(); } @@ -157,13 +157,13 @@ struct AssertpmuxWorker SigSpec cnt(State::S0, cntbits); for (int i = 0; i < swidth; i++) - cnt = module->Add(NEW_ID, cnt, sel[i]); + cnt = module->Add(NEW_TWINE, cnt, sel[i]); - SigSpec assert_a = module->Le(NEW_ID, cnt, SigSpec(1, cntbits)); + SigSpec assert_a = module->Le(NEW_TWINE, cnt, SigSpec(1, cntbits)); SigSpec assert_en; if (flag_noinit) - assert_en.append(module->LogicNot(NEW_ID, module->Initstate(NEW_ID))); + assert_en.append(module->LogicNot(NEW_TWINE, module->Initstate(module->design->twines.add(NEW_TWINE)))); if (!flag_always) assert_en.append(get_activation(pmux->getPort(TW::Y))); @@ -172,9 +172,9 @@ struct AssertpmuxWorker assert_en = State::S1; if (GetSize(assert_en) == 2) - assert_en = module->LogicAnd(NEW_ID, assert_en[0], assert_en[1]); + assert_en = module->LogicAnd(NEW_TWINE, assert_en[0], assert_en[1]); - Cell *assert_cell = module->addAssert(NEW_ID, assert_a, assert_en); + Cell *assert_cell = module->addAssert(NEW_TWINE, assert_a, assert_en); if (pmux->src_id() != Twine::Null && module->design) assert_cell->set_src_id(pmux->src_id()); diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc index c7960b7f6..828d630ac 100644 --- a/passes/sat/async2sync.cc +++ b/passes/sat/async2sync.cc @@ -95,10 +95,10 @@ struct Async2syncPass : public Pass { if (trg_width == 0) { if (initstate == State::S0) - initstate = module->Initstate(NEW_ID); + initstate = module->Initstate(module->design->twines.add(NEW_TWINE)); SigBit sig_en = cell->getPort(TW::EN); - cell->setPort(TW::EN, module->And(NEW_ID, sig_en, initstate)); + cell->setPort(TW::EN, module->And(NEW_TWINE, sig_en, initstate)); } else { SigBit sig_en = cell->getPort(TW::EN); SigSpec sig_args = cell->getPort(TW::ARGS); @@ -107,15 +107,15 @@ struct Async2syncPass : public Pass { Wire *sig_en_q = module->addWire(NEW_TWINE); Wire *sig_args_q = module->addWire(NEW_TWINE, GetSize(sig_args)); sig_en_q->attributes.emplace(ID::init, State::S0); - module->addDff(NEW_ID, sig_trg, sig_en, sig_en_q, trg_polarity, cell->src_ref()); - module->addDff(NEW_ID, sig_trg, sig_args, sig_args_q, trg_polarity, cell->src_ref()); + module->addDff(NEW_TWINE, sig_trg, sig_en, sig_en_q, trg_polarity, cell->src_ref()); + module->addDff(NEW_TWINE, sig_trg, sig_args, sig_args_q, trg_polarity, cell->src_ref()); cell->setPort(TW::EN, sig_en_q); cell->setPort(TW::ARGS, sig_args_q); if (cell->type == ID($check)) { SigBit sig_a = cell->getPort(TW::A); Wire *sig_a_q = module->addWire(NEW_TWINE); sig_a_q->attributes.emplace(ID::init, State::S1); - module->addDff(NEW_ID, sig_trg, sig_a, sig_a_q, trg_polarity, cell->src_ref()); + module->addDff(NEW_TWINE, sig_trg, sig_a, sig_a_q, trg_polarity, cell->src_ref()); cell->setPort(TW::A, sig_a_q); } } @@ -161,21 +161,21 @@ struct Async2syncPass : public Pass { if (!ff.pol_set) { if (!ff.is_fine) - sig_set = module->Not(NEW_ID, sig_set); + sig_set = module->Not(NEW_TWINE, sig_set); else - sig_set = module->NotGate(NEW_ID, sig_set); + sig_set = module->NotGate(NEW_TWINE, sig_set); } if (ff.pol_clr) { if (!ff.is_fine) - sig_clr_inv = module->Not(NEW_ID, sig_clr); + sig_clr_inv = module->Not(NEW_TWINE, sig_clr); else - sig_clr_inv = module->NotGate(NEW_ID, sig_clr); + sig_clr_inv = module->NotGate(NEW_TWINE, sig_clr); } else { if (!ff.is_fine) - sig_clr = module->Not(NEW_ID, sig_clr); + sig_clr = module->Not(NEW_TWINE, sig_clr); else - sig_clr = module->NotGate(NEW_ID, sig_clr); + sig_clr = module->NotGate(NEW_TWINE, sig_clr); } // At this point, sig_set and sig_clr are now unconditionally @@ -183,26 +183,26 @@ struct Async2syncPass : public Pass { SigSpec set_and_clr; if (!ff.is_fine) - set_and_clr = module->And(NEW_ID, sig_set, sig_clr); + set_and_clr = module->And(NEW_TWINE, sig_set, sig_clr); else - set_and_clr = module->AndGate(NEW_ID, sig_set, sig_clr); + set_and_clr = module->AndGate(NEW_TWINE, sig_set, sig_clr); if (!ff.is_fine) { - SigSpec tmp = module->Or(NEW_ID, ff.sig_d, sig_set); - tmp = module->And(NEW_ID, tmp, sig_clr_inv); - module->addBwmux(NEW_ID, tmp, Const(State::Sx, ff.width), set_and_clr, new_d); + SigSpec tmp = module->Or(NEW_TWINE, ff.sig_d, sig_set); + tmp = module->And(NEW_TWINE, tmp, sig_clr_inv); + module->addBwmux(NEW_TWINE, tmp, Const(State::Sx, ff.width), set_and_clr, new_d); - tmp = module->Or(NEW_ID, new_q, sig_set); - tmp = module->And(NEW_ID, tmp, sig_clr_inv); - module->addBwmux(NEW_ID, tmp, Const(State::Sx, ff.width), set_and_clr, ff.sig_q); + tmp = module->Or(NEW_TWINE, new_q, sig_set); + tmp = module->And(NEW_TWINE, tmp, sig_clr_inv); + module->addBwmux(NEW_TWINE, tmp, Const(State::Sx, ff.width), set_and_clr, ff.sig_q); } else { - SigSpec tmp = module->OrGate(NEW_ID, ff.sig_d, sig_set); - tmp = module->AndGate(NEW_ID, tmp, sig_clr_inv); - module->addMuxGate(NEW_ID, tmp, State::Sx, set_and_clr, new_d); + SigSpec tmp = module->OrGate(NEW_TWINE, ff.sig_d, sig_set); + tmp = module->AndGate(NEW_TWINE, tmp, sig_clr_inv); + module->addMuxGate(NEW_TWINE, tmp, State::Sx, set_and_clr, new_d); - tmp = module->OrGate(NEW_ID, new_q, sig_set); - tmp = module->AndGate(NEW_ID, tmp, sig_clr_inv); - module->addMuxGate(NEW_ID, tmp, State::Sx, set_and_clr, ff.sig_q); + tmp = module->OrGate(NEW_TWINE, new_q, sig_set); + tmp = module->AndGate(NEW_TWINE, tmp, sig_clr_inv); + module->addMuxGate(NEW_TWINE, tmp, State::Sx, set_and_clr, ff.sig_q); } ff.sig_d = new_d; @@ -222,19 +222,19 @@ struct Async2syncPass : public Pass { if (ff.pol_aload) { if (!ff.is_fine) { - module->addMux(NEW_ID, new_q, ff.sig_ad, ff.sig_aload, ff.sig_q); - module->addMux(NEW_ID, ff.sig_d, ff.sig_ad, ff.sig_aload, new_d); + module->addMux(NEW_TWINE, new_q, ff.sig_ad, ff.sig_aload, ff.sig_q); + module->addMux(NEW_TWINE, ff.sig_d, ff.sig_ad, ff.sig_aload, new_d); } else { - module->addMuxGate(NEW_ID, new_q, ff.sig_ad, ff.sig_aload, ff.sig_q); - module->addMuxGate(NEW_ID, ff.sig_d, ff.sig_ad, ff.sig_aload, new_d); + module->addMuxGate(NEW_TWINE, new_q, ff.sig_ad, ff.sig_aload, ff.sig_q); + module->addMuxGate(NEW_TWINE, ff.sig_d, ff.sig_ad, ff.sig_aload, new_d); } } else { if (!ff.is_fine) { - module->addMux(NEW_ID, ff.sig_ad, new_q, ff.sig_aload, ff.sig_q); - module->addMux(NEW_ID, ff.sig_ad, ff.sig_d, ff.sig_aload, new_d); + module->addMux(NEW_TWINE, ff.sig_ad, new_q, ff.sig_aload, ff.sig_q); + module->addMux(NEW_TWINE, ff.sig_ad, ff.sig_d, ff.sig_aload, new_d); } else { - module->addMuxGate(NEW_ID, ff.sig_ad, new_q, ff.sig_aload, ff.sig_q); - module->addMuxGate(NEW_ID, ff.sig_ad, ff.sig_d, ff.sig_aload, new_d); + module->addMuxGate(NEW_TWINE, ff.sig_ad, new_q, ff.sig_aload, ff.sig_q); + module->addMuxGate(NEW_TWINE, ff.sig_ad, ff.sig_d, ff.sig_aload, new_d); } } @@ -254,14 +254,14 @@ struct Async2syncPass : public Pass { if (ff.pol_arst) { if (!ff.is_fine) - module->addMux(NEW_ID, new_q, ff.val_arst, ff.sig_arst, ff.sig_q); + module->addMux(NEW_TWINE, new_q, ff.val_arst, ff.sig_arst, ff.sig_q); else - module->addMuxGate(NEW_ID, new_q, ff.val_arst[0], ff.sig_arst, ff.sig_q); + module->addMuxGate(NEW_TWINE, new_q, ff.val_arst[0], ff.sig_arst, ff.sig_q); } else { if (!ff.is_fine) - module->addMux(NEW_ID, ff.val_arst, new_q, ff.sig_arst, ff.sig_q); + module->addMux(NEW_TWINE, ff.val_arst, new_q, ff.sig_arst, ff.sig_q); else - module->addMuxGate(NEW_ID, ff.val_arst[0], new_q, ff.sig_arst, ff.sig_q); + module->addMuxGate(NEW_TWINE, ff.val_arst[0], new_q, ff.sig_arst, ff.sig_q); } ff.sig_q = new_q; @@ -291,14 +291,14 @@ struct Async2syncPass : public Pass { new_d = module->addWire(NEW_TWINE, ff.width); if (ff.pol_aload) { if (!ff.is_fine) - module->addMux(NEW_ID, new_q, ff.sig_ad, ff.sig_aload, new_d); + module->addMux(NEW_TWINE, new_q, ff.sig_ad, ff.sig_aload, new_d); else - module->addMuxGate(NEW_ID, new_q, ff.sig_ad, ff.sig_aload, new_d); + module->addMuxGate(NEW_TWINE, new_q, ff.sig_ad, ff.sig_aload, new_d); } else { if (!ff.is_fine) - module->addMux(NEW_ID, ff.sig_ad, new_q, ff.sig_aload, new_d); + module->addMux(NEW_TWINE, ff.sig_ad, new_q, ff.sig_aload, new_d); else - module->addMuxGate(NEW_ID, ff.sig_ad, new_q, ff.sig_aload, new_d); + module->addMuxGate(NEW_TWINE, ff.sig_ad, new_q, ff.sig_aload, new_d); } } else { new_d = new_q; @@ -310,36 +310,36 @@ struct Async2syncPass : public Pass { if (!ff.pol_set) { if (!ff.is_fine) - sig_set = module->Not(NEW_ID, sig_set); + sig_set = module->Not(NEW_TWINE, sig_set); else - sig_set = module->NotGate(NEW_ID, sig_set); + sig_set = module->NotGate(NEW_TWINE, sig_set); } if (ff.pol_clr) { if (!ff.is_fine) - sig_clr = module->Not(NEW_ID, sig_clr); + sig_clr = module->Not(NEW_TWINE, sig_clr); else - sig_clr = module->NotGate(NEW_ID, sig_clr); + sig_clr = module->NotGate(NEW_TWINE, sig_clr); } if (!ff.is_fine) { - SigSpec tmp = module->Or(NEW_ID, new_d, sig_set); - module->addAnd(NEW_ID, tmp, sig_clr, ff.sig_q); + SigSpec tmp = module->Or(NEW_TWINE, new_d, sig_set); + module->addAnd(NEW_TWINE, tmp, sig_clr, ff.sig_q); } else { - SigSpec tmp = module->OrGate(NEW_ID, new_d, sig_set); - module->addAndGate(NEW_ID, tmp, sig_clr, ff.sig_q); + SigSpec tmp = module->OrGate(NEW_TWINE, new_d, sig_set); + module->addAndGate(NEW_TWINE, tmp, sig_clr, ff.sig_q); } } else if (ff.has_arst) { if (ff.pol_arst) { if (!ff.is_fine) - module->addMux(NEW_ID, new_d, ff.val_arst, ff.sig_arst, ff.sig_q); + module->addMux(NEW_TWINE, new_d, ff.val_arst, ff.sig_arst, ff.sig_q); else - module->addMuxGate(NEW_ID, new_d, ff.val_arst[0], ff.sig_arst, ff.sig_q); + module->addMuxGate(NEW_TWINE, new_d, ff.val_arst[0], ff.sig_arst, ff.sig_q); } else { if (!ff.is_fine) - module->addMux(NEW_ID, ff.val_arst, new_d, ff.sig_arst, ff.sig_q); + module->addMux(NEW_TWINE, ff.val_arst, new_d, ff.sig_arst, ff.sig_q); else - module->addMuxGate(NEW_ID, ff.val_arst[0], new_d, ff.sig_arst, ff.sig_q); + module->addMuxGate(NEW_TWINE, ff.val_arst[0], new_d, ff.sig_arst, ff.sig_q); } } else { module->connect(ff.sig_q, new_d); diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index e295b4dea..c6d68894b 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -66,18 +66,18 @@ struct Clk2fflogicPass : public Pass { SampledSig sample_control(Module *module, SigSpec sig, bool polarity, bool is_fine) { if (!polarity) { if (is_fine) - sig = module->NotGate(NEW_ID, sig); + sig = module->NotGate(NEW_TWINE, sig); else - sig = module->Not(NEW_ID, sig); + sig = module->Not(NEW_TWINE, sig); } std::string sig_str = log_signal(sig); sig_str.erase(std::remove(sig_str.begin(), sig_str.end(), ' '), sig_str.end()); Wire *sampled_sig = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig)); sampled_sig->attributes[ID::init] = RTLIL::Const(State::S0, GetSize(sig)); if (is_fine) - module->addFfGate(NEW_ID, sig, sampled_sig); + module->addFfGate(NEW_TWINE, sig, sampled_sig); else - module->addFf(NEW_ID, sig, sampled_sig); + module->addFf(NEW_TWINE, sig, sampled_sig); return {sampled_sig, sig}; } // Active-high trigger signal for an edge-triggered control signal. Initial values is low/non-edge. @@ -87,10 +87,10 @@ struct Clk2fflogicPass : public Pass { Wire *sampled_sig = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig)); sampled_sig->attributes[ID::init] = RTLIL::Const(polarity ? State::S1 : State::S0, GetSize(sig)); if (is_fine) - module->addFfGate(NEW_ID, sig, sampled_sig); + module->addFfGate(NEW_TWINE, sig, sampled_sig); else - module->addFf(NEW_ID, sig, sampled_sig); - return module->Eqx(NEW_ID, {sampled_sig, sig}, polarity ? SigSpec {State::S0, State::S1} : SigSpec {State::S1, State::S0}); + module->addFf(NEW_TWINE, sig, sampled_sig); + return module->Eqx(NEW_TWINE, {sampled_sig, sig}, polarity ? SigSpec {State::S0, State::S1} : SigSpec {State::S1, State::S0}); } // Sampled and current value of a data signal. SampledSig sample_data(Module *module, SigSpec sig, RTLIL::Const init, bool is_fine, bool set_attribute = false) { @@ -103,9 +103,9 @@ struct Clk2fflogicPass : public Pass { Cell *cell; if (is_fine) - cell = module->addFfGate(NEW_ID, sig, sampled_sig); + cell = module->addFfGate(NEW_TWINE, sig, sampled_sig); else - cell = module->addFf(NEW_ID, sig, sampled_sig); + cell = module->addFf(NEW_TWINE, sig, sampled_sig); if (set_attribute) { for (auto &chunk : sig.chunks()) @@ -118,17 +118,17 @@ struct Clk2fflogicPass : public Pass { } SigSpec mux(Module *module, SigSpec a, SigSpec b, SigSpec s, bool is_fine) { if (is_fine) - return module->MuxGate(NEW_ID, a, b, s); + return module->MuxGate(NEW_TWINE, a, b, s); else - return module->Mux(NEW_ID, a, b, s); + return module->Mux(NEW_TWINE, a, b, s); } SigSpec bitwise_sr(Module *module, SigSpec a, SigSpec s, SigSpec r, bool is_fine) { if (is_fine) { - return module->MuxGate(NEW_ID, module->AndGate(NEW_ID, module->OrGate(NEW_ID, a, s), module->NotGate(NEW_ID, r)), RTLIL::State::Sx, module->AndGate(NEW_ID, s, r)); + return module->MuxGate(NEW_ID, module->AndGate(NEW_ID, module->OrGate(NEW_ID, a, s), module->NotGate(NEW_ID, r)), RTLIL::State::Sx, module->AndGate(NEW_TWINE, s, r)); } else { std::vector y; for (int i = 0; i < a.size(); i++) - y.push_back(module->MuxGate(NEW_ID, module->AndGate(NEW_ID, module->OrGate(NEW_ID, a[i], s[i]), module->NotGate(NEW_ID, r[i])), RTLIL::State::Sx, module->AndGate(NEW_ID, s[i], r[i]))); + y.push_back(module->MuxGate(NEW_ID, module->AndGate(NEW_ID, module->OrGate(NEW_ID, a[i], s[i]), module->NotGate(NEW_ID, r[i])), RTLIL::State::Sx, module->AndGate(NEW_TWINE, s[i], r[i]))); return y; } } @@ -189,7 +189,7 @@ struct Clk2fflogicPass : public Pass { Wire *past_clk = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#past_clk#%s", mem.memid.unescape(), i, log_signal(port.clk)))); past_clk->attributes[ID::init] = port.clk_polarity ? State::S1 : State::S0; - module->addFf(NEW_ID, port.clk, past_clk); + module->addFf(NEW_TWINE, port.clk, past_clk); SigSpec clock_edge_pattern; @@ -201,19 +201,19 @@ struct Clk2fflogicPass : public Pass { clock_edge_pattern.append(State::S0); } - SigSpec clock_edge = module->Eqx(NEW_ID, {port.clk, SigSpec(past_clk)}, clock_edge_pattern); + SigSpec clock_edge = module->Eqx(NEW_TWINE, {port.clk, SigSpec(past_clk)}, clock_edge_pattern); SigSpec en_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#en_q", mem.memid.unescape(), i)), GetSize(port.en)); - module->addFf(NEW_ID, port.en, en_q); + module->addFf(NEW_TWINE, port.en, en_q); SigSpec addr_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#addr_q", mem.memid.unescape(), i)), GetSize(port.addr)); - module->addFf(NEW_ID, port.addr, addr_q); + module->addFf(NEW_TWINE, port.addr, addr_q); SigSpec data_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#data_q", mem.memid.unescape(), i)), GetSize(port.data)); - module->addFf(NEW_ID, port.data, data_q); + module->addFf(NEW_TWINE, port.data, data_q); port.clk = State::S0; - port.en = module->Mux(NEW_ID, Const(0, GetSize(en_q)), en_q, clock_edge); + port.en = module->Mux(NEW_TWINE, Const(0, GetSize(en_q)), en_q, clock_edge); port.addr = addr_q; port.data = data_q; @@ -241,10 +241,10 @@ struct Clk2fflogicPass : public Pass { if (trg_width == 0) { if (initstate == State::S0) - initstate = module->Initstate(NEW_ID); + initstate = module->Initstate(NEW_TWINE); SigBit sig_en = cell->getPort(TW::EN); - cell->setPort(TW::EN, module->And(NEW_ID, sig_en, initstate)); + cell->setPort(TW::EN, module->And(NEW_TWINE, sig_en, initstate)); } else { SigBit sig_en = cell->getPort(TW::EN); SigSpec sig_args = cell->getPort(TW::ARGS); @@ -258,9 +258,9 @@ struct Clk2fflogicPass : public Pass { SigSpec sig_args_sampled = sample_data(module, sig_args, Const(State::S0, GetSize(sig_args)), false, false).sampled; SigBit sig_en_sampled = sample_data(module, sig_en, State::S0, false, false).sampled; - SigBit sig_trg_combined = module->ReduceOr(NEW_ID, sig_trg_sampled); + SigBit sig_trg_combined = module->ReduceOr(NEW_TWINE, sig_trg_sampled); - cell->setPort(TW::EN, module->And(NEW_ID, sig_en_sampled, sig_trg_combined)); + cell->setPort(TW::EN, module->And(NEW_TWINE, sig_en_sampled, sig_trg_combined)); cell->setPort(TW::ARGS, sig_args_sampled); if (cell->type == ID($check)) { SigBit sig_a = cell->getPort(TW::A); diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc index 24876aeec..38989ee12 100644 --- a/passes/sat/cutpoint.cc +++ b/passes/sat/cutpoint.cc @@ -105,7 +105,7 @@ struct CutpointPass : public Pass { if (wire->port_output) output_wires.push_back(wire); for (auto wire : output_wires) - module->connect(wire, flag_undef ? Const(State::Sx, GetSize(wire)) : module->Anyseq(NEW_ID, GetSize(wire))); + module->connect(wire, flag_undef ? Const(State::Sx, GetSize(wire)) : module->Anyseq(NEW_TWINE, GetSize(wire))); continue; } @@ -141,7 +141,7 @@ struct CutpointPass : public Pass { } if (do_cut) { - module->connect(conn.second, flag_undef ? Const(State::Sx, GetSize(conn.second)) : module->Anyseq(NEW_ID, GetSize(conn.second))); + module->connect(conn.second, flag_undef ? Const(State::Sx, GetSize(conn.second)) : module->Anyseq(NEW_TWINE, GetSize(conn.second))); if (cell->input(conn.first)) { log_debug(" Treating inout port '%s' as output.\n", conn.first.unescape()); for (auto bit : sigmap(conn.second)) @@ -177,7 +177,7 @@ struct CutpointPass : public Pass { log("Making output wire %s.%s a cutpoint.\n", module, wire); Wire *new_wire = module->addWire(NEW_TWINE, wire); module->swap_names(wire, new_wire); - module->connect(new_wire, flag_undef ? Const(State::Sx, GetSize(new_wire)) : module->Anyseq(NEW_ID, GetSize(new_wire))); + module->connect(new_wire, flag_undef ? Const(State::Sx, GetSize(new_wire)) : module->Anyseq(NEW_TWINE, GetSize(new_wire))); wire->port_id = 0; wire->port_input = false; wire->port_output = false; @@ -246,7 +246,7 @@ struct CutpointPass : public Pass { for (auto chunk : sig.chunks()) { SigSpec s(chunk); - module->connect(s, flag_undef ? Const(State::Sx, GetSize(s)) : module->Anyseq(NEW_ID, GetSize(s))); + module->connect(s, flag_undef ? Const(State::Sx, GetSize(s)) : module->Anyseq(NEW_TWINE, GetSize(s))); } } } diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 04e6d4a6a..bff31ed0b 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -85,7 +85,7 @@ void find_dff_wires(std::set &dff_wires, RTLIL::Module *module) SigPool dffsignals; for (auto cell : module->cells()) { - if (ct.cell_known(cell->type) && cell->hasPort(ID::Q)) + if (ct.cell_known(cell->type) && cell->hasPort(TW::Q)) dffsignals.add(sigmap(cell->getPort(TW::Q))); } diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc index d3550f7eb..c40803f08 100644 --- a/passes/sat/fmcombine.cc +++ b/passes/sat/fmcombine.cc @@ -121,9 +121,9 @@ struct FmcombineWorker if (cell->is_builtin_ff()) { SigSpec gold_q = gold->getPort(TW::Q); SigSpec gate_q = gate->getPort(TW::Q); - SigSpec en = module->Initstate(NEW_ID); - SigSpec eq = module->Eq(NEW_ID, gold_q, gate_q); - module->addAssume(NEW_ID, eq, en); + SigSpec en = module->Initstate(NEW_TWINE); + SigSpec eq = module->Eq(NEW_TWINE, gold_q, gate_q); + module->addAssume(NEW_TWINE, eq, en); } } } @@ -163,7 +163,7 @@ struct FmcombineWorker SigSpec A = import_sig(conn.second, "_gold"); SigSpec B = import_sig(conn.second, "_gate"); - SigBit EQ = module->Eq(NEW_ID, A, B); + SigBit EQ = module->Eq(NEW_TWINE, A, B); for (auto bit : sigmap({A, B})) data_bit_to_eq_net[bit] = EQ; @@ -205,7 +205,7 @@ struct FmcombineWorker if (GetSize(antecedent) > 1) { if (reduce_db.count(antecedent) == 0) - reduce_db[antecedent] = module->ReduceAnd(NEW_ID, antecedent); + reduce_db[antecedent] = module->ReduceAnd(NEW_TWINE, antecedent); antecedent = reduce_db.at(antecedent); } @@ -214,22 +214,22 @@ struct FmcombineWorker if (GetSize(consequent) > 1) { if (reduce_db.count(consequent) == 0) - reduce_db[consequent] = module->ReduceAnd(NEW_ID, consequent); + reduce_db[consequent] = module->ReduceAnd(NEW_TWINE, consequent); consequent = reduce_db.at(consequent); } if (opts.fwd) - module->addAssume(NEW_ID, consequent, antecedent); + module->addAssume(NEW_TWINE, consequent, antecedent); if (opts.bwd) { if (invert_db.count(antecedent) == 0) - invert_db[antecedent] = module->Not(NEW_ID, antecedent); + invert_db[antecedent] = module->Not(NEW_TWINE, antecedent); if (invert_db.count(consequent) == 0) - invert_db[consequent] = module->Not(NEW_ID, consequent); + invert_db[consequent] = module->Not(NEW_TWINE, consequent); - module->addAssume(NEW_ID, invert_db.at(antecedent), invert_db.at(consequent)); + module->addAssume(NEW_TWINE, invert_db.at(antecedent), invert_db.at(consequent)); } } } diff --git a/passes/sat/fminit.cc b/passes/sat/fminit.cc index e9cfc2f23..f788a73ec 100644 --- a/passes/sat/fminit.cc +++ b/passes/sat/fminit.cc @@ -131,8 +131,8 @@ struct FminitPass : public Pass { } if (!final_lhs.empty()) { - SigSpec eq = module->Eq(NEW_ID, final_lhs, final_rhs); - module->addAssume(NEW_ID, eq, State::S1); + SigSpec eq = module->Eq(NEW_TWINE, final_lhs, final_rhs); + module->addAssume(NEW_TWINE, eq, State::S1); } } @@ -156,9 +156,9 @@ struct FminitPass : public Pass { outwire->attributes[ID::init] = i > 0 ? State::S0 : State::S1; if (clksig.empty()) - module->addFf(NEW_ID, insig, outwire); + module->addFf(NEW_TWINE, insig, outwire); else - module->addDff(NEW_ID, clksig, insig, outwire, clockedge); + module->addDff(NEW_TWINE, clksig, insig, outwire, clockedge); ctrlsig.push_back(outwire); ctrlsig_latched.push_back(SigSpec()); @@ -168,12 +168,12 @@ struct FminitPass : public Pass { { Wire *ffwire = module->addWire(NEW_TWINE); ffwire->attributes[ID::init] = State::S0; - SigSpec outsig = module->Or(NEW_ID, ffwire, ctrlsig[i]); + SigSpec outsig = module->Or(NEW_TWINE, ffwire, ctrlsig[i]); if (clksig.empty()) - module->addFf(NEW_ID, outsig, ffwire); + module->addFf(NEW_TWINE, outsig, ffwire); else - module->addDff(NEW_ID, clksig, outsig, ffwire, clockedge); + module->addDff(NEW_TWINE, clksig, outsig, ffwire, clockedge); ctrlsig_latched[i] = outsig; } @@ -192,8 +192,8 @@ struct FminitPass : public Pass { } if (!final_lhs.empty()) { - SigSpec eq = module->Eq(NEW_ID, final_lhs, final_rhs); - module->addAssume(NEW_ID, eq, ctrl); + SigSpec eq = module->Eq(NEW_TWINE, final_lhs, final_rhs); + module->addAssume(NEW_TWINE, eq, ctrl); } } } diff --git a/passes/sat/formalff.cc b/passes/sat/formalff.cc index fefd5dc51..2165c7243 100644 --- a/passes/sat/formalff.cc +++ b/passes/sat/formalff.cc @@ -402,7 +402,7 @@ struct PropagateWorker sigmap.apply(bit); if (replaced_clk_bits.count(bit)) log_error("derived signal %s driven by %s (%s) from module %s is used as clock, derived clocks are only supported with clk2fflogic.\n", - log_signal(bit), cell->name.unescape(), cell->type.unescape(), module); + log_signal(bit), cell->module->design->twines.str(cell->meta_->name), cell->type.unescape(), module); } } } @@ -420,7 +420,7 @@ struct PropagateWorker replaced_clk_inputs.emplace_back(ReplacedPort {port, i, it->second}); if (it->second) { - bit = module->Not(NEW_ID, bit); + bit = module->Not(NEW_TWINE, bit); } } } @@ -802,9 +802,9 @@ struct FormalFfPass : public Pass { log_debug("patching rd port\n"); changed = true; rd_port.clk = gate_clock; - SigBit en_bit = pol_clk ? sig_gate : SigBit(module->Not(NEW_ID, sig_gate)); + SigBit en_bit = pol_clk ? sig_gate : SigBit(module->Not(NEW_TWINE, sig_gate)); SigSpec en_mask = SigSpec(en_bit, GetSize(rd_port.en)); - rd_port.en = module->And(NEW_ID, rd_port.en, en_mask); + rd_port.en = module->And(NEW_TWINE, rd_port.en, en_mask); } } for (auto &wr_port : mem.wr_ports) { @@ -812,9 +812,9 @@ struct FormalFfPass : public Pass { log_debug("patching wr port\n"); changed = true; wr_port.clk = gate_clock; - SigBit en_bit = pol_clk ? sig_gate : SigBit(module->Not(NEW_ID, sig_gate)); + SigBit en_bit = pol_clk ? sig_gate : SigBit(module->Not(NEW_TWINE, sig_gate)); SigSpec en_mask = SigSpec(en_bit, GetSize(wr_port.en)); - wr_port.en = module->And(NEW_ID, wr_port.en, en_mask); + wr_port.en = module->And(NEW_TWINE, wr_port.en, en_mask); } } if (changed) @@ -982,9 +982,9 @@ struct FormalFfPass : public Pass { SigBit clk = pair.first; if (pair.second) - clk = module->Not(NEW_ID, clk); + clk = module->Not(NEW_TWINE, clk); - module->addAssume(NEW_ID, clk, State::S1); + module->addAssume(NEW_TWINE, clk, State::S1); } } diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 2f7f66293..a5c11e9c5 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -597,7 +597,7 @@ struct FreduceWorker { std::string filename = stringf("%s_%s_%05d.il", dump_prefix, module, reduce_counter); log("%s Writing dump file `%s'.\n", reduce_counter ? " " : "", filename); - Pass::call(design, stringf("dump -outfile %s %s", filename, design->selected_active_module.empty() ? module->name.c_str() : "")); + Pass::call(design, stringf("dump -outfile %s %s", filename, design->selected_active_module == Twine::Null ? design->twines.str(module->meta_->name).c_str() : "")); } int run() diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 522fb6205..43ab0d34c 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -89,7 +89,7 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: for (auto gold_wire : gold_module->wires()) { if (gold_wire->port_id == 0) continue; - RTLIL::Wire *gate_wire = gate_module->wire(gold_wire->name); + RTLIL::Wire *gate_wire = gate_module->wire(gold_wire->meta_->name); if (gate_wire == nullptr) goto match_gold_port_error; if (gold_wire->width != gate_wire->width) @@ -105,13 +105,13 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: goto match_gold_port_error; continue; match_gold_port_error: - log_cmd_error("No matching port in gate module was found for %s!\n", gold_wire->name); + log_cmd_error("No matching port in gate module was found for %s!\n", design->twines.str(gold_wire->meta_->name).c_str()); } for (auto gate_wire : gate_module->wires()) { if (gate_wire->port_id == 0) continue; - RTLIL::Wire *gold_wire = gold_module->wire(gate_wire->name); + RTLIL::Wire *gold_wire = gold_module->wire(gate_wire->meta_->name); if (gold_wire == nullptr) goto match_gate_port_error; if (gate_wire->width != gold_wire->width) @@ -125,18 +125,18 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: goto match_gate_port_error; continue; match_gate_port_error: - log_cmd_error("No matching port in gold module was found for %s!\n", gate_wire->name); + log_cmd_error("No matching port in gold module was found for %s!\n", design->twines.str(gate_wire->meta_->name).c_str()); } log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", miter_name.unescape(), gold_name.unescape(), gate_name.unescape()); RTLIL::Module *miter_module = new RTLIL::Module; miter_module->design = design; - miter_module->name = miter_name; + miter_module->meta_->name = design->twines.add(Twine{miter_name.str()}); design->add(miter_module); - RTLIL::Cell *gold_cell = miter_module->addCell(ID(gold), gold_name); - RTLIL::Cell *gate_cell = miter_module->addCell(ID(gate), gate_name); + RTLIL::Cell *gold_cell = miter_module->addCell(TW::gold, gold_name); + RTLIL::Cell *gate_cell = miter_module->addCell(TW::gate, gate_name); RTLIL::SigSpec all_conditions; @@ -144,46 +144,46 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: { if (gold_cross_ports.count(gold_wire)) { - SigSpec w = miter_module->addWire("\\cross_" + gold_wire->name.unescape(), gold_wire->width); - gold_cell->setPort(gold_wire->name, w); + SigSpec w = miter_module->addWire(Twine{"\\cross_" + design->twines.str(gold_wire->meta_->name)}, GetSize(gold_wire)); + gold_cell->setPort(gold_wire->meta_->name, w); if (flag_ignore_gold_x) { RTLIL::SigSpec w_x = miter_module->addWire(NEW_TWINE, GetSize(w)); for (int i = 0; i < GetSize(w); i++) - miter_module->addEqx(NEW_ID, w[i], State::Sx, w_x[i]); - RTLIL::SigSpec w_any = miter_module->And(NEW_ID, miter_module->Anyseq(NEW_ID, GetSize(w)), w_x); - RTLIL::SigSpec w_masked = miter_module->And(NEW_ID, w, miter_module->Not(NEW_ID, w_x)); - w = miter_module->And(NEW_ID, w_any, w_masked); + miter_module->addEqx(NEW_TWINE, w[i], State::Sx, w_x[i]); + RTLIL::SigSpec w_any = miter_module->And(NEW_TWINE, miter_module->Anyseq(NEW_TWINE, GetSize(w)), w_x); + RTLIL::SigSpec w_masked = miter_module->And(NEW_TWINE, w, miter_module->Not(NEW_TWINE, w_x)); + w = miter_module->And(NEW_TWINE, w_any, w_masked); } - gate_cell->setPort(gold_wire->name, w); + gate_cell->setPort(gold_wire->meta_->name, w); continue; } if (gold_wire->port_input) { - RTLIL::Wire *w = miter_module->addWire("\\in_" + gold_wire->name.unescape(), gold_wire->width); + RTLIL::Wire *w = miter_module->addWire(Twine{"\\in_" + design->twines.str(gold_wire->meta_->name)}, GetSize(gold_wire)); w->port_input = true; - gold_cell->setPort(gold_wire->name, w); - gate_cell->setPort(gold_wire->name, w); + gold_cell->setPort(gold_wire->meta_->name, w); + gate_cell->setPort(gold_wire->meta_->name, w); } if (gold_wire->port_output) { - RTLIL::Wire *w_gold = miter_module->addWire("\\gold_" + gold_wire->name.unescape(), gold_wire->width); + RTLIL::Wire *w_gold = miter_module->addWire(Twine{"\\gold_" + design->twines.str(gold_wire->meta_->name)}, GetSize(gold_wire)); w_gold->port_output = flag_make_outputs; - RTLIL::Wire *w_gate = miter_module->addWire("\\gate_" + gold_wire->name.unescape(), gold_wire->width); + RTLIL::Wire *w_gate = miter_module->addWire(Twine{"\\gate_" + design->twines.str(gold_wire->meta_->name)}, GetSize(gold_wire)); w_gate->port_output = flag_make_outputs; - gold_cell->setPort(gold_wire->name, w_gold); - gate_cell->setPort(gold_wire->name, w_gate); + gold_cell->setPort(gold_wire->meta_->name, w_gold); + gate_cell->setPort(gold_wire->meta_->name, w_gate); RTLIL::SigSpec this_condition; if (flag_ignore_gold_x) { - RTLIL::SigSpec gold_x = miter_module->addWire(NEW_TWINE, w_gold->width); - for (int i = 0; i < w_gold->width; i++) { + RTLIL::SigSpec gold_x = miter_module->addWire(NEW_TWINE, GetSize(w_gold)); + for (int i = 0; i < GetSize(w_gold); i++) { RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_TWINE, ID($eqx)); eqx_cell->parameters[ID::A_WIDTH] = 1; eqx_cell->parameters[ID::B_WIDTH] = 1; @@ -199,9 +199,9 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_TWINE, w_gate->width); RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_TWINE, ID($or)); - or_gold_cell->parameters[ID::A_WIDTH] = w_gold->width; - or_gold_cell->parameters[ID::B_WIDTH] = w_gold->width; - or_gold_cell->parameters[ID::Y_WIDTH] = w_gold->width; + or_gold_cell->parameters[ID::A_WIDTH] = GetSize(w_gold); + or_gold_cell->parameters[ID::B_WIDTH] = GetSize(w_gold); + or_gold_cell->parameters[ID::Y_WIDTH] = GetSize(w_gold); or_gold_cell->parameters[ID::A_SIGNED] = 0; or_gold_cell->parameters[ID::B_SIGNED] = 0; or_gold_cell->setPort(TW::A, w_gold); @@ -209,9 +209,9 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: or_gold_cell->setPort(TW::Y, gold_masked); RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_TWINE, ID($or)); - or_gate_cell->parameters[ID::A_WIDTH] = w_gate->width; - or_gate_cell->parameters[ID::B_WIDTH] = w_gate->width; - or_gate_cell->parameters[ID::Y_WIDTH] = w_gate->width; + or_gate_cell->parameters[ID::A_WIDTH] = GetSize(w_gate); + or_gate_cell->parameters[ID::B_WIDTH] = GetSize(w_gate); + or_gate_cell->parameters[ID::Y_WIDTH] = GetSize(w_gate); or_gate_cell->parameters[ID::A_SIGNED] = 0; or_gate_cell->parameters[ID::B_SIGNED] = 0; or_gate_cell->setPort(TW::A, w_gate); @@ -219,8 +219,8 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: or_gate_cell->setPort(TW::Y, gate_masked); RTLIL::Cell *eq_cell = miter_module->addCell(NEW_TWINE, ID($eqx)); - eq_cell->parameters[ID::A_WIDTH] = w_gold->width; - eq_cell->parameters[ID::B_WIDTH] = w_gate->width; + eq_cell->parameters[ID::A_WIDTH] = GetSize(w_gold); + eq_cell->parameters[ID::B_WIDTH] = GetSize(w_gate); eq_cell->parameters[ID::Y_WIDTH] = 1; eq_cell->parameters[ID::A_SIGNED] = 0; eq_cell->parameters[ID::B_SIGNED] = 0; @@ -232,8 +232,8 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: else { RTLIL::Cell *eq_cell = miter_module->addCell(NEW_TWINE, ID($eqx)); - eq_cell->parameters[ID::A_WIDTH] = w_gold->width; - eq_cell->parameters[ID::B_WIDTH] = w_gate->width; + eq_cell->parameters[ID::A_WIDTH] = GetSize(w_gold); + eq_cell->parameters[ID::B_WIDTH] = GetSize(w_gate); eq_cell->parameters[ID::Y_WIDTH] = 1; eq_cell->parameters[ID::A_SIGNED] = 0; eq_cell->parameters[ID::B_SIGNED] = 0; @@ -245,15 +245,15 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: if (flag_make_outcmp) { - RTLIL::Wire *w_cmp = miter_module->addWire("\\cmp_" + gold_wire->name.unescape()); + RTLIL::Wire *w_cmp = miter_module->addWire(Twine{"\\cmp_" + design->twines.str(gold_wire->meta_->name)}); w_cmp->port_output = true; miter_module->connect(RTLIL::SigSig(w_cmp, this_condition)); } if (flag_make_cover) { - auto cover_condition = miter_module->Not(NEW_ID, this_condition); - miter_module->addCover("\\cover_" + gold_wire->name.unescape(), cover_condition, State::S1); + auto cover_condition = miter_module->Not(NEW_TWINE, this_condition); + miter_module->addCover(Twine{"\\cover_" + design->twines.str(gold_wire->meta_->name)}, cover_condition, State::S1); } all_conditions.append(this_condition); @@ -276,7 +276,7 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: assert_cell->setPort(TW::EN, State::S1); } - RTLIL::Wire *w_trigger = miter_module->addWire(ID(trigger)); + RTLIL::Wire *w_trigger = miter_module->addWire(TW::trigger); w_trigger->port_output = true; RTLIL::Cell *not_cell = miter_module->addCell(NEW_TWINE, ID($not)); @@ -331,7 +331,7 @@ void create_miter_assert(struct Pass *that, std::vector args, RTLIL if (!miter_name.empty()) { module = module->clone(); - module->name = miter_name; + module->meta_->name = design->twines.add(Twine{miter_name.str()}); design->add(module); } @@ -356,13 +356,13 @@ void create_miter_assert(struct Pass *that, std::vector args, RTLIL if (!cell->type.in(ID($assert), ID($assume))) continue; - SigBit is_active = module->Nex(NEW_ID, cell->getPort(TW::A), State::S1); - SigBit is_enabled = module->Eqx(NEW_ID, cell->getPort(TW::EN), State::S1); + SigBit is_active = module->Nex(NEW_TWINE, cell->getPort(TW::A), State::S1); + SigBit is_enabled = module->Eqx(NEW_TWINE, cell->getPort(TW::EN), State::S1); if (cell->type == ID($assert)) { - assert_signals.append(module->And(NEW_ID, is_active, is_enabled)); + assert_signals.append(module->And(NEW_TWINE, is_active, is_enabled)); } else { - assume_signals.append(module->And(NEW_ID, is_active, is_enabled)); + assume_signals.append(module->And(NEW_TWINE, is_active, is_enabled)); } module->remove(cell); @@ -370,7 +370,7 @@ void create_miter_assert(struct Pass *that, std::vector args, RTLIL if (assume_signals.empty()) { - module->addReduceOr(NEW_ID, assert_signals, trigger); + module->addReduceOr(NEW_TWINE, assert_signals, trigger); } else { @@ -378,12 +378,12 @@ void create_miter_assert(struct Pass *that, std::vector args, RTLIL assume_q->attributes[ID::init] = State::S0; assume_signals.append(assume_q); - SigSpec assume_nok = module->ReduceOr(NEW_ID, assume_signals); - SigSpec assume_ok = module->Not(NEW_ID, assume_nok); - module->addFf(NEW_ID, assume_nok, assume_q); + SigSpec assume_nok = module->ReduceOr(NEW_TWINE, assume_signals); + SigSpec assume_ok = module->Not(NEW_TWINE, assume_nok); + module->addFf(NEW_TWINE, assume_nok, assume_q); - SigSpec assert_fail = module->ReduceOr(NEW_ID, assert_signals); - module->addAnd(NEW_ID, assert_fail, assume_ok, trigger); + SigSpec assert_fail = module->ReduceOr(NEW_TWINE, assert_signals); + module->addAnd(NEW_TWINE, assert_fail, assume_ok, trigger); } if (flag_flatten) { diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc index eef56e7e1..e1cf0b4a1 100644 --- a/passes/sat/mutate.cc +++ b/passes/sat/mutate.cc @@ -629,7 +629,7 @@ SigBit mutate_ctrl(Module *module, const mutate_opts_t &opts) return State::S1; SigSpec sig = mutate_ctrl_sig(module, opts.ctrl_name, opts.ctrl_width); - return module->Eq(NEW_ID, sig, Const(opts.ctrl_value, GetSize(sig))); + return module->Eq(NEW_TWINE, sig, Const(opts.ctrl_value, GetSize(sig))); } SigSpec mutate_ctrl_mux(Module *module, const mutate_opts_t &opts, SigSpec unchanged_sig, SigSpec changed_sig) @@ -639,7 +639,7 @@ SigSpec mutate_ctrl_mux(Module *module, const mutate_opts_t &opts, SigSpec uncha return unchanged_sig; if (ctrl_bit == State::S1) return changed_sig; - return module->Mux(NEW_ID, unchanged_sig, changed_sig, ctrl_bit); + return module->Mux(NEW_TWINE, unchanged_sig, changed_sig, ctrl_bit); } void mutate_inv(Design *design, const mutate_opts_t &opts) @@ -653,14 +653,14 @@ void mutate_inv(Design *design, const mutate_opts_t &opts) if (cell->input(opts.port)) { log("Add input inverter at %s.%s.%s[%d].\n", module, cell, opts.port.unescape(), opts.portbit); - SigBit outbit = module->Not(NEW_ID, bit); + SigBit outbit = module->Not(NEW_TWINE, bit); bit = mutate_ctrl_mux(module, opts, bit, outbit); } else { log("Add output inverter at %s.%s.%s[%d].\n", module, cell, opts.port.unescape(), opts.portbit); SigBit inbit = module->addWire(NEW_TWINE); - SigBit outbit = module->Not(NEW_ID, inbit); + SigBit outbit = module->Not(NEW_TWINE, inbit); module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit)); bit = inbit; } @@ -710,14 +710,14 @@ void mutate_cnot(Design *design, const mutate_opts_t &opts, bool one) if (cell->input(opts.port)) { log("Add input cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit, opts.ctrlbit); - SigBit outbit = one ? module->Xor(NEW_ID, bit, ctrl) : module->Xnor(NEW_ID, bit, ctrl); + SigBit outbit = one ? module->Xor(NEW_ID, bit, ctrl) : module->Xnor(NEW_TWINE, bit, ctrl); bit = mutate_ctrl_mux(module, opts, bit, outbit); } else { log("Add output cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit, opts.ctrlbit); SigBit inbit = module->addWire(NEW_TWINE); - SigBit outbit = one ? module->Xor(NEW_ID, inbit, ctrl) : module->Xnor(NEW_ID, inbit, ctrl); + SigBit outbit = one ? module->Xor(NEW_ID, inbit, ctrl) : module->Xnor(NEW_TWINE, inbit, ctrl); module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit)); bit = inbit; } diff --git a/passes/sat/qbfsat.cc b/passes/sat/qbfsat.cc index e3d3cc59a..8d48a615d 100644 --- a/passes/sat/qbfsat.cc +++ b/passes/sat/qbfsat.cc @@ -312,8 +312,8 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) { if (cur_thresh != 0) { //Add thresholding logic (but not on the initial run when we don't have a sense of where to start): - RTLIL::SigSpec comparator = maximize? module->Ge(NEW_ID, module->wire(wire_to_optimize_name), RTLIL::Const(cur_thresh), false) - : module->Le(NEW_ID, module->wire(wire_to_optimize_name), RTLIL::Const(cur_thresh), false); + RTLIL::SigSpec comparator = maximize? module->Ge(NEW_TWINE, module->wire(wire_to_optimize_name), RTLIL::Const(cur_thresh), false) + : module->Le(NEW_TWINE, module->wire(wire_to_optimize_name), RTLIL::Const(cur_thresh), false); module->addAssume(wire_to_optimize_name.str() + "__threshold", comparator, RTLIL::Const(1, 1)); log("Trying to solve with %s %s %d.\n", wire_to_optimize_name, (maximize? ">=" : "<="), cur_thresh); diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 8236cfea0..b662f4974 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -533,9 +533,9 @@ struct SatHelper } else { for (auto &d : drivers) for (auto &p : d->connections()) { - if (d->type == ID($dff) && p.first == ID::CLK) + if (d->type == ID($dff) && p.first == TW::CLK) continue; - if (d->type.begins_with("$_DFF_") && p.first == ID::C) + if (d->type.begins_with("$_DFF_") && p.first == TW::C) continue; queued_signals.add(handled_signals.remove(sigmap(p.second))); } @@ -706,13 +706,13 @@ struct SatHelper fprintf(f, "$end\n"); fprintf(f, "$comment\n"); fprintf(f, " Generated from SAT problem in module %s (declared at %s)\n", - module->name.c_str(), module_fname.c_str()); + module->design->twines.str(module->meta_->name).c_str(), module_fname.c_str()); fprintf(f, "$end\n"); // VCD has some limits on internal (non-display) identifier names, so make legal ones std::map vcdnames; - fprintf(f, "$scope module %s $end\n", module->name.c_str()); + fprintf(f, "$scope module %s $end\n", module->design->twines.str(module->meta_->name).c_str()); for (auto &info : modelInfo) { if (vcdnames.find(info.description) != vcdnames.end()) diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 10efe497b..59f20ff70 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -292,8 +292,8 @@ struct SimInstance if (wire->port_input && instance != nullptr && parent != nullptr) { for (int i = 0; i < GetSize(sig); i++) { - if (instance->hasPort(wire->name)) - in_parent_drivers.emplace(sig[i], parent->sigmap(instance->getPort(wire->name)[i])); + if (instance->hasPort(wire->meta_->name)) + in_parent_drivers.emplace(sig[i], parent->sigmap(instance->getPort(wire->meta_->name)[i])); } } } @@ -316,7 +316,7 @@ struct SimInstance Module *mod = module->design->module(cell->type); if (mod != nullptr) { - dirty_children.insert(new SimInstance(shared, scope + "." + cell->name.unescape(), mod, cell, this)); + dirty_children.insert(new SimInstance(shared, scope + "." + cell->module->design->twines.str(cell->meta_->name), mod, cell, this)); } for (auto &port : cell->connections()) { @@ -403,11 +403,11 @@ struct SimInstance delete child.second; } - IdString name() const + TwineRef name() const { if (instance != nullptr) - return instance->name; - return module->name; + return instance->meta_->name; + return module->meta_->name; } std::string hiername() const @@ -415,7 +415,7 @@ struct SimInstance if (instance != nullptr) return parent->hiername() + "." + instance->name.unescape(); - return module->name.unescape(); + return module->design->twines.str(module->meta_->name); } vector witness_full_path() const @@ -558,12 +558,12 @@ struct SimInstance RTLIL::SigSpec sig_a, sig_b, sig_c, sig_d, sig_s, sig_y; bool has_a, has_b, has_c, has_d, has_s, has_y; - has_a = cell->hasPort(ID::A); - has_b = cell->hasPort(ID::B); - has_c = cell->hasPort(ID::C); - has_d = cell->hasPort(ID::D); - has_s = cell->hasPort(ID::S); - has_y = cell->hasPort(ID::Y); + has_a = cell->hasPort(TW::A); + has_b = cell->hasPort(TW::B); + has_c = cell->hasPort(TW::C); + has_d = cell->hasPort(TW::D); + has_s = cell->hasPort(TW::S); + has_y = cell->hasPort(TW::Y); if (has_a) sig_a = cell->getPort(TW::A); if (has_b) sig_b = cell->getPort(TW::B); @@ -672,9 +672,9 @@ struct SimInstance dirty_memories.clear(); for (auto wire : queue_outports) - if (instance->hasPort(wire->name)) { + if (instance->hasPort(wire->meta_->name)) { Const value = get_state(wire); - parent->set_state(instance->getPort(wire->name), value); + parent->set_state(instance->getPort(wire->meta_->name), value); } queue_outports.clear(); @@ -930,7 +930,7 @@ struct SimInstance { for (auto cell : formal_database) { - string label = cell->name.unescape(); + string label = cell->module->design->twines.str(cell->meta_->name); if (cell->has_attribute(ID::src)) label = cell->get_src_attribute(); @@ -1027,7 +1027,7 @@ struct SimInstance child.second->register_signals(id); } - void write_output_header(std::function enter_scope, std::function exit_scope, std::function register_signal) + void write_output_header(std::function enter_scope, std::function exit_scope, std::function register_signal) { int exit_scopes = 1; if (shared->hdlname && instance != nullptr && instance->name.isPublic() && instance->has_attribute(ID::hdlname)) { @@ -1808,6 +1808,8 @@ struct SimWorker : SimShared continue; } + TwinePool& twines = topmod->design->twines; + TwineSearch search(&twines); switch(state) { case 0: @@ -1826,13 +1828,15 @@ struct SimWorker : SimShared if (len<3 || len>4) log_error("Invalid set state line content.\n"); - RTLIL::IdString escaped_s = RTLIL::escape_id(signal_name(parts[len-1])); + std::string unescaped_s = signal_name(parts[len-1]); + std::string escaped_s = RTLIL::escape_id(unescaped_s); + TwineRef found = search.find(escaped_s); if (len==3) { - Wire *w = topmod->wire(escaped_s); + Wire *w = topmod->wire(found); if (!w) { - Cell *c = topmod->cell(escaped_s); + Cell *c = topmod->cell(found); if (!c) - log_warning("Wire/cell %s not present in module %s\n",escaped_s.unescape(),topmod); + log_warning("Wire/cell %s not present in module %s\n", unescaped_s, topmod); else if (c->type.in(ID($anyconst), ID($anyseq))) { SigSpec sig_y= c->getPort(TW::Y); if ((int)parts[1].size() != GetSize(sig_y)) @@ -1845,12 +1849,12 @@ struct SimWorker : SimShared top->set_state(w, Const::from_string(parts[1])); } } else { - Cell *c = topmod->cell(escaped_s); + Cell *c = topmod->cell(found); if (!c) - log_error("Cell %s not present in module %s\n",escaped_s.unescape(),topmod); + log_error("Cell %s not present in module %s\n", unescaped_s,topmod); if (!c->is_mem_cell()) - log_error("Cell %s is not memory cell in module %s\n",escaped_s.unescape(),topmod); - + log_error("Cell %s is not memory cell in module %s\n", unescaped_s,topmod); + Const addr = Const::from_string(parts[1].substr(1,parts[1].size()-2)); Const data = Const::from_string(parts[2]); top->set_memory_state(c->parameters.at(ID::MEMID).decode_string(), addr, data); diff --git a/passes/sat/supercover.cc b/passes/sat/supercover.cc index a2192dc8a..6e5e77163 100644 --- a/passes/sat/supercover.cc +++ b/passes/sat/supercover.cc @@ -78,9 +78,9 @@ struct SupercoverPass : public Pass { if (handled_bits.count(bit)) continue; - SigSpec inv = module->Not(NEW_ID, bit); - module->addCover(NEW_ID, bit, State::S1, src); - module->addCover(NEW_ID, inv, State::S1, src); + SigSpec inv = module->Not(NEW_TWINE, bit); + module->addCover(NEW_TWINE, bit, State::S1, src); + module->addCover(NEW_TWINE, inv, State::S1, src); handled_bits.insert(bit); if (!counted_wire) { diff --git a/passes/sat/synthprop.cc b/passes/sat/synthprop.cc index e41582c23..744a63673 100644 --- a/passes/sat/synthprop.cc +++ b/passes/sat/synthprop.cc @@ -68,12 +68,12 @@ void SynthPropWorker::tracing(RTLIL::Module *mod, int depth, TrackingData &traci log("%*sFound assert %s..\n", 2*(depth+1), "", cell); tracing_data[mod].assertion_cells.emplace(cell); if (!or_outputs) { - tracing_data[mod].names.push_back(hier_path + "." + cell->name.unescape()); + tracing_data[mod].names.push_back(hier_path + "." + cell->module->design->twines.str(cell->meta_->name)); } cnt++; } else if (RTLIL::Module *submod = design->module(cell->type)) { - tracing(submod, depth+1, tracing_data, hier_path + "." + cell->name.unescape()); + tracing(submod, depth+1, tracing_data, hier_path + "." + cell->module->design->twines.str(cell->meta_->name)); if (!or_outputs) { for (size_t i = 0; i < tracing_data[submod].names.size(); i++) tracing_data[mod].names.push_back(tracing_data[submod].names[i]); @@ -163,7 +163,7 @@ void SynthPropWorker::run() SigSpec reset = module->wire(reset_name); reset.extend_u0(width, true); - module->addDlatchsr(NEW_ID, State::S1, Const(State::S0,width), reset, output, module->wire(port_name), true, true, reset_pol); + module->addDlatchsr(NEW_TWINE, State::S1, Const(State::S0,width), reset, output, module->wire(port_name), true, true, reset_pol); } if (!map_file.empty()) { diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 2eef5936c..ef4c08062 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -473,7 +473,7 @@ void prep_dff(RTLIL::Design *design) // be instantiating the derived module which will have had any parameters constant-propagated. // This task is expected to be performed by `abc9_ops -prep_hier`, but it looks like it failed to do so for this design. // Please file a bug report! - log_error("Not expecting parameters on cell '%s' instantiating module '%s' marked (* abc9_flop *)\n", cell->name.unescape(), cell->type.unescape()); + log_error("Not expecting parameters on cell '%s' instantiating module '%s' marked (* abc9_flop *)\n", cell->module->design->twines.str(cell->meta_->name), cell->type.unescape()); } modules_sel.select(inst_module); } @@ -504,7 +504,7 @@ void prep_dff_submod(RTLIL::Design *design) // (a) flop box will have an output // (b) $_DFF_[NP]_.Q will be present as an input SigBit D = module->addWire(NEW_TWINE); - module->addMuxGate(NEW_ID, dff_cell->getPort(TW::D), Q, State::S0, D); + module->addMuxGate(NEW_TWINE, dff_cell->getPort(TW::D), Q, State::S0, D); dff_cell->setPort(TW::D, D); // Rewrite $specify cells that end with $_DFF_[NP]_.Q @@ -1389,8 +1389,8 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) log_error("Cannot find existing box cell with name '%s' in original design.\n", mapped_cell); if (existing_cell->type.begins_with("$paramod$__ABC9_DELAY\\DELAY=")) { - SigBit I = mapped_cell->getPort(ID(i)); - SigBit O = mapped_cell->getPort(ID(o)); + SigBit I = mapped_cell->getPort(TW::i); + SigBit O = mapped_cell->getPort(TW::o); if (I.wire) I.wire = module->wire(remap_name(I.wire->name)); log_assert(O.wire); @@ -1609,7 +1609,7 @@ clone_lut: if (b == RTLIL::State::S0) b = RTLIL::State::S1; else if (b == RTLIL::State::S1) b = RTLIL::State::S0; } - auto cell = module->addLut(NEW_ID, + auto cell = module->addLut(NEW_TWINE, driver_lut->getPort(TW::A), y_bit, driver_mask); diff --git a/passes/techmap/aigmap.cc b/passes/techmap/aigmap.cc index 11ea76e3a..51d79cff4 100644 --- a/passes/techmap/aigmap.cc +++ b/passes/techmap/aigmap.cc @@ -109,7 +109,7 @@ struct AigmapPass : public Pass { SigBit B = sigs.at(node.right_parent); if (nand_mode && node.inverter) { bit = module->addWire(NEW_TWINE); - auto gate = module->addNandGate(NEW_ID, A, B, bit); + auto gate = module->addNandGate(NEW_TWINE, A, B, bit); if (select_mode) new_sel.insert(gate->name); @@ -120,7 +120,7 @@ struct AigmapPass : public Pass { bit = and_cache.at(key); else { bit = module->addWire(NEW_TWINE); - auto gate = module->addAndGate(NEW_ID, A, B, bit); + auto gate = module->addAndGate(NEW_TWINE, A, B, bit); if (select_mode) new_sel.insert(gate->name); } @@ -129,7 +129,7 @@ struct AigmapPass : public Pass { if (node.inverter) { SigBit new_bit = module->addWire(NEW_TWINE); - auto gate = module->addNotGate(NEW_ID, bit, new_bit); + auto gate = module->addNotGate(NEW_TWINE, bit, new_bit); bit = new_bit; if (select_mode) new_sel.insert(gate->name); diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc index d81bd98b6..35221965e 100644 --- a/passes/techmap/alumacc.cc +++ b/passes/techmap/alumacc.cc @@ -52,7 +52,7 @@ struct AlumaccWorker if (GetSize(cached_slt) == 0) { get_of(); get_sf(); - cached_slt = alu_cell->module->Xor(NEW_ID, cached_of, cached_sf); + cached_slt = alu_cell->module->Xor(NEW_TWINE, cached_of, cached_sf); } return cached_slt; @@ -70,8 +70,8 @@ struct AlumaccWorker if (GetSize(cached_sgt) == 0) { get_lt(is_signed); get_eq(); - SigSpec Or = alu_cell->module->Or(NEW_ID, cached_slt, cached_eq); - cached_sgt = alu_cell->module->Not(NEW_ID, Or, false, alu_cell->src_ref()); + SigSpec Or = alu_cell->module->Or(NEW_TWINE, cached_slt, cached_eq); + cached_sgt = alu_cell->module->Not(NEW_TWINE, Or, false, alu_cell->src_ref()); } return cached_sgt; @@ -79,8 +79,8 @@ struct AlumaccWorker if (GetSize(cached_gt) == 0) { get_lt(is_signed); get_eq(); - SigSpec Or = alu_cell->module->Or(NEW_ID, cached_lt, cached_eq); - cached_gt = alu_cell->module->Not(NEW_ID, Or, false, alu_cell->src_ref()); + SigSpec Or = alu_cell->module->Or(NEW_TWINE, cached_lt, cached_eq); + cached_gt = alu_cell->module->Not(NEW_TWINE, Or, false, alu_cell->src_ref()); } return cached_gt; @@ -89,13 +89,13 @@ struct AlumaccWorker RTLIL::SigSpec get_eq() { if (GetSize(cached_eq) == 0) - cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort(TW::X), false, alu_cell->src_ref()); + cached_eq = alu_cell->module->ReduceAnd(NEW_TWINE, alu_cell->getPort(TW::X), false, alu_cell->src_ref()); return cached_eq; } RTLIL::SigSpec get_ne() { if (GetSize(cached_ne) == 0) - cached_ne = alu_cell->module->Not(NEW_ID, get_eq(), false, alu_cell->src_ref()); + cached_ne = alu_cell->module->Not(NEW_TWINE, get_eq(), false, alu_cell->src_ref()); return cached_ne; } @@ -103,7 +103,7 @@ struct AlumaccWorker if (GetSize(cached_cf) == 0) { cached_cf = alu_cell->getPort(TW::CO); log_assert(GetSize(cached_cf) >= 1); - cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->src_ref()); + cached_cf = alu_cell->module->Not(NEW_TWINE, cached_cf[GetSize(cached_cf)-1], false, alu_cell->src_ref()); } return cached_cf; } @@ -112,7 +112,7 @@ struct AlumaccWorker if (GetSize(cached_of) == 0) { cached_of = {alu_cell->getPort(TW::CO), alu_cell->getPort(TW::CI)}; log_assert(GetSize(cached_of) >= 2); - cached_of = alu_cell->module->Xor(NEW_ID, cached_of[GetSize(cached_of)-1], cached_of[GetSize(cached_of)-2]); + cached_of = alu_cell->module->Xor(NEW_TWINE, cached_of[GetSize(cached_of)-1], cached_of[GetSize(cached_of)-2]); } return cached_of; } @@ -499,7 +499,7 @@ struct AlumaccWorker { if (GetSize(n->b) == 0 && GetSize(n->c) == 0 && GetSize(n->cmp) == 0) { - n->alu_cell = module->addPos(NEW_ID, n->a, n->y, n->is_signed); + n->alu_cell = module->addPos(NEW_TWINE, n->a, n->y, n->is_signed); log(" creating $pos cell for "); for (int i = 0; i < GetSize(n->cells); i++) @@ -545,7 +545,7 @@ struct AlumaccWorker if (cmp_ne) sig.append(n->get_ne()); if (GetSize(sig) > 1) - sig = module->ReduceOr(NEW_ID, sig); + sig = module->ReduceOr(NEW_TWINE, sig); sig.extend_u0(GetSize(cmp_y)); module->connect(cmp_y, sig); diff --git a/passes/techmap/arith_tree.cc b/passes/techmap/arith_tree.cc index f993737c1..5854aa16e 100644 --- a/passes/techmap/arith_tree.cc +++ b/passes/techmap/arith_tree.cc @@ -309,7 +309,7 @@ struct Rewriter { for (auto &op : operands) { SigSpec s = extend_operand(op.sig, op.is_signed, width); if (op.negate) - s = module->Not(NEW_ID, s); + s = module->Not(NEW_TWINE, s); extended.push_back(s); } @@ -322,7 +322,7 @@ struct Rewriter { log(" %s -> %d $fa + 1 $add (%d operands, module %s)\n", desc, compressor_count, (int)operands.size(), module); // Emit final add - module->addAdd(NEW_ID, a, b, result_y, false); + module->addAdd(NEW_TWINE, a, b, result_y, false); } void process_chains() diff --git a/passes/techmap/bmuxmap.cc b/passes/techmap/bmuxmap.cc index 7ec37788c..14488fedf 100644 --- a/passes/techmap/bmuxmap.cc +++ b/passes/techmap/bmuxmap.cc @@ -72,9 +72,9 @@ struct BmuxmapPass : public Pass { SigSpec new_data = module->addWire(NEW_TWINE, width); for (int val = 0; val < num_cases; val++) { - module->addEq(NEW_ID, sel, SigSpec(val, GetSize(sel)), new_s[val]); + module->addEq(NEW_TWINE, sel, SigSpec(val, GetSize(sel)), new_s[val]); } - RTLIL::Cell *pmux = module->addPmux(NEW_ID, new_a, data, new_s, new_data); + RTLIL::Cell *pmux = module->addPmux(NEW_TWINE, new_a, data, new_s, new_data); module->design->merge_src(pmux, cell); data = new_data; } @@ -83,7 +83,7 @@ struct BmuxmapPass : public Pass { for (int idx = 0; idx < GetSize(sel); idx++) { SigSpec new_data = module->addWire(NEW_TWINE, GetSize(data)/2); for (int i = 0; i < GetSize(new_data); i += width) { - RTLIL::Cell *mux = module->addMux(NEW_ID, + RTLIL::Cell *mux = module->addMux(NEW_TWINE, data.extract(i*2, width), data.extract(i*2+width, width), sel[idx], diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index 6e2ce7094..5a74390e1 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -76,44 +76,44 @@ struct BoothPassWorker { // Booth unsigned decoder lsb SigBit Bur4d_lsb(std::string name, SigBit lsb_i, SigBit one_i, SigBit s_i) { - SigBit and_op = module->AndGate(NEW_ID_SUFFIX(name), lsb_i, one_i); - return module->XorGate(NEW_ID_SUFFIX(name), and_op, s_i); + SigBit and_op = module->AndGate(NEW_TWINE_SUFFIX(name), lsb_i, one_i); + return module->XorGate(NEW_TWINE_SUFFIX(name), and_op, s_i); } // Booth unsigned radix4 decoder SigBit Bur4d_n(std::string name, SigBit yn_i, SigBit ynm1_i, SigBit one_i, SigBit two_i, SigBit s_i) { // ppij = ((yn & one) | (ynm1 & two)) ^ s; - SigBit an1 = module->AndGate(NEW_ID_SUFFIX(name), yn_i, one_i); - SigBit an2 = module->AndGate(NEW_ID_SUFFIX(name), ynm1_i, two_i); - SigBit or1 = module->OrGate(NEW_ID_SUFFIX(name), an1, an2); - return module->XorGate(NEW_ID_SUFFIX(name), s_i, or1); + SigBit an1 = module->AndGate(NEW_TWINE_SUFFIX(name), yn_i, one_i); + SigBit an2 = module->AndGate(NEW_TWINE_SUFFIX(name), ynm1_i, two_i); + SigBit or1 = module->OrGate(NEW_TWINE_SUFFIX(name), an1, an2); + return module->XorGate(NEW_TWINE_SUFFIX(name), s_i, or1); } // Booth unsigned radix4 decoder SigBit Bur4d_msb(std::string name, SigBit msb_i, SigBit two_i, SigBit s_i) { // ppij = (msb & two) ^ s; - SigBit an1 = module->AndGate(NEW_ID_SUFFIX(name), msb_i, two_i); - return module->XorGate(NEW_ID_SUFFIX(name), s_i, an1); + SigBit an1 = module->AndGate(NEW_TWINE_SUFFIX(name), msb_i, two_i); + return module->XorGate(NEW_TWINE_SUFFIX(name), s_i, an1); } // half adder, used in CPA void BuildHa(std::string name, SigBit a_i, SigBit b_i, SigBit &s_o, SigBit &c_o) { - s_o = module->XorGate(NEW_ID_SUFFIX(name), a_i, b_i); - c_o = module->AndGate(NEW_ID_SUFFIX(name), a_i, b_i); + s_o = module->XorGate(NEW_TWINE_SUFFIX(name), a_i, b_i); + c_o = module->AndGate(NEW_TWINE_SUFFIX(name), a_i, b_i); } // Booth unsigned radix 4 encoder void BuildBur4e(std::string name, SigBit y0_i, SigBit y1_i, SigBit y2_i, SigBit &one_o, SigBit &two_o, SigBit &s_o, SigBit &sb_o) { - one_o = module->XorGate(NEW_ID_SUFFIX(name), y0_i, y1_i); + one_o = module->XorGate(NEW_TWINE_SUFFIX(name), y0_i, y1_i); s_o = y2_i; - sb_o = module->NotGate(NEW_ID_SUFFIX(name), y2_i); - SigBit y1_xnor_y2 = module->XnorGate(NEW_ID_SUFFIX(name), y1_i, y2_i); - two_o = module->NorGate(NEW_ID_SUFFIX(name), y1_xnor_y2, one_o); + sb_o = module->NotGate(NEW_TWINE_SUFFIX(name), y2_i); + SigBit y1_xnor_y2 = module->XnorGate(NEW_TWINE_SUFFIX(name), y1_i, y2_i); + two_o = module->NorGate(NEW_TWINE_SUFFIX(name), y1_xnor_y2, one_o); } void BuildBr4e(std::string name, SigBit y2_m1_i, @@ -121,9 +121,9 @@ struct BoothPassWorker { SigBit y2_p1_i, SigBit &negi_o, SigBit &twoi_n_o, SigBit &onei_n_o, SigBit &cori_o) { - auto y2_p1_n = module->NotGate(NEW_ID_SUFFIX(name), y2_p1_i); - auto y2_n = module->NotGate(NEW_ID_SUFFIX(name), y2_i); - auto y2_m1_n = module->NotGate(NEW_ID_SUFFIX(name), y2_m1_i); + auto y2_p1_n = module->NotGate(NEW_TWINE_SUFFIX(name), y2_p1_i); + auto y2_n = module->NotGate(NEW_TWINE_SUFFIX(name), y2_i); + auto y2_m1_n = module->NotGate(NEW_TWINE_SUFFIX(name), y2_m1_i); negi_o = y2_p1_i; @@ -131,15 +131,15 @@ struct BoothPassWorker { // (y2_p1_n & y2_i & y2_m1_i) | // (y2_p1 & y2_n & y2_m1_n) // ) - twoi_n_o = module->NorGate(NEW_ID_SUFFIX(name), - module->AndGate(NEW_ID_SUFFIX(name), y2_p1_n, module->AndGate(NEW_ID_SUFFIX(name), y2_i, y2_m1_i)), - module->AndGate(NEW_ID_SUFFIX(name), y2_p1_i, module->AndGate(NEW_ID_SUFFIX(name), y2_n, y2_m1_n)) + twoi_n_o = module->NorGate(NEW_TWINE_SUFFIX(name), + module->AndGate(NEW_ID_SUFFIX(name), y2_p1_n, module->AndGate(NEW_TWINE_SUFFIX(name), y2_i, y2_m1_i)), + module->AndGate(NEW_ID_SUFFIX(name), y2_p1_i, module->AndGate(NEW_TWINE_SUFFIX(name), y2_n, y2_m1_n)) ); // onei_n = ~(y2_m1_i ^ y2_i); - onei_n_o = module->XnorGate(NEW_ID_SUFFIX(name), y2_m1_i, y2_i); + onei_n_o = module->XnorGate(NEW_TWINE_SUFFIX(name), y2_m1_i, y2_i); // cori = (y2_m1_n | y2_n) & y2_p1_i; - cori_o = module->AndGate(NEW_ID_SUFFIX(name), module->OrGate(NEW_ID_SUFFIX(name), y2_m1_n, y2_n), y2_p1_i); + cori_o = module->AndGate(NEW_ID_SUFFIX(name), module->OrGate(NEW_TWINE_SUFFIX(name), y2_m1_n, y2_n), y2_p1_i); } // @@ -151,10 +151,10 @@ struct BoothPassWorker { // nxj_in = xnor(xj,negi) // nxj_o = xnj_in, // ppij = ~( (nxj_m1_i | twoi_n_i) & (nxj_int | onei_n_i)); - nxj_o = module->XnorGate(NEW_ID_SUFFIX(name), xj_i, negi_i); - ppij_o = module->NandGate(NEW_ID_SUFFIX(name), - module->OrGate(NEW_ID_SUFFIX(name), nxj_m1_i, twoi_n_i), - module->OrGate(NEW_ID_SUFFIX(name), nxj_o, onei_n_i) + nxj_o = module->XnorGate(NEW_TWINE_SUFFIX(name), xj_i, negi_i); + ppij_o = module->NandGate(NEW_TWINE_SUFFIX(name), + module->OrGate(NEW_TWINE_SUFFIX(name), nxj_m1_i, twoi_n_i), + module->OrGate(NEW_TWINE_SUFFIX(name), nxj_o, onei_n_i) ); } @@ -178,14 +178,14 @@ struct BoothPassWorker { //correction propagation assign CORO = (~PP1 & ~PP0)? CORI : 1'b0; */ - nxj_o = module->XnorGate(NEW_ID_SUFFIX(name), x1_i, negi_i); - pp0_o = module->AndGate(NEW_ID_SUFFIX(name), x0_i, y0_i); - SigBit pp1_1_int = module->AndGate(NEW_ID_SUFFIX(name), x1_i, y0_i); - SigBit pp1_2_int = module->AndGate(NEW_ID_SUFFIX(name), x0_i, y1_i); - pp1_o = module->XorGate(NEW_ID_SUFFIX(name), pp1_1_int, pp1_2_int); + nxj_o = module->XnorGate(NEW_TWINE_SUFFIX(name), x1_i, negi_i); + pp0_o = module->AndGate(NEW_TWINE_SUFFIX(name), x0_i, y0_i); + SigBit pp1_1_int = module->AndGate(NEW_TWINE_SUFFIX(name), x1_i, y0_i); + SigBit pp1_2_int = module->AndGate(NEW_TWINE_SUFFIX(name), x0_i, y1_i); + pp1_o = module->XorGate(NEW_TWINE_SUFFIX(name), pp1_1_int, pp1_2_int); - SigBit pp1_nor_pp0 = module->NorGate(NEW_ID_SUFFIX(name), pp1_o, pp0_o); - cor_o = module->AndGate(NEW_ID_SUFFIX(name), pp1_nor_pp0, cori_i); + SigBit pp1_nor_pp0 = module->NorGate(NEW_TWINE_SUFFIX(name), pp1_o, pp0_o); + cor_o = module->AndGate(NEW_TWINE_SUFFIX(name), pp1_nor_pp0, cori_i); } void BuildBitwiseFa(Module *mod, std::string name, const SigSpec &sig_a, const SigSpec &sig_b, @@ -395,7 +395,7 @@ struct BoothPassWorker { if (mapped_cpa) BuildCPA(module, wtree_a, wtree_b, Z); else - module->addAdd(NEW_ID, wtree_a, wtree_b, Z); + module->addAdd(NEW_TWINE, wtree_a, wtree_b, Z); } /* @@ -431,11 +431,11 @@ struct BoothPassWorker { // append the sign bits if (is_signed) { - SigBit e = module->XorGate(NEW_ID, s_int[0], module->AndGate(NEW_ID, X.msb(), module->OrGate(NEW_ID, two_int[0], one_int[0]))); - ppij_vec.append({module->NotGate(NEW_ID, e), e, e}); + SigBit e = module->XorGate(NEW_ID, s_int[0], module->AndGate(NEW_ID, X.msb(), module->OrGate(NEW_TWINE, two_int[0], one_int[0]))); + ppij_vec.append({module->NotGate(NEW_TWINE, e), e, e}); } else { // append the sign bits - ppij_vec.append({module->NotGate(NEW_ID, s_int[0]), s_int[0], s_int[0]}); + ppij_vec.append({module->NotGate(NEW_TWINE, s_int[0]), s_int[0], s_int[0]}); } } @@ -465,7 +465,7 @@ struct BoothPassWorker { one_int, two_int, s_int)); } - ppij_vec.append(!is_signed ? sb_int[0] : module->XorGate(NEW_ID, sb_int, module->AndGate(NEW_ID, X.msb(), module->OrGate(NEW_ID, two_int, one_int)))); + ppij_vec.append(!is_signed ? sb_int[0] : module->XorGate(NEW_ID, sb_int, module->AndGate(NEW_ID, X.msb(), module->OrGate(NEW_TWINE, two_int, one_int)))); ppij_vec.append(State::S1); } @@ -692,7 +692,7 @@ struct BoothPassWorker { // Base Case: Bit 0 is sum 0 if (n == 0) { - module->addBufGate(NEW_ID_SUFFIX(stringf("base_buf_%d_%d", cpa_id, n)), s_vec[0], result[0]); + module->addBufGate(NEW_TWINE_SUFFIX(stringf("base_buf_%d_%d", cpa_id, n)), s_vec[0], result[0]); #ifdef DEBUG_CPA printf("CPA bit [%d] Cell %s IP 0 %s \n", n, buf->name.c_str(), s_vec[0]->name.c_str()); @@ -719,7 +719,7 @@ struct BoothPassWorker { else if (n == s_vec.size() - 1) { // Make the carry results.. Two extra bits after fa. SigBit carry_out = module->addWire(NEW_TWINE, 1); - module->addFa(NEW_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)), + module->addFa(NEW_TWINE_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)), /* A */ s_vec[n], /* B */ c_vec[n - 1], /* C */ carry, @@ -747,7 +747,7 @@ struct BoothPassWorker { // Step case else { SigBit carry_out = module->addWire(NEW_TWINE_SUFFIX(stringf("cpa_%d_carry_%d", cpa_id, n)), 1); - module->addFa(NEW_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)), + module->addFa(NEW_TWINE_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)), /* A */ s_vec[n], /* B */ c_vec[n - 1], /* C */ carry, @@ -788,7 +788,7 @@ struct BoothPassWorker { auto s_wire = module->addWire(NEW_TWINE_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1); auto c_wire = module->addWire(NEW_TWINE_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1); - auto csa = module->addFa(NEW_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)), + auto csa = module->addFa(NEW_TWINE_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)), /* A */ first_csa_ips[0], /* B */ first_csa_ips.size() > 1 ? first_csa_ips[1] : State::S0, /* C */ first_csa_ips.size() > 2 ? first_csa_ips[2] : State::S0, @@ -820,7 +820,7 @@ struct BoothPassWorker { auto c_wire = module->addWire(NEW_TWINE_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1); auto s_wire = module->addWire(NEW_TWINE_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1); - auto csa = module->addFa(NEW_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)), + auto csa = module->addFa(NEW_TWINE_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)), /* A */ s_result, /* B */ csa_ips[0], /* C */ csa_ips.size() > 1 ? csa_ips[1] : State::S0, @@ -1013,7 +1013,7 @@ struct BoothPassWorker { if (encoder_ix == 1) { // quadrant 1 optimization } else { - module->addNotGate(NEW_ID_SUFFIX(stringf("pre_dec_%d", encoder_ix)), + module->addNotGate(NEW_TWINE_SUFFIX(stringf("pre_dec_%d", encoder_ix)), negi_n_int[encoder_ix - 1], nxj[(encoder_ix - 1) * dec_count] ); @@ -1072,8 +1072,8 @@ struct BoothPassWorker { // full adder creation // base case: 1st row: Inputs from decoders // 1st row exception: two localized inverters due to sign extension structure - SigBit d08_inv = module->NotGate(NEW_ID_SUFFIX("bfa_0_exc_inv1"), PPij[(0 * dec_count) + dec_count - 1]); - SigBit d18_inv = module->NotGate(NEW_ID_SUFFIX("bfa_0_exc_inv2"), PPij[(1 * dec_count) + dec_count - 1]); + SigBit d08_inv = module->NotGate(NEW_TWINE_SUFFIX("bfa_0_exc_inv1"), PPij[(0 * dec_count) + dec_count - 1]); + SigBit d18_inv = module->NotGate(NEW_TWINE_SUFFIX("bfa_0_exc_inv2"), PPij[(1 * dec_count) + dec_count - 1]); BuildBitwiseFa(module, NEW_ID_SUFFIX("fa_row_0").str(), /* A */ {State::S0, d08_inv, PPij[(0 * dec_count) + x_sz], PPij.extract((0 * dec_count) + 2, x_sz - 1)}, /* B */ {State::S1, d18_inv, PPij.extract((1 * dec_count), x_sz)}, @@ -1087,7 +1087,7 @@ struct BoothPassWorker { // special because these are driven by a decoder and prior fa. for (fa_row_ix = 1; fa_row_ix < fa_row_count; fa_row_ix++) { // end two bits: sign extension - SigBit d_inv = module->NotGate(NEW_ID_SUFFIX(stringf("bfa_se_inv_%d_L", fa_row_ix)), + SigBit d_inv = module->NotGate(NEW_TWINE_SUFFIX(stringf("bfa_se_inv_%d_L", fa_row_ix)), PPij[((fa_row_ix + 1) * dec_count) + dec_count - 1]); BuildBitwiseFa(module, NEW_ID_SUFFIX(stringf("fa_row_%d", fa_row_ix)).str(), diff --git a/passes/techmap/bwmuxmap.cc b/passes/techmap/bwmuxmap.cc index 3bd794ed1..53ea04e4f 100644 --- a/passes/techmap/bwmuxmap.cc +++ b/passes/techmap/bwmuxmap.cc @@ -57,10 +57,10 @@ struct BwmuxmapPass : public Pass { auto &sig_b = cell->getPort(TW::B); auto &sig_s = cell->getPort(TW::S); - auto not_s = module->Not(NEW_ID, sig_s); - auto masked_b = module->And(NEW_ID, sig_s, sig_b); - auto masked_a = module->And(NEW_ID, not_s, sig_a); - module->addOr(NEW_ID, masked_a, masked_b, sig_y); + auto not_s = module->Not(NEW_TWINE, sig_s); + auto masked_b = module->And(NEW_TWINE, sig_s, sig_b); + auto masked_a = module->And(NEW_TWINE, not_s, sig_a); + module->addOr(NEW_TWINE, masked_a, masked_b, sig_y); module->remove(cell); } diff --git a/passes/techmap/clockgate.cc b/passes/techmap/clockgate.cc index af2d2afe8..9c81f658e 100644 --- a/passes/techmap/clockgate.cc +++ b/passes/techmap/clockgate.cc @@ -381,7 +381,7 @@ struct ClockgatePass : public Pass { icg->setPort(port, Const(0, 1)); // Fix CE polarity if needed if (!clk.pol_ce) { - SigBit ce_fixed_pol = module->NotGate(NEW_ID, clk.ce_bit); + SigBit ce_fixed_pol = module->NotGate(NEW_TWINE, clk.ce_bit); icg->setPort(matching_icg_desc->ce_pin, ce_fixed_pol); } } diff --git a/passes/techmap/demuxmap.cc b/passes/techmap/demuxmap.cc index f1a31b8e9..db62d1c8b 100644 --- a/passes/techmap/demuxmap.cc +++ b/passes/techmap/demuxmap.cc @@ -57,13 +57,13 @@ struct DemuxmapPass : public Pass { for (int i = 0; i < 1 << GetSize(sel); i++) { if (width == 1 && data == State::S1) { - RTLIL::Cell *eq_cell = module->addEq(NEW_ID, sel, Const(i, GetSize(sel)), out[i]); + RTLIL::Cell *eq_cell = module->addEq(NEW_TWINE, sel, Const(i, GetSize(sel)), out[i]); module->design->merge_src(eq_cell, cell); } else { Wire *eq = module->addWire(NEW_TWINE); - RTLIL::Cell *eq_cell = module->addEq(NEW_ID, sel, Const(i, GetSize(sel)), eq); + RTLIL::Cell *eq_cell = module->addEq(NEW_TWINE, sel, Const(i, GetSize(sel)), eq); module->design->merge_src(eq_cell, cell); - RTLIL::Cell *mux = module->addMux(NEW_ID, + RTLIL::Cell *mux = module->addMux(NEW_TWINE, Const(State::S0, width), data, eq, diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc index 90ac12a03..c39eda1c1 100644 --- a/passes/techmap/dfflegalize.cc +++ b/passes/techmap/dfflegalize.cc @@ -263,7 +263,7 @@ struct DffLegalizePass : public Pass { } void fail_ff(const FfData &ff, const char *reason) { - log_error("FF %s.%s (type %s) cannot be legalized: %s\n", ff.module->name.unescape(), ff.cell->name.unescape(), ff.cell->type.unescape(), reason); + log_error("FF %s.%s (type %s) cannot be legalized: %s\n", ff.module->name.unescape(), ff.cell->module->design->twines.str(cell->meta_->name), ff.cell->type.unescape(), reason); } bool try_flip(FfData &ff, int supported_mask) { @@ -329,9 +329,9 @@ struct DffLegalizePass : public Pass { ff_sel.is_fine = ff.is_fine; if (ff.is_fine) - ff.module->addMuxGate(NEW_ID, ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q); + ff.module->addMuxGate(NEW_TWINE, ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q); else - ff.module->addMux(NEW_ID, ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q); + ff.module->addMux(NEW_TWINE, ff_dff.sig_q, ff_adff.sig_q, ff_sel.sig_q, ff.sig_q); legalize_ff(ff_dff); legalize_ff(ff_adff); @@ -381,7 +381,7 @@ struct DffLegalizePass : public Pass { if (ff.has_ce && !supported_cells[FF_ADFFE]) ff.unmap_ce(); - log_warning("Emulating async set + reset with several FFs and a mux for %s.%s\n", ff.module->name.unescape(), ff.cell->name.unescape()); + log_warning("Emulating async set + reset with several FFs and a mux for %s.%s\n", ff.module->name.unescape(), ff.cell->module->design->twines.str(cell->meta_->name)); log_assert(ff.width == 1); ff.remove(); @@ -440,9 +440,9 @@ struct DffLegalizePass : public Pass { ff_sel.is_fine = ff.is_fine; if (!ff.is_fine) - ff.module->addMux(NEW_ID, ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q); + ff.module->addMux(NEW_TWINE, ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q); else - ff.module->addMuxGate(NEW_ID, ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q); + ff.module->addMuxGate(NEW_TWINE, ff_clr.sig_q, ff_set.sig_q, ff_sel.sig_q, ff.sig_q); legalize_ff(ff_clr); legalize_ff(ff_set); @@ -600,7 +600,7 @@ struct DffLegalizePass : public Pass { ff.unmap_ce(); if (ff.cell) - log_warning("Emulating mismatched async reset and init with several FFs and a mux for %s.%s\n", ff.module->name.unescape(), ff.cell->name.unescape()); + log_warning("Emulating mismatched async reset and init with several FFs and a mux for %s.%s\n", ff.module->name.unescape(), ff.cell->module->design->twines.str(cell->meta_->name)); emulate_split_init_arst(ff); return; } @@ -752,7 +752,7 @@ struct DffLegalizePass : public Pass { // The only hope left is breaking down to adlatch + dlatch + dlatch + mux. if (ff.cell) - log_warning("Emulating mismatched async reset and init with several latches and a mux for %s.%s\n", ff.module->name.unescape(), ff.cell->name.unescape()); + log_warning("Emulating mismatched async reset and init with several latches and a mux for %s.%s\n", ff.module->name.unescape(), ff.cell->module->design->twines.str(cell->meta_->name)); ff.remove(); emulate_split_init_arst(ff); @@ -843,9 +843,9 @@ struct DffLegalizePass : public Pass { ff.remove_init(); Wire *new_q = ff.module->addWire(NEW_TWINE); if (ff.is_fine) - ff.module->addNotGate(NEW_ID, new_q, ff.sig_q); + ff.module->addNotGate(NEW_TWINE, new_q, ff.sig_q); else - ff.module->addNot(NEW_ID, new_q, ff.sig_q); + ff.module->addNot(NEW_TWINE, new_q, ff.sig_q); ff.sig_q = new_q; if (ff.val_init == State::S0) ff.val_init = State::S1; @@ -938,9 +938,9 @@ struct DffLegalizePass : public Pass { } else if (sig == State::S1) { sig = State::S0; } else if (ff.is_fine) { - sig = ff.module->NotGate(NEW_ID, sig); + sig = ff.module->NotGate(NEW_TWINE, sig); } else { - sig = ff.module->Not(NEW_ID, sig); + sig = ff.module->Not(NEW_TWINE, sig); } pol = !pol; } diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 2fc3a3461..2b544f09f 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -543,12 +543,12 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) it->setPort(TW::Y, module->addWire(NEW_TWINE, GetSize(old_sig))); } } else { - module->addNotGate(NEW_ID, sig, old_sig); + module->addNotGate(NEW_TWINE, sig, old_sig); } } else if ('a' <= port.second && port.second <= 'z') { sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))]; - sig = module->NotGate(NEW_ID, sig); + sig = module->NotGate(NEW_TWINE, sig); } else if (port.second == '0' || port.second == '1') { sig = RTLIL::SigSpec(port.second == '0' ? 0 : 1, 1); diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index d920289d9..2d7295345 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -299,7 +299,7 @@ RTLIL::Cell *replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit: if (wire->port_id > 0) { for (int i = 0; i < wire->width; i++) sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair(wire->name, i)); - cell->setPort(wire->name, RTLIL::SigSpec(RTLIL::State::Sz, wire->width)); + cell->setPort(wire->meta_->name, RTLIL::SigSpec(RTLIL::State::Sz, wire->width)); } } @@ -674,7 +674,7 @@ struct ExtractPass : public Pass { } RTLIL::Cell *new_cell = replace(needle_map.at(result.needleGraphId), haystack_map.at(result.haystackGraphId), result); design->select(haystack_map.at(result.haystackGraphId), new_cell); - log(" new cell: %s\n", new_cell->name.unescape()); + log(" new cell: %s\n", new_cell->module->design->twines.str(cell->meta_->name)); } } } diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc index a19449727..173e411f6 100644 --- a/passes/techmap/extract_counter.cc +++ b/passes/techmap/extract_counter.cc @@ -640,16 +640,16 @@ void counter_worker( if(extract.rst_inverted) { auto realreset = cell->module->addWire(NEW_TWINE); - cell->module->addNot(NEW_ID, extract.rst, RTLIL::SigSpec(realreset)); - cell->setPort(ID(RST), realreset); + cell->module->addNot(NEW_TWINE, extract.rst, RTLIL::SigSpec(realreset)); + cell->setPort(TW::RST, realreset); } else - cell->setPort(ID(RST), extract.rst); + cell->setPort(TW::RST, extract.rst); } else { cell->setParam(ID(RESET_MODE), RTLIL::Const("RISING")); - cell->setPort(ID(RST), RTLIL::SigSpec(false)); + cell->setPort(TW::RST, RTLIL::SigSpec(false)); } //Hook up other stuff @@ -657,7 +657,7 @@ void counter_worker( cell->setParam(ID(COUNT_TO), RTLIL::Const(extract.count_value)); cell->setParam(ID::WIDTH, RTLIL::Const(extract.width)); cell->setPort(TW::CLK, extract.clk); - cell->setPort(ID(OUT), extract.outsig); + cell->setPort(TW::OUT, extract.outsig); //Hook up clock enable if(extract.has_ce) @@ -666,28 +666,28 @@ void counter_worker( if(extract.ce_inverted) { auto realce = cell->module->addWire(NEW_TWINE); - cell->module->addNot(NEW_ID, extract.ce, RTLIL::SigSpec(realce)); - cell->setPort(ID(CE), realce); + cell->module->addNot(NEW_TWINE, extract.ce, RTLIL::SigSpec(realce)); + cell->setPort(TW::CE, realce); } else - cell->setPort(ID(CE), extract.ce); + cell->setPort(TW::CE, extract.ce); } else { cell->setParam(ID(HAS_CE), RTLIL::Const(0)); - cell->setPort(ID(CE), RTLIL::Const(1)); + cell->setPort(TW::CE, RTLIL::Const(1)); } if(extract.count_is_up) { cell->setParam(ID(DIRECTION), RTLIL::Const("UP")); //XXX: What is this supposed to do? - cell->setPort(ID(UP), RTLIL::Const(1)); + cell->setPort(TW::UP, RTLIL::Const(1)); } else { cell->setParam(ID(DIRECTION), RTLIL::Const("DOWN")); - cell->setPort(ID(UP), RTLIL::Const(0)); + cell->setPort(TW::UP, RTLIL::Const(0)); } //Hook up hard-wired ports, default to no parallel output @@ -697,12 +697,12 @@ void counter_worker( //Hook up any parallel outputs for(auto load : extract.pouts) { - log(" Counter has parallel output to cell %s port %s\n", load.cell->name.unescape(), load.port.unescape()); + log(" Counter has parallel output to cell %s port %s\n", load.cell->module->design->twines.str(cell->meta_->name), load.port.unescape()); } if(extract.has_pout) { //Connect it to our parallel output - cell->setPort(ID(POUT), extract.poutsig); + cell->setPort(TW::POUT, extract.poutsig); cell->setParam(ID(HAS_POUT), RTLIL::Const(1)); } diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc index 181de6a2a..d6a41c33f 100644 --- a/passes/techmap/extract_fa.cc +++ b/passes/techmap/extract_fa.cc @@ -399,9 +399,9 @@ struct ExtractFaWorker log(" Created $fa cell %s.\n", cell); - cell->setPort(TW::A, f3i.inv_a ? module->NotGate(NEW_ID, A) : A); - cell->setPort(TW::B, f3i.inv_b ? module->NotGate(NEW_ID, B) : B); - cell->setPort(TW::C, f3i.inv_c ? module->NotGate(NEW_ID, C) : C); + cell->setPort(TW::A, f3i.inv_a ? module->NotGate(NEW_TWINE, A) : A); + cell->setPort(TW::B, f3i.inv_b ? module->NotGate(NEW_TWINE, B) : B); + cell->setPort(TW::C, f3i.inv_c ? module->NotGate(NEW_TWINE, C) : C); X = module->addWire(NEW_TWINE); Y = module->addWire(NEW_TWINE); @@ -414,18 +414,18 @@ struct ExtractFaWorker bool invert_y = f3i.inv_a ^ f3i.inv_b ^ f3i.inv_c; if (func3.at(key).count(xor3_func)) { - SigBit YY = invert_xy ^ invert_y ? module->NotGate(NEW_ID, Y) : Y; + SigBit YY = invert_xy ^ invert_y ? module->NotGate(NEW_TWINE, Y) : Y; for (auto bit : func3.at(key).at(xor3_func)) assign_new_driver(bit, YY); } if (func3.at(key).count(xnor3_func)) { - SigBit YY = invert_xy ^ invert_y ? Y : module->NotGate(NEW_ID, Y); + SigBit YY = invert_xy ^ invert_y ? Y : module->NotGate(NEW_TWINE, Y); for (auto bit : func3.at(key).at(xnor3_func)) assign_new_driver(bit, YY); } - SigBit XX = invert_xy != f3i.inv_y ? module->NotGate(NEW_ID, X) : X; + SigBit XX = invert_xy != f3i.inv_y ? module->NotGate(NEW_TWINE, X) : X; for (auto bit : func3.at(key).at(func)) assign_new_driver(bit, XX); @@ -506,8 +506,8 @@ struct ExtractFaWorker log(" Created $fa cell %s.\n", cell); - cell->setPort(TW::A, f2i.inv_a ? module->NotGate(NEW_ID, A) : A); - cell->setPort(TW::B, f2i.inv_b ? module->NotGate(NEW_ID, B) : B); + cell->setPort(TW::A, f2i.inv_a ? module->NotGate(NEW_TWINE, A) : A); + cell->setPort(TW::B, f2i.inv_b ? module->NotGate(NEW_TWINE, B) : B); cell->setPort(TW::C, State::S0); X = module->addWire(NEW_TWINE); @@ -518,18 +518,18 @@ struct ExtractFaWorker } if (func2.at(key).count(xor2_func)) { - SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? module->NotGate(NEW_ID, Y) : Y; + SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? module->NotGate(NEW_TWINE, Y) : Y; for (auto bit : func2.at(key).at(xor2_func)) assign_new_driver(bit, YY); } if (func2.at(key).count(xnor2_func)) { - SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? Y : module->NotGate(NEW_ID, Y); + SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? Y : module->NotGate(NEW_TWINE, Y); for (auto bit : func2.at(key).at(xnor2_func)) assign_new_driver(bit, YY); } - SigBit XX = invert_xy != f2i.inv_y ? module->NotGate(NEW_ID, X) : X; + SigBit XX = invert_xy != f2i.inv_y ? module->NotGate(NEW_TWINE, X) : X; for (auto bit : func2.at(key).at(func)) assign_new_driver(bit, XX); diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc index 3e196fc91..ca7226e76 100644 --- a/passes/techmap/extract_reduce.cc +++ b/passes/techmap/extract_reduce.cc @@ -270,11 +270,11 @@ struct ExtractReducePass : public Pass } if (head_cell->type == ID($_AND_)) { - module->addReduceAnd(NEW_ID, input, output); + module->addReduceAnd(NEW_TWINE, input, output); } else if (head_cell->type == ID($_OR_)) { - module->addReduceOr(NEW_ID, input, output); + module->addReduceOr(NEW_TWINE, input, output); } else if (head_cell->type == ID($_XOR_)) { - module->addReduceXor(NEW_ID, input, output); + module->addReduceXor(NEW_TWINE, input, output); } else { log_assert(false); } diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc index 3d2eb1fbe..a7c779a50 100644 --- a/passes/techmap/flowmap.cc +++ b/passes/techmap/flowmap.cc @@ -1411,7 +1411,7 @@ struct FlowmapWorker if ((int)input_nodes.size() < minlut) lut_a.append(RTLIL::Const(State::Sx, minlut - input_nodes.size())); - RTLIL::Cell *lut = module->addLut(NEW_ID, lut_a, lut_y, lut_table); + RTLIL::Cell *lut = module->addLut(NEW_TWINE, lut_a, lut_y, lut_table); mapped_nodes.insert(node); for (auto gate_node : lut_gates[node]) { diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 64b09f7e6..87db13eed 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -334,7 +334,7 @@ struct IopadmapPass : public Pass { RTLIL::escape_id(tinoutpad_celltype)); if (tinoutpad_neg_oe) - en_sig = module->NotGate(NEW_ID, en_sig); + en_sig = module->NotGate(NEW_TWINE, en_sig); cell->setPort(RTLIL::escape_id(tinoutpad_portname_oe), en_sig); cell->attributes[ID::keep] = RTLIL::Const(1); @@ -358,7 +358,7 @@ struct IopadmapPass : public Pass { RTLIL::escape_id(toutpad_celltype)); if (toutpad_neg_oe) - en_sig = module->NotGate(NEW_ID, en_sig); + en_sig = module->NotGate(NEW_TWINE, en_sig); cell->setPort(RTLIL::escape_id(toutpad_portname_oe), en_sig); cell->setPort(RTLIL::escape_id(toutpad_portname_i), data_sig); cell->attributes[ID::keep] = RTLIL::Const(1); diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc index 24c44028d..db36bce42 100644 --- a/passes/techmap/lut2mux.cc +++ b/passes/techmap/lut2mux.cc @@ -33,9 +33,9 @@ int lut2mux(Cell *cell, bool word_mode) if (GetSize(sig_a) == 1) { if (!word_mode) - cell->module->addMuxGate(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y); + cell->module->addMuxGate(NEW_TWINE, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y); else - cell->module->addMux(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y); + cell->module->addMux(NEW_TWINE, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y); } else { @@ -47,13 +47,13 @@ int lut2mux(Cell *cell, bool word_mode) Const lut1 = lut.extract(0, GetSize(lut)/2); Const lut2 = lut.extract(GetSize(lut)/2, GetSize(lut)/2); - count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y1, lut1), word_mode); - count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y2, lut2), word_mode); + count += lut2mux(cell->module->addLut(NEW_TWINE, sig_a_lo, sig_y1, lut1), word_mode); + count += lut2mux(cell->module->addLut(NEW_TWINE, sig_a_lo, sig_y2, lut2), word_mode); if (!word_mode) - cell->module->addMuxGate(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y); + cell->module->addMuxGate(NEW_TWINE, sig_y1, sig_y2, sig_a_hi, sig_y); else - cell->module->addMux(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y); + cell->module->addMux(NEW_TWINE, sig_y1, sig_y2, sig_a_hi, sig_y); } cell->module->remove(cell); diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc index 72b6a3232..825eb5e0e 100644 --- a/passes/techmap/maccmap.cc +++ b/passes/techmap/maccmap.cc @@ -52,7 +52,7 @@ struct MaccmapWorker a.extend_u0(width, is_signed); if (do_subtract) { - a = module->Not(NEW_ID, a); + a = module->Not(NEW_TWINE, a); add(State::S1, 0); } @@ -73,13 +73,13 @@ struct MaccmapWorker for (int i = 0; i < GetSize(b); i++) if (is_signed && i+1 == GetSize(b)) { - a = {module->Not(NEW_ID, a.extract(i, width-i)), RTLIL::SigSpec(0, i)}; - add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract); + a = {module->Not(NEW_TWINE, a.extract(i, width-i)), RTLIL::SigSpec(0, i)}; + add(module->And(NEW_TWINE, a, RTLIL::SigSpec(b[i], width)), false, do_subtract); add({b[i], RTLIL::SigSpec(0, i)}, false, do_subtract); } else { - add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract); + add(module->And(NEW_TWINE, a, RTLIL::SigSpec(b[i], width)), false, do_subtract); a = {a.extract(0, width-1), State::S0}; } } @@ -297,7 +297,7 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap) summand_t this_summand; if (GetSize(term.in_b)) { this_summand.first = module->addWire(NEW_TWINE, width); - module->addMul(NEW_ID, term.in_a, term.in_b, this_summand.first, term.is_signed); + module->addMul(NEW_TWINE, term.in_a, term.in_b, this_summand.first, term.is_signed); } else if (GetSize(term.in_a) == 1 && GetSize(term.in_b) == 0 && !term.is_signed && !term.do_subtract) { // Mimic old 'bit_terms' treatment in case it's relevant for performance, // i.e. defer single-bit summands to be the last ones @@ -305,7 +305,7 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap) continue; } else if (GetSize(term.in_a) != width) { this_summand.first = module->addWire(NEW_TWINE, width); - module->addPos(NEW_ID, term.in_a, this_summand.first, term.is_signed); + module->addPos(NEW_TWINE, term.in_a, this_summand.first, term.is_signed); } else { this_summand.first = term.in_a; } @@ -328,11 +328,11 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap) this_summand.first = module->addWire(NEW_TWINE, width); this_summand.second = summands[i].second && summands[i+1].second; if (summands[i].second == summands[i+1].second) - module->addAdd(NEW_ID, summands[i].first, summands[i+1].first, this_summand.first); + module->addAdd(NEW_TWINE, summands[i].first, summands[i+1].first, this_summand.first); else if (summands[i].second) - module->addSub(NEW_ID, summands[i+1].first, summands[i].first, this_summand.first); + module->addSub(NEW_TWINE, summands[i+1].first, summands[i].first, this_summand.first); else if (summands[i+1].second) - module->addSub(NEW_ID, summands[i].first, summands[i+1].first, this_summand.first); + module->addSub(NEW_TWINE, summands[i].first, summands[i+1].first, this_summand.first); else log_abort(); new_summands.push_back(this_summand); @@ -343,7 +343,7 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap) } if (summands.front().second) - module->addNeg(NEW_ID, summands.front().first, cell->getPort(TW::Y)); + module->addNeg(NEW_TWINE, summands.front().first, cell->getPort(TW::Y)); else module->connect(cell->getPort(TW::Y), summands.front().first); } diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc index 04ff966f7..5a43cfa95 100644 --- a/passes/techmap/muxcover.cc +++ b/passes/techmap/muxcover.cc @@ -215,11 +215,11 @@ struct MuxcoverWorker implement_decode_mux(std::get<1>(key)); if (std::get<0>(key) == State::Sx) { - module->addBufGate(NEW_ID, std::get<1>(key), ctrl_bit); + module->addBufGate(NEW_TWINE, std::get<1>(key), ctrl_bit); } else if (std::get<1>(key) == State::Sx) { - module->addBufGate(NEW_ID, std::get<0>(key), ctrl_bit); + module->addBufGate(NEW_TWINE, std::get<0>(key), ctrl_bit); } else { - module->addMuxGate(NEW_ID, std::get<0>(key), std::get<1>(key), std::get<2>(key), ctrl_bit); + module->addMuxGate(NEW_TWINE, std::get<0>(key), std::get<1>(key), std::get<2>(key), ctrl_bit); decode_mux_counter++; } std::get<2>(entry) = true; diff --git a/passes/techmap/pmuxtree.cc b/passes/techmap/pmuxtree.cc index d916c8608..06e3b40be 100644 --- a/passes/techmap/pmuxtree.cc +++ b/passes/techmap/pmuxtree.cc @@ -32,9 +32,9 @@ static SigSpec or_generator(Module *module, const SigSpec &sig) case 1: return sig; case 2: - return module->Or(NEW_ID, sig[0], sig[1]); + return module->Or(NEW_TWINE, sig[0], sig[1]); default: - return module->ReduceOr(NEW_ID, sig); + return module->ReduceOr(NEW_TWINE, sig); } } @@ -62,7 +62,7 @@ static SigSpec recursive_mux_generator(Module *module, const SigSpec &sig_data, left_or = or_generator(module, left_or); sig_or.append(left_or); - return module->Mux(NEW_ID, right_result, left_result, left_or); + return module->Mux(NEW_TWINE, right_result, left_result, left_or); } struct PmuxtreePass : public Pass { @@ -97,8 +97,8 @@ struct PmuxtreePass : public Pass { if (!cell->getPort(TW::A).is_fully_undef()) { sig_data.append(cell->getPort(TW::A)); - SigSpec sig_sel_or = module->ReduceOr(NEW_ID, sig_sel); - sig_sel.append(module->Not(NEW_ID, sig_sel_or)); + SigSpec sig_sel_or = module->ReduceOr(NEW_TWINE, sig_sel); + sig_sel.append(module->Not(NEW_TWINE, sig_sel_or)); } SigSpec result, result_or; diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 3c7e78e4d..d9d3973f0 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -76,9 +76,9 @@ struct ShregmapTechGreenpak4 : ShregmapTech auto C = cell->getPort(TW::C); auto newcell = cell->module->addCell(NEW_TWINE, ID(GP_SHREG)); - newcell->setPort(ID(nRST), State::S1); + newcell->setPort(TW::nRST, State::S1); newcell->setPort(TW::CLK, C); - newcell->setPort(ID(IN), D); + newcell->setPort(TW::IN, D); int i = 0; for (auto tap : taps) { diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 2837e0989..1474330b1 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -266,19 +266,19 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell) bool is_ne = cell->type.in(ID($ne), ID($nex)); RTLIL::SigSpec xor_out = module->addWire(NEW_TWINE, max(GetSize(sig_a), GetSize(sig_b))); - RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed); + RTLIL::Cell *xor_cell = module->addXor(NEW_TWINE, sig_a, sig_b, xor_out, is_signed); transfer_src(xor_cell, cell); simplemap_bitop(module, xor_cell); module->remove(xor_cell); RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_TWINE); - RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out); + RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_TWINE, xor_out, reduce_out); transfer_src(reduce_cell, cell); simplemap_reduce(module, reduce_cell); module->remove(reduce_cell); if (!is_ne) { - RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y); + RTLIL::Cell *not_cell = module->addLogicNot(NEW_TWINE, reduce_out, sig_y); transfer_src(not_cell, cell); simplemap_lognot(module, not_cell); module->remove(not_cell); @@ -403,10 +403,10 @@ void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell) } } - products.append(GetSize(in) > 0 ? module->Eq(NEW_ID, in, pat) : State::S1); + products.append(GetSize(in) > 0 ? module->Eq(NEW_TWINE, in, pat) : State::S1); } - module->connect(cell->getPort(TW::Y), module->ReduceOr(NEW_ID, products)); + module->connect(cell->getPort(TW::Y), module->ReduceOr(NEW_TWINE, products)); } void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell) diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index e77ee3374..693064357 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -625,7 +625,7 @@ struct TechmapWorker if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0) parameters.emplace(ID::_TECHMAP_CELLTYPE_, cell->type.unescape()); if (tpl->avail_parameters.count(ID::_TECHMAP_CELLNAME_) != 0) - parameters.emplace(ID::_TECHMAP_CELLNAME_, cell->name.unescape()); + parameters.emplace(ID::_TECHMAP_CELLNAME_, cell->module->design->twines.str(cell->meta_->name)); for (auto &conn : cell->connections()) { if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", conn.first.unescape())) != 0) { diff --git a/passes/techmap/tribuf.cc b/passes/techmap/tribuf.cc index 3810d0bfc..1845df38e 100644 --- a/passes/techmap/tribuf.cc +++ b/passes/techmap/tribuf.cc @@ -93,7 +93,7 @@ struct TribufWorker { } if (is_all_z(cell->getPort(TW::B))) { - cell->setPort(en_port, module->Not(NEW_ID, cell->getPort(TW::S))); + cell->setPort(en_port, module->Not(NEW_TWINE, cell->getPort(TW::S))); cell->unsetPort(TW::B); cell->unsetPort(TW::S); cell->type = tri_type; @@ -138,12 +138,12 @@ struct TribufWorker { auto cell_s = cell->type == ID($tribuf) ? cell->getPort(TW::EN) : cell->getPort(TW::E); - auto other_s = module->ReduceOr(NEW_ID, others_s); + auto other_s = module->ReduceOr(NEW_TWINE, others_s); - auto conflict = module->And(NEW_ID, cell_s, other_s); + auto conflict = module->And(NEW_TWINE, cell_s, other_s); - std::string name = stringf("$tribuf_conflict$%s", cell->name.unescape()); - auto assert_cell = module->addAssert(name, module->Not(NEW_ID, conflict), SigSpec(true)); + std::string name = stringf("$tribuf_conflict$%s", cell->module->design->twines.str(cell->meta_->name)); + auto assert_cell = module->addAssert(name, module->Not(NEW_TWINE, conflict), SigSpec(true)); assert_cell->adopt_src_from(cell); assert_cell->set_bool_attribute(ID::keep); @@ -162,12 +162,12 @@ struct TribufWorker { module->remove(cell); } - SigSpec muxout = GetSize(pmux_s) > 1 ? module->Pmux(NEW_ID, SigSpec(State::Sx, GetSize(it.first)), pmux_b, pmux_s) : pmux_b; + SigSpec muxout = GetSize(pmux_s) > 1 ? module->Pmux(NEW_TWINE, SigSpec(State::Sx, GetSize(it.first)), pmux_b, pmux_s) : pmux_b; if (no_tribuf) module->connect(it.first, muxout); else { - module->addTribuf(NEW_ID, muxout, module->ReduceOr(NEW_ID, pmux_s), it.first); + module->addTribuf(NEW_TWINE, muxout, module->ReduceOr(NEW_TWINE, pmux_s), it.first); module->design->scratchpad_set_bool("tribuf.added_something", true); } } diff --git a/passes/tests/test_abcloop.cc b/passes/tests/test_abcloop.cc index ed54ce164..e321a72b9 100644 --- a/passes/tests/test_abcloop.cc +++ b/passes/tests/test_abcloop.cc @@ -55,7 +55,7 @@ static void test_abcloop() while (1) { - module = design->addModule(ID(UUT)); + module = design->addModule(design->twines.add(Twine{ID(UUT).str()})); create_cycles++; in_sig = {}; @@ -64,21 +64,21 @@ static void test_abcloop() std::vector wires; for (int i = 0; i < 4; i++) { - RTLIL::Wire *w = module->addWire(stringf("\\i%d", i)); + RTLIL::Wire *w = module->addWire(Twine{stringf("\\i%d", i)}); w->port_input = true; wires.push_back(w); in_sig.append(w); } for (int i = 0; i < 4; i++) { - RTLIL::Wire *w = module->addWire(stringf("\\o%d", i)); + RTLIL::Wire *w = module->addWire(Twine{stringf("\\o%d", i)}); w->port_output = true; wires.push_back(w); out_sig.append(w); } for (int i = 0; i < 16; i++) { - RTLIL::Wire *w = module->addWire(stringf("\\t%d", i)); + RTLIL::Wire *w = module->addWire(Twine{stringf("\\t%d", i)}); wires.push_back(w); } @@ -87,40 +87,40 @@ static void test_abcloop() switch (xorshift32(12)) { case 0: - module->addNotGate(w->name.str() + "g", getw(wires, w), w); + module->addNotGate(Twine{w->name.str() + "g"}, getw(wires, w), w); break; case 1: - module->addAndGate(w->name.str() + "g", getw(wires, w), getw(wires, w), w); + module->addAndGate(Twine{w->name.str() + "g"}, getw(wires, w), getw(wires, w), w); break; case 2: - module->addNandGate(w->name.str() + "g", getw(wires, w), getw(wires, w), w); + module->addNandGate(Twine{w->name.str() + "g"}, getw(wires, w), getw(wires, w), w); break; case 3: - module->addOrGate(w->name.str() + "g", getw(wires, w), getw(wires, w), w); + module->addOrGate(Twine{w->name.str() + "g"}, getw(wires, w), getw(wires, w), w); break; case 4: - module->addNorGate(w->name.str() + "g", getw(wires, w), getw(wires, w), w); + module->addNorGate(Twine{w->name.str() + "g"}, getw(wires, w), getw(wires, w), w); break; case 5: - module->addXorGate(w->name.str() + "g", getw(wires, w), getw(wires, w), w); + module->addXorGate(Twine{w->name.str() + "g"}, getw(wires, w), getw(wires, w), w); break; case 6: - module->addXnorGate(w->name.str() + "g", getw(wires, w), getw(wires, w), w); + module->addXnorGate(Twine{w->name.str() + "g"}, getw(wires, w), getw(wires, w), w); break; case 7: - module->addMuxGate(w->name.str() + "g", getw(wires, w), getw(wires, w), getw(wires, w), w); + module->addMuxGate(Twine{w->name.str() + "g"}, getw(wires, w), getw(wires, w), getw(wires, w), w); break; case 8: - module->addAoi3Gate(w->name.str() + "g", getw(wires, w), getw(wires, w), getw(wires, w), w); + module->addAoi3Gate(Twine{w->name.str() + "g"}, getw(wires, w), getw(wires, w), getw(wires, w), w); break; case 9: - module->addOai3Gate(w->name.str() + "g", getw(wires, w), getw(wires, w), getw(wires, w), w); + module->addOai3Gate(Twine{w->name.str() + "g"}, getw(wires, w), getw(wires, w), getw(wires, w), w); break; case 10: - module->addAoi4Gate(w->name.str() + "g", getw(wires, w), getw(wires, w), getw(wires, w), getw(wires, w), w); + module->addAoi4Gate(Twine{w->name.str() + "g"}, getw(wires, w), getw(wires, w), getw(wires, w), getw(wires, w), w); break; case 11: - module->addOai4Gate(w->name.str() + "g", getw(wires, w), getw(wires, w), getw(wires, w), getw(wires, w), w); + module->addOai4Gate(Twine{w->name.str() + "g"}, getw(wires, w), getw(wires, w), getw(wires, w), getw(wires, w), w); break; } diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc index 52cb8e28c..fb171c765 100644 --- a/passes/tests/test_autotb.cc +++ b/passes/tests/test_autotb.cc @@ -109,12 +109,12 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s continue; int count_ports = 0; - log("Generating test bench for module `%s'.\n", mod->name); + log("Generating test bench for module `%s'.\n", design->twines.str(mod->meta_->name)); for (auto wire : mod->wires()) { if (wire->port_output) { count_ports++; - signal_out[idy("sig", mod->name.str(), wire->name.str())] = wire->width; - f << stringf("wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str())); + signal_out[idy("sig", design->twines.str(mod->meta_->name), wire->name.str())] = wire->width; + f << stringf("wire [%d:0] %s;\n", wire->width-1, idy("sig", design->twines.str(mod->meta_->name), wire->name.str())); } else if (wire->port_input) { count_ports++; bool is_clksignal = wire->get_bool_attribute(ID::gentb_clock); @@ -128,24 +128,24 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s is_clksignal = true; } if (is_clksignal && wire->attributes.count(ID::gentb_constant) == 0) { - signal_clk[idy("sig", mod->name.str(), wire->name.str())] = wire->width; + signal_clk[idy("sig", design->twines.str(mod->meta_->name), wire->name.str())] = wire->width; } else { - signal_in[idy("sig", mod->name.str(), wire->name.str())] = wire->width; + signal_in[idy("sig", design->twines.str(mod->meta_->name), wire->name.str())] = wire->width; if (wire->attributes.count(ID::gentb_constant) != 0) - signal_const[idy("sig", mod->name.str(), wire->name.str())] = wire->attributes[ID::gentb_constant].as_string(); + signal_const[idy("sig", design->twines.str(mod->meta_->name), wire->name.str())] = wire->attributes[ID::gentb_constant].as_string(); } - f << stringf("reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str())); + f << stringf("reg [%d:0] %s;\n", wire->width-1, idy("sig", design->twines.str(mod->meta_->name), wire->name.str())); } } - f << stringf("%s %s(\n", id(mod->name.str()), idy("uut", mod->name.str())); + f << stringf("%s %s(\n", id(design->twines.str(mod->meta_->name)), idy("uut", design->twines.str(mod->meta_->name))); for (auto wire : mod->wires()) { if (wire->port_output || wire->port_input) f << stringf("\t.%s(%s)%s\n", id(wire->name.str()), - idy("sig", mod->name.str(), wire->name.str()).c_str(), --count_ports ? "," : ""); + idy("sig", design->twines.str(mod->meta_->name), wire->name.str()).c_str(), --count_ports ? "," : ""); } f << stringf(");\n\n"); - f << stringf("task %s;\n", idy(mod->name.str(), "reset")); + f << stringf("task %s;\n", idy(design->twines.str(mod->meta_->name), "reset")); f << stringf("begin\n"); int delay_counter = 0; for (auto it = signal_in.begin(); it != signal_in.end(); ++it) @@ -175,7 +175,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s f << stringf("end\n"); f << stringf("endtask\n\n"); - f << stringf("task %s;\n", idy(mod->name.str(), "update_data")); + f << stringf("task %s;\n", idy(design->twines.str(mod->meta_->name), "update_data")); f << stringf("begin\n"); delay_counter = 0; for (auto it = signal_in.begin(); it != signal_in.end(); it++) { @@ -188,7 +188,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s f << stringf("end\n"); f << stringf("endtask\n\n"); - f << stringf("task %s;\n", idy(mod->name.str(), "update_clock")); + f << stringf("task %s;\n", idy(design->twines.str(mod->meta_->name), "update_clock")); f << stringf("begin\n"); if (signal_clk.size()) { f << stringf("\txorshift128;\n"); @@ -210,7 +210,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s std::vector header1; std::string header2 = ""; - f << stringf("task %s;\n", idy(mod->name.str(), "print_status")); + f << stringf("task %s;\n", idy(design->twines.str(mod->meta_->name), "print_status")); f << stringf("begin\n"); f << stringf("\t$fdisplay(file, \"#OUT# %%b %%b %%b %%t %%d\", {"); if (signal_in.size()) @@ -281,7 +281,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s f << stringf("end\n"); f << stringf("endtask\n\n"); - f << stringf("task %s;\n", idy(mod->name.str(), "print_header")); + f << stringf("task %s;\n", idy(design->twines.str(mod->meta_->name), "print_header")); f << stringf("begin\n"); f << stringf("\t$fdisplay(file, \"#OUT#\");\n"); for (auto &hdr : header1) @@ -291,15 +291,15 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s f << stringf("end\n"); f << stringf("endtask\n\n"); - f << stringf("task %s;\n", idy(mod->name.str(), "test")); + f << stringf("task %s;\n", idy(design->twines.str(mod->meta_->name), "test")); f << stringf("begin\n"); - f << stringf("\t$fdisplay(file, \"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name.str())); - f << stringf("\t%s;\n", idy(mod->name.str(), "reset")); + f << stringf("\t$fdisplay(file, \"#OUT#\\n#OUT# ==== %s ====\");\n", idy(design->twines.str(mod->meta_->name))); + f << stringf("\t%s;\n", idy(design->twines.str(mod->meta_->name), "reset")); f << stringf("\tfor (i=0; i<%d; i=i+1) begin\n", num_iter); - f << stringf("\t\tif (i %% 20 == 0) %s;\n", idy(mod->name.str(), "print_header")); - f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "update_data")); - f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "update_clock")); - f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "print_status")); + f << stringf("\t\tif (i %% 20 == 0) %s;\n", idy(design->twines.str(mod->meta_->name), "print_header")); + f << stringf("\t\t#100; %s;\n", idy(design->twines.str(mod->meta_->name), "update_data")); + f << stringf("\t\t#100; %s;\n", idy(design->twines.str(mod->meta_->name), "update_clock")); + f << stringf("\t\t#100; %s;\n", idy(design->twines.str(mod->meta_->name), "print_status")); f << stringf("\tend\n"); f << stringf("end\n"); f << stringf("endtask\n\n"); @@ -317,7 +317,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s f << stringf("\tend\n"); for (auto module : design->modules()) if (!module->get_bool_attribute(ID::gentb_skip)) - f << stringf("\t%s;\n", idy(module->name.str(), "test")); + f << stringf("\t%s;\n", idy(design->twines.str(module->meta_->name), "test")); f << stringf("\t$fclose(file);\n"); f << stringf("\t$finish;\n"); f << stringf("end\n\n"); diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 1182f4fee..9133462ad 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -41,8 +41,8 @@ static uint32_t xorshift32(uint32_t limit) { static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, std::string cell_type_flags, bool constmode, bool muxdiv) { - RTLIL::Module *module = design->addModule(ID(gold)); - RTLIL::Cell *cell = module->addCell(ID(UUT), cell_type); + RTLIL::Module *module = design->addModule(design->twines.add(Twine{ID(gold).str()})); + RTLIL::Cell *cell = module->addCell(design->twines.add(Twine{ID(UUT).str()}), cell_type); RTLIL::Wire *wire; if (cell_type.in(ID($mux), ID($pmux))) @@ -50,22 +50,22 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce int width = 1 + xorshift32(8 * bloat_factor); int swidth = cell_type == ID($mux) ? 1 : 1 + xorshift32(8); - wire = module->addWire(ID::A); + wire = module->addWire(design->twines.add(Twine{ID::A.str()})); wire->width = width; wire->port_input = true; cell->setPort(TW::A, wire); - wire = module->addWire(ID::B); + wire = module->addWire(design->twines.add(Twine{ID::B.str()})); wire->width = width * swidth; wire->port_input = true; cell->setPort(TW::B, wire); - wire = module->addWire(ID::S); + wire = module->addWire(design->twines.add(Twine{ID::S.str()})); wire->width = swidth; wire->port_input = true; cell->setPort(TW::S, wire); - wire = module->addWire(ID::Y); + wire = module->addWire(design->twines.add(Twine{ID::Y.str()})); wire->width = width; wire->port_output = true; cell->setPort(TW::Y, wire); @@ -73,22 +73,22 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce if (cell_type.in(ID($_MUX_), ID($_NMUX_))) { - wire = module->addWire(ID::A); + wire = module->addWire(design->twines.add(Twine{ID::A.str()})); wire->width = 1; wire->port_input = true; cell->setPort(TW::A, wire); - wire = module->addWire(ID::B); + wire = module->addWire(design->twines.add(Twine{ID::B.str()})); wire->width = 1; wire->port_input = true; cell->setPort(TW::B, wire); - wire = module->addWire(ID::S); + wire = module->addWire(design->twines.add(Twine{ID::S.str()})); wire->width = 1; wire->port_input = true; cell->setPort(TW::S, wire); - wire = module->addWire(ID::Y); + wire = module->addWire(design->twines.add(Twine{ID::Y.str()})); wire->width = 1; wire->port_output = true; cell->setPort(TW::Y, wire); @@ -99,17 +99,17 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce int width = 1 + xorshift32(8 * bloat_factor); int swidth = 1 + xorshift32(4 * bloat_factor); - wire = module->addWire(ID::A); + wire = module->addWire(design->twines.add(Twine{ID::A.str()})); wire->width = width << swidth; wire->port_input = true; cell->setPort(TW::A, wire); - wire = module->addWire(ID::S); + wire = module->addWire(design->twines.add(Twine{ID::S.str()})); wire->width = swidth; wire->port_input = true; cell->setPort(TW::S, wire); - wire = module->addWire(ID::Y); + wire = module->addWire(design->twines.add(Twine{ID::Y.str()})); wire->width = width; wire->port_output = true; cell->setPort(TW::Y, wire); @@ -120,17 +120,17 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce int width = 1 + xorshift32(8 * bloat_factor); int swidth = 1 + xorshift32(6 * bloat_factor); - wire = module->addWire(ID::A); + wire = module->addWire(design->twines.add(Twine{ID::A.str()})); wire->width = width; wire->port_input = true; cell->setPort(TW::A, wire); - wire = module->addWire(ID::S); + wire = module->addWire(design->twines.add(Twine{ID::S.str()})); wire->width = swidth; wire->port_input = true; cell->setPort(TW::S, wire); - wire = module->addWire(ID::Y); + wire = module->addWire(design->twines.add(Twine{ID::Y.str()})); wire->width = width << swidth; wire->port_output = true; cell->setPort(TW::Y, wire); @@ -140,27 +140,27 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce { int width = 1 + xorshift32(8 * bloat_factor); - wire = module->addWire(ID::A); + wire = module->addWire(design->twines.add(Twine{ID::A.str()})); wire->width = width; wire->port_input = true; cell->setPort(TW::A, wire); - wire = module->addWire(ID::B); + wire = module->addWire(design->twines.add(Twine{ID::B.str()})); wire->width = width; wire->port_input = true; cell->setPort(TW::B, wire); - wire = module->addWire(ID::C); + wire = module->addWire(design->twines.add(Twine{ID::C.str()})); wire->width = width; wire->port_input = true; cell->setPort(TW::C, wire); - wire = module->addWire(ID::X); + wire = module->addWire(design->twines.add(Twine{ID::X.str()})); wire->width = width; wire->port_output = true; cell->setPort(TW::X, wire); - wire = module->addWire(ID::Y); + wire = module->addWire(design->twines.add(Twine{ID::Y.str()})); wire->width = width; wire->port_output = true; cell->setPort(TW::Y, wire); @@ -170,21 +170,21 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce { int width = 1 + xorshift32(8 * bloat_factor); - wire = module->addWire(ID::P); + wire = module->addWire(design->twines.add(Twine{ID::P.str()})); wire->width = width; wire->port_input = true; cell->setPort(TW::P, wire); - wire = module->addWire(ID::G); + wire = module->addWire(design->twines.add(Twine{ID::G.str()})); wire->width = width; wire->port_input = true; cell->setPort(TW::G, wire); - wire = module->addWire(ID::CI); + wire = module->addWire(design->twines.add(Twine{ID::CI.str()})); wire->port_input = true; cell->setPort(TW::CI, wire); - wire = module->addWire(ID::CO); + wire = module->addWire(design->twines.add(Twine{ID::CO.str()})); wire->width = width; wire->port_output = true; cell->setPort(TW::CO, wire); @@ -197,7 +197,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce int depth = 1 + xorshift32(6); int mulbits_a = 0, mulbits_b = 0; - RTLIL::Wire *wire_a = module->addWire(ID::A); + RTLIL::Wire *wire_a = module->addWire(design->twines.add(Twine{ID::A.str()})); wire_a->width = 0; wire_a->port_input = true; @@ -228,7 +228,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce // Macc::to_cell sets the input ports macc.to_cell(cell); - wire = module->addWire(ID::Y); + wire = module->addWire(design->twines.add(Twine{ID::Y.str()})); wire->width = width; wire->port_output = true; cell->setPort(TW::Y, wire); @@ -238,12 +238,12 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce { int width = 1 + xorshift32(6 * bloat_factor); - wire = module->addWire(ID::A); + wire = module->addWire(design->twines.add(Twine{ID::A.str()})); wire->width = width; wire->port_input = true; cell->setPort(TW::A, wire); - wire = module->addWire(ID::Y); + wire = module->addWire(design->twines.add(Twine{ID::Y.str()})); wire->port_output = true; cell->setPort(TW::Y, wire); @@ -259,12 +259,12 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce int width = 1 + xorshift32(8 * bloat_factor); int depth = 1 + xorshift32(8 * bloat_factor); - wire = module->addWire(ID::A); + wire = module->addWire(design->twines.add(Twine{ID::A.str()})); wire->width = width; wire->port_input = true; cell->setPort(TW::A, wire); - wire = module->addWire(ID::Y); + wire = module->addWire(design->twines.add(Twine{ID::Y.str()})); wire->port_output = true; cell->setPort(TW::Y, wire); @@ -290,7 +290,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce } if (cell_type_flags.find('A') != std::string::npos) { - wire = module->addWire(ID::A); + wire = module->addWire(design->twines.add(Twine{ID::A.str()})); if (cell_type_flags.find('b') != std::string::npos) wire->width = 1; else @@ -300,7 +300,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce } if (cell_type_flags.find('B') != std::string::npos) { - wire = module->addWire(ID::B); + wire = module->addWire(design->twines.add(Twine{ID::B.str()})); if (cell_type_flags.find('b') != std::string::npos) wire->width = 1; else if (cell_type_flags.find('h') != std::string::npos) @@ -312,7 +312,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce } if (cell_type_flags.find('C') != std::string::npos) { - wire = module->addWire(ID::C); + wire = module->addWire(design->twines.add(Twine{ID::C.str()})); if (cell_type_flags.find('b') != std::string::npos) wire->width = 1; else @@ -322,7 +322,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce } if (cell_type_flags.find('D') != std::string::npos) { - wire = module->addWire(ID::D); + wire = module->addWire(design->twines.add(Twine{ID::D.str()})); if (cell_type_flags.find('b') != std::string::npos) wire->width = 1; else @@ -346,7 +346,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce } if (cell_type_flags.find('Y') != std::string::npos) { - wire = module->addWire(ID::Y); + wire = module->addWire(design->twines.add(Twine{ID::Y.str()})); if (cell_type_flags.find('b') != std::string::npos) wire->width = 1; else @@ -364,28 +364,28 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce } if (muxdiv && cell_type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) { - auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort(TW::B)); + auto b_not_zero = module->ReduceBool(NEW_TWINE, cell->getPort(TW::B)); auto div_out = module->addWire(NEW_TWINE, GetSize(cell->getPort(TW::Y))); - module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort(TW::Y)); + module->addMux(NEW_TWINE, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort(TW::Y)); cell->setPort(TW::Y, div_out); } if (cell_type == ID($alu)) { - wire = module->addWire(ID::CI); + wire = module->addWire(design->twines.add(Twine{ID::CI.str()})); wire->port_input = true; cell->setPort(TW::CI, wire); - wire = module->addWire(ID::BI); + wire = module->addWire(design->twines.add(Twine{ID::BI.str()})); wire->port_input = true; cell->setPort(TW::BI, wire); - wire = module->addWire(ID::X); + wire = module->addWire(design->twines.add(Twine{ID::X.str()})); wire->width = GetSize(cell->getPort(TW::Y)); wire->port_output = true; cell->setPort(TW::X, wire); - wire = module->addWire(ID::CO); + wire = module->addWire(design->twines.add(Twine{ID::CO.str()})); wire->width = GetSize(cell->getPort(TW::Y)); wire->port_output = true; cell->setPort(TW::CO, wire); @@ -397,7 +397,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce int y_size = 1; if (a_size > 1) y_size += (xorshift32(8 * bloat_factor) % (a_size - 1)); - wire = module->addWire(ID::Y); + wire = module->addWire(design->twines.add(Twine{ID::Y.str()})); wire->width = y_size; wire->port_output = true; cell->setPort(TW::Y, wire); @@ -409,7 +409,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce if (cell_type == ID($concat)) { - wire = module->addWire(ID::Y); + wire = module->addWire(design->twines.add(Twine{ID::Y.str()})); wire->width = GetSize(cell->getPort(TW::A)) + GetSize(cell->getPort(TW::B)); wire->port_output = true; cell->setPort(TW::Y, wire); @@ -417,7 +417,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce if (cell_type == ID($buf)) { - wire = module->addWire(ID::Y); + wire = module->addWire(design->twines.add(Twine{ID::Y.str()})); wire->width = GetSize(cell->getPort(TW::A)); wire->port_output = true; cell->setPort(TW::Y, wire); @@ -426,18 +426,18 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce if (cell_type.in(ID($bwmux), ID($bweqx))) { int a_size = GetSize(cell->getPort(TW::A)); - wire = module->addWire(ID::B); + wire = module->addWire(design->twines.add(Twine{ID::B.str()})); wire->width = a_size; wire->port_input = true; cell->setPort(TW::B, wire); if (cell_type == ID($bwmux)) { - wire = module->addWire(ID::S); + wire = module->addWire(design->twines.add(Twine{ID::S.str()})); wire->width = a_size; wire->port_input = true; cell->setPort(TW::S, wire); } - wire = module->addWire(ID::Y); + wire = module->addWire(design->twines.add(Twine{ID::Y.str()})); wire->width = a_size; wire->port_output = true; cell->setPort(TW::Y, wire); @@ -602,15 +602,19 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std:: } vlog_file << stringf(" %s_expr uut_expr(", uut_name); - for (int i = 0; i < GetSize(gold_mod->ports); i++) - vlog_file << stringf("%s.%s(%s%s)", i ? ", " : "", gold_mod->ports[i].unescape(), gold_mod->ports[i].unescape(), + for (int i = 0; i < GetSize(gold_mod->ports); i++) { + std::string port_name = gold_mod->design->twines.str(gold_mod->ports[i]); + vlog_file << stringf("%s.%s(%s%s)", i ? ", " : "", port_name, port_name, gold_mod->wire(gold_mod->ports[i])->port_input ? "" : "_expr"); + } vlog_file << stringf(");\n"); vlog_file << stringf(" %s_expr uut_noexpr(", uut_name); - for (int i = 0; i < GetSize(gold_mod->ports); i++) - vlog_file << stringf("%s.%s(%s%s)", i ? ", " : "", gold_mod->ports[i].unescape(), gold_mod->ports[i].unescape(), + for (int i = 0; i < GetSize(gold_mod->ports); i++) { + std::string port_name = gold_mod->design->twines.str(gold_mod->ports[i]); + vlog_file << stringf("%s.%s(%s%s)", i ? ", " : "", port_name, port_name, gold_mod->wire(gold_mod->ports[i])->port_input ? "" : "_noexpr"); + } vlog_file << stringf(");\n"); vlog_file << stringf(" task run;\n"); @@ -1203,7 +1207,7 @@ struct TestCellPass : public Pass { CellCosts costs(design); Pass::call(design, "select gold"); for (auto mod : design->selected_modules()) { - log_assert(mod->name.str() == "\\gold"); + log_assert(design->twines.str(mod->meta_->name) == "\\gold"); // Expected to run once int num_cells_estimate = costs.get(uut); if (num_cells <= num_cells_estimate) { diff --git a/techlibs/anlogic/anlogic_fixcarry.cc b/techlibs/anlogic/anlogic_fixcarry.cc index 1f38e0608..408ce5d75 100644 --- a/techlibs/anlogic/anlogic_fixcarry.cc +++ b/techlibs/anlogic/anlogic_fixcarry.cc @@ -41,11 +41,11 @@ static void fix_carry_chain(Module *module) { if (cell->type == ID(AL_MAP_ADDER)) { if (cell->getParam(ID(ALUTYPE)) != Const("ADD")) continue; - SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(a))); - SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(b))); + SigBit bit_i0 = get_bit_or_zero(cell->getPort(TW::a)); + SigBit bit_i1 = get_bit_or_zero(cell->getPort(TW::b)); if (bit_i0 == State::S0 && bit_i1== State::S0) { - SigBit bit_ci = get_bit_or_zero(cell->getPort(ID(c))); - SigSpec o = cell->getPort(ID(o)); + SigBit bit_ci = get_bit_or_zero(cell->getPort(TW::c)); + SigSpec o = cell->getPort(TW::o); if (GetSize(o) == 2) { SigBit bit_o = o[0]; ci_bits.insert(bit_ci); @@ -59,9 +59,9 @@ static void fix_carry_chain(Module *module) { if (cell->type == ID(AL_MAP_ADDER)) { if (cell->getParam(ID(ALUTYPE)) != Const("ADD")) continue; - SigBit bit_ci = get_bit_or_zero(cell->getPort(ID(c))); - SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(a))); - SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(b))); + SigBit bit_ci = get_bit_or_zero(cell->getPort(TW::c)); + SigBit bit_i0 = get_bit_or_zero(cell->getPort(TW::a)); + SigBit bit_i1 = get_bit_or_zero(cell->getPort(TW::b)); SigBit canonical_bit = sigmap(bit_ci); if (!ci_bits.count(canonical_bit)) continue; @@ -75,7 +75,7 @@ static void fix_carry_chain(Module *module) for (auto cell : adders_to_fix_cells) { - SigBit bit_ci = get_bit_or_zero(cell->getPort(ID(c))); + SigBit bit_ci = get_bit_or_zero(cell->getPort(TW::c)); SigBit canonical_bit = sigmap(bit_ci); auto bit = mapping_bits.at(canonical_bit); log("Fixing %s cell named %s breaking carry chain.\n", cell->type.unescape(), cell); @@ -86,12 +86,12 @@ static void fix_carry_chain(Module *module) bits.append(dummy_bit); bits.append(new_bit); c->setParam(ID(ALUTYPE), Const("ADD_CARRY")); - c->setPort(ID(a), bit); - c->setPort(ID(b), State::S0); - c->setPort(ID(c), State::S0); - c->setPort(ID(o), bits); + c->setPort(TW::a, bit); + c->setPort(TW::b, State::S0); + c->setPort(TW::c, State::S0); + c->setPort(TW::o, bits); - cell->setPort(ID(c), new_bit); + cell->setPort(TW::c, new_bit); } } diff --git a/techlibs/coolrunner2/coolrunner2_fixup.cc b/techlibs/coolrunner2/coolrunner2_fixup.cc index 3ba797a9d..09b3a05d3 100644 --- a/techlibs/coolrunner2/coolrunner2_fixup.cc +++ b/techlibs/coolrunner2/coolrunner2_fixup.cc @@ -36,7 +36,7 @@ RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cel module->uniquify(stringf("$xc2fix$%s_BUF1_XOR", cellname)), ID(MACROCELL_XOR)); xor_cell->setParam(ID(INVERT_OUT), true); - xor_cell->setPort(ID(OUT), outwire); + xor_cell->setPort(TW::OUT, outwire); } else if (inwire == SigBit(false)) { @@ -47,7 +47,7 @@ RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cel module->uniquify(stringf("$xc2fix$%s_BUF0_XOR", cellname)), ID(MACROCELL_XOR)); xor_cell->setParam(ID(INVERT_OUT), false); - xor_cell->setPort(ID(OUT), outwire); + xor_cell->setPort(TW::OUT, outwire); } else if (inwire == SigBit(RTLIL::State::Sx)) { @@ -59,7 +59,7 @@ RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cel module->uniquify(stringf("$xc2fix$%s_BUF0_XOR", cellname)), ID(MACROCELL_XOR)); xor_cell->setParam(ID(INVERT_OUT), false); - xor_cell->setPort(ID(OUT), outwire); + xor_cell->setPort(TW::OUT, outwire); } else { @@ -76,16 +76,16 @@ RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cel ID(ANDTERM)); and_cell->setParam(ID(TRUE_INP), 1); and_cell->setParam(ID(COMP_INP), 0); - and_cell->setPort(ID(OUT), and_to_xor_wire); - and_cell->setPort(ID(IN), inwire); - and_cell->setPort(ID(IN_B), SigSpec()); + and_cell->setPort(TW::OUT, and_to_xor_wire); + and_cell->setPort(TW::IN, inwire); + and_cell->setPort(TW::IN_B, SigSpec()); auto xor_cell = module->addCell( module->uniquify(stringf("$xc2fix$%s_BUF_XOR", inwire_name)), ID(MACROCELL_XOR)); xor_cell->setParam(ID(INVERT_OUT), false); - xor_cell->setPort(ID(IN_PTC), and_to_xor_wire); - xor_cell->setPort(ID(OUT), outwire); + xor_cell->setPort(TW::IN_PTC, and_to_xor_wire); + xor_cell->setPort(TW::OUT, outwire); } return outwire; @@ -103,9 +103,9 @@ RTLIL::Wire *makeptermbuffer(RTLIL::Module *module, SigBit inwire) ID(ANDTERM)); and_cell->setParam(ID(TRUE_INP), 1); and_cell->setParam(ID(COMP_INP), 0); - and_cell->setPort(ID(OUT), outwire); - and_cell->setPort(ID(IN), inwire); - and_cell->setPort(ID(IN_B), SigSpec()); + and_cell->setPort(TW::OUT, outwire); + and_cell->setPort(TW::IN, inwire); + and_cell->setPort(TW::IN_B, SigSpec()); return outwire; } @@ -147,7 +147,7 @@ struct Coolrunner2FixupPass : public Pass { { if (cell->type == ID(MACROCELL_XOR)) { - auto output = sigmap(cell->getPort(ID(OUT))[0]); + auto output = sigmap(cell->getPort(TW::OUT)[0]); sig_fed_by_xor.insert(output); } } @@ -158,7 +158,7 @@ struct Coolrunner2FixupPass : public Pass { { if (cell->type.in(ID(IBUF), ID(IOBUFE))) { - if (cell->hasPort(ID::O)) { + if (cell->hasPort(TW::O)) { auto output = sigmap(cell->getPort(TW::O)[0]); sig_fed_by_io.insert(output); } @@ -171,7 +171,7 @@ struct Coolrunner2FixupPass : public Pass { { if (cell->type == ID(ANDTERM)) { - auto output = sigmap(cell->getPort(ID(OUT))[0]); + auto output = sigmap(cell->getPort(TW::OUT)[0]); sig_fed_by_pterm.insert(output); } } @@ -333,7 +333,7 @@ struct Coolrunner2FixupPass : public Pass { // Buffering FF set/reset. This can only come from either // a pterm or a bufgsr. SigBit set; - set = sigmap(cell->getPort(ID(PRE))[0]); + set = sigmap(cell->getPort(TW::PRE)[0]); if (set != SigBit(false)) { if (!sig_fed_by_pterm[set] && !sig_fed_by_bufgsr[set]) @@ -342,7 +342,7 @@ struct Coolrunner2FixupPass : public Pass { auto pterm_to_ff_wire = makeptermbuffer(module, set); - cell->setPort(ID(PRE), pterm_to_ff_wire); + cell->setPort(TW::PRE, pterm_to_ff_wire); } } @@ -366,14 +366,14 @@ struct Coolrunner2FixupPass : public Pass { if (cell->type.in(ID(FDCPE), ID(FDCPE_N), ID(FDDCPE))) { SigBit ce; - ce = sigmap(cell->getPort(ID(CE))[0]); + ce = sigmap(cell->getPort(TW::CE)[0]); if (!sig_fed_by_pterm[ce]) { log("Buffering clock enable to \"%s\"\n", cell->name); auto pterm_to_ff_wire = makeptermbuffer(module, ce); - cell->setPort(ID(CE), pterm_to_ff_wire); + cell->setPort(TW::CE, pterm_to_ff_wire); } } } @@ -398,7 +398,7 @@ struct Coolrunner2FixupPass : public Pass { // Buffer IOBUFE enables. This can only be fed from a pterm // or a bufgts. - if (cell->hasPort(ID::E)) + if (cell->hasPort(TW::E)) { SigBit oe; oe = sigmap(cell->getPort(TW::E)[0]); @@ -424,7 +424,7 @@ struct Coolrunner2FixupPass : public Pass { { if (cell->type == ID(MACROCELL_XOR)) { - auto output = sigmap(cell->getPort(ID(OUT))[0]); + auto output = sigmap(cell->getPort(TW::OUT)[0]); xor_out_to_xor_cell[output] = cell; } } @@ -456,7 +456,7 @@ struct Coolrunner2FixupPass : public Pass { module->uniquify(xor_cell->name), xor_cell); auto new_wire = module->addWire( module->uniquify(wire_in.wire->name)); - new_xor_cell->setPort(ID(OUT), new_wire); + new_xor_cell->setPort(TW::OUT, new_wire); cell->setPort(conn.first, new_wire); } xor_fanout_once.insert(wire_in); @@ -475,7 +475,7 @@ struct Coolrunner2FixupPass : public Pass { { if (cell->type == ID(ORTERM)) { - auto output = sigmap(cell->getPort(ID(OUT))[0]); + auto output = sigmap(cell->getPort(TW::OUT)[0]); or_out_to_or_cell[output] = cell; } } @@ -504,7 +504,7 @@ struct Coolrunner2FixupPass : public Pass { module->uniquify(or_cell->name), or_cell); auto new_wire = module->addWire( module->uniquify(wire_in.wire->name)); - new_or_cell->setPort(ID(OUT), new_wire); + new_or_cell->setPort(TW::OUT, new_wire); cell->setPort(conn.first, new_wire); } or_fanout_once.insert(wire_in); diff --git a/techlibs/coolrunner2/coolrunner2_sop.cc b/techlibs/coolrunner2/coolrunner2_sop.cc index 3546d39ee..e2c30d50a 100644 --- a/techlibs/coolrunner2/coolrunner2_sop.cc +++ b/techlibs/coolrunner2/coolrunner2_sop.cc @@ -63,20 +63,20 @@ struct Coolrunner2SopPass : public Pass { if (cell->type.in(ID(FDCP), ID(FDCP_N), ID(FDDCP), ID(FTCP), ID(FTCP_N), ID(FTDCP), ID(FDCPE), ID(FDCPE_N), ID(FDDCPE), ID(LDCP), ID(LDCP_N))) { - if (cell->hasPort(ID(PRE))) - special_pterms_no_inv[sigmap(cell->getPort(ID(PRE))[0])].insert( + if (cell->hasPort(TW(PRE))) + special_pterms_no_inv[sigmap(cell->getPort(TW::PRE)[0])].insert( make_tuple(cell, ID(PRE))); - if (cell->hasPort(ID::CLR)) + if (cell->hasPort(TW::CLR)) special_pterms_no_inv[sigmap(cell->getPort(TW::CLR)[0])].insert( make_tuple(cell, ID::CLR)); - if (cell->hasPort(ID(CE))) - special_pterms_no_inv[sigmap(cell->getPort(ID(CE))[0])].insert( + if (cell->hasPort(TW(CE))) + special_pterms_no_inv[sigmap(cell->getPort(TW::CE)[0])].insert( make_tuple(cell, ID(CE))); - if (cell->hasPort(ID::C)) + if (cell->hasPort(TW::C)) special_pterms_inv[sigmap(cell->getPort(TW::C)[0])].insert( make_tuple(cell, ID::C)); - if (cell->hasPort(ID::G)) + if (cell->hasPort(TW::G)) special_pterms_inv[sigmap(cell->getPort(TW::G)[0])].insert( make_tuple(cell, ID::G)); } @@ -142,9 +142,9 @@ struct Coolrunner2SopPass : public Pass { ID(ANDTERM)); and_cell->setParam(ID(TRUE_INP), GetSize(and_in_true)); and_cell->setParam(ID(COMP_INP), GetSize(and_in_comp)); - and_cell->setPort(ID(OUT), and_out); - and_cell->setPort(ID(IN), and_in_true); - and_cell->setPort(ID(IN_B), and_in_comp); + and_cell->setPort(TW::OUT, and_out); + and_cell->setPort(TW::IN, and_in_true); + and_cell->setPort(TW::IN_B, and_in_comp); } if (sop_depth == 1) @@ -154,8 +154,8 @@ struct Coolrunner2SopPass : public Pass { module->uniquify(stringf("$xc2sop$%s_XOR", sop_output_wire_name)), ID(MACROCELL_XOR)); xor_cell->setParam(ID(INVERT_OUT), has_invert); - xor_cell->setPort(ID(IN_PTC), *intermed_wires.begin()); - xor_cell->setPort(ID(OUT), sop_output); + xor_cell->setPort(TW::IN_PTC, *intermed_wires.begin()); + xor_cell->setPort(TW::OUT, sop_output); // Special P-term handling if (is_special_pterm) @@ -205,16 +205,16 @@ struct Coolrunner2SopPass : public Pass { module->uniquify(stringf("$xc2sop$%s_OR", sop_output_wire_name)), ID(ORTERM)); or_cell->setParam(ID::WIDTH, sop_depth); - or_cell->setPort(ID(IN), intermed_wires); - or_cell->setPort(ID(OUT), or_to_xor_wire); + or_cell->setPort(TW::IN, intermed_wires); + or_cell->setPort(TW::OUT, or_to_xor_wire); // Construct the XOR cell auto xor_cell = module->addCell( module->uniquify(stringf("$xc2sop$%s_XOR", sop_output_wire_name)), ID(MACROCELL_XOR)); xor_cell->setParam(ID(INVERT_OUT), has_invert); - xor_cell->setPort(ID(IN_ORTERM), or_to_xor_wire); - xor_cell->setPort(ID(OUT), sop_output); + xor_cell->setPort(TW::IN_ORTERM, or_to_xor_wire); + xor_cell->setPort(TW::OUT, sop_output); } // Finally, remove the $sop cell diff --git a/techlibs/efinix/efinix_fixcarry.cc b/techlibs/efinix/efinix_fixcarry.cc index 4b267954d..cb415ffa3 100644 --- a/techlibs/efinix/efinix_fixcarry.cc +++ b/techlibs/efinix/efinix_fixcarry.cc @@ -40,8 +40,8 @@ static void fix_carry_chain(Module *module) for (auto cell : module->cells()) { if (cell->type == ID(EFX_ADD)) { - SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(I0))); - SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(I1))); + SigBit bit_i0 = get_bit_or_zero(cell->getPort(TW::I0)); + SigBit bit_i1 = get_bit_or_zero(cell->getPort(TW::I1)); if (bit_i0 == State::S0 && bit_i1== State::S0) { SigBit bit_ci = get_bit_or_zero(cell->getPort(TW::CI)); SigBit bit_o = sigmap(cell->getPort(TW::O)); @@ -56,8 +56,8 @@ static void fix_carry_chain(Module *module) { if (cell->type == ID(EFX_ADD)) { SigBit bit_ci = get_bit_or_zero(cell->getPort(TW::CI)); - SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(I0))); - SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(I1))); + SigBit bit_i0 = get_bit_or_zero(cell->getPort(TW::I0)); + SigBit bit_i1 = get_bit_or_zero(cell->getPort(TW::I1)); SigBit canonical_bit = sigmap(bit_ci); if (!ci_bits.count(canonical_bit)) continue; @@ -79,8 +79,8 @@ static void fix_carry_chain(Module *module) SigBit new_bit = module->addWire(NEW_TWINE); c->setParam(ID(I0_POLARITY), State::S1); c->setParam(ID(I1_POLARITY), State::S1); - c->setPort(ID(I0), bit); - c->setPort(ID(I1), State::S1); + c->setPort(TW::I0, bit); + c->setPort(TW::I1, State::S1); c->setPort(TW::CI, State::S0); c->setPort(TW::CO, new_bit); diff --git a/techlibs/gatemate/gatemate_foldinv.cc b/techlibs/gatemate/gatemate_foldinv.cc index 66d56188c..0c1f39e32 100644 --- a/techlibs/gatemate/gatemate_foldinv.cc +++ b/techlibs/gatemate/gatemate_foldinv.cc @@ -141,7 +141,7 @@ struct FoldInvWorker { auto found_type = lut_types.find(cell->type); if (found_type == lut_types.end()) continue; - if (!cell->hasPort(ID::O)) + if (!cell->hasPort(TW::O)) continue; auto o_sig = cell->getPort(TW::O); if (GetSize(o_sig) == 0) diff --git a/techlibs/greenpak4/greenpak4_dffinv.cc b/techlibs/greenpak4/greenpak4_dffinv.cc index b15874360..30e6d99cd 100644 --- a/techlibs/greenpak4/greenpak4_dffinv.cc +++ b/techlibs/greenpak4/greenpak4_dffinv.cc @@ -56,14 +56,14 @@ void invert_gp_dff(Cell *cell, bool invert_input) else { if (cell_type_r) { - cell->setPort(ID(nSET), cell->getPort(ID(nRST))); - cell->unsetPort(ID(nRST)); + cell->setPort(TW::nSET, cell->getPort(TW::nRST)); + cell->unsetPort(TW::nRST); cell_type_r = false; cell_type_s = true; } else if (cell_type_s) { - cell->setPort(ID(nRST), cell->getPort(ID(nSET))); - cell->unsetPort(ID(nSET)); + cell->setPort(TW::nRST, cell->getPort(TW::nSET)); + cell->unsetPort(TW::nSET); cell_type_r = true; cell_type_s = false; } @@ -71,11 +71,11 @@ void invert_gp_dff(Cell *cell, bool invert_input) } if (cell_type_i) { - cell->setPort(TW::Q, cell->getPort(ID(nQ))); - cell->unsetPort(ID(nQ)); + cell->setPort(TW::Q, cell->getPort(TW::nQ)); + cell->unsetPort(TW::nQ); cell_type_i = false; } else { - cell->setPort(ID(nQ), cell->getPort(TW::Q)); + cell->setPort(TW::nQ, cell->getPort(TW::Q)); cell->unsetPort(TW::Q); cell_type_i = true; } @@ -164,8 +164,8 @@ struct Greenpak4DffInvPass : public Pass { } if (cell->type == ID(GP_INV)) { - SigBit in_bit = sigmap(cell->getPort(ID(IN))); - SigBit out_bit = sigmap(cell->getPort(ID(OUT))); + SigBit in_bit = sigmap(cell->getPort(TW::IN)); + SigBit out_bit = sigmap(cell->getPort(TW::OUT)); inv_in2out[in_bit] = out_bit; inv_out2in[out_bit] = in_bit; inv_in2cell[in_bit] = cell; @@ -176,7 +176,7 @@ struct Greenpak4DffInvPass : public Pass { for (auto cell : dff_cells) { SigBit d_bit = sigmap(cell->getPort(TW::D)); - SigBit q_bit = sigmap(cell->hasPort(ID::Q) ? cell->getPort(TW::Q) : cell->getPort(ID(nQ))); + SigBit q_bit = sigmap(cell->hasPort(TW::Q) ? cell->getPort(TW::Q) : cell->getPort(TW::nQ)); while (inv_out2in.count(d_bit)) { @@ -197,10 +197,10 @@ struct Greenpak4DffInvPass : public Pass { inv_in2cell.erase(q_bit); invert_gp_dff(cell, false); - if (cell->hasPort(ID::Q)) + if (cell->hasPort(TW::Q)) cell->setPort(TW::Q, new_q_bit); else - cell->setPort(ID(nQ), new_q_bit); + cell->setPort(TW::nQ, new_q_bit); } } } diff --git a/techlibs/ice40/ice40_dsp.cc b/techlibs/ice40/ice40_dsp.cc index d6a080ac6..a63105348 100644 --- a/techlibs/ice40/ice40_dsp.cc +++ b/techlibs/ice40/ice40_dsp.cc @@ -97,39 +97,39 @@ void create_ice40_dsp(ice40_dsp_pm &pm) cell->setParam(ID(D_REG), st.ffCD ? State::S1 : State::S0); SigSpec AHOLD, BHOLD, CDHOLD; - if (st.ffA && st.ffA->hasPort(ID::EN)) - AHOLD = st.ffA->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffA->getPort(TW::EN)) : st.ffA->getPort(TW::EN); + if (st.ffA && st.ffA->hasPort(TW::EN)) + AHOLD = st.ffA->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_TWINE, st.ffA->getPort(TW::EN)) : st.ffA->getPort(TW::EN); else AHOLD = State::S0; - if (st.ffB && st.ffB->hasPort(ID::EN)) - BHOLD = st.ffB->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffB->getPort(TW::EN)) : st.ffB->getPort(TW::EN); + if (st.ffB && st.ffB->hasPort(TW::EN)) + BHOLD = st.ffB->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_TWINE, st.ffB->getPort(TW::EN)) : st.ffB->getPort(TW::EN); else BHOLD = State::S0; - if (st.ffCD && st.ffCD->hasPort(ID::EN)) - CDHOLD = st.ffCD->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffCD->getPort(TW::EN)) : st.ffCD->getPort(TW::EN); + if (st.ffCD && st.ffCD->hasPort(TW::EN)) + CDHOLD = st.ffCD->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_TWINE, st.ffCD->getPort(TW::EN)) : st.ffCD->getPort(TW::EN); else CDHOLD = State::S0; - cell->setPort(ID(AHOLD), AHOLD); - cell->setPort(ID(BHOLD), BHOLD); - cell->setPort(ID(CHOLD), CDHOLD); - cell->setPort(ID(DHOLD), CDHOLD); + cell->setPort(TW::AHOLD, AHOLD); + cell->setPort(TW::BHOLD, BHOLD); + cell->setPort(TW::CHOLD, CDHOLD); + cell->setPort(TW::DHOLD, CDHOLD); SigSpec IRSTTOP, IRSTBOT; - if (st.ffA && st.ffA->hasPort(ID::ARST)) - IRSTTOP = st.ffA->getParam(ID::ARST_POLARITY).as_bool() ? st.ffA->getPort(TW::ARST) : pm.module->Not(NEW_ID, st.ffA->getPort(TW::ARST)); + if (st.ffA && st.ffA->hasPort(TW::ARST)) + IRSTTOP = st.ffA->getParam(ID::ARST_POLARITY).as_bool() ? st.ffA->getPort(TW::ARST) : pm.module->Not(NEW_TWINE, st.ffA->getPort(TW::ARST)); else IRSTTOP = State::S0; - if (st.ffB && st.ffB->hasPort(ID::ARST)) - IRSTBOT = st.ffB->getParam(ID::ARST_POLARITY).as_bool() ? st.ffB->getPort(TW::ARST) : pm.module->Not(NEW_ID, st.ffB->getPort(TW::ARST)); + if (st.ffB && st.ffB->hasPort(TW::ARST)) + IRSTBOT = st.ffB->getParam(ID::ARST_POLARITY).as_bool() ? st.ffB->getPort(TW::ARST) : pm.module->Not(NEW_TWINE, st.ffB->getPort(TW::ARST)); else IRSTBOT = State::S0; - cell->setPort(ID(IRSTTOP), IRSTTOP); - cell->setPort(ID(IRSTBOT), IRSTBOT); + cell->setPort(TW::IRSTTOP, IRSTTOP); + cell->setPort(TW::IRSTBOT, IRSTBOT); if (st.clock != SigBit()) { cell->setPort(TW::CLK, st.clock); - cell->setPort(ID(CE), State::S1); + cell->setPort(TW::CE, State::S1); cell->setParam(ID(NEG_TRIGGER), st.clock_pol ? State::S0 : State::S1); log(" clock: %s (%s)", log_signal(st.clock), st.clock_pol ? "posedge" : "negedge"); @@ -157,19 +157,19 @@ void create_ice40_dsp(ice40_dsp_pm &pm) else { cell->setPort(TW::CLK, State::S0); - cell->setPort(ID(CE), State::S0); + cell->setPort(TW::CE, State::S0); cell->setParam(ID(NEG_TRIGGER), State::S0); } // SB_MAC16 Cascade Interface - cell->setPort(ID(SIGNEXTIN), State::Sx); - cell->setPort(ID(SIGNEXTOUT), pm.module->addWire(NEW_TWINE)); + cell->setPort(TW::SIGNEXTIN, State::Sx); + cell->setPort(TW::SIGNEXTOUT, pm.module->addWire(NEW_TWINE)); cell->setPort(TW::CI, State::Sx); - cell->setPort(ID(ACCUMCI), State::Sx); - cell->setPort(ID(ACCUMCO), pm.module->addWire(NEW_TWINE)); + cell->setPort(TW::ACCUMCI, State::Sx); + cell->setPort(TW::ACCUMCO, pm.module->addWire(NEW_TWINE)); // SB_MAC16 Output Interface @@ -199,40 +199,40 @@ void create_ice40_dsp(ice40_dsp_pm &pm) log(" accumulator %s (%s)\n", st.add, st.add->type.unescape()); else log(" adder %s (%s)\n", st.add, st.add->type.unescape()); - cell->setPort(ID(ADDSUBTOP), st.add->type == ID($add) ? State::S0 : State::S1); - cell->setPort(ID(ADDSUBBOT), st.add->type == ID($add) ? State::S0 : State::S1); + cell->setPort(TW::ADDSUBTOP, st.add->type == ID($add) ? State::S0 : State::S1); + cell->setPort(TW::ADDSUBBOT, st.add->type == ID($add) ? State::S0 : State::S1); } else { - cell->setPort(ID(ADDSUBTOP), State::S0); - cell->setPort(ID(ADDSUBBOT), State::S0); + cell->setPort(TW::ADDSUBTOP, State::S0); + cell->setPort(TW::ADDSUBBOT, State::S0); } SigSpec OHOLD; - if (st.ffO && st.ffO->hasPort(ID::EN)) - OHOLD = st.ffO->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffO->getPort(TW::EN)) : st.ffO->getPort(TW::EN); + if (st.ffO && st.ffO->hasPort(TW::EN)) + OHOLD = st.ffO->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_TWINE, st.ffO->getPort(TW::EN)) : st.ffO->getPort(TW::EN); else OHOLD = State::S0; - cell->setPort(ID(OHOLDTOP), OHOLD); - cell->setPort(ID(OHOLDBOT), OHOLD); + cell->setPort(TW::OHOLDTOP, OHOLD); + cell->setPort(TW::OHOLDBOT, OHOLD); SigSpec ORST; - if (st.ffO && st.ffO->hasPort(ID::ARST)) - ORST = st.ffO->getParam(ID::ARST_POLARITY).as_bool() ? st.ffO->getPort(TW::ARST) : pm.module->Not(NEW_ID, st.ffO->getPort(TW::ARST)); + if (st.ffO && st.ffO->hasPort(TW::ARST)) + ORST = st.ffO->getParam(ID::ARST_POLARITY).as_bool() ? st.ffO->getPort(TW::ARST) : pm.module->Not(NEW_TWINE, st.ffO->getPort(TW::ARST)); else ORST = State::S0; - cell->setPort(ID(ORSTTOP), ORST); - cell->setPort(ID(ORSTBOT), ORST); + cell->setPort(TW::ORSTTOP, ORST); + cell->setPort(TW::ORSTBOT, ORST); SigSpec acc_reset = State::S0; if (st.mux) { if (st.muxAB == ID::A) acc_reset = st.mux->getPort(TW::S); else - acc_reset = pm.module->Not(NEW_ID, st.mux->getPort(TW::S)); - } else if (st.ffO && st.ffO->hasPort(ID::SRST)) { - acc_reset = st.ffO->getParam(ID::SRST_POLARITY).as_bool() ? st.ffO->getPort(TW::SRST) : pm.module->Not(NEW_ID, st.ffO->getPort(TW::SRST)); + acc_reset = pm.module->Not(NEW_TWINE, st.mux->getPort(TW::S)); + } else if (st.ffO && st.ffO->hasPort(TW::SRST)) { + acc_reset = st.ffO->getParam(ID::SRST_POLARITY).as_bool() ? st.ffO->getPort(TW::SRST) : pm.module->Not(NEW_TWINE, st.ffO->getPort(TW::SRST)); } - cell->setPort(ID(OLOADTOP), acc_reset); - cell->setPort(ID(OLOADBOT), acc_reset); + cell->setPort(TW::OLOADTOP, acc_reset); + cell->setPort(TW::OLOADBOT, acc_reset); // SB_MAC16 Remaining Parameters diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 0221cc7b2..07f386a9b 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -58,8 +58,8 @@ static void run_ice40_opts(Module *module) int count_zeros = 0, count_ones = 0; SigBit inbit[3] = { - get_bit_or_zero(cell->getPort(ID(I0))), - get_bit_or_zero(cell->getPort(ID(I1))), + get_bit_or_zero(cell->getPort(TW::I0)), + get_bit_or_zero(cell->getPort(TW::I1)), get_bit_or_zero(cell->getPort(TW::CI)) }; for (int i = 0; i < 3; i++) @@ -140,12 +140,12 @@ static void run_ice40_opts(Module *module) module, cell, log_signal(replacement_output)); cell->type = ID($lut); auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3))); - cell->setPort(TW::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(ID(I0))) }); + cell->setPort(TW::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(TW::I0)) }); cell->setPort(TW::Y, cell->getPort(TW::O)); cell->unsetPort(TW::B); cell->unsetPort(TW::CI); - cell->unsetPort(ID(I0)); - cell->unsetPort(ID(I3)); + cell->unsetPort(TW::I0); + cell->unsetPort(TW::I3); cell->unsetPort(TW::CO); cell->unsetPort(TW::O); cell->setParam(ID::WIDTH, 4); @@ -159,10 +159,10 @@ static void run_ice40_opts(Module *module) { SigSpec inbits; - inbits.append(get_bit_or_zero(cell->getPort(ID(I0)))); - inbits.append(get_bit_or_zero(cell->getPort(ID(I1)))); - inbits.append(get_bit_or_zero(cell->getPort(ID(I2)))); - inbits.append(get_bit_or_zero(cell->getPort(ID(I3)))); + inbits.append(get_bit_or_zero(cell->getPort(TW::I0))); + inbits.append(get_bit_or_zero(cell->getPort(TW::I1))); + inbits.append(get_bit_or_zero(cell->getPort(TW::I2))); + inbits.append(get_bit_or_zero(cell->getPort(TW::I3))); sigmap.apply(inbits); if (optimized_co.count(inbits[0])) goto remap_lut; @@ -183,16 +183,16 @@ static void run_ice40_opts(Module *module) cell->unsetParam(ID(LUT_INIT)); cell->setPort(TW::A, SigSpec({ - get_bit_or_zero(cell->getPort(ID(I3))), - get_bit_or_zero(cell->getPort(ID(I2))), - get_bit_or_zero(cell->getPort(ID(I1))), - get_bit_or_zero(cell->getPort(ID(I0))) + get_bit_or_zero(cell->getPort(TW::I3)), + get_bit_or_zero(cell->getPort(TW::I2)), + get_bit_or_zero(cell->getPort(TW::I1)), + get_bit_or_zero(cell->getPort(TW::I0)) })); cell->setPort(TW::Y, cell->getPort(TW::O)[0]); - cell->unsetPort(ID(I0)); - cell->unsetPort(ID(I1)); - cell->unsetPort(ID(I2)); - cell->unsetPort(ID(I3)); + cell->unsetPort(TW::I0); + cell->unsetPort(TW::I1); + cell->unsetPort(TW::I2); + cell->unsetPort(TW::I3); cell->unsetPort(TW::O); cell->check(); diff --git a/techlibs/ice40/ice40_wrapcarry.cc b/techlibs/ice40/ice40_wrapcarry.cc index f680207a5..d8fa85b78 100644 --- a/techlibs/ice40/ice40_wrapcarry.cc +++ b/techlibs/ice40/ice40_wrapcarry.cc @@ -40,21 +40,21 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm) Cell *cell = pm.module->addCell(NEW_TWINE, ID($__ICE40_CARRY_WRAPPER)); pm.module->swap_names(cell, st.carry); - cell->setPort(TW::A, st.carry->getPort(ID(I0))); - cell->setPort(TW::B, st.carry->getPort(ID(I1))); + cell->setPort(TW::A, st.carry->getPort(TW::I0)); + cell->setPort(TW::B, st.carry->getPort(TW::I1)); auto CI = st.carry->getPort(TW::CI); cell->setPort(TW::CI, CI); cell->setPort(TW::CO, st.carry->getPort(TW::CO)); - cell->setPort(ID(I0), st.lut->getPort(ID(I0))); - auto I3 = st.lut->getPort(ID(I3)); + cell->setPort(TW::I0, st.lut->getPort(TW::I0)); + auto I3 = st.lut->getPort(TW::I3); if ((*pm.sigmap)(CI) == (*pm.sigmap)(I3)) { cell->setParam(ID(I3_IS_CI), State::S1); I3 = State::Sx; } else cell->setParam(ID(I3_IS_CI), State::S0); - cell->setPort(ID(I3), I3); + cell->setPort(TW::I3, I3); cell->setPort(TW::O, st.lut->getPort(TW::O)); cell->setParam(ID::LUT, st.lut->getParam(ID(LUT_INIT))); @@ -135,8 +135,8 @@ struct Ice40WrapCarryPass : public Pass { continue; auto carry = module->addCell(NEW_TWINE, ID(SB_CARRY)); - carry->setPort(ID(I0), cell->getPort(TW::A)); - carry->setPort(ID(I1), cell->getPort(TW::B)); + carry->setPort(TW::I0, cell->getPort(TW::A)); + carry->setPort(TW::I1, cell->getPort(TW::B)); carry->setPort(TW::CI, cell->getPort(TW::CI)); carry->setPort(TW::CO, cell->getPort(TW::CO)); module->swap_names(carry, cell); @@ -145,7 +145,7 @@ struct Ice40WrapCarryPass : public Pass { lut->setParam(ID::WIDTH, 4); lut->setParam(ID::LUT, cell->getParam(ID::LUT)); auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3)); - lut->setPort(TW::A, { I3, cell->getPort(TW::B), cell->getPort(TW::A), cell->getPort(ID(I0)) }); + lut->setPort(TW::A, { I3, cell->getPort(TW::B), cell->getPort(TW::A), cell->getPort(TW::I0) }); lut->setPort(TW::Y, cell->getPort(TW::O)); std::string carry_src, lut_src, fallback_src; diff --git a/techlibs/lattice/lattice_gsr.cc b/techlibs/lattice/lattice_gsr.cc index 3840bc3eb..3903f04c4 100644 --- a/techlibs/lattice/lattice_gsr.cc +++ b/techlibs/lattice/lattice_gsr.cc @@ -71,7 +71,7 @@ struct LatticeGsrPass : public Pass { if (found_gsr) log_error("Found more than one GSR or SGSR cell in module %s.\n", module); found_gsr = true; - SigSpec sig_gsr = cell->getPort(ID(GSR)); + SigSpec sig_gsr = cell->getPort(TW::GSR); if (GetSize(sig_gsr) < 1) log_error("GSR cell %s has disconnected GSR input.\n", cell); gsr = sigmap(sig_gsr[0]); @@ -118,14 +118,14 @@ struct LatticeGsrPass : public Pass { continue; if (cell->getParam(ID(SRMODE)).decode_string() != "ASYNC") continue; - SigSpec sig_lsr = cell->getPort(ID(LSR)); + SigSpec sig_lsr = cell->getPort(TW::LSR); if (GetSize(sig_lsr) < 1) continue; SigBit lsr = sigmap(sig_lsr[0]); if (!inverted_gsr.count(lsr)) continue; cell->setParam(ID(SRMODE), Const("LSR_OVER_CE")); - cell->unsetPort(ID(LSR)); + cell->unsetPort(TW::LSR); } } diff --git a/techlibs/microchip/microchip_dffopt.cc b/techlibs/microchip/microchip_dffopt.cc index 4a5e3264e..9e26a4af9 100644 --- a/techlibs/microchip/microchip_dffopt.cc +++ b/techlibs/microchip/microchip_dffopt.cc @@ -142,16 +142,16 @@ struct MicrochipDffOptPass : public Pass { SigBit sigout = sigmap(cell->getPort(TW::Y)); const Const &init = cell->getParam(ID::INIT); std::vector sigin; - sigin.push_back(sigmap(cell->getPort(ID(A)))); + sigin.push_back(sigmap(cell->getPort(TW::A))); if (cell->type == ID(CFG1)) goto lut_sigin_done; - sigin.push_back(sigmap(cell->getPort(ID(B)))); + sigin.push_back(sigmap(cell->getPort(TW::B))); if (cell->type == ID(CFG2)) goto lut_sigin_done; - sigin.push_back(sigmap(cell->getPort(ID(C)))); + sigin.push_back(sigmap(cell->getPort(TW::C))); if (cell->type == ID(CFG3)) goto lut_sigin_done; - sigin.push_back(sigmap(cell->getPort(ID(D)))); + sigin.push_back(sigmap(cell->getPort(TW::D))); lut_sigin_done: bit_to_lut[sigout] = make_pair(LutData(init, sigin), cell); @@ -167,16 +167,16 @@ struct MicrochipDffOptPass : public Pass { if (!cell->type.in(ID(SLE))) // not a SLE continue; - if (cell->getPort(ID(LAT)).is_fully_ones()) // skip latch + if (cell->getPort(TW::LAT).is_fully_ones()) // skip latch continue; if (cell->get_bool_attribute(ID::keep)) // keep attribute continue; - if (!cell->getPort(ID(ALn)).is_fully_ones()) // async FF + if (!cell->getPort(TW::ALn).is_fully_ones()) // async FF continue; - const bool hasSyncLoad = cell->getPort(ID(SLn)).is_wire(); - const bool has_s = hasSyncLoad && cell->getPort(ID(SD)).is_fully_ones(); - const bool has_r = hasSyncLoad && cell->getPort(ID(SD)).is_fully_zero(); + const bool hasSyncLoad = cell->getPort(TW::SLn).is_wire(); + const bool has_s = hasSyncLoad && cell->getPort(TW::SD).is_fully_ones(); + const bool has_r = hasSyncLoad && cell->getPort(TW::SD).is_fully_zero(); // SLE cannot have both synchronous set and reset implemented at the same time log_assert(!(has_s && has_r)); @@ -202,7 +202,7 @@ struct MicrochipDffOptPass : public Pass { // First, unmap CE. SigBit sig_Q = sigmap(cell->getPort(TW::Q)); - SigBit sig_CE = sigmap(cell->getPort(ID(EN))); + SigBit sig_CE = sigmap(cell->getPort(TW::EN)); LutData lut_ce = LutData(Const(2, 2), {sig_CE}); // INIT = 10 auto it_CE = bit_to_lut.find(sig_CE); if (it_CE != bit_to_lut.end()) @@ -227,7 +227,7 @@ struct MicrochipDffOptPass : public Pass { // Second, unmap S, if any. lut_d_post_s = lut_d_post_ce; if (has_s) { - SigBit sig_S = sigmap(cell->getPort(ID(SLn))); + SigBit sig_S = sigmap(cell->getPort(TW::SLn)); LutData lut_s = LutData(Const(2, 2), {sig_S}); // INIT = 10 bool inv_s = true; // active low auto it_S = bit_to_lut.find(sig_S); @@ -250,7 +250,7 @@ struct MicrochipDffOptPass : public Pass { // Third, unmap R, if any. lut_d_post_r = lut_d_post_s; if (has_r) { - SigBit sig_R = sigmap(cell->getPort(ID(SLn))); + SigBit sig_R = sigmap(cell->getPort(TW::SLn)); LutData lut_r = LutData(Const(2, 2), {sig_R}); // INIT = 10 bool inv_r = true; // active low auto it_R = bit_to_lut.find(sig_R); @@ -299,11 +299,11 @@ struct MicrochipDffOptPass : public Pass { // Okay, we're doing it. Unmap ports. if ((has_s && worthy_post_s) || worthy_post_r) { - cell->setPort(ID(SLn), Const(1, 1)); + cell->setPort(TW::SLn, Const(1, 1)); } // if we made it this far, clk enable is always merged into D - cell->setPort(ID(EN), Const(1, 1)); + cell->setPort(TW::EN, Const(1, 1)); // Create the new LUT. Cell *lut_cell = nullptr; @@ -328,13 +328,13 @@ struct MicrochipDffOptPass : public Pass { lut_cell->setParam(ID::INIT, final_lut.first); cell->setPort(TW::D, lut_out); lut_cell->setPort(TW::Y, lut_out); - lut_cell->setPort(ID(A), final_lut.second[0]); + lut_cell->setPort(TW::A, final_lut.second[0]); if (GetSize(final_lut.second) >= 2) - lut_cell->setPort(ID(B), final_lut.second[1]); + lut_cell->setPort(TW::B, final_lut.second[1]); if (GetSize(final_lut.second) >= 3) - lut_cell->setPort(ID(C), final_lut.second[2]); + lut_cell->setPort(TW::C, final_lut.second[2]); if (GetSize(final_lut.second) >= 4) - lut_cell->setPort(ID(D), final_lut.second[3]); + lut_cell->setPort(TW::D, final_lut.second[3]); } } } diff --git a/techlibs/microchip/microchip_dsp.cc b/techlibs/microchip/microchip_dsp.cc index a1669036e..7d706d87f 100644 --- a/techlibs/microchip/microchip_dsp.cc +++ b/techlibs/microchip/microchip_dsp.cc @@ -72,7 +72,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm) log_assert(!"strange post-adder type"); if (st.useFeedBack) { - cell->setPort(ID(CDIN_FDBK_SEL), {State::S0, State::S1}); + cell->setPort(TW::CDIN_FDBK_SEL, {State::S0, State::S1}); } else { st.sigC.extend_u0(48, st.postAdderStatic->getParam(ID::A_SIGNED).as_bool()); cell->setPort(TW::C, st.sigC); @@ -98,12 +98,12 @@ void microchip_dsp_pack(microchip_dsp_pm &pm) SigSpec srst = ff->getPort(TW::SRST); bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool(); // active low sync rst - cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_ID, srst)); + cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_TWINE, srst)); } else if (ff->type.in(ID($adff), ID($adffe))) { SigSpec arst = ff->getPort(TW::ARST); bool rstpol_n = !ff->getParam(ID::ARST_POLARITY).as_bool(); // active low async rst - cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_ID, arst)); + cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_TWINE, arst)); } else { // active low async/sync rst cell->setPort(rstport, State::S1); @@ -113,7 +113,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm) SigSpec ce = ff->getPort(TW::EN); bool cepol = ff->getParam(ID::EN_POLARITY).as_bool(); // enables are all active high - cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce)); + cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_TWINE, ce)); } else { // enables are all active high cell->setPort(ceport, State::S1); @@ -214,12 +214,12 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm) SigSpec srst = ff->getPort(TW::SRST); bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool(); // active low sync rst - cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_ID, srst)); + cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_TWINE, srst)); } else if (ff->type.in(ID($adff), ID($adffe))) { SigSpec arst = ff->getPort(TW::ARST); bool rstpol_n = !ff->getParam(ID::ARST_POLARITY).as_bool(); // active low async rst - cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_ID, arst)); + cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_TWINE, arst)); } else { // active low async/sync rst cell->setPort(rstport, State::S1); @@ -229,7 +229,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm) SigSpec ce = ff->getPort(TW::EN); bool cepol = ff->getParam(ID::EN_POLARITY).as_bool(); // enables are all active high - cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce)); + cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_TWINE, ce)); } else { // enables are all active high cell->setPort(ceport, State::S1); diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc index d5ad26bbe..f43f4deaf 100644 --- a/techlibs/nanoxplore/nx_carry.cc +++ b/techlibs/nanoxplore/nx_carry.cc @@ -39,9 +39,9 @@ static void nx_carry_chain(Module *module) { if (cell->type == ID(NX_CY_1BIT)) { if (cell->getParam(ID(first)).as_int() == 1) continue; - if (!cell->hasPort(ID(CI))) + if (!cell->hasPort(TW(CI))) log_error("Not able to find connected carry.\n"); - SigBit ci = sigmap(cell->getPort(ID(CI)).as_bit()); + SigBit ci = sigmap(cell->getPort(TW::CI).as_bit()); carry[ci] = cell; } } @@ -57,7 +57,7 @@ static void nx_carry_chain(Module *module) Cell *current = cell; chain.push_back(current); - SigBit co = sigmap(cell->getPort(ID(CO)).as_bit()); + SigBit co = sigmap(cell->getPort(TW::CO).as_bit()); while (co.is_wire()) { if (carry.count(co)==0) @@ -65,8 +65,8 @@ static void nx_carry_chain(Module *module) //log_error("Not able to find connected carry.\n"); current = carry[co]; chain.push_back(current); - if (!current->hasPort(ID(CO))) break; - co = sigmap(current->getPort(ID(CO)).as_bit()); + if (!current->hasPort(TW(CO))) break; + co = sigmap(current->getPort(TW::CO).as_bit()); } carry_chains[cell] = chain; } @@ -80,12 +80,12 @@ static void nx_carry_chain(Module *module) IdString names_A[] = { ID(A1), ID(A2), ID(A3), ID(A4) }; IdString names_B[] = { ID(B1), ID(B2), ID(B3), ID(B4) }; IdString names_S[] = { ID(S1), ID(S2), ID(S3), ID(S4) }; - if (!c.second.at(0)->getPort(ID(CI)).is_fully_const()) { + if (!c.second.at(0)->getPort(TW::CI).is_fully_const()) { cell = module->addCell(NEW_TWINE, ID(NX_CY)); cell->setParam(ID(add_carry), Const(1,2)); - cell->setPort(ID(CI), State::S1); + cell->setPort(TW::CI, State::S1); - cell->setPort(names_A[0], c.second.at(0)->getPort(ID(CI)).as_bit()); + cell->setPort(names_A[0], c.second.at(0)->getPort(TW::CI).as_bit()); cell->setPort(names_B[0], State::S0); j++; } @@ -93,8 +93,8 @@ static void nx_carry_chain(Module *module) for (size_t i=0 ; iaddCell(NEW_TWINE, ID(NX_CY)); - SigBit ci = c.second.at(i)->getPort(ID(CI)).as_bit(); - cell->setPort(ID(CI), ci); + SigBit ci = c.second.at(i)->getPort(TW::CI).as_bit(); + cell->setPort(TW::CI, ci); if (ci.is_wire()) { cell->setParam(ID(add_carry), Const(2,2)); } else { @@ -107,26 +107,26 @@ static void nx_carry_chain(Module *module) if (j==3) { if (cnt !=0 && (cnt % 24 == 0)) { SigBit new_co = module->addWire(NEW_TWINE); - cell->setPort(ID(A4), State::S0); - cell->setPort(ID(B4), State::S0); - cell->setPort(ID(S4), new_co); + cell->setPort(TW::A4, State::S0); + cell->setPort(TW::B4, State::S0); + cell->setPort(TW::S4, new_co); cell = module->addCell(NEW_TWINE, ID(NX_CY)); cell->setParam(ID(add_carry), Const(1,2)); - cell->setPort(ID(CI), State::S1); - cell->setPort(ID(A1), new_co); - cell->setPort(ID(B1), State::S0); + cell->setPort(TW::CI, State::S1); + cell->setPort(TW::A1, new_co); + cell->setPort(TW::B1, State::S0); j = 1; } else { - if (c.second.at(i)->hasPort(ID(CO))) - cell->setPort(ID(CO), c.second.at(i)->getPort(ID(CO))); + if (c.second.at(i)->hasPort(TW(CO))) + cell->setPort(TW::CO, c.second.at(i)->getPort(TW::CO)); } cnt++; } - cell->setPort(names_A[j], get_bit_or_zero(c.second.at(i)->getPort(ID(A)))); - cell->setPort(names_B[j], get_bit_or_zero(c.second.at(i)->getPort(ID(B)))); + cell->setPort(names_A[j], get_bit_or_zero(c.second.at(i)->getPort(TW::A))); + cell->setPort(names_B[j], get_bit_or_zero(c.second.at(i)->getPort(TW::B))); - if (c.second.at(i)->hasPort(ID(S))) - cell->setPort(names_S[j], c.second.at(i)->getPort(ID(S))); + if (c.second.at(i)->hasPort(TW(S))) + cell->setPort(names_S[j], c.second.at(i)->getPort(TW::S)); j = (j + 1) % 4; module->remove(c.second.at(i)); diff --git a/techlibs/quicklogic/ql_bram_types.cc b/techlibs/quicklogic/ql_bram_types.cc index 2599303bd..c525afcfa 100644 --- a/techlibs/quicklogic/ql_bram_types.cc +++ b/techlibs/quicklogic/ql_bram_types.cc @@ -155,7 +155,7 @@ struct QlBramTypesPass : public Pass { } cell->type = RTLIL::escape_id(type); - log_debug("Changed type of memory cell %s to %s\n", cell->name.unescape(), cell->type.unescape()); + log_debug("Changed type of memory cell %s to %s\n", cell->module->design->twines.str(cell->meta_->name), cell->type.unescape()); } } diff --git a/techlibs/quicklogic/ql_dsp_io_regs.cc b/techlibs/quicklogic/ql_dsp_io_regs.cc index d7255d761..ee3e46bb2 100644 --- a/techlibs/quicklogic/ql_dsp_io_regs.cc +++ b/techlibs/quicklogic/ql_dsp_io_regs.cc @@ -84,13 +84,13 @@ struct QlDspIORegs : public Pass { if (!cell->hasPort(cfg_port) || !sigmap(cell->getPort(cfg_port)).is_fully_const()) log_error("Missing or non-constant '%s' port on DSP cell %s\n", cfg_port, cell); - int reg_in_i = sigmap(cell->getPort(ID(register_inputs))).as_int(); - int out_sel_i = sigmap(cell->getPort(ID(output_select))).as_int(); + int reg_in_i = sigmap(cell->getPort(TW::register_inputs)).as_int(); + int out_sel_i = sigmap(cell->getPort(TW::output_select)).as_int(); // Get the feedback port - if (!cell->hasPort(ID(feedback))) + if (!cell->hasPort(TW(feedback))) log_error("Missing 'feedback' port on %s", cell); - SigSpec feedback = sigmap(cell->getPort(ID(feedback))); + SigSpec feedback = sigmap(cell->getPort(TW::feedback)); // Check the top two bits on 'feedback' to be constant zero. // That's what we are expecting from inference. @@ -132,7 +132,7 @@ struct QlDspIORegs : public Pass { std::vector ports2del; if (del_clk) - cell->unsetPort(ID(clk)); + cell->unsetPort(TW::clk); switch (out_sel_i) { case 0: diff --git a/techlibs/quicklogic/ql_dsp_macc.cc b/techlibs/quicklogic/ql_dsp_macc.cc index ca6daa94d..46dd90de3 100644 --- a/techlibs/quicklogic/ql_dsp_macc.cc +++ b/techlibs/quicklogic/ql_dsp_macc.cc @@ -32,9 +32,9 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm) auto &st = pm.st_ql_dsp_macc; // Get port widths - size_t a_width = GetSize(st.mul->getPort(ID(A))); - size_t b_width = GetSize(st.mul->getPort(ID(B))); - size_t z_width = GetSize(st.ff->getPort(ID(Q))); + size_t a_width = GetSize(st.mul->getPort(TW::A)); + size_t b_width = GetSize(st.mul->getPort(TW::B)); + size_t z_width = GetSize(st.ff->getPort(TW::Q)); size_t min_width = std::min(a_width, b_width); size_t max_width = std::max(a_width, b_width); @@ -87,9 +87,9 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm) // Get input/output data signals RTLIL::SigSpec sig_a, sig_b, sig_z; - sig_a = st.mul->getPort(ID(A)); - sig_b = st.mul->getPort(ID(B)); - sig_z = st.output_registered ? st.ff->getPort(ID(Q)) : st.ff->getPort(ID(D)); + sig_a = st.mul->getPort(TW::A); + sig_b = st.mul->getPort(TW::B); + sig_z = st.output_registered ? st.ff->getPort(TW::Q) : st.ff->getPort(TW::D); if (a_width < b_width) std::swap(sig_a, sig_b); @@ -97,80 +97,80 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm) // Connect input data ports, sign extend / pad with zeros sig_a.extend_u0(tgt_a_width, ab_signed); sig_b.extend_u0(tgt_b_width, ab_signed); - cell->setPort(ID(a_i), sig_a); - cell->setPort(ID(b_i), sig_b); + cell->setPort(TW::a_i, sig_a); + cell->setPort(TW::b_i, sig_b); // Connect output data port, pad if needed if ((size_t) GetSize(sig_z) < tgt_z_width) { auto *wire = pm.module->addWire(NEW_TWINE, tgt_z_width - GetSize(sig_z)); sig_z.append(wire); } - cell->setPort(ID(z_o), sig_z); + cell->setPort(TW::z_o, sig_z); // Connect clock, reset and enable - cell->setPort(ID(clock_i), st.ff->getPort(ID(CLK))); + cell->setPort(TW::clock_i, st.ff->getPort(TW::CLK)); RTLIL::SigSpec rst; RTLIL::SigSpec ena; - if (st.ff->hasPort(ID(ARST))) { + if (st.ff->hasPort(TW(ARST))) { if (st.ff->getParam(ID(ARST_POLARITY)).as_int() != 1) { - rst = pm.module->Not(NEW_ID, st.ff->getPort(ID(ARST))); + rst = pm.module->Not(NEW_TWINE, st.ff->getPort(TW::ARST)); } else { - rst = st.ff->getPort(ID(ARST)); + rst = st.ff->getPort(TW::ARST); } } else { rst = RTLIL::SigSpec(RTLIL::S0); } - if (st.ff->hasPort(ID(EN))) { + if (st.ff->hasPort(TW(EN))) { if (st.ff->getParam(ID(EN_POLARITY)).as_int() != 1) { - ena = pm.module->Not(NEW_ID, st.ff->getPort(ID(EN))); + ena = pm.module->Not(NEW_TWINE, st.ff->getPort(TW::EN)); } else { - ena = st.ff->getPort(ID(EN)); + ena = st.ff->getPort(TW::EN); } } else { ena = RTLIL::SigSpec(RTLIL::S1); } - cell->setPort(ID(reset_i), rst); - cell->setPort(ID(load_acc_i), ena); + cell->setPort(TW::reset_i, rst); + cell->setPort(TW::load_acc_i, ena); // Insert feedback_i control logic used for clearing / loading the accumulator if (st.mux_in_pattern) { - RTLIL::SigSpec sig_s = st.mux->getPort(ID(S)); + RTLIL::SigSpec sig_s = st.mux->getPort(TW::S); // Depending on the mux port ordering insert inverter if needed log_assert(st.mux_ab.in(ID(A), ID(B))); if (st.mux_ab == ID(A)) - sig_s = pm.module->Not(NEW_ID, sig_s); + sig_s = pm.module->Not(NEW_TWINE, sig_s); // Assemble the full control signal for the feedback_i port RTLIL::SigSpec sig_f; sig_f.append(sig_s); sig_f.append(RTLIL::S0); sig_f.append(RTLIL::S0); - cell->setPort(ID(feedback_i), sig_f); + cell->setPort(TW::feedback_i, sig_f); } // No acc clear/load else { - cell->setPort(ID(feedback_i), RTLIL::SigSpec(RTLIL::S0, 3)); + cell->setPort(TW::feedback_i, RTLIL::SigSpec(RTLIL::S0, 3)); } // Connect control ports - cell->setPort(ID(unsigned_a_i), RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1)); - cell->setPort(ID(unsigned_b_i), RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1)); + cell->setPort(TW::unsigned_a_i, RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1)); + cell->setPort(TW::unsigned_b_i, RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1)); // Connect config bits - cell->setPort(ID(saturate_enable_i), RTLIL::SigSpec(RTLIL::S0)); - cell->setPort(ID(shift_right_i), RTLIL::SigSpec(RTLIL::S0, 6)); - cell->setPort(ID(round_i), RTLIL::SigSpec(RTLIL::S0)); - cell->setPort(ID(register_inputs_i), RTLIL::SigSpec(RTLIL::S0)); + cell->setPort(TW::saturate_enable_i, RTLIL::SigSpec(RTLIL::S0)); + cell->setPort(TW::shift_right_i, RTLIL::SigSpec(RTLIL::S0, 6)); + cell->setPort(TW::round_i, RTLIL::SigSpec(RTLIL::S0)); + cell->setPort(TW::register_inputs_i, RTLIL::SigSpec(RTLIL::S0)); // 3 - output post acc; 1 - output pre acc - cell->setPort(ID(output_select_i), RTLIL::Const(st.output_registered ? 1 : 3, 3)); + cell->setPort(TW::output_select_i, RTLIL::Const(st.output_registered ? 1 : 3, 3)); bool subtract = (st.add->type == ID($sub)); - cell->setPort(ID(subtract_i), RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0)); + cell->setPort(TW::subtract_i, RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0)); // Mark the cells for removal pm.autoremove(st.mul); diff --git a/techlibs/quicklogic/ql_dsp_simd.cc b/techlibs/quicklogic/ql_dsp_simd.cc index 21420002e..97c36dd22 100644 --- a/techlibs/quicklogic/ql_dsp_simd.cc +++ b/techlibs/quicklogic/ql_dsp_simd.cc @@ -206,7 +206,7 @@ struct QlDspSimdPass : public Pass { // Enable the fractured mode by connecting the control // port. - simd->setPort(ID(f_mode), State::S1); + simd->setPort(TW::f_mode, State::S1); simd->setParam(ID(MODE_BITS), mode_bits); log_assert(mode_bits.size() == m_ModeBitsSize); diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc index c15b9e710..0e55f3672 100644 --- a/techlibs/xilinx/xilinx_dffopt.cc +++ b/techlibs/xilinx/xilinx_dffopt.cc @@ -153,22 +153,22 @@ struct XilinxDffOptPass : public Pass { SigBit sigout = sigmap(cell->getPort(TW::O)); const Const &init = cell->getParam(ID::INIT); std::vector sigin; - sigin.push_back(sigmap(cell->getPort(ID(I0)))); + sigin.push_back(sigmap(cell->getPort(TW::I0))); if (cell->type == ID(LUT1)) goto lut_sigin_done; - sigin.push_back(sigmap(cell->getPort(ID(I1)))); + sigin.push_back(sigmap(cell->getPort(TW::I1))); if (cell->type == ID(LUT2)) goto lut_sigin_done; - sigin.push_back(sigmap(cell->getPort(ID(I2)))); + sigin.push_back(sigmap(cell->getPort(TW::I2))); if (cell->type == ID(LUT3)) goto lut_sigin_done; - sigin.push_back(sigmap(cell->getPort(ID(I3)))); + sigin.push_back(sigmap(cell->getPort(TW::I3))); if (cell->type == ID(LUT4)) goto lut_sigin_done; - sigin.push_back(sigmap(cell->getPort(ID(I4)))); + sigin.push_back(sigmap(cell->getPort(TW::I4))); if (cell->type == ID(LUT5)) goto lut_sigin_done; - sigin.push_back(sigmap(cell->getPort(ID(I5)))); + sigin.push_back(sigmap(cell->getPort(TW::I5))); lut_sigin_done: bit_to_lut[sigout] = make_pair(LutData(init, sigin), cell); } @@ -224,7 +224,7 @@ lut_sigin_done: // First, unmap CE. SigBit sig_Q = sigmap(cell->getPort(TW::Q)); - SigBit sig_CE = sigmap(cell->getPort(ID(CE))); + SigBit sig_CE = sigmap(cell->getPort(TW::CE)); LutData lut_ce = LutData(Const(2, 2), {sig_CE}); auto it_CE = bit_to_lut.find(sig_CE); if (it_CE != bit_to_lut.end()) @@ -316,7 +316,7 @@ unmap: cell->unsetParam(ID(IS_S_INVERTED)); cell->setPort(TW::S, Const(0, 1)); } - cell->setPort(ID(CE), Const(1, 1)); + cell->setPort(TW::CE, Const(1, 1)); cell->unsetParam(ID(IS_D_INVERTED)); // Create the new LUT. @@ -348,17 +348,17 @@ unmap: lut_cell->setParam(ID::INIT, final_lut.first); cell->setPort(TW::D, lut_out); lut_cell->setPort(TW::O, lut_out); - lut_cell->setPort(ID(I0), final_lut.second[0]); + lut_cell->setPort(TW::I0, final_lut.second[0]); if (GetSize(final_lut.second) >= 2) - lut_cell->setPort(ID(I1), final_lut.second[1]); + lut_cell->setPort(TW::I1, final_lut.second[1]); if (GetSize(final_lut.second) >= 3) - lut_cell->setPort(ID(I2), final_lut.second[2]); + lut_cell->setPort(TW::I2, final_lut.second[2]); if (GetSize(final_lut.second) >= 4) - lut_cell->setPort(ID(I3), final_lut.second[3]); + lut_cell->setPort(TW::I3, final_lut.second[3]); if (GetSize(final_lut.second) >= 5) - lut_cell->setPort(ID(I4), final_lut.second[4]); + lut_cell->setPort(TW::I4, final_lut.second[4]); if (GetSize(final_lut.second) >= 6) - lut_cell->setPort(ID(I5), final_lut.second[5]); + lut_cell->setPort(TW::I5, final_lut.second[5]); } } } diff --git a/techlibs/xilinx/xilinx_dsp.cc b/techlibs/xilinx/xilinx_dsp.cc index 0dbeb9920..725a1c28a 100644 --- a/techlibs/xilinx/xilinx_dsp.cc +++ b/techlibs/xilinx/xilinx_dsp.cc @@ -53,14 +53,14 @@ static Cell* addDsp(Module *module) { cell->setParam(ID(USE_DPORT), Const("FALSE")); cell->setPort(TW::D, Const(0, 25)); - cell->setPort(ID(INMODE), Const(0, 5)); - cell->setPort(ID(ALUMODE), Const(0, 4)); - cell->setPort(ID(OPMODE), Const(0, 7)); - cell->setPort(ID(CARRYINSEL), Const(0, 3)); - cell->setPort(ID(ACIN), Const(0, 30)); - cell->setPort(ID(BCIN), Const(0, 18)); - cell->setPort(ID(PCIN), Const(0, 48)); - cell->setPort(ID(CARRYIN), Const(0, 1)); + cell->setPort(TW::INMODE, Const(0, 5)); + cell->setPort(TW::ALUMODE, Const(0, 4)); + cell->setPort(TW::OPMODE, Const(0, 7)); + cell->setPort(TW::CARRYINSEL, Const(0, 3)); + cell->setPort(TW::ACIN, Const(0, 30)); + cell->setPort(TW::BCIN, Const(0, 18)); + cell->setPort(TW::PCIN, Const(0, 48)); + cell->setPort(TW::CARRYIN, Const(0, 1)); return cell; } @@ -190,7 +190,7 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector & // X = A:B // Y = 0 // Z = C - cell->setPort(ID(OPMODE), Const::from_string("0110011")); + cell->setPort(TW::OPMODE, Const::from_string("0110011")); log_assert(lane1); log_assert(lane2); @@ -221,9 +221,9 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector & cell->setPort(TW::B, AB.extract(0, 18)); cell->setPort(TW::C, C); cell->setPort(TW::P, P); - cell->setPort(ID(CARRYOUT), CARRYOUT); + cell->setPort(TW::CARRYOUT, CARRYOUT); if (lane1->type == ID($sub)) - cell->setPort(ID(ALUMODE), Const::from_string("0011")); + cell->setPort(TW::ALUMODE, Const::from_string("0011")); module->remove(lane1); module->remove(lane2); @@ -271,7 +271,7 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector & // X = A:B // Y = 0 // Z = C - cell->setPort(ID(OPMODE), Const::from_string("0110011")); + cell->setPort(TW::OPMODE, Const::from_string("0110011")); log_assert(lane1); log_assert(lane2); @@ -285,9 +285,9 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector & cell->setPort(TW::B, AB.extract(0, 18)); cell->setPort(TW::C, C); cell->setPort(TW::P, P); - cell->setPort(ID(CARRYOUT), CARRYOUT); + cell->setPort(TW::CARRYOUT, CARRYOUT); if (lane1->type == ID($sub)) - cell->setPort(ID(ALUMODE), Const::from_string("0011")); + cell->setPort(TW::ALUMODE, Const::from_string("0011")); module->remove(lane1); module->remove(lane2); @@ -335,18 +335,18 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) cell->setPort(TW::A, st.sigA); cell->setPort(TW::D, st.sigD); if (preAdder->type == ID($add)) - cell->setPort(ID(INMODE), Const::from_string("00100")); + cell->setPort(TW::INMODE, Const::from_string("00100")); else - cell->setPort(ID(INMODE), Const::from_string("01100")); + cell->setPort(TW::INMODE, Const::from_string("01100")); if (st.ffAD) { if (st.ffAD->type.in(ID($dffe), ID($sdffe))) { bool pol = st.ffAD->getParam(ID::EN_POLARITY).as_bool(); SigSpec S = st.ffAD->getPort(TW::EN); - cell->setPort(ID(CEAD), pol ? S : pm.module->Not(NEW_ID, S)); + cell->setPort(TW::CEAD, pol ? S : pm.module->Not(NEW_TWINE, S)); } else - cell->setPort(ID(CEAD), State::S1); + cell->setPort(TW::CEAD, State::S1); cell->setParam(ID(ADREG), 1); } @@ -402,7 +402,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) cell->setParam(ID(MASK), B); cell->setParam(ID(PATTERN), Const(0, 48)); - cell->setPort(ID(OVERFLOW), st.overflow->getPort(TW::Y)); + cell->setPort(TW::OVERFLOW, st.overflow->getPort(TW::Y)); } else log_abort(); @@ -422,7 +422,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) if (ff->type.in(ID($sdff), ID($sdffe))) { SigSpec srst = ff->getPort(TW::SRST); bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool(); - cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst)); + cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_TWINE, srst)); } else { cell->setPort(rstport, State::S0); } @@ -430,7 +430,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm) if (ff->type.in(ID($dffe), ID($sdffe))) { SigSpec ce = ff->getPort(TW::EN); bool cepol = ff->getParam(ID::EN_POLARITY).as_bool(); - cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce)); + cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_TWINE, ce)); } else cell->setPort(ceport, State::S1); @@ -609,7 +609,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) if (ff->type.in(ID($sdff), ID($sdffe))) { SigSpec srst = ff->getPort(TW::SRST); bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool(); - cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst)); + cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_TWINE, srst)); } else { cell->setPort(rstport, State::S0); } @@ -617,7 +617,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm) if (ff->type.in(ID($dffe), ID($sdffe))) { SigSpec ce = ff->getPort(TW::EN); bool cepol = ff->getParam(ID::EN_POLARITY).as_bool(); - cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce)); + cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_TWINE, ce)); } else cell->setPort(ceport, State::S1); @@ -732,7 +732,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm) if (ff->type.in(ID($sdff), ID($sdffe))) { SigSpec srst = ff->getPort(TW::SRST); bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool(); - cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst)); + cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_TWINE, srst)); } else { cell->setPort(rstport, State::S0); } @@ -740,7 +740,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm) if (ff->type.in(ID($dffe), ID($sdffe))) { SigSpec ce = ff->getPort(TW::EN); bool cepol = ff->getParam(ID::EN_POLARITY).as_bool(); - cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce)); + cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_TWINE, ce)); } else cell->setPort(ceport, State::S1); diff --git a/techlibs/xilinx/xilinx_srl.cc b/techlibs/xilinx/xilinx_srl.cc index 5c7e5391a..74139784e 100644 --- a/techlibs/xilinx/xilinx_srl.cc +++ b/techlibs/xilinx/xilinx_srl.cc @@ -93,7 +93,7 @@ void run_fixed(xilinx_srl_pm &pm) else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) c->setPort(TW::E, first_cell->getPort(TW::E)); else if (first_cell->type.in(ID(FDRE), ID(FDRE_1))) - c->setPort(TW::E, first_cell->getPort(ID(CE))); + c->setPort(TW::E, first_cell->getPort(TW::CE)); else log_abort(); } diff --git a/techlibs/xilinx/xilinx_srl.pmg b/techlibs/xilinx/xilinx_srl.pmg index 585400725..b553aeaaa 100644 --- a/techlibs/xilinx/xilinx_srl.pmg +++ b/techlibs/xilinx/xilinx_srl.pmg @@ -41,13 +41,13 @@ generate break; case 2: case 3: - cell = module->addDffGate(NEW_ID, C, D, Q, r & 1); + cell = module->addDffGate(NEW_TWINE, C, D, Q, r & 1); break; case 4: case 5: case 6: case 7: - cell = module->addDffeGate(NEW_ID, C, module->addWire(NEW_TWINE), D, Q, r & 1, r & 2); + cell = module->addDffeGate(NEW_TWINE, C, module->addWire(NEW_TWINE), D, Q, r & 1, r & 2); break; default: log_abort(); } @@ -191,7 +191,7 @@ match shiftx filter param(shiftx, \A_WIDTH).as_int() >= minlen generate minlen = 3; - module->addShiftx(NEW_ID, module->addWire(NEW_TWINE, rng(6)+minlen), module->addWire(NEW_TWINE, 3), module->addWire(NEW_TWINE)); + module->addShiftx(NEW_TWINE, module->addWire(NEW_TWINE, rng(6)+minlen), module->addWire(NEW_TWINE, 3), module->addWire(NEW_TWINE)); endmatch code shiftx_width @@ -217,18 +217,18 @@ generate { case 0: case 1: - cell = module->addDff(NEW_ID, C, D, Q, r & 1); + cell = module->addDff(NEW_TWINE, C, D, Q, r & 1); break; case 2: case 3: case 4: case 5: - //cell = module->addDffe(NEW_ID, C, module->addWire(NEW_TWINE), D, Q, r & 1, r & 4); + //cell = module->addDffe(NEW_TWINE, C, module->addWire(NEW_TWINE), D, Q, r & 1, r & 4); //break; case 6: case 7: WIDTH = 1; - cell = module->addDffGate(NEW_ID, C, D[0], Q[0], r & 1); + cell = module->addDffGate(NEW_TWINE, C, D[0], Q[0], r & 1); break; default: log_abort(); } @@ -297,9 +297,9 @@ generate else { auto D = module->addWire(NEW_TWINE, WIDTH); if (back->type == $dff) - module->addDff(NEW_ID, port(back, \CLK), D, port(back, \D), param(back, \CLK_POLARITY).as_bool()); + module->addDff(NEW_TWINE, port(back, \CLK), D, port(back, \D), param(back, \CLK_POLARITY).as_bool()); else if (back->type == $dffe) - module->addDffe(NEW_ID, port(back, \CLK), port(back, \EN), D, port(back, \D), param(back, \CLK_POLARITY).as_bool(), param(back, \EN_POLARITY).as_bool()); + module->addDffe(NEW_TWINE, port(back, \CLK), port(back, \EN), D, port(back, \D), param(back, \CLK_POLARITY).as_bool(), param(back, \EN_POLARITY).as_bool()); else log_abort(); }