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https://github.com/YosysHQ/yosys
synced 2026-07-26 09:02:37 +00:00
WIP
This commit is contained in:
Emil J. Tywoniak
parent
f592f2f3af
commit
8e522b08c0
206 changed files with 3081 additions and 2782 deletions
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@ -142,16 +142,16 @@ struct MicrochipDffOptPass : public Pass {
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SigBit sigout = sigmap(cell->getPort(TW::Y));
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const Const &init = cell->getParam(ID::INIT);
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std::vector<SigBit> sigin;
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sigin.push_back(sigmap(cell->getPort(ID(A))));
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sigin.push_back(sigmap(cell->getPort(TW::A)));
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if (cell->type == ID(CFG1))
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goto lut_sigin_done;
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sigin.push_back(sigmap(cell->getPort(ID(B))));
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sigin.push_back(sigmap(cell->getPort(TW::B)));
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if (cell->type == ID(CFG2))
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goto lut_sigin_done;
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sigin.push_back(sigmap(cell->getPort(ID(C))));
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sigin.push_back(sigmap(cell->getPort(TW::C)));
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if (cell->type == ID(CFG3))
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goto lut_sigin_done;
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sigin.push_back(sigmap(cell->getPort(ID(D))));
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sigin.push_back(sigmap(cell->getPort(TW::D)));
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lut_sigin_done:
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bit_to_lut[sigout] = make_pair(LutData(init, sigin), cell);
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@ -167,16 +167,16 @@ struct MicrochipDffOptPass : public Pass {
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if (!cell->type.in(ID(SLE))) // not a SLE
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continue;
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if (cell->getPort(ID(LAT)).is_fully_ones()) // skip latch
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if (cell->getPort(TW::LAT).is_fully_ones()) // skip latch
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continue;
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if (cell->get_bool_attribute(ID::keep)) // keep attribute
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continue;
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if (!cell->getPort(ID(ALn)).is_fully_ones()) // async FF
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if (!cell->getPort(TW::ALn).is_fully_ones()) // async FF
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continue;
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const bool hasSyncLoad = cell->getPort(ID(SLn)).is_wire();
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const bool has_s = hasSyncLoad && cell->getPort(ID(SD)).is_fully_ones();
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const bool has_r = hasSyncLoad && cell->getPort(ID(SD)).is_fully_zero();
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const bool hasSyncLoad = cell->getPort(TW::SLn).is_wire();
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const bool has_s = hasSyncLoad && cell->getPort(TW::SD).is_fully_ones();
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const bool has_r = hasSyncLoad && cell->getPort(TW::SD).is_fully_zero();
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// SLE cannot have both synchronous set and reset implemented at the same time
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log_assert(!(has_s && has_r));
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@ -202,7 +202,7 @@ struct MicrochipDffOptPass : public Pass {
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// First, unmap CE.
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SigBit sig_Q = sigmap(cell->getPort(TW::Q));
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SigBit sig_CE = sigmap(cell->getPort(ID(EN)));
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SigBit sig_CE = sigmap(cell->getPort(TW::EN));
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LutData lut_ce = LutData(Const(2, 2), {sig_CE}); // INIT = 10
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auto it_CE = bit_to_lut.find(sig_CE);
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if (it_CE != bit_to_lut.end())
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@ -227,7 +227,7 @@ struct MicrochipDffOptPass : public Pass {
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// Second, unmap S, if any.
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lut_d_post_s = lut_d_post_ce;
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if (has_s) {
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SigBit sig_S = sigmap(cell->getPort(ID(SLn)));
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SigBit sig_S = sigmap(cell->getPort(TW::SLn));
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LutData lut_s = LutData(Const(2, 2), {sig_S}); // INIT = 10
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bool inv_s = true; // active low
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auto it_S = bit_to_lut.find(sig_S);
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@ -250,7 +250,7 @@ struct MicrochipDffOptPass : public Pass {
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// Third, unmap R, if any.
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lut_d_post_r = lut_d_post_s;
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if (has_r) {
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SigBit sig_R = sigmap(cell->getPort(ID(SLn)));
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SigBit sig_R = sigmap(cell->getPort(TW::SLn));
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LutData lut_r = LutData(Const(2, 2), {sig_R}); // INIT = 10
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bool inv_r = true; // active low
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auto it_R = bit_to_lut.find(sig_R);
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@ -299,11 +299,11 @@ struct MicrochipDffOptPass : public Pass {
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// Okay, we're doing it. Unmap ports.
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if ((has_s && worthy_post_s) || worthy_post_r) {
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cell->setPort(ID(SLn), Const(1, 1));
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cell->setPort(TW::SLn, Const(1, 1));
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}
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// if we made it this far, clk enable is always merged into D
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cell->setPort(ID(EN), Const(1, 1));
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cell->setPort(TW::EN, Const(1, 1));
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// Create the new LUT.
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Cell *lut_cell = nullptr;
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@ -328,13 +328,13 @@ struct MicrochipDffOptPass : public Pass {
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lut_cell->setParam(ID::INIT, final_lut.first);
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cell->setPort(TW::D, lut_out);
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lut_cell->setPort(TW::Y, lut_out);
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lut_cell->setPort(ID(A), final_lut.second[0]);
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lut_cell->setPort(TW::A, final_lut.second[0]);
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if (GetSize(final_lut.second) >= 2)
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lut_cell->setPort(ID(B), final_lut.second[1]);
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lut_cell->setPort(TW::B, final_lut.second[1]);
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if (GetSize(final_lut.second) >= 3)
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lut_cell->setPort(ID(C), final_lut.second[2]);
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lut_cell->setPort(TW::C, final_lut.second[2]);
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if (GetSize(final_lut.second) >= 4)
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lut_cell->setPort(ID(D), final_lut.second[3]);
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lut_cell->setPort(TW::D, final_lut.second[3]);
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}
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}
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}
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@ -72,7 +72,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
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log_assert(!"strange post-adder type");
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if (st.useFeedBack) {
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cell->setPort(ID(CDIN_FDBK_SEL), {State::S0, State::S1});
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cell->setPort(TW::CDIN_FDBK_SEL, {State::S0, State::S1});
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} else {
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st.sigC.extend_u0(48, st.postAdderStatic->getParam(ID::A_SIGNED).as_bool());
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cell->setPort(TW::C, st.sigC);
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@ -98,12 +98,12 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
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SigSpec srst = ff->getPort(TW::SRST);
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bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool();
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// active low sync rst
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cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_ID, srst));
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cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_TWINE, srst));
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} else if (ff->type.in(ID($adff), ID($adffe))) {
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SigSpec arst = ff->getPort(TW::ARST);
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bool rstpol_n = !ff->getParam(ID::ARST_POLARITY).as_bool();
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// active low async rst
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cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_ID, arst));
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cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_TWINE, arst));
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} else {
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// active low async/sync rst
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cell->setPort(rstport, State::S1);
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@ -113,7 +113,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
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SigSpec ce = ff->getPort(TW::EN);
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bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
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// enables are all active high
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cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
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cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_TWINE, ce));
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} else {
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// enables are all active high
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cell->setPort(ceport, State::S1);
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@ -214,12 +214,12 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
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SigSpec srst = ff->getPort(TW::SRST);
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bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool();
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// active low sync rst
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cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_ID, srst));
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cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_TWINE, srst));
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} else if (ff->type.in(ID($adff), ID($adffe))) {
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SigSpec arst = ff->getPort(TW::ARST);
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bool rstpol_n = !ff->getParam(ID::ARST_POLARITY).as_bool();
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// active low async rst
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cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_ID, arst));
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cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_TWINE, arst));
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} else {
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// active low async/sync rst
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cell->setPort(rstport, State::S1);
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@ -229,7 +229,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
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SigSpec ce = ff->getPort(TW::EN);
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bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
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// enables are all active high
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cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
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cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_TWINE, ce));
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} else {
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// enables are all active high
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cell->setPort(ceport, State::S1);
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