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This commit is contained in:
Emil J. Tywoniak 2026-06-11 13:17:54 +02:00
parent f592f2f3af
commit 8e522b08c0
206 changed files with 3081 additions and 2782 deletions
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26
techlibs/anlogic/anlogic_fixcarry.cc
View file

@ -41,11 +41,11 @@ static void fix_carry_chain(Module *module)
{
if (cell->type == ID(AL_MAP_ADDER)) {
if (cell->getParam(ID(ALUTYPE)) != Const("ADD")) continue;
SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(a)));
SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(b)));
SigBit bit_i0 = get_bit_or_zero(cell->getPort(TW::a));
SigBit bit_i1 = get_bit_or_zero(cell->getPort(TW::b));
if (bit_i0 == State::S0 && bit_i1== State::S0) {
SigBit bit_ci = get_bit_or_zero(cell->getPort(ID(c)));
SigSpec o = cell->getPort(ID(o));
SigBit bit_ci = get_bit_or_zero(cell->getPort(TW::c));
SigSpec o = cell->getPort(TW::o);
if (GetSize(o) == 2) {
SigBit bit_o = o[0];
ci_bits.insert(bit_ci);
@ -59,9 +59,9 @@ static void fix_carry_chain(Module *module)
{
if (cell->type == ID(AL_MAP_ADDER)) {
if (cell->getParam(ID(ALUTYPE)) != Const("ADD")) continue;
SigBit bit_ci = get_bit_or_zero(cell->getPort(ID(c)));
SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(a)));
SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(b)));
SigBit bit_ci = get_bit_or_zero(cell->getPort(TW::c));
SigBit bit_i0 = get_bit_or_zero(cell->getPort(TW::a));
SigBit bit_i1 = get_bit_or_zero(cell->getPort(TW::b));
SigBit canonical_bit = sigmap(bit_ci);
if (!ci_bits.count(canonical_bit))
continue;
@ -75,7 +75,7 @@ static void fix_carry_chain(Module *module)
for (auto cell : adders_to_fix_cells)
{
SigBit bit_ci = get_bit_or_zero(cell->getPort(ID(c)));
SigBit bit_ci = get_bit_or_zero(cell->getPort(TW::c));
SigBit canonical_bit = sigmap(bit_ci);
auto bit = mapping_bits.at(canonical_bit);
log("Fixing %s cell named %s breaking carry chain.\n", cell->type.unescape(), cell);
@ -86,12 +86,12 @@ static void fix_carry_chain(Module *module)
bits.append(dummy_bit);
bits.append(new_bit);
c->setParam(ID(ALUTYPE), Const("ADD_CARRY"));
c->setPort(ID(a), bit);
c->setPort(ID(b), State::S0);
c->setPort(ID(c), State::S0);
c->setPort(ID(o), bits);
c->setPort(TW::a, bit);
c->setPort(TW::b, State::S0);
c->setPort(TW::c, State::S0);
c->setPort(TW::o, bits);
cell->setPort(ID(c), new_bit);
cell->setPort(TW::c, new_bit);
}
}

46
techlibs/coolrunner2/coolrunner2_fixup.cc
View file

@ -36,7 +36,7 @@ RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cel
module->uniquify(stringf("$xc2fix$%s_BUF1_XOR", cellname)),
ID(MACROCELL_XOR));
xor_cell->setParam(ID(INVERT_OUT), true);
xor_cell->setPort(ID(OUT), outwire);
xor_cell->setPort(TW::OUT, outwire);
}
else if (inwire == SigBit(false))
{
@ -47,7 +47,7 @@ RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cel
module->uniquify(stringf("$xc2fix$%s_BUF0_XOR", cellname)),
ID(MACROCELL_XOR));
xor_cell->setParam(ID(INVERT_OUT), false);
xor_cell->setPort(ID(OUT), outwire);
xor_cell->setPort(TW::OUT, outwire);
}
else if (inwire == SigBit(RTLIL::State::Sx))
{
@ -59,7 +59,7 @@ RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cel
module->uniquify(stringf("$xc2fix$%s_BUF0_XOR", cellname)),
ID(MACROCELL_XOR));
xor_cell->setParam(ID(INVERT_OUT), false);
xor_cell->setPort(ID(OUT), outwire);
xor_cell->setPort(TW::OUT, outwire);
}
else
{
@ -76,16 +76,16 @@ RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cel
ID(ANDTERM));
and_cell->setParam(ID(TRUE_INP), 1);
and_cell->setParam(ID(COMP_INP), 0);
and_cell->setPort(ID(OUT), and_to_xor_wire);
and_cell->setPort(ID(IN), inwire);
and_cell->setPort(ID(IN_B), SigSpec());
and_cell->setPort(TW::OUT, and_to_xor_wire);
and_cell->setPort(TW::IN, inwire);
and_cell->setPort(TW::IN_B, SigSpec());
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF_XOR", inwire_name)),
ID(MACROCELL_XOR));
xor_cell->setParam(ID(INVERT_OUT), false);
xor_cell->setPort(ID(IN_PTC), and_to_xor_wire);
xor_cell->setPort(ID(OUT), outwire);
xor_cell->setPort(TW::IN_PTC, and_to_xor_wire);
xor_cell->setPort(TW::OUT, outwire);
}
return outwire;
@ -103,9 +103,9 @@ RTLIL::Wire *makeptermbuffer(RTLIL::Module *module, SigBit inwire)
ID(ANDTERM));
and_cell->setParam(ID(TRUE_INP), 1);
and_cell->setParam(ID(COMP_INP), 0);
and_cell->setPort(ID(OUT), outwire);
and_cell->setPort(ID(IN), inwire);
and_cell->setPort(ID(IN_B), SigSpec());
and_cell->setPort(TW::OUT, outwire);
and_cell->setPort(TW::IN, inwire);
and_cell->setPort(TW::IN_B, SigSpec());
return outwire;
}
@ -147,7 +147,7 @@ struct Coolrunner2FixupPass : public Pass {
{
if (cell->type == ID(MACROCELL_XOR))
{
auto output = sigmap(cell->getPort(ID(OUT))[0]);
auto output = sigmap(cell->getPort(TW::OUT)[0]);
sig_fed_by_xor.insert(output);
}
}
@ -158,7 +158,7 @@ struct Coolrunner2FixupPass : public Pass {
{
if (cell->type.in(ID(IBUF), ID(IOBUFE)))
{
if (cell->hasPort(ID::O)) {
if (cell->hasPort(TW::O)) {
auto output = sigmap(cell->getPort(TW::O)[0]);
sig_fed_by_io.insert(output);
}
@ -171,7 +171,7 @@ struct Coolrunner2FixupPass : public Pass {
{
if (cell->type == ID(ANDTERM))
{
auto output = sigmap(cell->getPort(ID(OUT))[0]);
auto output = sigmap(cell->getPort(TW::OUT)[0]);
sig_fed_by_pterm.insert(output);
}
}
@ -333,7 +333,7 @@ struct Coolrunner2FixupPass : public Pass {
// Buffering FF set/reset. This can only come from either
// a pterm or a bufgsr.
SigBit set;
set = sigmap(cell->getPort(ID(PRE))[0]);
set = sigmap(cell->getPort(TW::PRE)[0]);
if (set != SigBit(false))
{
if (!sig_fed_by_pterm[set] && !sig_fed_by_bufgsr[set])
@ -342,7 +342,7 @@ struct Coolrunner2FixupPass : public Pass {
auto pterm_to_ff_wire = makeptermbuffer(module, set);
cell->setPort(ID(PRE), pterm_to_ff_wire);
cell->setPort(TW::PRE, pterm_to_ff_wire);
}
}
@ -366,14 +366,14 @@ struct Coolrunner2FixupPass : public Pass {
if (cell->type.in(ID(FDCPE), ID(FDCPE_N), ID(FDDCPE)))
{
SigBit ce;
ce = sigmap(cell->getPort(ID(CE))[0]);
ce = sigmap(cell->getPort(TW::CE)[0]);
if (!sig_fed_by_pterm[ce])
{
log("Buffering clock enable to \"%s\"\n", cell->name);
auto pterm_to_ff_wire = makeptermbuffer(module, ce);
cell->setPort(ID(CE), pterm_to_ff_wire);
cell->setPort(TW::CE, pterm_to_ff_wire);
}
}
}
@ -398,7 +398,7 @@ struct Coolrunner2FixupPass : public Pass {
// Buffer IOBUFE enables. This can only be fed from a pterm
// or a bufgts.
if (cell->hasPort(ID::E))
if (cell->hasPort(TW::E))
{
SigBit oe;
oe = sigmap(cell->getPort(TW::E)[0]);
@ -424,7 +424,7 @@ struct Coolrunner2FixupPass : public Pass {
{
if (cell->type == ID(MACROCELL_XOR))
{
auto output = sigmap(cell->getPort(ID(OUT))[0]);
auto output = sigmap(cell->getPort(TW::OUT)[0]);
xor_out_to_xor_cell[output] = cell;
}
}
@ -456,7 +456,7 @@ struct Coolrunner2FixupPass : public Pass {
module->uniquify(xor_cell->name), xor_cell);
auto new_wire = module->addWire(
module->uniquify(wire_in.wire->name));
new_xor_cell->setPort(ID(OUT), new_wire);
new_xor_cell->setPort(TW::OUT, new_wire);
cell->setPort(conn.first, new_wire);
}
xor_fanout_once.insert(wire_in);
@ -475,7 +475,7 @@ struct Coolrunner2FixupPass : public Pass {
{
if (cell->type == ID(ORTERM))
{
auto output = sigmap(cell->getPort(ID(OUT))[0]);
auto output = sigmap(cell->getPort(TW::OUT)[0]);
or_out_to_or_cell[output] = cell;
}
}
@ -504,7 +504,7 @@ struct Coolrunner2FixupPass : public Pass {
module->uniquify(or_cell->name), or_cell);
auto new_wire = module->addWire(
module->uniquify(wire_in.wire->name));
new_or_cell->setPort(ID(OUT), new_wire);
new_or_cell->setPort(TW::OUT, new_wire);
cell->setPort(conn.first, new_wire);
}
or_fanout_once.insert(wire_in);

32
techlibs/coolrunner2/coolrunner2_sop.cc
View file

@ -63,20 +63,20 @@ struct Coolrunner2SopPass : public Pass {
if (cell->type.in(ID(FDCP), ID(FDCP_N), ID(FDDCP), ID(FTCP), ID(FTCP_N), ID(FTDCP),
ID(FDCPE), ID(FDCPE_N), ID(FDDCPE), ID(LDCP), ID(LDCP_N)))
{
if (cell->hasPort(ID(PRE)))
special_pterms_no_inv[sigmap(cell->getPort(ID(PRE))[0])].insert(
if (cell->hasPort(TW(PRE)))
special_pterms_no_inv[sigmap(cell->getPort(TW::PRE)[0])].insert(
make_tuple(cell, ID(PRE)));
if (cell->hasPort(ID::CLR))
if (cell->hasPort(TW::CLR))
special_pterms_no_inv[sigmap(cell->getPort(TW::CLR)[0])].insert(
make_tuple(cell, ID::CLR));
if (cell->hasPort(ID(CE)))
special_pterms_no_inv[sigmap(cell->getPort(ID(CE))[0])].insert(
if (cell->hasPort(TW(CE)))
special_pterms_no_inv[sigmap(cell->getPort(TW::CE)[0])].insert(
make_tuple(cell, ID(CE)));
if (cell->hasPort(ID::C))
if (cell->hasPort(TW::C))
special_pterms_inv[sigmap(cell->getPort(TW::C)[0])].insert(
make_tuple(cell, ID::C));
if (cell->hasPort(ID::G))
if (cell->hasPort(TW::G))
special_pterms_inv[sigmap(cell->getPort(TW::G)[0])].insert(
make_tuple(cell, ID::G));
}
@ -142,9 +142,9 @@ struct Coolrunner2SopPass : public Pass {
ID(ANDTERM));
and_cell->setParam(ID(TRUE_INP), GetSize(and_in_true));
and_cell->setParam(ID(COMP_INP), GetSize(and_in_comp));
and_cell->setPort(ID(OUT), and_out);
and_cell->setPort(ID(IN), and_in_true);
and_cell->setPort(ID(IN_B), and_in_comp);
and_cell->setPort(TW::OUT, and_out);
and_cell->setPort(TW::IN, and_in_true);
and_cell->setPort(TW::IN_B, and_in_comp);
}
if (sop_depth == 1)
@ -154,8 +154,8 @@ struct Coolrunner2SopPass : public Pass {
module->uniquify(stringf("$xc2sop$%s_XOR", sop_output_wire_name)),
ID(MACROCELL_XOR));
xor_cell->setParam(ID(INVERT_OUT), has_invert);
xor_cell->setPort(ID(IN_PTC), *intermed_wires.begin());
xor_cell->setPort(ID(OUT), sop_output);
xor_cell->setPort(TW::IN_PTC, *intermed_wires.begin());
xor_cell->setPort(TW::OUT, sop_output);
// Special P-term handling
if (is_special_pterm)
@ -205,16 +205,16 @@ struct Coolrunner2SopPass : public Pass {
module->uniquify(stringf("$xc2sop$%s_OR", sop_output_wire_name)),
ID(ORTERM));
or_cell->setParam(ID::WIDTH, sop_depth);
or_cell->setPort(ID(IN), intermed_wires);
or_cell->setPort(ID(OUT), or_to_xor_wire);
or_cell->setPort(TW::IN, intermed_wires);
or_cell->setPort(TW::OUT, or_to_xor_wire);
// Construct the XOR cell
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2sop$%s_XOR", sop_output_wire_name)),
ID(MACROCELL_XOR));
xor_cell->setParam(ID(INVERT_OUT), has_invert);
xor_cell->setPort(ID(IN_ORTERM), or_to_xor_wire);
xor_cell->setPort(ID(OUT), sop_output);
xor_cell->setPort(TW::IN_ORTERM, or_to_xor_wire);
xor_cell->setPort(TW::OUT, sop_output);
}
// Finally, remove the $sop cell

12
techlibs/efinix/efinix_fixcarry.cc
View file

@ -40,8 +40,8 @@ static void fix_carry_chain(Module *module)
for (auto cell : module->cells())
{
if (cell->type == ID(EFX_ADD)) {
SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(I0)));
SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(I1)));
SigBit bit_i0 = get_bit_or_zero(cell->getPort(TW::I0));
SigBit bit_i1 = get_bit_or_zero(cell->getPort(TW::I1));
if (bit_i0 == State::S0 && bit_i1== State::S0) {
SigBit bit_ci = get_bit_or_zero(cell->getPort(TW::CI));
SigBit bit_o = sigmap(cell->getPort(TW::O));
@ -56,8 +56,8 @@ static void fix_carry_chain(Module *module)
{
if (cell->type == ID(EFX_ADD)) {
SigBit bit_ci = get_bit_or_zero(cell->getPort(TW::CI));
SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(I0)));
SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(I1)));
SigBit bit_i0 = get_bit_or_zero(cell->getPort(TW::I0));
SigBit bit_i1 = get_bit_or_zero(cell->getPort(TW::I1));
SigBit canonical_bit = sigmap(bit_ci);
if (!ci_bits.count(canonical_bit))
continue;
@ -79,8 +79,8 @@ static void fix_carry_chain(Module *module)
SigBit new_bit = module->addWire(NEW_TWINE);
c->setParam(ID(I0_POLARITY), State::S1);
c->setParam(ID(I1_POLARITY), State::S1);
c->setPort(ID(I0), bit);
c->setPort(ID(I1), State::S1);
c->setPort(TW::I0, bit);
c->setPort(TW::I1, State::S1);
c->setPort(TW::CI, State::S0);
c->setPort(TW::CO, new_bit);

2
techlibs/gatemate/gatemate_foldinv.cc
View file

@ -141,7 +141,7 @@ struct FoldInvWorker {
auto found_type = lut_types.find(cell->type);
if (found_type == lut_types.end())
continue;
if (!cell->hasPort(ID::O))
if (!cell->hasPort(TW::O))
continue;
auto o_sig = cell->getPort(TW::O);
if (GetSize(o_sig) == 0)

24
techlibs/greenpak4/greenpak4_dffinv.cc
View file

@ -56,14 +56,14 @@ void invert_gp_dff(Cell *cell, bool invert_input)
else
{
if (cell_type_r) {
cell->setPort(ID(nSET), cell->getPort(ID(nRST)));
cell->unsetPort(ID(nRST));
cell->setPort(TW::nSET, cell->getPort(TW::nRST));
cell->unsetPort(TW::nRST);
cell_type_r = false;
cell_type_s = true;
} else
if (cell_type_s) {
cell->setPort(ID(nRST), cell->getPort(ID(nSET)));
cell->unsetPort(ID(nSET));
cell->setPort(TW::nRST, cell->getPort(TW::nSET));
cell->unsetPort(TW::nSET);
cell_type_r = true;
cell_type_s = false;
}
@ -71,11 +71,11 @@ void invert_gp_dff(Cell *cell, bool invert_input)
}
if (cell_type_i) {
cell->setPort(TW::Q, cell->getPort(ID(nQ)));
cell->unsetPort(ID(nQ));
cell->setPort(TW::Q, cell->getPort(TW::nQ));
cell->unsetPort(TW::nQ);
cell_type_i = false;
} else {
cell->setPort(ID(nQ), cell->getPort(TW::Q));
cell->setPort(TW::nQ, cell->getPort(TW::Q));
cell->unsetPort(TW::Q);
cell_type_i = true;
}
@ -164,8 +164,8 @@ struct Greenpak4DffInvPass : public Pass {
}
if (cell->type == ID(GP_INV)) {
SigBit in_bit = sigmap(cell->getPort(ID(IN)));
SigBit out_bit = sigmap(cell->getPort(ID(OUT)));
SigBit in_bit = sigmap(cell->getPort(TW::IN));
SigBit out_bit = sigmap(cell->getPort(TW::OUT));
inv_in2out[in_bit] = out_bit;
inv_out2in[out_bit] = in_bit;
inv_in2cell[in_bit] = cell;
@ -176,7 +176,7 @@ struct Greenpak4DffInvPass : public Pass {
for (auto cell : dff_cells)
{
SigBit d_bit = sigmap(cell->getPort(TW::D));
SigBit q_bit = sigmap(cell->hasPort(ID::Q) ? cell->getPort(TW::Q) : cell->getPort(ID(nQ)));
SigBit q_bit = sigmap(cell->hasPort(TW::Q) ? cell->getPort(TW::Q) : cell->getPort(TW::nQ));
while (inv_out2in.count(d_bit))
{
@ -197,10 +197,10 @@ struct Greenpak4DffInvPass : public Pass {
inv_in2cell.erase(q_bit);
invert_gp_dff(cell, false);
if (cell->hasPort(ID::Q))
if (cell->hasPort(TW::Q))
cell->setPort(TW::Q, new_q_bit);
else
cell->setPort(ID(nQ), new_q_bit);
cell->setPort(TW::nQ, new_q_bit);
}
}
}

78
techlibs/ice40/ice40_dsp.cc
View file

@ -97,39 +97,39 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
cell->setParam(ID(D_REG), st.ffCD ? State::S1 : State::S0);
SigSpec AHOLD, BHOLD, CDHOLD;
if (st.ffA && st.ffA->hasPort(ID::EN))
AHOLD = st.ffA->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffA->getPort(TW::EN)) : st.ffA->getPort(TW::EN);
if (st.ffA && st.ffA->hasPort(TW::EN))
AHOLD = st.ffA->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_TWINE, st.ffA->getPort(TW::EN)) : st.ffA->getPort(TW::EN);
else
AHOLD = State::S0;
if (st.ffB && st.ffB->hasPort(ID::EN))
BHOLD = st.ffB->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffB->getPort(TW::EN)) : st.ffB->getPort(TW::EN);
if (st.ffB && st.ffB->hasPort(TW::EN))
BHOLD = st.ffB->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_TWINE, st.ffB->getPort(TW::EN)) : st.ffB->getPort(TW::EN);
else
BHOLD = State::S0;
if (st.ffCD && st.ffCD->hasPort(ID::EN))
CDHOLD = st.ffCD->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffCD->getPort(TW::EN)) : st.ffCD->getPort(TW::EN);
if (st.ffCD && st.ffCD->hasPort(TW::EN))
CDHOLD = st.ffCD->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_TWINE, st.ffCD->getPort(TW::EN)) : st.ffCD->getPort(TW::EN);
else
CDHOLD = State::S0;
cell->setPort(ID(AHOLD), AHOLD);
cell->setPort(ID(BHOLD), BHOLD);
cell->setPort(ID(CHOLD), CDHOLD);
cell->setPort(ID(DHOLD), CDHOLD);
cell->setPort(TW::AHOLD, AHOLD);
cell->setPort(TW::BHOLD, BHOLD);
cell->setPort(TW::CHOLD, CDHOLD);
cell->setPort(TW::DHOLD, CDHOLD);
SigSpec IRSTTOP, IRSTBOT;
if (st.ffA && st.ffA->hasPort(ID::ARST))
IRSTTOP = st.ffA->getParam(ID::ARST_POLARITY).as_bool() ? st.ffA->getPort(TW::ARST) : pm.module->Not(NEW_ID, st.ffA->getPort(TW::ARST));
if (st.ffA && st.ffA->hasPort(TW::ARST))
IRSTTOP = st.ffA->getParam(ID::ARST_POLARITY).as_bool() ? st.ffA->getPort(TW::ARST) : pm.module->Not(NEW_TWINE, st.ffA->getPort(TW::ARST));
else
IRSTTOP = State::S0;
if (st.ffB && st.ffB->hasPort(ID::ARST))
IRSTBOT = st.ffB->getParam(ID::ARST_POLARITY).as_bool() ? st.ffB->getPort(TW::ARST) : pm.module->Not(NEW_ID, st.ffB->getPort(TW::ARST));
if (st.ffB && st.ffB->hasPort(TW::ARST))
IRSTBOT = st.ffB->getParam(ID::ARST_POLARITY).as_bool() ? st.ffB->getPort(TW::ARST) : pm.module->Not(NEW_TWINE, st.ffB->getPort(TW::ARST));
else
IRSTBOT = State::S0;
cell->setPort(ID(IRSTTOP), IRSTTOP);
cell->setPort(ID(IRSTBOT), IRSTBOT);
cell->setPort(TW::IRSTTOP, IRSTTOP);
cell->setPort(TW::IRSTBOT, IRSTBOT);
if (st.clock != SigBit())
{
cell->setPort(TW::CLK, st.clock);
cell->setPort(ID(CE), State::S1);
cell->setPort(TW::CE, State::S1);
cell->setParam(ID(NEG_TRIGGER), st.clock_pol ? State::S0 : State::S1);
log(" clock: %s (%s)", log_signal(st.clock), st.clock_pol ? "posedge" : "negedge");
@ -157,19 +157,19 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
else
{
cell->setPort(TW::CLK, State::S0);
cell->setPort(ID(CE), State::S0);
cell->setPort(TW::CE, State::S0);
cell->setParam(ID(NEG_TRIGGER), State::S0);
}
// SB_MAC16 Cascade Interface
cell->setPort(ID(SIGNEXTIN), State::Sx);
cell->setPort(ID(SIGNEXTOUT), pm.module->addWire(NEW_TWINE));
cell->setPort(TW::SIGNEXTIN, State::Sx);
cell->setPort(TW::SIGNEXTOUT, pm.module->addWire(NEW_TWINE));
cell->setPort(TW::CI, State::Sx);
cell->setPort(ID(ACCUMCI), State::Sx);
cell->setPort(ID(ACCUMCO), pm.module->addWire(NEW_TWINE));
cell->setPort(TW::ACCUMCI, State::Sx);
cell->setPort(TW::ACCUMCO, pm.module->addWire(NEW_TWINE));
// SB_MAC16 Output Interface
@ -199,40 +199,40 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
log(" accumulator %s (%s)\n", st.add, st.add->type.unescape());
else
log(" adder %s (%s)\n", st.add, st.add->type.unescape());
cell->setPort(ID(ADDSUBTOP), st.add->type == ID($add) ? State::S0 : State::S1);
cell->setPort(ID(ADDSUBBOT), st.add->type == ID($add) ? State::S0 : State::S1);
cell->setPort(TW::ADDSUBTOP, st.add->type == ID($add) ? State::S0 : State::S1);
cell->setPort(TW::ADDSUBBOT, st.add->type == ID($add) ? State::S0 : State::S1);
} else {
cell->setPort(ID(ADDSUBTOP), State::S0);
cell->setPort(ID(ADDSUBBOT), State::S0);
cell->setPort(TW::ADDSUBTOP, State::S0);
cell->setPort(TW::ADDSUBBOT, State::S0);
}
SigSpec OHOLD;
if (st.ffO && st.ffO->hasPort(ID::EN))
OHOLD = st.ffO->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_ID, st.ffO->getPort(TW::EN)) : st.ffO->getPort(TW::EN);
if (st.ffO && st.ffO->hasPort(TW::EN))
OHOLD = st.ffO->getParam(ID::EN_POLARITY).as_bool() ? pm.module->Not(NEW_TWINE, st.ffO->getPort(TW::EN)) : st.ffO->getPort(TW::EN);
else
OHOLD = State::S0;
cell->setPort(ID(OHOLDTOP), OHOLD);
cell->setPort(ID(OHOLDBOT), OHOLD);
cell->setPort(TW::OHOLDTOP, OHOLD);
cell->setPort(TW::OHOLDBOT, OHOLD);
SigSpec ORST;
if (st.ffO && st.ffO->hasPort(ID::ARST))
ORST = st.ffO->getParam(ID::ARST_POLARITY).as_bool() ? st.ffO->getPort(TW::ARST) : pm.module->Not(NEW_ID, st.ffO->getPort(TW::ARST));
if (st.ffO && st.ffO->hasPort(TW::ARST))
ORST = st.ffO->getParam(ID::ARST_POLARITY).as_bool() ? st.ffO->getPort(TW::ARST) : pm.module->Not(NEW_TWINE, st.ffO->getPort(TW::ARST));
else
ORST = State::S0;
cell->setPort(ID(ORSTTOP), ORST);
cell->setPort(ID(ORSTBOT), ORST);
cell->setPort(TW::ORSTTOP, ORST);
cell->setPort(TW::ORSTBOT, ORST);
SigSpec acc_reset = State::S0;
if (st.mux) {
if (st.muxAB == ID::A)
acc_reset = st.mux->getPort(TW::S);
else
acc_reset = pm.module->Not(NEW_ID, st.mux->getPort(TW::S));
} else if (st.ffO && st.ffO->hasPort(ID::SRST)) {
acc_reset = st.ffO->getParam(ID::SRST_POLARITY).as_bool() ? st.ffO->getPort(TW::SRST) : pm.module->Not(NEW_ID, st.ffO->getPort(TW::SRST));
acc_reset = pm.module->Not(NEW_TWINE, st.mux->getPort(TW::S));
} else if (st.ffO && st.ffO->hasPort(TW::SRST)) {
acc_reset = st.ffO->getParam(ID::SRST_POLARITY).as_bool() ? st.ffO->getPort(TW::SRST) : pm.module->Not(NEW_TWINE, st.ffO->getPort(TW::SRST));
}
cell->setPort(ID(OLOADTOP), acc_reset);
cell->setPort(ID(OLOADBOT), acc_reset);
cell->setPort(TW::OLOADTOP, acc_reset);
cell->setPort(TW::OLOADBOT, acc_reset);
// SB_MAC16 Remaining Parameters

34
techlibs/ice40/ice40_opt.cc
View file

@ -58,8 +58,8 @@ static void run_ice40_opts(Module *module)
int count_zeros = 0, count_ones = 0;
SigBit inbit[3] = {
get_bit_or_zero(cell->getPort(ID(I0))),
get_bit_or_zero(cell->getPort(ID(I1))),
get_bit_or_zero(cell->getPort(TW::I0)),
get_bit_or_zero(cell->getPort(TW::I1)),
get_bit_or_zero(cell->getPort(TW::CI))
};
for (int i = 0; i < 3; i++)
@ -140,12 +140,12 @@ static void run_ice40_opts(Module *module)
module, cell, log_signal(replacement_output));
cell->type = ID($lut);
auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3)));
cell->setPort(TW::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(ID(I0))) });
cell->setPort(TW::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(TW::I0)) });
cell->setPort(TW::Y, cell->getPort(TW::O));
cell->unsetPort(TW::B);
cell->unsetPort(TW::CI);
cell->unsetPort(ID(I0));
cell->unsetPort(ID(I3));
cell->unsetPort(TW::I0);
cell->unsetPort(TW::I3);
cell->unsetPort(TW::CO);
cell->unsetPort(TW::O);
cell->setParam(ID::WIDTH, 4);
@ -159,10 +159,10 @@ static void run_ice40_opts(Module *module)
{
SigSpec inbits;
inbits.append(get_bit_or_zero(cell->getPort(ID(I0))));
inbits.append(get_bit_or_zero(cell->getPort(ID(I1))));
inbits.append(get_bit_or_zero(cell->getPort(ID(I2))));
inbits.append(get_bit_or_zero(cell->getPort(ID(I3))));
inbits.append(get_bit_or_zero(cell->getPort(TW::I0)));
inbits.append(get_bit_or_zero(cell->getPort(TW::I1)));
inbits.append(get_bit_or_zero(cell->getPort(TW::I2)));
inbits.append(get_bit_or_zero(cell->getPort(TW::I3)));
sigmap.apply(inbits);
if (optimized_co.count(inbits[0])) goto remap_lut;
@ -183,16 +183,16 @@ static void run_ice40_opts(Module *module)
cell->unsetParam(ID(LUT_INIT));
cell->setPort(TW::A, SigSpec({
get_bit_or_zero(cell->getPort(ID(I3))),
get_bit_or_zero(cell->getPort(ID(I2))),
get_bit_or_zero(cell->getPort(ID(I1))),
get_bit_or_zero(cell->getPort(ID(I0)))
get_bit_or_zero(cell->getPort(TW::I3)),
get_bit_or_zero(cell->getPort(TW::I2)),
get_bit_or_zero(cell->getPort(TW::I1)),
get_bit_or_zero(cell->getPort(TW::I0))
}));
cell->setPort(TW::Y, cell->getPort(TW::O)[0]);
cell->unsetPort(ID(I0));
cell->unsetPort(ID(I1));
cell->unsetPort(ID(I2));
cell->unsetPort(ID(I3));
cell->unsetPort(TW::I0);
cell->unsetPort(TW::I1);
cell->unsetPort(TW::I2);
cell->unsetPort(TW::I3);
cell->unsetPort(TW::O);
cell->check();

16
techlibs/ice40/ice40_wrapcarry.cc
View file

@ -40,21 +40,21 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm)
Cell *cell = pm.module->addCell(NEW_TWINE, ID($__ICE40_CARRY_WRAPPER));
pm.module->swap_names(cell, st.carry);
cell->setPort(TW::A, st.carry->getPort(ID(I0)));
cell->setPort(TW::B, st.carry->getPort(ID(I1)));
cell->setPort(TW::A, st.carry->getPort(TW::I0));
cell->setPort(TW::B, st.carry->getPort(TW::I1));
auto CI = st.carry->getPort(TW::CI);
cell->setPort(TW::CI, CI);
cell->setPort(TW::CO, st.carry->getPort(TW::CO));
cell->setPort(ID(I0), st.lut->getPort(ID(I0)));
auto I3 = st.lut->getPort(ID(I3));
cell->setPort(TW::I0, st.lut->getPort(TW::I0));
auto I3 = st.lut->getPort(TW::I3);
if ((*pm.sigmap)(CI) == (*pm.sigmap)(I3)) {
cell->setParam(ID(I3_IS_CI), State::S1);
I3 = State::Sx;
}
else
cell->setParam(ID(I3_IS_CI), State::S0);
cell->setPort(ID(I3), I3);
cell->setPort(TW::I3, I3);
cell->setPort(TW::O, st.lut->getPort(TW::O));
cell->setParam(ID::LUT, st.lut->getParam(ID(LUT_INIT)));
@ -135,8 +135,8 @@ struct Ice40WrapCarryPass : public Pass {
continue;
auto carry = module->addCell(NEW_TWINE, ID(SB_CARRY));
carry->setPort(ID(I0), cell->getPort(TW::A));
carry->setPort(ID(I1), cell->getPort(TW::B));
carry->setPort(TW::I0, cell->getPort(TW::A));
carry->setPort(TW::I1, cell->getPort(TW::B));
carry->setPort(TW::CI, cell->getPort(TW::CI));
carry->setPort(TW::CO, cell->getPort(TW::CO));
module->swap_names(carry, cell);
@ -145,7 +145,7 @@ struct Ice40WrapCarryPass : public Pass {
lut->setParam(ID::WIDTH, 4);
lut->setParam(ID::LUT, cell->getParam(ID::LUT));
auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3));
lut->setPort(TW::A, { I3, cell->getPort(TW::B), cell->getPort(TW::A), cell->getPort(ID(I0)) });
lut->setPort(TW::A, { I3, cell->getPort(TW::B), cell->getPort(TW::A), cell->getPort(TW::I0) });
lut->setPort(TW::Y, cell->getPort(TW::O));
std::string carry_src, lut_src, fallback_src;

6
techlibs/lattice/lattice_gsr.cc
View file

@ -71,7 +71,7 @@ struct LatticeGsrPass : public Pass {
if (found_gsr)
log_error("Found more than one GSR or SGSR cell in module %s.\n", module);
found_gsr = true;
SigSpec sig_gsr = cell->getPort(ID(GSR));
SigSpec sig_gsr = cell->getPort(TW::GSR);
if (GetSize(sig_gsr) < 1)
log_error("GSR cell %s has disconnected GSR input.\n", cell);
gsr = sigmap(sig_gsr[0]);
@ -118,14 +118,14 @@ struct LatticeGsrPass : public Pass {
continue;
if (cell->getParam(ID(SRMODE)).decode_string() != "ASYNC")
continue;
SigSpec sig_lsr = cell->getPort(ID(LSR));
SigSpec sig_lsr = cell->getPort(TW::LSR);
if (GetSize(sig_lsr) < 1)
continue;
SigBit lsr = sigmap(sig_lsr[0]);
if (!inverted_gsr.count(lsr))
continue;
cell->setParam(ID(SRMODE), Const("LSR_OVER_CE"));
cell->unsetPort(ID(LSR));
cell->unsetPort(TW::LSR);
}
}

36
techlibs/microchip/microchip_dffopt.cc
View file

@ -142,16 +142,16 @@ struct MicrochipDffOptPass : public Pass {
SigBit sigout = sigmap(cell->getPort(TW::Y));
const Const &init = cell->getParam(ID::INIT);
std::vector<SigBit> sigin;
sigin.push_back(sigmap(cell->getPort(ID(A))));
sigin.push_back(sigmap(cell->getPort(TW::A)));
if (cell->type == ID(CFG1))
goto lut_sigin_done;
sigin.push_back(sigmap(cell->getPort(ID(B))));
sigin.push_back(sigmap(cell->getPort(TW::B)));
if (cell->type == ID(CFG2))
goto lut_sigin_done;
sigin.push_back(sigmap(cell->getPort(ID(C))));
sigin.push_back(sigmap(cell->getPort(TW::C)));
if (cell->type == ID(CFG3))
goto lut_sigin_done;
sigin.push_back(sigmap(cell->getPort(ID(D))));
sigin.push_back(sigmap(cell->getPort(TW::D)));
lut_sigin_done:
bit_to_lut[sigout] = make_pair(LutData(init, sigin), cell);
@ -167,16 +167,16 @@ struct MicrochipDffOptPass : public Pass {
if (!cell->type.in(ID(SLE))) // not a SLE
continue;
if (cell->getPort(ID(LAT)).is_fully_ones()) // skip latch
if (cell->getPort(TW::LAT).is_fully_ones()) // skip latch
continue;
if (cell->get_bool_attribute(ID::keep)) // keep attribute
continue;
if (!cell->getPort(ID(ALn)).is_fully_ones()) // async FF
if (!cell->getPort(TW::ALn).is_fully_ones()) // async FF
continue;
const bool hasSyncLoad = cell->getPort(ID(SLn)).is_wire();
const bool has_s = hasSyncLoad && cell->getPort(ID(SD)).is_fully_ones();
const bool has_r = hasSyncLoad && cell->getPort(ID(SD)).is_fully_zero();
const bool hasSyncLoad = cell->getPort(TW::SLn).is_wire();
const bool has_s = hasSyncLoad && cell->getPort(TW::SD).is_fully_ones();
const bool has_r = hasSyncLoad && cell->getPort(TW::SD).is_fully_zero();
// SLE cannot have both synchronous set and reset implemented at the same time
log_assert(!(has_s && has_r));
@ -202,7 +202,7 @@ struct MicrochipDffOptPass : public Pass {
// First, unmap CE.
SigBit sig_Q = sigmap(cell->getPort(TW::Q));
SigBit sig_CE = sigmap(cell->getPort(ID(EN)));
SigBit sig_CE = sigmap(cell->getPort(TW::EN));
LutData lut_ce = LutData(Const(2, 2), {sig_CE}); // INIT = 10
auto it_CE = bit_to_lut.find(sig_CE);
if (it_CE != bit_to_lut.end())
@ -227,7 +227,7 @@ struct MicrochipDffOptPass : public Pass {
// Second, unmap S, if any.
lut_d_post_s = lut_d_post_ce;
if (has_s) {
SigBit sig_S = sigmap(cell->getPort(ID(SLn)));
SigBit sig_S = sigmap(cell->getPort(TW::SLn));
LutData lut_s = LutData(Const(2, 2), {sig_S}); // INIT = 10
bool inv_s = true; // active low
auto it_S = bit_to_lut.find(sig_S);
@ -250,7 +250,7 @@ struct MicrochipDffOptPass : public Pass {
// Third, unmap R, if any.
lut_d_post_r = lut_d_post_s;
if (has_r) {
SigBit sig_R = sigmap(cell->getPort(ID(SLn)));
SigBit sig_R = sigmap(cell->getPort(TW::SLn));
LutData lut_r = LutData(Const(2, 2), {sig_R}); // INIT = 10
bool inv_r = true; // active low
auto it_R = bit_to_lut.find(sig_R);
@ -299,11 +299,11 @@ struct MicrochipDffOptPass : public Pass {
// Okay, we're doing it. Unmap ports.
if ((has_s && worthy_post_s) || worthy_post_r) {
cell->setPort(ID(SLn), Const(1, 1));
cell->setPort(TW::SLn, Const(1, 1));
}
// if we made it this far, clk enable is always merged into D
cell->setPort(ID(EN), Const(1, 1));
cell->setPort(TW::EN, Const(1, 1));
// Create the new LUT.
Cell *lut_cell = nullptr;
@ -328,13 +328,13 @@ struct MicrochipDffOptPass : public Pass {
lut_cell->setParam(ID::INIT, final_lut.first);
cell->setPort(TW::D, lut_out);
lut_cell->setPort(TW::Y, lut_out);
lut_cell->setPort(ID(A), final_lut.second[0]);
lut_cell->setPort(TW::A, final_lut.second[0]);
if (GetSize(final_lut.second) >= 2)
lut_cell->setPort(ID(B), final_lut.second[1]);
lut_cell->setPort(TW::B, final_lut.second[1]);
if (GetSize(final_lut.second) >= 3)
lut_cell->setPort(ID(C), final_lut.second[2]);
lut_cell->setPort(TW::C, final_lut.second[2]);
if (GetSize(final_lut.second) >= 4)
lut_cell->setPort(ID(D), final_lut.second[3]);
lut_cell->setPort(TW::D, final_lut.second[3]);
}
}
}

14
techlibs/microchip/microchip_dsp.cc
View file

@ -72,7 +72,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
log_assert(!"strange post-adder type");
if (st.useFeedBack) {
cell->setPort(ID(CDIN_FDBK_SEL), {State::S0, State::S1});
cell->setPort(TW::CDIN_FDBK_SEL, {State::S0, State::S1});
} else {
st.sigC.extend_u0(48, st.postAdderStatic->getParam(ID::A_SIGNED).as_bool());
cell->setPort(TW::C, st.sigC);
@ -98,12 +98,12 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
SigSpec srst = ff->getPort(TW::SRST);
bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool();
// active low sync rst
cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_ID, srst));
cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_TWINE, srst));
} else if (ff->type.in(ID($adff), ID($adffe))) {
SigSpec arst = ff->getPort(TW::ARST);
bool rstpol_n = !ff->getParam(ID::ARST_POLARITY).as_bool();
// active low async rst
cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_ID, arst));
cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_TWINE, arst));
} else {
// active low async/sync rst
cell->setPort(rstport, State::S1);
@ -113,7 +113,7 @@ void microchip_dsp_pack(microchip_dsp_pm &pm)
SigSpec ce = ff->getPort(TW::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
// enables are all active high
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_TWINE, ce));
} else {
// enables are all active high
cell->setPort(ceport, State::S1);
@ -214,12 +214,12 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
SigSpec srst = ff->getPort(TW::SRST);
bool rstpol_n = !ff->getParam(ID::SRST_POLARITY).as_bool();
// active low sync rst
cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_ID, srst));
cell->setPort(rstport, rstpol_n ? srst : pm.module->Not(NEW_TWINE, srst));
} else if (ff->type.in(ID($adff), ID($adffe))) {
SigSpec arst = ff->getPort(TW::ARST);
bool rstpol_n = !ff->getParam(ID::ARST_POLARITY).as_bool();
// active low async rst
cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_ID, arst));
cell->setPort(rstport, rstpol_n ? arst : pm.module->Not(NEW_TWINE, arst));
} else {
// active low async/sync rst
cell->setPort(rstport, State::S1);
@ -229,7 +229,7 @@ void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
SigSpec ce = ff->getPort(TW::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
// enables are all active high
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_TWINE, ce));
} else {
// enables are all active high
cell->setPort(ceport, State::S1);

44
techlibs/nanoxplore/nx_carry.cc
View file

@ -39,9 +39,9 @@ static void nx_carry_chain(Module *module)
{
if (cell->type == ID(NX_CY_1BIT)) {
if (cell->getParam(ID(first)).as_int() == 1) continue;
if (!cell->hasPort(ID(CI)))
if (!cell->hasPort(TW(CI)))
log_error("Not able to find connected carry.\n");
SigBit ci = sigmap(cell->getPort(ID(CI)).as_bit());
SigBit ci = sigmap(cell->getPort(TW::CI).as_bit());
carry[ci] = cell;
}
}
@ -57,7 +57,7 @@ static void nx_carry_chain(Module *module)
Cell *current = cell;
chain.push_back(current);
SigBit co = sigmap(cell->getPort(ID(CO)).as_bit());
SigBit co = sigmap(cell->getPort(TW::CO).as_bit());
while (co.is_wire())
{
if (carry.count(co)==0)
@ -65,8 +65,8 @@ static void nx_carry_chain(Module *module)
//log_error("Not able to find connected carry.\n");
current = carry[co];
chain.push_back(current);
if (!current->hasPort(ID(CO))) break;
co = sigmap(current->getPort(ID(CO)).as_bit());
if (!current->hasPort(TW(CO))) break;
co = sigmap(current->getPort(TW::CO).as_bit());
}
carry_chains[cell] = chain;
}
@ -80,12 +80,12 @@ static void nx_carry_chain(Module *module)
IdString names_A[] = { ID(A1), ID(A2), ID(A3), ID(A4) };
IdString names_B[] = { ID(B1), ID(B2), ID(B3), ID(B4) };
IdString names_S[] = { ID(S1), ID(S2), ID(S3), ID(S4) };
if (!c.second.at(0)->getPort(ID(CI)).is_fully_const()) {
if (!c.second.at(0)->getPort(TW::CI).is_fully_const()) {
cell = module->addCell(NEW_TWINE, ID(NX_CY));
cell->setParam(ID(add_carry), Const(1,2));
cell->setPort(ID(CI), State::S1);
cell->setPort(TW::CI, State::S1);
cell->setPort(names_A[0], c.second.at(0)->getPort(ID(CI)).as_bit());
cell->setPort(names_A[0], c.second.at(0)->getPort(TW::CI).as_bit());
cell->setPort(names_B[0], State::S0);
j++;
}
@ -93,8 +93,8 @@ static void nx_carry_chain(Module *module)
for (size_t i=0 ; i<c.second.size(); i++) {
if (j==0) {
cell = module->addCell(NEW_TWINE, ID(NX_CY));
SigBit ci = c.second.at(i)->getPort(ID(CI)).as_bit();
cell->setPort(ID(CI), ci);
SigBit ci = c.second.at(i)->getPort(TW::CI).as_bit();
cell->setPort(TW::CI, ci);
if (ci.is_wire()) {
cell->setParam(ID(add_carry), Const(2,2));
} else {
@ -107,26 +107,26 @@ static void nx_carry_chain(Module *module)
if (j==3) {
if (cnt !=0 && (cnt % 24 == 0)) {
SigBit new_co = module->addWire(NEW_TWINE);
cell->setPort(ID(A4), State::S0);
cell->setPort(ID(B4), State::S0);
cell->setPort(ID(S4), new_co);
cell->setPort(TW::A4, State::S0);
cell->setPort(TW::B4, State::S0);
cell->setPort(TW::S4, new_co);
cell = module->addCell(NEW_TWINE, ID(NX_CY));
cell->setParam(ID(add_carry), Const(1,2));
cell->setPort(ID(CI), State::S1);
cell->setPort(ID(A1), new_co);
cell->setPort(ID(B1), State::S0);
cell->setPort(TW::CI, State::S1);
cell->setPort(TW::A1, new_co);
cell->setPort(TW::B1, State::S0);
j = 1;
} else {
if (c.second.at(i)->hasPort(ID(CO)))
cell->setPort(ID(CO), c.second.at(i)->getPort(ID(CO)));
if (c.second.at(i)->hasPort(TW(CO)))
cell->setPort(TW::CO, c.second.at(i)->getPort(TW::CO));
}
cnt++;
}
cell->setPort(names_A[j], get_bit_or_zero(c.second.at(i)->getPort(ID(A))));
cell->setPort(names_B[j], get_bit_or_zero(c.second.at(i)->getPort(ID(B))));
cell->setPort(names_A[j], get_bit_or_zero(c.second.at(i)->getPort(TW::A)));
cell->setPort(names_B[j], get_bit_or_zero(c.second.at(i)->getPort(TW::B)));
if (c.second.at(i)->hasPort(ID(S)))
cell->setPort(names_S[j], c.second.at(i)->getPort(ID(S)));
if (c.second.at(i)->hasPort(TW(S)))
cell->setPort(names_S[j], c.second.at(i)->getPort(TW::S));
j = (j + 1) % 4;
module->remove(c.second.at(i));

2
techlibs/quicklogic/ql_bram_types.cc
View file

@ -155,7 +155,7 @@ struct QlBramTypesPass : public Pass {
}
cell->type = RTLIL::escape_id(type);
log_debug("Changed type of memory cell %s to %s\n", cell->name.unescape(), cell->type.unescape());
log_debug("Changed type of memory cell %s to %s\n", cell->module->design->twines.str(cell->meta_->name), cell->type.unescape());
}
}

10
techlibs/quicklogic/ql_dsp_io_regs.cc
View file

@ -84,13 +84,13 @@ struct QlDspIORegs : public Pass {
if (!cell->hasPort(cfg_port) || !sigmap(cell->getPort(cfg_port)).is_fully_const())
log_error("Missing or non-constant '%s' port on DSP cell %s\n",
cfg_port, cell);
int reg_in_i = sigmap(cell->getPort(ID(register_inputs))).as_int();
int out_sel_i = sigmap(cell->getPort(ID(output_select))).as_int();
int reg_in_i = sigmap(cell->getPort(TW::register_inputs)).as_int();
int out_sel_i = sigmap(cell->getPort(TW::output_select)).as_int();
// Get the feedback port
if (!cell->hasPort(ID(feedback)))
if (!cell->hasPort(TW(feedback)))
log_error("Missing 'feedback' port on %s", cell);
SigSpec feedback = sigmap(cell->getPort(ID(feedback)));
SigSpec feedback = sigmap(cell->getPort(TW::feedback));
// Check the top two bits on 'feedback' to be constant zero.
// That's what we are expecting from inference.
@ -132,7 +132,7 @@ struct QlDspIORegs : public Pass {
std::vector<std::string> ports2del;
if (del_clk)
cell->unsetPort(ID(clk));
cell->unsetPort(TW::clk);
switch (out_sel_i) {
case 0:

60
techlibs/quicklogic/ql_dsp_macc.cc
View file

@ -32,9 +32,9 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
auto &st = pm.st_ql_dsp_macc;
// Get port widths
size_t a_width = GetSize(st.mul->getPort(ID(A)));
size_t b_width = GetSize(st.mul->getPort(ID(B)));
size_t z_width = GetSize(st.ff->getPort(ID(Q)));
size_t a_width = GetSize(st.mul->getPort(TW::A));
size_t b_width = GetSize(st.mul->getPort(TW::B));
size_t z_width = GetSize(st.ff->getPort(TW::Q));
size_t min_width = std::min(a_width, b_width);
size_t max_width = std::max(a_width, b_width);
@ -87,9 +87,9 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
// Get input/output data signals
RTLIL::SigSpec sig_a, sig_b, sig_z;
sig_a = st.mul->getPort(ID(A));
sig_b = st.mul->getPort(ID(B));
sig_z = st.output_registered ? st.ff->getPort(ID(Q)) : st.ff->getPort(ID(D));
sig_a = st.mul->getPort(TW::A);
sig_b = st.mul->getPort(TW::B);
sig_z = st.output_registered ? st.ff->getPort(TW::Q) : st.ff->getPort(TW::D);
if (a_width < b_width)
std::swap(sig_a, sig_b);
@ -97,80 +97,80 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
// Connect input data ports, sign extend / pad with zeros
sig_a.extend_u0(tgt_a_width, ab_signed);
sig_b.extend_u0(tgt_b_width, ab_signed);
cell->setPort(ID(a_i), sig_a);
cell->setPort(ID(b_i), sig_b);
cell->setPort(TW::a_i, sig_a);
cell->setPort(TW::b_i, sig_b);
// Connect output data port, pad if needed
if ((size_t) GetSize(sig_z) < tgt_z_width) {
auto *wire = pm.module->addWire(NEW_TWINE, tgt_z_width - GetSize(sig_z));
sig_z.append(wire);
}
cell->setPort(ID(z_o), sig_z);
cell->setPort(TW::z_o, sig_z);
// Connect clock, reset and enable
cell->setPort(ID(clock_i), st.ff->getPort(ID(CLK)));
cell->setPort(TW::clock_i, st.ff->getPort(TW::CLK));
RTLIL::SigSpec rst;
RTLIL::SigSpec ena;
if (st.ff->hasPort(ID(ARST))) {
if (st.ff->hasPort(TW(ARST))) {
if (st.ff->getParam(ID(ARST_POLARITY)).as_int() != 1) {
rst = pm.module->Not(NEW_ID, st.ff->getPort(ID(ARST)));
rst = pm.module->Not(NEW_TWINE, st.ff->getPort(TW::ARST));
} else {
rst = st.ff->getPort(ID(ARST));
rst = st.ff->getPort(TW::ARST);
}
} else {
rst = RTLIL::SigSpec(RTLIL::S0);
}
if (st.ff->hasPort(ID(EN))) {
if (st.ff->hasPort(TW(EN))) {
if (st.ff->getParam(ID(EN_POLARITY)).as_int() != 1) {
ena = pm.module->Not(NEW_ID, st.ff->getPort(ID(EN)));
ena = pm.module->Not(NEW_TWINE, st.ff->getPort(TW::EN));
} else {
ena = st.ff->getPort(ID(EN));
ena = st.ff->getPort(TW::EN);
}
} else {
ena = RTLIL::SigSpec(RTLIL::S1);
}
cell->setPort(ID(reset_i), rst);
cell->setPort(ID(load_acc_i), ena);
cell->setPort(TW::reset_i, rst);
cell->setPort(TW::load_acc_i, ena);
// Insert feedback_i control logic used for clearing / loading the accumulator
if (st.mux_in_pattern) {
RTLIL::SigSpec sig_s = st.mux->getPort(ID(S));
RTLIL::SigSpec sig_s = st.mux->getPort(TW::S);
// Depending on the mux port ordering insert inverter if needed
log_assert(st.mux_ab.in(ID(A), ID(B)));
if (st.mux_ab == ID(A))
sig_s = pm.module->Not(NEW_ID, sig_s);
sig_s = pm.module->Not(NEW_TWINE, sig_s);
// Assemble the full control signal for the feedback_i port
RTLIL::SigSpec sig_f;
sig_f.append(sig_s);
sig_f.append(RTLIL::S0);
sig_f.append(RTLIL::S0);
cell->setPort(ID(feedback_i), sig_f);
cell->setPort(TW::feedback_i, sig_f);
}
// No acc clear/load
else {
cell->setPort(ID(feedback_i), RTLIL::SigSpec(RTLIL::S0, 3));
cell->setPort(TW::feedback_i, RTLIL::SigSpec(RTLIL::S0, 3));
}
// Connect control ports
cell->setPort(ID(unsigned_a_i), RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1));
cell->setPort(ID(unsigned_b_i), RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1));
cell->setPort(TW::unsigned_a_i, RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1));
cell->setPort(TW::unsigned_b_i, RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1));
// Connect config bits
cell->setPort(ID(saturate_enable_i), RTLIL::SigSpec(RTLIL::S0));
cell->setPort(ID(shift_right_i), RTLIL::SigSpec(RTLIL::S0, 6));
cell->setPort(ID(round_i), RTLIL::SigSpec(RTLIL::S0));
cell->setPort(ID(register_inputs_i), RTLIL::SigSpec(RTLIL::S0));
cell->setPort(TW::saturate_enable_i, RTLIL::SigSpec(RTLIL::S0));
cell->setPort(TW::shift_right_i, RTLIL::SigSpec(RTLIL::S0, 6));
cell->setPort(TW::round_i, RTLIL::SigSpec(RTLIL::S0));
cell->setPort(TW::register_inputs_i, RTLIL::SigSpec(RTLIL::S0));
// 3 - output post acc; 1 - output pre acc
cell->setPort(ID(output_select_i), RTLIL::Const(st.output_registered ? 1 : 3, 3));
cell->setPort(TW::output_select_i, RTLIL::Const(st.output_registered ? 1 : 3, 3));
bool subtract = (st.add->type == ID($sub));
cell->setPort(ID(subtract_i), RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0));
cell->setPort(TW::subtract_i, RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0));
// Mark the cells for removal
pm.autoremove(st.mul);

2
techlibs/quicklogic/ql_dsp_simd.cc
View file

@ -206,7 +206,7 @@ struct QlDspSimdPass : public Pass {
// Enable the fractured mode by connecting the control
// port.
simd->setPort(ID(f_mode), State::S1);
simd->setPort(TW::f_mode, State::S1);
simd->setParam(ID(MODE_BITS), mode_bits);
log_assert(mode_bits.size() == m_ModeBitsSize);

28
techlibs/xilinx/xilinx_dffopt.cc
View file

@ -153,22 +153,22 @@ struct XilinxDffOptPass : public Pass {
SigBit sigout = sigmap(cell->getPort(TW::O));
const Const &init = cell->getParam(ID::INIT);
std::vector<SigBit> sigin;
sigin.push_back(sigmap(cell->getPort(ID(I0))));
sigin.push_back(sigmap(cell->getPort(TW::I0)));
if (cell->type == ID(LUT1))
goto lut_sigin_done;
sigin.push_back(sigmap(cell->getPort(ID(I1))));
sigin.push_back(sigmap(cell->getPort(TW::I1)));
if (cell->type == ID(LUT2))
goto lut_sigin_done;
sigin.push_back(sigmap(cell->getPort(ID(I2))));
sigin.push_back(sigmap(cell->getPort(TW::I2)));
if (cell->type == ID(LUT3))
goto lut_sigin_done;
sigin.push_back(sigmap(cell->getPort(ID(I3))));
sigin.push_back(sigmap(cell->getPort(TW::I3)));
if (cell->type == ID(LUT4))
goto lut_sigin_done;
sigin.push_back(sigmap(cell->getPort(ID(I4))));
sigin.push_back(sigmap(cell->getPort(TW::I4)));
if (cell->type == ID(LUT5))
goto lut_sigin_done;
sigin.push_back(sigmap(cell->getPort(ID(I5))));
sigin.push_back(sigmap(cell->getPort(TW::I5)));
lut_sigin_done:
bit_to_lut[sigout] = make_pair(LutData(init, sigin), cell);
}
@ -224,7 +224,7 @@ lut_sigin_done:
// First, unmap CE.
SigBit sig_Q = sigmap(cell->getPort(TW::Q));
SigBit sig_CE = sigmap(cell->getPort(ID(CE)));
SigBit sig_CE = sigmap(cell->getPort(TW::CE));
LutData lut_ce = LutData(Const(2, 2), {sig_CE});
auto it_CE = bit_to_lut.find(sig_CE);
if (it_CE != bit_to_lut.end())
@ -316,7 +316,7 @@ unmap:
cell->unsetParam(ID(IS_S_INVERTED));
cell->setPort(TW::S, Const(0, 1));
}
cell->setPort(ID(CE), Const(1, 1));
cell->setPort(TW::CE, Const(1, 1));
cell->unsetParam(ID(IS_D_INVERTED));
// Create the new LUT.
@ -348,17 +348,17 @@ unmap:
lut_cell->setParam(ID::INIT, final_lut.first);
cell->setPort(TW::D, lut_out);
lut_cell->setPort(TW::O, lut_out);
lut_cell->setPort(ID(I0), final_lut.second[0]);
lut_cell->setPort(TW::I0, final_lut.second[0]);
if (GetSize(final_lut.second) >= 2)
lut_cell->setPort(ID(I1), final_lut.second[1]);
lut_cell->setPort(TW::I1, final_lut.second[1]);
if (GetSize(final_lut.second) >= 3)
lut_cell->setPort(ID(I2), final_lut.second[2]);
lut_cell->setPort(TW::I2, final_lut.second[2]);
if (GetSize(final_lut.second) >= 4)
lut_cell->setPort(ID(I3), final_lut.second[3]);
lut_cell->setPort(TW::I3, final_lut.second[3]);
if (GetSize(final_lut.second) >= 5)
lut_cell->setPort(ID(I4), final_lut.second[4]);
lut_cell->setPort(TW::I4, final_lut.second[4]);
if (GetSize(final_lut.second) >= 6)
lut_cell->setPort(ID(I5), final_lut.second[5]);
lut_cell->setPort(TW::I5, final_lut.second[5]);
}
}
}

50
techlibs/xilinx/xilinx_dsp.cc
View file

@ -53,14 +53,14 @@ static Cell* addDsp(Module *module) {
cell->setParam(ID(USE_DPORT), Const("FALSE"));
cell->setPort(TW::D, Const(0, 25));
cell->setPort(ID(INMODE), Const(0, 5));
cell->setPort(ID(ALUMODE), Const(0, 4));
cell->setPort(ID(OPMODE), Const(0, 7));
cell->setPort(ID(CARRYINSEL), Const(0, 3));
cell->setPort(ID(ACIN), Const(0, 30));
cell->setPort(ID(BCIN), Const(0, 18));
cell->setPort(ID(PCIN), Const(0, 48));
cell->setPort(ID(CARRYIN), Const(0, 1));
cell->setPort(TW::INMODE, Const(0, 5));
cell->setPort(TW::ALUMODE, Const(0, 4));
cell->setPort(TW::OPMODE, Const(0, 7));
cell->setPort(TW::CARRYINSEL, Const(0, 3));
cell->setPort(TW::ACIN, Const(0, 30));
cell->setPort(TW::BCIN, Const(0, 18));
cell->setPort(TW::PCIN, Const(0, 48));
cell->setPort(TW::CARRYIN, Const(0, 1));
return cell;
}
@ -190,7 +190,7 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
// X = A:B
// Y = 0
// Z = C
cell->setPort(ID(OPMODE), Const::from_string("0110011"));
cell->setPort(TW::OPMODE, Const::from_string("0110011"));
log_assert(lane1);
log_assert(lane2);
@ -221,9 +221,9 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
cell->setPort(TW::B, AB.extract(0, 18));
cell->setPort(TW::C, C);
cell->setPort(TW::P, P);
cell->setPort(ID(CARRYOUT), CARRYOUT);
cell->setPort(TW::CARRYOUT, CARRYOUT);
if (lane1->type == ID($sub))
cell->setPort(ID(ALUMODE), Const::from_string("0011"));
cell->setPort(TW::ALUMODE, Const::from_string("0011"));
module->remove(lane1);
module->remove(lane2);
@ -271,7 +271,7 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
// X = A:B
// Y = 0
// Z = C
cell->setPort(ID(OPMODE), Const::from_string("0110011"));
cell->setPort(TW::OPMODE, Const::from_string("0110011"));
log_assert(lane1);
log_assert(lane2);
@ -285,9 +285,9 @@ void xilinx_simd_pack(Module *module, SigMap* sigmap, const std::vector<Cell*> &
cell->setPort(TW::B, AB.extract(0, 18));
cell->setPort(TW::C, C);
cell->setPort(TW::P, P);
cell->setPort(ID(CARRYOUT), CARRYOUT);
cell->setPort(TW::CARRYOUT, CARRYOUT);
if (lane1->type == ID($sub))
cell->setPort(ID(ALUMODE), Const::from_string("0011"));
cell->setPort(TW::ALUMODE, Const::from_string("0011"));
module->remove(lane1);
module->remove(lane2);
@ -335,18 +335,18 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
cell->setPort(TW::A, st.sigA);
cell->setPort(TW::D, st.sigD);
if (preAdder->type == ID($add))
cell->setPort(ID(INMODE), Const::from_string("00100"));
cell->setPort(TW::INMODE, Const::from_string("00100"));
else
cell->setPort(ID(INMODE), Const::from_string("01100"));
cell->setPort(TW::INMODE, Const::from_string("01100"));
if (st.ffAD) {
if (st.ffAD->type.in(ID($dffe), ID($sdffe))) {
bool pol = st.ffAD->getParam(ID::EN_POLARITY).as_bool();
SigSpec S = st.ffAD->getPort(TW::EN);
cell->setPort(ID(CEAD), pol ? S : pm.module->Not(NEW_ID, S));
cell->setPort(TW::CEAD, pol ? S : pm.module->Not(NEW_TWINE, S));
}
else
cell->setPort(ID(CEAD), State::S1);
cell->setPort(TW::CEAD, State::S1);
cell->setParam(ID(ADREG), 1);
}
@ -402,7 +402,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
cell->setParam(ID(MASK), B);
cell->setParam(ID(PATTERN), Const(0, 48));
cell->setPort(ID(OVERFLOW), st.overflow->getPort(TW::Y));
cell->setPort(TW::OVERFLOW, st.overflow->getPort(TW::Y));
}
else log_abort();
@ -422,7 +422,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
if (ff->type.in(ID($sdff), ID($sdffe))) {
SigSpec srst = ff->getPort(TW::SRST);
bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst));
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_TWINE, srst));
} else {
cell->setPort(rstport, State::S0);
}
@ -430,7 +430,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
if (ff->type.in(ID($dffe), ID($sdffe))) {
SigSpec ce = ff->getPort(TW::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_TWINE, ce));
}
else
cell->setPort(ceport, State::S1);
@ -609,7 +609,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
if (ff->type.in(ID($sdff), ID($sdffe))) {
SigSpec srst = ff->getPort(TW::SRST);
bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst));
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_TWINE, srst));
} else {
cell->setPort(rstport, State::S0);
}
@ -617,7 +617,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
if (ff->type.in(ID($dffe), ID($sdffe))) {
SigSpec ce = ff->getPort(TW::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_TWINE, ce));
}
else
cell->setPort(ceport, State::S1);
@ -732,7 +732,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
if (ff->type.in(ID($sdff), ID($sdffe))) {
SigSpec srst = ff->getPort(TW::SRST);
bool rstpol = ff->getParam(ID::SRST_POLARITY).as_bool();
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_ID, srst));
cell->setPort(rstport, rstpol ? srst : pm.module->Not(NEW_TWINE, srst));
} else {
cell->setPort(rstport, State::S0);
}
@ -740,7 +740,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
if (ff->type.in(ID($dffe), ID($sdffe))) {
SigSpec ce = ff->getPort(TW::EN);
bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_TWINE, ce));
}
else
cell->setPort(ceport, State::S1);

2
techlibs/xilinx/xilinx_srl.cc
View file

@ -93,7 +93,7 @@ void run_fixed(xilinx_srl_pm &pm)
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
c->setPort(TW::E, first_cell->getPort(TW::E));
else if (first_cell->type.in(ID(FDRE), ID(FDRE_1)))
c->setPort(TW::E, first_cell->getPort(ID(CE)));
c->setPort(TW::E, first_cell->getPort(TW::CE));
else
log_abort();
}

16
techlibs/xilinx/xilinx_srl.pmg
View file

@ -41,13 +41,13 @@ generate
break;
case 2:
case 3:
cell = module->addDffGate(NEW_ID, C, D, Q, r & 1);
cell = module->addDffGate(NEW_TWINE, C, D, Q, r & 1);
break;
case 4:
case 5:
case 6:
case 7:
cell = module->addDffeGate(NEW_ID, C, module->addWire(NEW_TWINE), D, Q, r & 1, r & 2);
cell = module->addDffeGate(NEW_TWINE, C, module->addWire(NEW_TWINE), D, Q, r & 1, r & 2);
break;
default: log_abort();
}
@ -191,7 +191,7 @@ match shiftx
filter param(shiftx, \A_WIDTH).as_int() >= minlen
generate
minlen = 3;
module->addShiftx(NEW_ID, module->addWire(NEW_TWINE, rng(6)+minlen), module->addWire(NEW_TWINE, 3), module->addWire(NEW_TWINE));
module->addShiftx(NEW_TWINE, module->addWire(NEW_TWINE, rng(6)+minlen), module->addWire(NEW_TWINE, 3), module->addWire(NEW_TWINE));
endmatch
code shiftx_width
@ -217,18 +217,18 @@ generate
{
case 0:
case 1:
cell = module->addDff(NEW_ID, C, D, Q, r & 1);
cell = module->addDff(NEW_TWINE, C, D, Q, r & 1);
break;
case 2:
case 3:
case 4:
case 5:
//cell = module->addDffe(NEW_ID, C, module->addWire(NEW_TWINE), D, Q, r & 1, r & 4);
//cell = module->addDffe(NEW_TWINE, C, module->addWire(NEW_TWINE), D, Q, r & 1, r & 4);
//break;
case 6:
case 7:
WIDTH = 1;
cell = module->addDffGate(NEW_ID, C, D[0], Q[0], r & 1);
cell = module->addDffGate(NEW_TWINE, C, D[0], Q[0], r & 1);
break;
default: log_abort();
}
@ -297,9 +297,9 @@ generate
else {
auto D = module->addWire(NEW_TWINE, WIDTH);
if (back->type == $dff)
module->addDff(NEW_ID, port(back, \CLK), D, port(back, \D), param(back, \CLK_POLARITY).as_bool());
module->addDff(NEW_TWINE, port(back, \CLK), D, port(back, \D), param(back, \CLK_POLARITY).as_bool());
else if (back->type == $dffe)
module->addDffe(NEW_ID, port(back, \CLK), port(back, \EN), D, port(back, \D), param(back, \CLK_POLARITY).as_bool(), param(back, \EN_POLARITY).as_bool());
module->addDffe(NEW_TWINE, port(back, \CLK), port(back, \EN), D, port(back, \D), param(back, \CLK_POLARITY).as_bool(), param(back, \EN_POLARITY).as_bool());
else
log_abort();
}