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This commit is contained in:
Emil J. Tywoniak 2026-06-11 13:17:54 +02:00
parent f592f2f3af
commit 8e522b08c0
206 changed files with 3081 additions and 2782 deletions
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4
passes/techmap/dfflibmap.cc
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@ -543,12 +543,12 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
it->setPort(TW::Y, module->addWire(NEW_TWINE, GetSize(old_sig)));
}
} else {
module->addNotGate(NEW_ID, sig, old_sig);
module->addNotGate(NEW_TWINE, sig, old_sig);
}
} else
if ('a' <= port.second && port.second <= 'z') {
sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
sig = module->NotGate(NEW_ID, sig);
sig = module->NotGate(NEW_TWINE, sig);
} else
if (port.second == '0' || port.second == '1') {
sig = RTLIL::SigSpec(port.second == '0' ? 0 : 1, 1);