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https://github.com/YosysHQ/yosys
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WIP
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f592f2f3af
commit
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206 changed files with 3081 additions and 2782 deletions
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@ -305,8 +305,8 @@ void Pass::call(RTLIL::Design *design, std::vector<std::string> args)
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void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command)
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{
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std::string backup_selected_active_module = design->selected_active_module;
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design->selected_active_module.clear();
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TwineRef backup_selected_active_module = design->selected_active_module;
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design->selected_active_module = Twine::Null;
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design->push_selection(selection);
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Pass::call(design, command);
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@ -317,8 +317,8 @@ void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &sele
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void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::vector<std::string> args)
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{
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std::string backup_selected_active_module = design->selected_active_module;
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design->selected_active_module.clear();
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TwineRef backup_selected_active_module = design->selected_active_module;
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design->selected_active_module = Twine::Null;
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design->push_selection(selection);
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Pass::call(design, args);
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@ -329,8 +329,8 @@ void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &sele
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void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command)
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{
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std::string backup_selected_active_module = design->selected_active_module;
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design->selected_active_module = module->name.str();
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TwineRef backup_selected_active_module = design->selected_active_module;
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design->selected_active_module = module->meta_->name;
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design->push_empty_selection();
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design->select(module);
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@ -342,8 +342,8 @@ void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::str
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void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vector<std::string> args)
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{
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std::string backup_selected_active_module = design->selected_active_module;
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design->selected_active_module = module->name.str();
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TwineRef backup_selected_active_module = design->selected_active_module;
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design->selected_active_module = module->meta_->name;
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design->push_empty_selection();
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design->select(module);
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@ -1021,10 +1021,10 @@ struct HelpPass : public Pass {
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json.name("code"); json.value(ch.code);
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vector<string> inputs, outputs;
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for (auto &input : ct.inputs)
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inputs.push_back(input.str());
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inputs.push_back(RTLIL::IdString((RTLIL::StaticId)input).str());
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json.name("inputs"); json.value(inputs);
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for (auto &output : ct.outputs)
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outputs.push_back(output.str());
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outputs.push_back(RTLIL::IdString((RTLIL::StaticId)output).str());
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json.name("outputs"); json.value(outputs);
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vector<string> properties;
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// CellType properties
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