mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-22 15:15:51 +00:00
WIP
This commit is contained in:
parent
f592f2f3af
commit
8e522b08c0
206 changed files with 3081 additions and 2782 deletions
|
|
@ -746,7 +746,7 @@ void DriverMap::add(SigSpec const &a, SigSpec const &b)
|
|||
}
|
||||
}
|
||||
|
||||
void DriverMap::add_port(Cell *cell, IdString const &port, SigSpec const &b)
|
||||
void DriverMap::add_port(Cell *cell, TwineRef port, SigSpec const &b)
|
||||
{
|
||||
int offset = 0;
|
||||
for (auto const &chunk : b.chunks()) {
|
||||
|
|
@ -877,8 +877,8 @@ std::string log_signal(DriveChunkWire const &chunk)
|
|||
|
||||
std::string log_signal(DriveChunkPort const &chunk)
|
||||
{
|
||||
std::string cell_id = chunk.cell->name.unescape();
|
||||
std::string port_id = chunk.port.unescape();
|
||||
std::string cell_id = chunk.cell->module->design->twines.str(cell->meta_->name);
|
||||
std::string port_id = chunk.cell->module->design->twines.str(chunk.port);
|
||||
if (chunk.is_whole())
|
||||
return stringf("%s <%s>", cell_id, port_id);
|
||||
if (chunk.width == 1)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue