3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-24 08:02:32 +00:00
This commit is contained in:
Emil J. Tywoniak 2026-06-11 13:17:54 +02:00
parent f592f2f3af
commit 8e522b08c0
206 changed files with 3081 additions and 2782 deletions

View file

@ -75,7 +75,7 @@ struct CellTypes
if (wire->port_output)
outputs.insert(wire->meta_->name);
}
setup_type(module->name, inputs, outputs);
setup_type(RTLIL::IdString(module->design->twines.str(module->meta_->name)), inputs, outputs);
}
void setup_design(RTLIL::Design *design)