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Add quick test

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This commit is contained in:
Eddie Hung 2019-09-30 15:34:04 -07:00
parent f2f19df2d4
commit 8b239ee707
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tests/techmap/aigmap.ys Normal file
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read_verilog <<EOT
module top(input i, j, s, output o, p);
assign o = s ? j : i;
assign p = ~i;
endmodule
EOT
select t:$mux
aigmap -select
select -assert-any %