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test_patch total basics

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This commit is contained in:
Emil J. Tywoniak 2025-12-31 17:46:27 +01:00
parent 6f0be1b4e9
commit 89e5c4ccca
4 changed files with 62 additions and 3 deletions
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1
passes/cmds/Makefile.inc
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@ -60,5 +60,6 @@ OBJS += passes/cmds/timeest.o
OBJS += passes/cmds/linecoverage.o
OBJS += passes/cmds/sort.o
OBJS += passes/cmds/icell_liberty.o
OBJS += passes/cmds/test_patch.o
include $(YOSYS_SRC)/passes/cmds/sdc/Makefile.inc

36
passes/cmds/test_patch.cc Normal file
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@ -0,0 +1,36 @@
#include "kernel/rtlil.h"
#include "kernel/yosys.h"
#include "kernel/unstable/patch.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct TestPatchPass : public Pass {
TestPatchPass() : Pass("test_patch", "test patcher") { }
void help() override
{
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
(void) args;
RTLIL::Patch patcher;
design->bufNormalize();
for (auto module : design->selected_modules()) {
patcher.mod = module;
patcher.map = SigMap(module);
for (auto cell : module->selected_cells()) {
if (cell->type == ID($add)) {
RTLIL::Cell* sub = patcher.addCell(NEW_ID, ID($sub));
sub->connections_ = cell->connections();
sub->parameters = cell->parameters;
sub->setPort(ID::A, cell->getPort(ID::A));
sub->setPort(ID::B, cell->getPort(ID::B));
sub->setPort(ID::Y, cell->getPort(ID::Y));
patcher.patch();
}
}
}
}
} TestPatchPass;
PRIVATE_NAMESPACE_END