diff --git a/kernel/unstable/patch.cc b/kernel/unstable/patch.cc
index 8f01daaee..976a769fe 100644
--- a/kernel/unstable/patch.cc
+++ b/kernel/unstable/patch.cc
@@ -1,4 +1,6 @@
 #include "kernel/unstable/patch.h"
+#include "kernel/celltypes.h"
+#include "kernel/rtlil.h"
 
 YOSYS_NAMESPACE_BEGIN
 
@@ -10,6 +12,24 @@ Cell* Patch::addCell(IdString name, IdString type) {
     return &cell;
 }
 
+void Patch::patch() {
+    for (auto& cell: cells_) {
+        Cell* new_cell = mod->addCell(cell.name, &cell);
+        for (auto [port_name, sig] : new_cell->connections()) {
+            log_assert(yosys_celltypes.cell_known(cell.type));
+            auto dir = cell.port_dir(port_name);
+            if (dir == PD_OUTPUT || dir == PD_INOUT) {
+                for (auto chunk : sig.chunks()) {
+                    log_assert(chunk.is_wire());
+                    auto* wire = chunk.wire;
+                    wire->driverCell_->setPort(wire->driverPort_, SigSpec());
+                    wire->driverCell_ = new_cell;
+                    wire->driverPort_ = port_name;
+                }
+            }
+        }
+    }
+}
 
 
 YOSYS_NAMESPACE_END
\ No newline at end of file
diff --git a/kernel/unstable/patch.h b/kernel/unstable/patch.h
index ede8b57cb..150ca379a 100644
--- a/kernel/unstable/patch.h
+++ b/kernel/unstable/patch.h
@@ -2,6 +2,7 @@
 #define PATCH_H
 
 #include "kernel/rtlil.h"
+#include "kernel/sigtools.h"
 
 YOSYS_NAMESPACE_BEGIN
 
@@ -16,17 +17,18 @@ protected:
 	void add(RTLIL::Process *process);
 
 public:
-	// RTLIL::Design *design;
+	Module *mod;
+	SigMap map;
 	vector<Wire> wires_;
 	vector<Cell> cells_;
 
-	vector<RTLIL::SigSig>   connections_;
+	vector<RTLIL::SigSig> connections_;
 
 	void connect(const RTLIL::SigSig &conn);
 	void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
 	const std::vector<RTLIL::SigSig> &connections() const;
 
-	void patch(RTLIL::Module *mod);
+	void patch();
 	RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
 	RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);
 
diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index 5e2994a53..587963095 100644
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -60,5 +60,6 @@ OBJS += passes/cmds/timeest.o
 OBJS += passes/cmds/linecoverage.o
 OBJS += passes/cmds/sort.o
 OBJS += passes/cmds/icell_liberty.o
+OBJS += passes/cmds/test_patch.o
 
 include $(YOSYS_SRC)/passes/cmds/sdc/Makefile.inc
diff --git a/passes/cmds/test_patch.cc b/passes/cmds/test_patch.cc
new file mode 100644
index 000000000..ba7ad851f
--- /dev/null
+++ b/passes/cmds/test_patch.cc
@@ -0,0 +1,36 @@
+#include "kernel/rtlil.h"
+#include "kernel/yosys.h"
+#include "kernel/unstable/patch.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct TestPatchPass : public Pass {
+	TestPatchPass() : Pass("test_patch", "test patcher") { }
+	void help() override
+	{
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		(void) args;
+		RTLIL::Patch patcher;
+		design->bufNormalize();
+		for (auto module : design->selected_modules()) {
+			patcher.mod = module;
+			patcher.map = SigMap(module);
+			for (auto cell : module->selected_cells()) {
+				if (cell->type == ID($add)) {
+					RTLIL::Cell* sub = patcher.addCell(NEW_ID, ID($sub));
+					sub->connections_ = cell->connections();
+					sub->parameters = cell->parameters;
+					sub->setPort(ID::A, cell->getPort(ID::A));
+					sub->setPort(ID::B, cell->getPort(ID::B));
+					sub->setPort(ID::Y, cell->getPort(ID::Y));
+					patcher.patch();
+				}
+			}
+		}
+	}
+} TestPatchPass;
+
+PRIVATE_NAMESPACE_END