mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-05-25 11:26:22 +00:00
Code Activity

test_patch total basics

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-12-31 17:46:27 +01:00
parent 6f0be1b4e9
commit 89e5c4ccca
4 changed files with 62 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

8
kernel/unstable/patch.h
View file

@ -2,6 +2,7 @@
#define PATCH_H
#include "kernel/rtlil.h"
#include "kernel/sigtools.h"
YOSYS_NAMESPACE_BEGIN
@ -16,17 +17,18 @@ protected:
void add(RTLIL::Process *process);
public:
// RTLIL::Design *design;
Module *mod;
SigMap map;
vector<Wire> wires_;
vector<Cell> cells_;
vector<RTLIL::SigSig> connections_;
vector<RTLIL::SigSig> connections_;
void connect(const RTLIL::SigSig &conn);
void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
const std::vector<RTLIL::SigSig> &connections() const;
void patch(RTLIL::Module *mod);
void patch();
RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);