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test_patch total basics

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This commit is contained in:
Emil J. Tywoniak 2025-12-31 17:46:27 +01:00
parent 6f0be1b4e9
commit 89e5c4ccca
4 changed files with 62 additions and 3 deletions
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20
kernel/unstable/patch.cc
View file

@ -1,4 +1,6 @@
#include "kernel/unstable/patch.h"
#include "kernel/celltypes.h"
#include "kernel/rtlil.h"
YOSYS_NAMESPACE_BEGIN
@ -10,6 +12,24 @@ Cell* Patch::addCell(IdString name, IdString type) {
return &cell;
}
void Patch::patch() {
for (auto& cell: cells_) {
Cell* new_cell = mod->addCell(cell.name, &cell);
for (auto [port_name, sig] : new_cell->connections()) {
log_assert(yosys_celltypes.cell_known(cell.type));
auto dir = cell.port_dir(port_name);
if (dir == PD_OUTPUT || dir == PD_INOUT) {
for (auto chunk : sig.chunks()) {
log_assert(chunk.is_wire());
auto* wire = chunk.wire;
wire->driverCell_->setPort(wire->driverPort_, SigSpec());
wire->driverCell_ = new_cell;
wire->driverPort_ = port_name;
}
}
}
}
}
YOSYS_NAMESPACE_END

8
kernel/unstable/patch.h
View file

@ -2,6 +2,7 @@
#define PATCH_H
#include "kernel/rtlil.h"
#include "kernel/sigtools.h"
YOSYS_NAMESPACE_BEGIN
@ -16,17 +17,18 @@ protected:
void add(RTLIL::Process *process);
public:
// RTLIL::Design *design;
Module *mod;
SigMap map;
vector<Wire> wires_;
vector<Cell> cells_;
vector<RTLIL::SigSig> connections_;
vector<RTLIL::SigSig> connections_;
void connect(const RTLIL::SigSig &conn);
void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
const std::vector<RTLIL::SigSig> &connections() const;
void patch(RTLIL::Module *mod);
void patch();
RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);