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Merge 72c2081e29 into a80462f27f

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Emil J 2025-10-09 02:08:25 +02:00 • committed by GitHub
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3 changed files with 96 additions and 13 deletions
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37
passes/cmds/box_derive.cc
View file

@ -51,6 +51,9 @@ struct BoxDerivePass : Pass {
log(" replaces the internal Yosys naming scheme in which the names of derived\n");
log(" modules start with '$paramod$')\n");
log("\n");
log(" -apply_derived_type\n");
log(" use the derived modules\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *d) override
{
@ -59,11 +62,14 @@ struct BoxDerivePass : Pass {
size_t argidx;
IdString naming_attr;
IdString base_name;
bool apply_mode = false;
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-naming_attr" && argidx + 1 < args.size())
naming_attr = RTLIL::escape_id(args[++argidx]);
else if (args[argidx] == "-base" && argidx + 1 < args.size())
base_name = RTLIL::escape_id(args[++argidx]);
else if (args[argidx] == "-apply")
apply_mode = true;
else
break;
}
@ -90,24 +96,29 @@ struct BoxDerivePass : Pass {
auto index = std::make_pair(base->name, cell->parameters);
if (cell->parameters.empty() || done.count(index))
if (cell->parameters.empty())
continue;
IdString derived_type = base->derive(d, cell->parameters);
Module *derived = d->module(derived_type);
log_assert(derived && "Failed to derive module\n");
log_debug("derived %s\n", derived_type);
if (!done.count(index)) {
IdString derived_type = base->derive(d, cell->parameters);
Module *derived = d->module(derived_type);
log_assert(derived && "Failed to derive module\n");
log("derived %s\n", derived_type);
if (!naming_attr.empty() && derived->has_attribute(naming_attr)) {
IdString new_name = RTLIL::escape_id(derived->get_string_attribute(naming_attr));
if (!new_name.isPublic())
log_error("Derived module %s cannot be renamed to private name %s.\n",
log_id(derived), log_id(new_name));
derived->attributes.erase(naming_attr);
d->rename(derived, new_name);
if (!naming_attr.empty() && derived->has_attribute(naming_attr)) {
IdString new_name = RTLIL::escape_id(derived->get_string_attribute(naming_attr));
if (!new_name.isPublic())
log_error("Derived module %s cannot be renamed to private name %s.\n",
log_id(derived), log_id(new_name));
derived->attributes.erase(naming_attr);
d->rename(derived, new_name);
}
done[index] = derived;
}
done[index] = derived;
if (apply_mode)
cell->type = done[index]->name;
}
}
}

32
passes/cmds/chtype.cc
View file

@ -22,6 +22,27 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
static void publish(RTLIL::IdString& id) {
if (id.begins_with("$")) {
log_debug("publishing %s\n", id.c_str());
id = "\\" + id.str();
log_debug("published %s\n", id.c_str());
}
}
static void publish_design(RTLIL::Design* design) {
auto saved_modules = design->modules_;
design->modules_.clear();
for (auto& [name, mod] : saved_modules) {
publish(mod->name);
design->modules_[mod->name] = mod;
for (auto* cell : mod->cells()) {
publish(cell->type);
}
}
}
struct ChtypePass : public Pass {
ChtypePass() : Pass("chtype", "change type of cells in the design") { }
void help() override
@ -38,12 +59,16 @@ struct ChtypePass : public Pass {
log(" -map <old_type> <new_type>\n");
log(" change cells types that match <old_type> to <new_type>\n");
log("\n");
log(" -publish_icells\n");
log(" change internal cells types to public types\n");
log("\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
IdString set_type;
dict<IdString, IdString> map_types;
bool publish_mode = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@ -58,10 +83,17 @@ struct ChtypePass : public Pass {
map_types[old_type] = new_type;
continue;
}
if (args[argidx] == "-publish_icells") {
publish_mode = true;
continue;
}
break;
}
extra_args(args, argidx, design);
if (publish_mode)
publish_design(design);
for (auto module : design->selected_modules())
{
for (auto cell : module->selected_cells())

40
tests/various/box_derive.ys
View file

@ -34,6 +34,7 @@ module top;
endmodule
EOF
design -save before
box_derive -naming_attr final_name top
select -assert-mod-count 1 =aa1
@ -48,6 +49,45 @@ select -assert-mod-count 1 =cc1
select -assert-mod-count 0 =cc2
select -assert-mod-count 0 =cc3
# no instances of the new derived modules
# you could use wildcards like t:aa* here - if that wasn't just broken
select -assert-count 0 t:aa1 t:aa2 t:aa3
select -assert-count 0 t:bb1 t:bb2 t:bb3
select -assert-count 0 t:cc1 t:cc2 t:cc3
design -load before
# same command but with -apply_derived_type
box_derive -apply_derived_type -naming_attr final_name top
# same derived modules created as without -apply_derived_type
select -assert-mod-count 1 =aa1
select -assert-mod-count 1 =aa2
select -assert-mod-count 0 =aa3
select -assert-mod-count 1 =bb1
select -assert-mod-count 0 =bb2
select -assert-mod-count 1 =bb3
select -assert-mod-count 1 =cc1
select -assert-mod-count 0 =cc2
select -assert-mod-count 0 =cc3
# but we have instances of the new derived modules
select -assert-count 1 t:aa1
select -assert-count 1 t:aa2
select -assert-count 0 t:aa3
select -assert-count 1 t:bb1
select -assert-count 0 t:bb2
select -assert-count 1 t:bb3
select -assert-count 2 t:cc1
select -assert-count 0 t:cc2
select -assert-count 0 t:cc3
# we are expecting the original aa, bb, cc modules
# and 5 specializations generated by box_derive
select -assert-mod-count 8 =A:whitebox