From ba4f9f5f6718f9d60aa6175954c1b2dd5f436b4d Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 25 Jun 2025 12:43:01 +0200 Subject: [PATCH 1/4] publish: add pass for renaming private cell types to public --- passes/cmds/Makefile.inc | 1 + passes/cmds/publish.cc | 43 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) create mode 100644 passes/cmds/publish.cc diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index 9bf615a7e..f4c4db2f8 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -57,3 +57,4 @@ OBJS += passes/cmds/abstract.o OBJS += passes/cmds/test_select.o OBJS += passes/cmds/timeest.o OBJS += passes/cmds/linecoverage.o +OBJS += passes/cmds/publish.o diff --git a/passes/cmds/publish.cc b/passes/cmds/publish.cc new file mode 100644 index 000000000..45a3ef5de --- /dev/null +++ b/passes/cmds/publish.cc @@ -0,0 +1,43 @@ +#include "kernel/register.h" +#include "kernel/rtlil.h" +#include "kernel/log.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct PublishPass : public Pass { +private: + static void publish(RTLIL::IdString& id) { + if (id.begins_with("$")) { + log_debug("publishing %s\n", id.c_str()); + id = "\\" + id.str(); + log_debug("published %s\n", id.c_str()); + } + } +public: + PublishPass() : Pass("publish", "publish private cell types") { } + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" publish\n"); + log("Makes all module names and cell types public by prefixing\n"); + log("%% with \\.\n"); + } + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing PUBLISH pass. (make cell types public)\n"); + extra_args(args, 1, design); + auto saved_modules = design->modules_; + design->modules_.clear(); + for (auto& [name, mod] : saved_modules) { + publish(mod->name); + design->modules_[mod->name] = mod; + for (auto* cell : mod->cells()) { + publish(cell->type); + } + } + } +} PublishPass; + +PRIVATE_NAMESPACE_END From b735f2f1d33b8fd5edf05f246969c5caacbb46b7 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Wed, 25 Jun 2025 12:43:15 +0200 Subject: [PATCH 2/4] box_derive: add -apply --- passes/cmds/box_derive.cc | 37 ++++++++++++++++++++++------------ tests/various/box_derive.ys | 40 +++++++++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+), 13 deletions(-) diff --git a/passes/cmds/box_derive.cc b/passes/cmds/box_derive.cc index a0faacc9a..c193e91ae 100644 --- a/passes/cmds/box_derive.cc +++ b/passes/cmds/box_derive.cc @@ -51,6 +51,9 @@ struct BoxDerivePass : Pass { log(" replaces the internal Yosys naming scheme in which the names of derived\n"); log(" modules start with '$paramod$')\n"); log("\n"); + log(" -apply\n"); + log(" use the derived modules\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *d) override { @@ -59,11 +62,14 @@ struct BoxDerivePass : Pass { size_t argidx; IdString naming_attr; IdString base_name; + bool apply_mode = false; for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-naming_attr" && argidx + 1 < args.size()) naming_attr = RTLIL::escape_id(args[++argidx]); else if (args[argidx] == "-base" && argidx + 1 < args.size()) base_name = RTLIL::escape_id(args[++argidx]); + else if (args[argidx] == "-apply") + apply_mode = true; else break; } @@ -90,24 +96,29 @@ struct BoxDerivePass : Pass { auto index = std::make_pair(base->name, cell->parameters); - if (cell->parameters.empty() || done.count(index)) + if (cell->parameters.empty()) continue; - IdString derived_type = base->derive(d, cell->parameters); - Module *derived = d->module(derived_type); - log_assert(derived && "Failed to derive module\n"); - log_debug("derived %s\n", derived_type); + if (!done.count(index)) { + IdString derived_type = base->derive(d, cell->parameters); + Module *derived = d->module(derived_type); + log_assert(derived && "Failed to derive module\n"); + log("derived %s\n", derived_type); - if (!naming_attr.empty() && derived->has_attribute(naming_attr)) { - IdString new_name = RTLIL::escape_id(derived->get_string_attribute(naming_attr)); - if (!new_name.isPublic()) - log_error("Derived module %s cannot be renamed to private name %s.\n", - log_id(derived), log_id(new_name)); - derived->attributes.erase(naming_attr); - d->rename(derived, new_name); + if (!naming_attr.empty() && derived->has_attribute(naming_attr)) { + IdString new_name = RTLIL::escape_id(derived->get_string_attribute(naming_attr)); + if (!new_name.isPublic()) + log_error("Derived module %s cannot be renamed to private name %s.\n", + log_id(derived), log_id(new_name)); + derived->attributes.erase(naming_attr); + d->rename(derived, new_name); + } + + done[index] = derived; } - done[index] = derived; + if (apply_mode) + cell->type = done[index]->name; } } } diff --git a/tests/various/box_derive.ys b/tests/various/box_derive.ys index f02e13360..ef6c87193 100644 --- a/tests/various/box_derive.ys +++ b/tests/various/box_derive.ys @@ -34,6 +34,7 @@ module top; endmodule EOF +design -save before box_derive -naming_attr final_name top select -assert-mod-count 1 =aa1 @@ -48,6 +49,45 @@ select -assert-mod-count 1 =cc1 select -assert-mod-count 0 =cc2 select -assert-mod-count 0 =cc3 +# no instances of the new derived modules +# you could use wildcards like t:aa* here - if that wasn't just broken +select -assert-count 0 t:aa1 t:aa2 t:aa3 +select -assert-count 0 t:bb1 t:bb2 t:bb3 +select -assert-count 0 t:cc1 t:cc2 t:cc3 + +design -load before + +# same command but with -apply +box_derive -apply -naming_attr final_name top + +# same derived modules created as without -apply +select -assert-mod-count 1 =aa1 +select -assert-mod-count 1 =aa2 +select -assert-mod-count 0 =aa3 + +select -assert-mod-count 1 =bb1 +select -assert-mod-count 0 =bb2 +select -assert-mod-count 1 =bb3 + +select -assert-mod-count 1 =cc1 +select -assert-mod-count 0 =cc2 +select -assert-mod-count 0 =cc3 + +# but we have instances of the new derived modules +select -assert-count 1 t:aa1 +select -assert-count 1 t:aa2 +select -assert-count 0 t:aa3 + +select -assert-count 1 t:bb1 +select -assert-count 0 t:bb2 +select -assert-count 1 t:bb3 + +select -assert-count 2 t:cc1 +select -assert-count 0 t:cc2 +select -assert-count 0 t:cc3 + + + # we are expecting the original aa, bb, cc modules # and 5 specializations generated by box_derive select -assert-mod-count 8 =A:whitebox From 4706c82c3152f3d0b83ca7a297720b8f53dba64c Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 9 Oct 2025 01:44:13 +0200 Subject: [PATCH 3/4] box_derive: rename -apply to -apply_derived_type --- passes/cmds/box_derive.cc | 2 +- tests/various/box_derive.ys | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/passes/cmds/box_derive.cc b/passes/cmds/box_derive.cc index c193e91ae..dd085876e 100644 --- a/passes/cmds/box_derive.cc +++ b/passes/cmds/box_derive.cc @@ -51,7 +51,7 @@ struct BoxDerivePass : Pass { log(" replaces the internal Yosys naming scheme in which the names of derived\n"); log(" modules start with '$paramod$')\n"); log("\n"); - log(" -apply\n"); + log(" -apply_derived_type\n"); log(" use the derived modules\n"); log("\n"); } diff --git a/tests/various/box_derive.ys b/tests/various/box_derive.ys index ef6c87193..465eab284 100644 --- a/tests/various/box_derive.ys +++ b/tests/various/box_derive.ys @@ -57,10 +57,10 @@ select -assert-count 0 t:cc1 t:cc2 t:cc3 design -load before -# same command but with -apply -box_derive -apply -naming_attr final_name top +# same command but with -apply_derived_type +box_derive -apply_derived_type -naming_attr final_name top -# same derived modules created as without -apply +# same derived modules created as without -apply_derived_type select -assert-mod-count 1 =aa1 select -assert-mod-count 1 =aa2 select -assert-mod-count 0 =aa3 From 72c2081e29e22f3145f26c7e02c4a5f94283e045 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 9 Oct 2025 02:08:20 +0200 Subject: [PATCH 4/4] chtype: replace publish pass with chtype -publish_icells --- passes/cmds/Makefile.inc | 1 - passes/cmds/chtype.cc | 32 ++++++++++++++++++++++++++++++ passes/cmds/publish.cc | 43 ---------------------------------------- 3 files changed, 32 insertions(+), 44 deletions(-) delete mode 100644 passes/cmds/publish.cc diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index f4c4db2f8..9bf615a7e 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -57,4 +57,3 @@ OBJS += passes/cmds/abstract.o OBJS += passes/cmds/test_select.o OBJS += passes/cmds/timeest.o OBJS += passes/cmds/linecoverage.o -OBJS += passes/cmds/publish.o diff --git a/passes/cmds/chtype.cc b/passes/cmds/chtype.cc index 6f9ca9a45..eb194f3e3 100644 --- a/passes/cmds/chtype.cc +++ b/passes/cmds/chtype.cc @@ -22,6 +22,27 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +static void publish(RTLIL::IdString& id) { + if (id.begins_with("$")) { + log_debug("publishing %s\n", id.c_str()); + id = "\\" + id.str(); + log_debug("published %s\n", id.c_str()); + } +} + +static void publish_design(RTLIL::Design* design) { + auto saved_modules = design->modules_; + design->modules_.clear(); + for (auto& [name, mod] : saved_modules) { + publish(mod->name); + design->modules_[mod->name] = mod; + for (auto* cell : mod->cells()) { + publish(cell->type); + } + } +} + + struct ChtypePass : public Pass { ChtypePass() : Pass("chtype", "change type of cells in the design") { } void help() override @@ -38,12 +59,16 @@ struct ChtypePass : public Pass { log(" -map \n"); log(" change cells types that match to \n"); log("\n"); + log(" -publish_icells\n"); + log(" change internal cells types to public types\n"); + log("\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *design) override { IdString set_type; dict map_types; + bool publish_mode = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -58,10 +83,17 @@ struct ChtypePass : public Pass { map_types[old_type] = new_type; continue; } + if (args[argidx] == "-publish_icells") { + publish_mode = true; + continue; + } break; } extra_args(args, argidx, design); + if (publish_mode) + publish_design(design); + for (auto module : design->selected_modules()) { for (auto cell : module->selected_cells()) diff --git a/passes/cmds/publish.cc b/passes/cmds/publish.cc deleted file mode 100644 index 45a3ef5de..000000000 --- a/passes/cmds/publish.cc +++ /dev/null @@ -1,43 +0,0 @@ -#include "kernel/register.h" -#include "kernel/rtlil.h" -#include "kernel/log.h" - -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN - -struct PublishPass : public Pass { -private: - static void publish(RTLIL::IdString& id) { - if (id.begins_with("$")) { - log_debug("publishing %s\n", id.c_str()); - id = "\\" + id.str(); - log_debug("published %s\n", id.c_str()); - } - } -public: - PublishPass() : Pass("publish", "publish private cell types") { } - void help() override - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" publish\n"); - log("Makes all module names and cell types public by prefixing\n"); - log("%% with \\.\n"); - } - void execute(std::vector args, RTLIL::Design *design) override - { - log_header(design, "Executing PUBLISH pass. (make cell types public)\n"); - extra_args(args, 1, design); - auto saved_modules = design->modules_; - design->modules_.clear(); - for (auto& [name, mod] : saved_modules) { - publish(mod->name); - design->modules_[mod->name] = mod; - for (auto* cell : mod->cells()) { - publish(cell->type); - } - } - } -} PublishPass; - -PRIVATE_NAMESPACE_END