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SystemVerilog support for implicit named port connections

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This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
This commit is contained in:
tux3 2019-06-05 00:47:54 +02:00
parent 1332051f33
commit 88f5977093
5 changed files with 59 additions and 12 deletions
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8
tests/various/implicit_ports.ys Normal file
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read_verilog -sv implicit_ports.sv
proc; opt
flatten
select -module named_ports
sat -verify -prove alu_result 6
sat -verify -set-all-undef cout