pyosys: rewrite using pybind11

- Rewrite all Python features to use the pybind11 library instead of boost::python.
  Unlike boost::python, pybind11 is a header-only library that is just included by Pyosys code, saving a lot of compile time on wheels.
- Factor out as much "translation" code from the generator into proper C++ files
- Fix running the embedded interpreter not supporting "from pyosys import libyosys as ys" like wheels
- Move Python-related elements to `pyosys` directory at the root of the repo
- Slight shift in bridging semantics:
  - Containers are declared as "opaque types" and are passed by reference to Python - many methods have been implemented to make them feel right at home without the overhead/ambiguity of copying to Python and then copying back after mutation
  - Monitor/Pass use "trampoline" pattern to support virual methods overridable in Python: virtual methods no longer require `py_` prefix
- Create really short test set for pyosys that just exercises basic functionality

examples/python-api/pass.py

@@ -1,22 +1,25 @@
 #!/usr/bin/python3
 
-import libyosys as ys
+from pyosys import libyosys as ys
+
+from pathlib import Path
 
 import matplotlib.pyplot as plt
-import numpy as np
+
+__file_dir__ = Path(__file__).absolute().parent
 
 class CellStatsPass(ys.Pass):
 
     def __init__(self):
         super().__init__("cell_stats", "Shows cell stats as plot")
 
-    def py_help(self):
+    def help(self):
         ys.log("This pass uses the matplotlib library to display cell stats\n")
 
-    def py_execute(self, args, design):
+    def execute(self, args, design):
         ys.log_header(design, "Plotting cell stats\n")
         cell_stats = {}
-        for module in design.selected_whole_modules_warn():
+        for module in design.all_selected_whole_modules():
             for cell in module.selected_cells():
                 if cell.type.str() in cell_stats:
                     cell_stats[cell.type.str()] += 1
@@ -29,4 +32,11 @@ class CellStatsPass(ys.Pass):
     def py_clear_flags(self):
         ys.log("Clear Flags - CellStatsPass\n")
 
-p = CellStatsPass()
+p = CellStatsPass() # register
+
+if __name__ == "__main__":
+    design = ys.Design()
+    ys.run_pass(f"read_verilog {__file_dir__.parents[1] / 'tests' / 'simple' / 'fiedler-cooley.v'}", design)
+    ys.run_pass("prep", design)
+    ys.run_pass("opt -full", design)
+    ys.run_pass("cell_stats", design)