mirror of
https://github.com/YosysHQ/yosys
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- Rewrite all Python features to use the pybind11 library instead of boost::python. Unlike boost::python, pybind11 is a header-only library that is just included by Pyosys code, saving a lot of compile time on wheels. - Factor out as much "translation" code from the generator into proper C++ files - Fix running the embedded interpreter not supporting "from pyosys import libyosys as ys" like wheels - Move Python-related elements to `pyosys` directory at the root of the repo - Slight shift in bridging semantics: - Containers are declared as "opaque types" and are passed by reference to Python - many methods have been implemented to make them feel right at home without the overhead/ambiguity of copying to Python and then copying back after mutation - Monitor/Pass use "trampoline" pattern to support virual methods overridable in Python: virtual methods no longer require `py_` prefix - Create really short test set for pyosys that just exercises basic functionality
42 lines
1.3 KiB
Python
Executable file
42 lines
1.3 KiB
Python
Executable file
#!/usr/bin/python3
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from pyosys import libyosys as ys
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from pathlib import Path
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import matplotlib.pyplot as plt
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__file_dir__ = Path(__file__).absolute().parent
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class CellStatsPass(ys.Pass):
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def __init__(self):
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super().__init__("cell_stats", "Shows cell stats as plot")
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def help(self):
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ys.log("This pass uses the matplotlib library to display cell stats\n")
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def execute(self, args, design):
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ys.log_header(design, "Plotting cell stats\n")
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cell_stats = {}
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for module in design.all_selected_whole_modules():
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for cell in module.selected_cells():
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if cell.type.str() in cell_stats:
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cell_stats[cell.type.str()] += 1
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else:
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cell_stats[cell.type.str()] = 1
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plt.bar(range(len(cell_stats)), height = list(cell_stats.values()),align='center')
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plt.xticks(range(len(cell_stats)), list(cell_stats.keys()))
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plt.show()
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def py_clear_flags(self):
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ys.log("Clear Flags - CellStatsPass\n")
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p = CellStatsPass() # register
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if __name__ == "__main__":
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design = ys.Design()
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ys.run_pass(f"read_verilog {__file_dir__.parents[1] / 'tests' / 'simple' / 'fiedler-cooley.v'}", design)
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ys.run_pass("prep", design)
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ys.run_pass("opt -full", design)
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ys.run_pass("cell_stats", design)
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