mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-04-14 08:15:11 +00:00
Code Activity

rtlil: sigNormalize Module when added to Design in signorm mode

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-04-07 20:05:51 +02:00
parent b6ca1beabc
commit 8831f3245d
2 changed files with 21 additions and 16 deletions
Download patch file Download diff file Expand all files Collapse all files

16
kernel/rtlil.cc
View file

@ -1137,22 +1137,6 @@ RTLIL::Module *RTLIL::Design::top_module() const
return module_count == 1 ? module : nullptr;
}
void RTLIL::Design::add(RTLIL::Module *module)
{
log_assert(modules_.count(module->name) == 0);
log_assert(refcount_modules_ == 0);
modules_[module->name] = module;
module->design = this;
for (auto mon : monitors)
mon->notify_module_add(module);
if (yosys_xtrace) {
log("#X# New Module: %s\n", log_id(module));
log_backtrace("-X- ", yosys_xtrace-1);
}
}
void RTLIL::Design::add(RTLIL::Binding *binding)
{
log_assert(binding != nullptr);

21
kernel/rtlil_bufnorm.cc
View file

@ -1203,4 +1203,25 @@ void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal
}
void RTLIL::Design::add(RTLIL::Module *module)
{
log_assert(modules_.count(module->name) == 0);
log_assert(refcount_modules_ == 0);
modules_[module->name] = module;
module->design = this;
for (auto mon : monitors)
mon->notify_module_add(module);
if (yosys_xtrace) {
log("#X# New Module: %s\n", log_id(module));
log_backtrace("-X- ", yosys_xtrace-1);
}
if (flagSigNormalized) {
module->sigNormalize();
}
}
YOSYS_NAMESPACE_END